Low power filtering of pulse density modulated data using digital filters with gray coding / decoding

By employing multi-stage delay lines and encoding/decoding techniques in the ΣΔ-ADC circuit, and utilizing binary-Gray encoding and Gray-binary decoding, the power consumption of the digital filter is reduced, solving the high power consumption problem of broadband high-speed filters and achieving low-power operation.

CN122247424APending Publication Date: 2026-06-19STMICROELECTRONICS INT NV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
STMICROELECTRONICS INT NV
Filing Date
2025-12-17
Publication Date
2026-06-19

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Abstract

This disclosure relates to low-power filtering of pulse density modulated data using a digital filter with Gray encoding / decoding. A Σ-Δ (ΣΔ) analog-to-digital converter (ADC) circuit receives an analog signal and outputs a pulse density modulated digital signal. The digital filter filters a sequence of data values ​​from the pulse density modulated digital signal. The digital filter includes a multi-stage delay line, an encoder circuit, and a decoder circuit. The encoder circuit is configured to encode data values ​​in the data value sequence for input to the multi-stage delay line, and the decoder circuit is configured to decode data values ​​output from corresponding taps of the multi-stage delay line. The encoder may be a binary-Gray code encoder, and the decoder may be a Gray-binary code decoder.
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