Time modulation array integrated radio frequency front end device and control method

Abstract

This invention discloses an integrated radio frequency (RF) front-end device and control method for time-modulated arrays, belonging to the field of microwave RF and array signal processing technology. The device integrates an RF switch module with an RF switch unit and a 180-degree phase-shifting network. The RF switch unit uses PIN diodes to control signal switching, and the 180-degree phase-shifting network employs a coupled three-wire structure. The control layer attaches an FPGA to the back of the RF circuit layer, generating multiple synchronous timing signals to drive the switches, achieving periodic switching and phase shifting. The multiple outputs are combined and then enter the receiving link, where they are processed sequentially by a limiter, attenuator, amplifier, and filter. The control method receives instructions from the host computer via the FPGA and outputs synchronous control signals in parallel under a unified clock. This invention integrates switching, phase shifting, and control, shortening the control link, reducing timing jitter, improving multi-channel synchronization accuracy, and simultaneously achieving wideband matching and high spurious suppression.

Description

Technical Field

[0001] This invention relates to the field of microwave radio frequency and array signal processing technology, and in particular to an integrated radio frequency front-end device and control method for time modulation array. Background Technology

[0002] Traditional time-modulated arrays typically rely on preset periodic modulation sequences to achieve beam control and harmonic utilization, but this approach still has many limitations in practical applications. On the one hand, fixed modulation sequences are difficult to accommodate multi-functional requirements, resulting in insufficient beam control flexibility. On the other hand, the introduction of multi-channel independent RF links and complex feeding networks not only increases system hardware complexity and power consumption but also makes it difficult to guarantee amplitude and phase consistency and channel isolation, thus limiting further improvements in overall performance. In addition, in traditional structures, switching and phase-shifting functions are often implemented separately, resulting in low system integration and hindering engineering and miniaturization development.

[0003] With the continuous development of time-modulated arrays in beamforming and direction-of-arrival estimation, RF front-end architecture is evolving towards high integration and multi-functionality. While using external field-programmable gate arrays (FPGAs) and equal-length cables to drive the RF switches of each channel can achieve some degree of synchronous distribution of multiple control signals, this method primarily compensates for geometric length differences in transmission. It fails to fundamentally eliminate time delay offsets and edge distortions caused by connectors, cable bends, board interfaces, load differences, parasitic parameters, and environmental changes in actual systems. Especially under multi-channel, high-frequency, and fast-switching operating conditions, excessively long control links can easily introduce additional jitter, reflections, crosstalk, and electromagnetic interference, thereby reducing timing control accuracy and channel repeatability. Summary of the Invention

[0004] The purpose of this invention is to provide an integrated radio frequency front-end device and control method for time modulation arrays, which solves the technical problems of complex links, large size, high transmission loss and poor timing consistency of multiple channels caused by the separate implementation of switching, phase shifting and control in existing time modulation arrays.

[0005] To achieve the above objectives, this invention provides an integrated time-modulation array RF front-end device, including an integrated RF switch module, an RF combining network, and a three-stage superheterodyne receiver link. The integrated RF switch module includes an RF circuit layer and a control circuit layer. The RF circuit layer integrates an RF switch and a 180-degree phase-shifting network. The RF switch uses a PIN diode as the core switching device. The 180-degree phase-shifting network consists of a coupled three-wire structure and a transmission line with two short-circuited stubs. The control circuit layer is equipped with a field-programmable gate array (FPGA) chip, which is mounted on the back of the RF circuit layer and electrically connected to the RF switch and the 180-degree phase-shifting network through a drive interface. This FPGA chip is used to generate multiple synchronous timing control signals to drive the RF switch for periodic on / off control. The output of the multi-channel integrated RF switch module is connected to the input of the three-stage superheterodyne receiver link via the RF combining network.

[0006] Preferably, the outer two lines of the parallel-coupled three-wire structure are merged to form an equivalent parallel-coupled two-wire structure; the 180-degree phase-shifting network includes branch 1 and branch 2, which are equivalent circuits across the entire frequency band, with only a fixed phase difference of 180 degrees between them; wherein, The even-mode impedance of the coupled line. Here is the odd-mode impedance of the coupled line; the relationship between the odd-mode impedance and the even-mode impedance is: ; in, The characteristic impedance of the transmission line, The coupling coefficient is defined as: .

[0007] Preferably, the parameters are described as follows: when hour, At this point, branch 2 is equivalent to a 50Ω transmission line, and the phase shifter achieves infinite bandwidth; the parameter expression for branch 1 is... and In the form of a transmission line, where The center frequency corresponding to a quarter wavelength.

[0008] Preferably, the control circuit layer also includes a comparator chip; the logic output terminal of the field-programmable gate array chip is connected to the input terminal of the comparator chip, and the output terminal of the comparator chip is connected to the bias control terminal of the PIN diode as a drive interface; the comparator chip adopts the TLV3603 model and is used to complete level conversion and drive amplification.

[0009] Preferably, the field-programmable gate array (FPGA) chip is the EP4CE6E22C8N model; the clock input terminal of the FPGA chip is connected to an external 100MHz high-speed reference clock signal; the FPGA chip receives modulation parameters sent by the host computer, including modulation frequency, duty cycle and relative delay of each channel; the FPGA chip parses the modulation parameters in a unified clock domain and outputs a synchronous timing control signal with a frequency range of 1MHz to 10MHz.

[0010] Preferably, the three-stage superheterodyne receiver link includes a pre-stage low-noise amplifier, a first bandpass filter, a first mixer, a first intermediate frequency amplifier, a second mixer, a second intermediate frequency amplifier, a third mixer, a third intermediate frequency amplifier, and a second bandpass filter, which are cascaded in sequence; the first mixer, the second mixer, and the third mixer are respectively connected to a first local oscillator drive module, a second local oscillator drive module, and a third local oscillator drive module.

[0011] Preferably, the signal receiving and processing method of the device includes the following steps: The radio frequency signals received by each array element are time-modulated and phase-shifted by the integrated radio frequency switch module, and then power-combined through the radio frequency combining network to form a composite radio frequency signal. The composite radio frequency signal enters the three-stage superheterodyne receiver link, and is successively amplified by the front-stage low-noise amplifier and pre-filtered by the first bandpass filter. The amplified and pre-selected signal passes through the first mixer, the second mixer, and the third mixer in sequence, and completes the frequency conversion step by step under the drive of the corresponding local oscillator signal; the frequency conversion between each stage is amplified and spurious suppressed by the corresponding intermediate frequency amplifier and bandpass filter; The target intermediate frequency signal output from the third mixer is amplified by the third intermediate frequency amplifier and then output to the analog-to-digital converter for digital sampling.

[0012] Preferably, the three-stage superheterodyne receiver link distributes the receiver gain and filtering selectivity to three frequency conversion stages; the local oscillator frequencies of the first, second, and third mixers are planned according to the system's preset RF operating frequency band and target intermediate frequency to achieve graded suppression of image signals and out-of-band interference; within the 0.8GHz to 2.0GHz operating frequency band, the return loss S11 of the integrated RF switch module is less than -15dB.

[0013] The present invention also provides a control method for the above-mentioned device, comprising the following steps: An external, highly stable clock signal is input to a field-programmable gate array (FPGA) chip as a unified time reference. The host computer writes modulation parameters and operating mode information to the field-programmable gate array chip; Field-programmable gate array (FPGA) chips parse control words under a unified clock constraint and generate multiple synchronous timing control signals in parallel within the same clock domain; The multi-channel synchronous timing control signal is amplified by the drive interface and applied to the corresponding RF switch and 180-degree phase shift network, enabling the PIN diode to switch at high speed between two sets of bias states, thereby realizing the periodic on / off switching of the RF signal and the 180-degree phase shift state transition.

[0014] Preferably, after the field-programmable gate array chip outputs logic control signals, a comparator chip performs level conversion and amplifies the driving capability to ensure that the amplitude and edge of the driving signal meet the response requirements of the PIN diode; the period, pulse width and relative delay of the multi-channel synchronous timing control signals are independently configured by the modulation parameters issued by the host computer.

[0015] Therefore, the time modulation array integrated RF front-end device and control method of the present invention, which adopts the above structure, has the following beneficial effects: (1) The present invention deploys the field programmable gate array chip on the back of the radio frequency switch to form an integrated architecture of control-phase shifting-switching, which greatly shortens the control link length of the radio frequency switch, reduces the transmission delay and timing jitter of the control signal, improves the synchronization accuracy of multi-channel time modulation, and effectively suppresses modulation sideband spurious.

[0016] (2) The present invention adopts a coupled three-wire structure and a short-circuit stub to form a 180-degree phase-shifting network, and integrates it with a PIN diode switch, so that a single device can simultaneously have the capabilities of radio frequency switching and phase shifting, reducing system redundancy and ensuring signal utilization.

[0017] (3) The present invention adopts a three-stage superheterodyne receiver link. Through multi-stage amplification, graded filtering and step-by-step down-conversion processing, it effectively reduces the design pressure of single-stage frequency conversion, improves the ability to suppress out-of-band interference, image signals and spurious components, and ensures the stable output of the target intermediate frequency signal.

[0018] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a general architecture diagram of an integrated time modulation array radio frequency front-end device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a 180-degree phase-shifting network structure provided in an embodiment of the present invention; Figure 3 This is a block diagram of the integrated radio frequency switch module control architecture provided in an embodiment of the present invention; Figure 4 This is a block diagram illustrating the principle of a three-stage superheterodyne receiver link provided in an embodiment of the present invention. Figure 5 The phase characteristic curve of the 180-degree phase-shifting network provided in the embodiment of the present invention; Figure 6 The return loss (S11) test curve of the integrated RF switch module provided in the embodiment of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Example like Figure 1 As shown, this embodiment of the invention provides an integrated RF front-end device for a time modulation array, including an integrated RF switch module, an RF combining network, and a three-stage superheterodyne receiver link. The integrated RF switch module includes an RF circuit layer and a control circuit layer. The RF circuit layer integrates an RF switch and a 180-degree phase-shifting network. The control circuit layer is equipped with an FPGA (Field-Programmable Gate Array), which is mounted on the back of the RF circuit layer and electrically connected to the RF switch and the 180-degree phase-shifting network via a drive interface. The FPGA is used to generate multiple synchronous timing control signals to drive the RF switch for periodic on / off control. The output of the multi-channel integrated RF switch module is connected to the input of the three-stage superheterodyne receiver link via the RF combining network.

[0023] like Figure 2As shown, the control circuit layer of the integrated RF switch module also includes a comparator chip, a power supply module, a communication module, and a clock module. The communication module includes a host computer, an RS232 communication interface, and a SATOK (serial communication protocol conversion module). The host computer connects to the SATOK via the RS232 communication interface. The SATOK receives modulation parameters (including modulation frequency, duty cycle, and relative delay of each channel) from the host computer and transmits the parameters to the FPGA. The FPGA's clock input is connected to an external 100MHz high-speed reference clock signal, and the output 10MHz clock signal is multiplied (×2) to generate a synchronization signal. The comparator chip includes a shaping comparator and an inverting comparator. The FPGA's logic output is connected to the comparator chip's input, and the comparator chip's output serves as a drive interface connected to the bias control terminal of the PIN diode (the PIN diode has two states: 0° and 180°). The power supply module includes a DC / DC power supply module, with a 12V input and outputs 3V3 and 5V to power the FPGA and comparator, respectively.

[0024] like Figure 3 As shown, the control circuit layer of the integrated RF switch module also includes a comparator chip. The logic output of the FPGA is connected to the input of the comparator chip, and the output of the comparator chip serves as a drive interface connected to the bias control terminal of the PIN diode. The comparator chip is a TLV3603, used for level conversion and drive amplification. The FPGA is an EP4CE6E22C8N, whose clock input is connected to an external 100MHz high-speed reference clock signal. It receives modulation parameters (including modulation frequency, duty cycle, and relative delay of each channel) from the host computer, parses the modulation parameters in a unified clock domain, and outputs a synchronous timing control signal with a frequency range of 1MHz to 10MHz.

[0025] like Figure 4 As shown, the specific architecture of the three-stage superheterodyne receiver link includes a pre-stage low-noise amplifier, a first bandpass filter, a first mixer, a first intermediate frequency (IF) amplifier, a second mixer, a second IF amplifier, a third mixer, a third IF amplifier, and a second bandpass filter, all cascaded sequentially. The first, second, and third mixers are respectively connected to the first, second, and third local oscillator (LO) drive modules. This three-stage superheterodyne structure can improve the overall receiving performance of the entire system by balancing link gain, noise performance, and dynamic range while meeting the target IF output requirements.

[0026] An embodiment of the present invention provides a time modulation control method based on the above-mentioned device, comprising the following steps: An external, highly stable clock signal is input to a field-programmable gate array (FPGA) chip as a unified time reference. The host computer writes modulation parameters and operating mode information to the field-programmable gate array chip; Field-programmable gate array (FPGA) chips parse control words under a unified clock constraint and generate multiple synchronous timing control signals in parallel within the same clock domain; The multi-channel synchronous timing control signal is amplified by the drive interface and applied to the corresponding RF switch and 180-degree phase shift network, enabling the PIN diode to switch at high speed between two sets of bias states, thereby realizing the periodic on / off switching of the RF signal and the 180-degree phase shift state transition.

[0027] In the above method, after the field-programmable gate array (FPGA) chip outputs logic control signals, a comparator chip performs level conversion and amplifies the drive capability to ensure that the amplitude and edge of the drive signal meet the response requirements of the PIN diode. The period, pulse width, and relative delay of the multiple synchronous timing control signals are independently configured by the modulation parameters issued by the host computer. The advantage of the FPGA chip control method is that it can generate multiple control pulses in parallel under the same clock domain, effectively ensuring high consistency of each channel in terms of period, pulse width, and relative delay, while also exhibiting good repeatability and low timing jitter.

[0028] An embodiment of the present invention provides a signal receiving and processing method based on the above-described device, comprising the following steps: The radio frequency signals received by each array element are time-modulated and phase-shifted by the integrated radio frequency switch module, and then power-combined through the radio frequency combining network to form a composite radio frequency signal. The composite radio frequency signal enters the three-stage superheterodyne receiver link, and is successively amplified by the front-stage low-noise amplifier and pre-filtered by the first bandpass filter. The amplified and pre-selected signal passes through the first mixer, the second mixer, and the third mixer in sequence, and completes the frequency conversion step by step under the drive of the corresponding local oscillator signal; the frequency conversion between each stage is amplified and spurious suppressed by the corresponding intermediate frequency amplifier and bandpass filter; The target intermediate frequency signal output from the third mixer is amplified by the third intermediate frequency amplifier and then output to the analog-to-digital converter for digital sampling.

[0029] In the above method, the three-stage superheterodyne receiver link distributes the receiver gain and filtering selectivity across three frequency conversion stages. The local oscillator frequencies of the first, second, and third mixers are planned according to the system's preset RF operating frequency band and target intermediate frequency, achieving graded suppression of image signals and out-of-band interference. Within the 0.8GHz to 2.0GHz operating frequency band, the return loss S11 of the integrated RF switch module is less than -15dB.

[0030] To verify the technical effect of the present invention, the inventors processed a physical object and conducted specific tests. The test results are as follows: Figure 5 and Figure 6 As shown.

[0031] like Figure 5 As shown, the phase of the 180-degree phase-shifted network was tested using a Siyi 3656D vector network analyzer. Within the operating frequency range of 0.8GHz to 2.0GHz, the phase difference remained stable at around 180° (the dashed line is the 180° reference line), verifying the broadband phase stability of the phase-shifted network.

[0032] like Figure 6 As shown, the S-parameters of the integrated RF switch module were tested using a Siyi 3656D vector network analyzer. Within the operating frequency range of 0.8GHz to 2.0GHz, S11 was less than -15dB (the dashed line is the -15dB reference line), verifying the module's broadband matching performance.

[0033] Through the above tests, the integrated RF front-end device of the present invention achieves stable 180-degree phase shift and good impedance matching in the 0.8GHz to 2.0GHz operating frequency band, solving the problems of link complexity and poor timing consistency caused by the separate implementation of switching, phase shifting and control in traditional time modulation arrays.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. An integrated radio frequency front-end device for time modulation arrays, comprising an integrated radio frequency switch module, a radio frequency combining network, and a three-stage superheterodyne receiver link, characterized in that, The integrated RF switch module includes an RF circuit layer and a control circuit layer; The radio frequency circuit layer integrates radio frequency switches and a 180-degree phase-shifting network; RF switches use PIN diodes as the core switching device; A 180-degree phase-shifting network consists of a coupled three-wire structure and a transmission line with two short-circuited stubs; The control circuit layer is equipped with a field-programmable gate array (FPGA) chip, which is attached to the back of the radio frequency (RF) circuit layer and electrically connected to the RF switch and the 180-degree phase-shifting network through a drive interface. It is used to generate multiple synchronous timing control signals to drive the RF switch to perform periodic on / off control. The output of the multi-channel integrated RF switch module is connected to the input of the three-stage superheterodyne receiver link via an RF combining network.

2. The time-modulation array integrated radio frequency front-end device according to claim 1, characterized in that, The outer two lines of the parallel-coupled three-wire structure, when merged, are equivalent to a parallel-coupled two-wire structure; the 180-degree phase-shifting network includes branch 1 and branch 2, which are equivalent circuits across the entire frequency band, with only a fixed phase difference of 180 degrees between them; among which, The even-mode impedance of the coupled line. Here is the odd-mode impedance of the coupled line; the relationship between the odd-mode impedance and the even-mode impedance is: ； in, The characteristic impedance of the transmission line, The coupling coefficient is defined as: 。 3. The time-modulation array integrated radio frequency front-end device according to claim 2, characterized in that, The parameters are described as follows: when hour, At this point, branch 2 is equivalent to a 50Ω transmission line, and the phase shifter achieves infinite bandwidth; the parameter expression for branch 1 is... and In the form of a transmission line, where The center frequency corresponding to a quarter wavelength.

4. The time-modulation array integrated radio frequency front-end device according to claim 1, characterized in that, The control circuit layer also includes a comparator chip; the logic output of the field-programmable gate array chip is connected to the input of the comparator chip, and the output of the comparator chip is connected to the bias control terminal of the PIN diode as a drive interface; the comparator chip adopts the TLV3603 model, which is used to complete level conversion and drive amplification.

5. The time-modulation array integrated RF front-end device according to claim 4, characterized in that, The field-programmable gate array (FPGA) chip used is the EP4CE6E22C8N model. The clock input of the FPGA chip is connected to an external 100MHz high-speed reference clock signal. The FPGA chip receives modulation parameters from the host computer, including modulation frequency, duty cycle, and relative delay of each channel. The FPGA chip parses the modulation parameters in a unified clock domain and outputs a synchronous timing control signal with a frequency range of 1MHz to 10MHz.

6. The integrated radio frequency front-end device for time modulation array according to claim 1, characterized in that, The three-stage superheterodyne receiver link includes a pre-stage low-noise amplifier, a first bandpass filter, a first mixer, a first intermediate frequency amplifier, a second mixer, a second intermediate frequency amplifier, a third mixer, a third intermediate frequency amplifier, and a second bandpass filter, which are cascaded in sequence. The first mixer, the second mixer, and the third mixer are respectively connected to the first local oscillator drive module, the second local oscillator drive module, and the third local oscillator drive module.

7. The integrated radio frequency front-end device for time modulation array according to claim 6, characterized in that, The signal receiving and processing method of the device includes the following steps: The radio frequency signals received by each array element are time-modulated and phase-shifted by the integrated radio frequency switch module, and then power-combined through the radio frequency combining network to form a composite radio frequency signal. The composite radio frequency signal enters the three-stage superheterodyne receiver link, and is successively amplified by the front-stage low-noise amplifier and pre-filtered by the first bandpass filter. The amplified and pre-selected signal passes through the first mixer, the second mixer, and the third mixer in sequence, and completes the frequency conversion step by step under the drive of the corresponding local oscillator signal; the frequency conversion between each stage is amplified and spurious suppressed by the corresponding intermediate frequency amplifier and bandpass filter; The target intermediate frequency signal output from the third mixer is amplified by the third intermediate frequency amplifier and then output to the analog-to-digital converter for digital sampling.

8. The time-modulation array integrated radio frequency front-end device according to claim 7, characterized in that, The three-stage superheterodyne receiver link achieves selective distribution of receiver gain and filtering across three frequency conversion stages; the local oscillator frequencies of the first, second, and third mixers are planned according to the system's preset RF operating frequency band and target intermediate frequency, achieving graded suppression of image signals and out-of-band interference; within the 0.8GHz to 2.0GHz operating frequency band, the return loss S11 of the integrated RF switch module is less than -15dB.

9. A time modulation control method based on the device according to any one of claims 1-8, characterized in that, Includes the following steps: An external, highly stable clock signal is input to a field-programmable gate array (FPGA) chip as a unified time reference. The host computer writes modulation parameters and operating mode information to the field-programmable gate array chip; Field-programmable gate array (FPGA) chips parse control words under a unified clock constraint and generate multiple synchronous timing control signals in parallel within the same clock domain; The multi-channel synchronous timing control signal is amplified by the drive interface and applied to the corresponding RF switch and 180-degree phase shift network, enabling the PIN diode to switch at high speed between two sets of bias states, thereby realizing the periodic on / off switching of the RF signal and the 180-degree phase shift state transition.

10. The time modulation control method according to claim 9, characterized in that, After the field-programmable gate array chip outputs logic control signals, a comparator chip performs level conversion and amplifies the driving capability to ensure that the amplitude and edge of the driving signal meet the response requirements of the PIN diode. The period, pulse width, and relative delay of the multi-channel synchronous timing control signals are independently configured by the modulation parameters sent by the host computer.

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