Timestamp parallel access method, system and device based on fttr gateway and medium
By injecting and mapping timestamps to Ethernet preamble bits in the FTTR gateway, the problem of the FTTR gateway being unable to make a determination before the MAC layer buffer is solved, realizing low latency determination and differentiated uplink scheduling, improving PON time slot utilization, and supporting the mixed deployment of new and old terminals.
CN122247549BActive Publication Date: 2026-07-21TECHNICOLOR (CHINA) TECH CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TECHNICOLOR (CHINA) TECH CO LTD
- Filing Date
- 2026-05-25
- Publication Date
- 2026-07-21
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Figure CN122247549B_ABST
Abstract
The application discloses a timestamp parallel access method, system, device and medium based on an FTTR gateway. When a terminal device sends a time delay sensitive service data frame, a timestamp is injected to a PHY layer coding stream at a MAC-PHY interface and is mapped to preset bit positions of an Ethernet preamble; a user side PHY layer of the FTTR gateway extracts the timestamp in a preamble receiving stage and generates a frame attribute marking signal; a user side MAC layer distributes the data frame to different service queues according to the marking signal; and a network side PON module sends according to an uplink time slot type allocated by an OLT and the marking signal from a corresponding queue. The application uses preamble bit flipping to establish PHY layer bypass signaling, buffers service judgment before completion, does not modify the frame format, does not occupy the CPU, supports mixed deployment of new and old terminals, and realizes low delay, zero cost parallel access.
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