integrated circuit

Abstract

An integrated circuit is provided. The integrated circuit includes: a first wiring layer including a plurality of patterns, each extending in a first horizontal direction; active contacts; and active vias connecting the active contacts and at least two of the plurality of patterns.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0189072, filed on December 17, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosure relates to integrated circuits, and more specifically, to integrated circuits including horizontally extended mid-range (MOL) structures. Background Technology

[0003] With advancements in semiconductor technology, the size of devices, including those in integrated circuits, has decreased, and the integration density of integrated circuits has increased. As semiconductor manufacturing processes become increasingly specialized, research is underway into improved placement methods for circuit patterns used to supply power or signals to semiconductor devices. For example, research aims to provide sufficient space for circuit patterns in semiconductor devices while simultaneously enhancing the voltage drop characteristics of these patterns. Summary of the Invention

[0004] Integrated circuits including horizontally extended mid-process (MOL) structures (e.g., strip patterns formed in the MOL layer) are disclosed.

[0005] The purpose of this disclosure is not limited to the foregoing, but rather other purposes not described herein will be clearly understood by those skilled in the art from the following description.

[0006] An integrated circuit according to one or more embodiments includes: a first wiring layer including a plurality of patterns, each extending in a first horizontal direction; an active contact; and an active via connecting the active contact and at least two of the plurality of patterns and extending along the active contact.

[0007] An integrated circuit according to one or more embodiments includes: a wiring layer including a plurality of patterns each extending in a first horizontal direction; a first gate line and a second gate line each extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; and a first gate contact connecting the first gate line and at least two of the plurality of patterns, or connecting the first gate line, the second gate line and a pattern of the plurality of patterns.

[0008] An integrated circuit according to one or more embodiments includes: a wiring layer including a plurality of patterns, each extending in a first horizontal direction; an active contact; and a via connecting the active contact and the wiring layer, wherein the active via overlaps with a first pattern and a second pattern among the plurality of patterns in a vertical direction. Attached Figure Description

[0009] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 It is a plan view used to describe the layout of an integrated circuit according to one or more embodiments.

[0011] Figure 2 It is along Figure 1 The sectional view taken by line Y1-Y1'.

[0012] Figure 3 It is a plan view used to describe the layout of an integrated circuit according to one or more embodiments.

[0013] Figure 4 It is along Figure 3 A cross-sectional view taken by line Y2-Y2'.

[0014] Figure 5 It is a plan view used to describe the layout of standard cells included in an integrated circuit according to one or more embodiments.

[0015] Figure 6 yes Figure 5 A magnified perspective view of region A.

[0016] Figure 7 It is along Figure 5 A sectional view taken by line X1-X1'.

[0017] Figure 8 It is a plan view used to describe the layout of standard cells included in an integrated circuit according to one or more embodiments.

[0018] Figure 9 It is a plan view used to describe the layout of standard cells included in an integrated circuit according to one or more embodiments.

[0019] Figure 10 yes Figure 9 A magnified perspective view of region B.

[0020] Figure 11 This is a block diagram of a memory device according to one or more embodiments.

[0021] Figure 12 It is a circuit diagram used to describe the bit cells of an integrated circuit according to one or more embodiments.

[0022] Figure 13 It is a plan view used to describe a portion of the control block of a memory device according to one or more embodiments.

[0023] Figure 14A and Figure 14BIt is a plan view used to describe a layout of a portion of a row driver of a memory device according to one or more embodiments.

[0024] Figure 15 This is a block diagram illustrating a system-on-a-chip (SoC) according to one or more embodiments.

[0025] Figure 16 This is a flowchart illustrating a method for manufacturing an integrated circuit according to one or more embodiments. Detailed Implementation

[0026] The embodiments described herein are non-limiting exemplary embodiments, and therefore the disclosure is not limited thereto, and may be implemented in various other forms. Each of the embodiments provided herein does not exclude association with one or more features of other examples or embodiments also provided herein, or other examples or embodiments not provided herein but consistent with the disclosure. For example, unless otherwise mentioned in its description, even if the content described in a particular example or embodiment is not described in other examples or embodiments, such content may be understood to be related to or may be combined with different examples or embodiments.

[0027] It will be understood that when a component or layer is described as being "above," "on," "over," "below," "under," "connected to," or "bonded to" another component or layer, it may be directly above, on, above, below, under, connected to, or bonded to the other component or layer, or there may be intermediate components or layers present. Conversely, when a component is described as being "directly above," "directly on," "directly above," "directly below," "directly under," "directly connected to," or "directly bonded to," there are no intermediate components or layers present.

[0028] In the following description, various embodiments will be illustrated with reference to the accompanying drawings. Here, the X-axis direction and the Y-axis direction may be referred to as the first horizontal direction and the second horizontal direction, respectively (the second horizontal direction may intersect with the first horizontal direction), and the Z-axis direction may be referred to as the vertical direction.

[0029] Figure 1 It is a plan view used to describe the layout of an integrated circuit 10 according to one or more embodiments. Figure 2 It is along Figure 1 A cross-sectional view of line Y1-Y1'.

[0030] Reference Figure 1The integrated circuit 10 may include a gate line extending along the Y-axis on a substrate, and may include an active region extending along the X-axis on a substrate. The active region and gate line of the integrated circuit 10 can be configured with transistors (e.g., field-effect transistors (FETs)).

[0031] The substrate may include semiconductor materials (such as silicon (Si) or germanium (Ge)) or III-V compounds (such as GaAs, AlGaAs, InAs, InGaAs, InSb, GaSb, InGaSb, InP, GaP, InGaP, InN, GaN, or InGaN). In one or more embodiments, the substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0032] Multiple active contacts (also called contact structures or contact plugs) may be formed in an active region formed in the substrate. The multiple active contacts may be formed to extend in the Y-axis direction. Figure 1 The diagram shows multiple active contacts extending to the same length, but this can be used to describe the direction of extension of the multiple active contacts, and each of the multiple active contacts can be formed in various lengths based on the type of semiconductor devices formed in the integrated circuit 10 and the connection relationships between them.

[0033] Multiple wiring layers forming wiring for interconnecting semiconductor devices can be stacked in integrated circuit 10. Patterns formed in the multiple wiring layers may include metals (e.g., metal lines, patterns, contacts, vias, etc.), conductive metal nitrides, metal silicides, or combinations thereof. In the accompanying drawings, for ease of illustration, only some wiring layers may be shown, and Figure 1 The first routing layer M1 shown can be the layer closest to the substrate (i.e., the bottom routing layer) among multiple routing layers.

[0034] In each of the multiple routing layers, the direction of pattern extension can be specified. In each of the multiple routing layers, the area forming the pattern (e.g., a metal wire) can be defined as a track. For example, a pattern extending in the X-axis direction can be formed in odd-numbered routing layers from the substrate, and a pattern extending in the Y-axis direction can be formed in even-numbered routing layers from the substrate. Different routing layers among the multiple routing layers can be interconnected via vias that "pass through the insulating layer surrounding the pattern".

[0035] Multiple traces forming a pattern can be defined at least within a first wiring layer M1. These traces of the first wiring layer M1 can extend in the X-axis direction and can be separated from each other in the Y-axis direction. For example, the first trace TR1 to the fifth trace TR5 of the first wiring layer M1 can be disposed between the first power rail PR1 and the second power rail PR2 of the integrated circuit 10. However, the disclosure is not limited to this, and the number of traces disposed in the first wiring layer M1 can be modified in various ways based on the distance between the first power rail PR1 and the second power rail PR2 (i.e., the cell height of the standard cell).

[0036] Furthermore, the multiple traces of the pattern can be defined on a second wiring layer disposed on the first wiring layer M1 (e.g., Figure 9 In M2). The second wiring layer M2 can be a wiring layer disposed on the first wiring layer M1, and can be the second lowest wiring layer among multiple wiring layers. Multiple traces of the second wiring layer M2 can extend in the Y-axis direction and can be separated from each other in the X-axis direction. The first wiring layer M1 and the second wiring layer M2 can be connected through at least one first via (e.g., Figure 9 The V1s are connected to each other.

[0037] Reference Figure 1 and Figure 2 The integrated circuit 10 may include a strip active via (VAB) that connects the first wiring layer M1 to an active contact selected from a plurality of active contacts. The strip active via (VAB) may extend along the contacting active contact in the Y-axis direction and may be formed as at least two patterns of contacts that are continuously disposed or arranged in the first wiring layer M1 in the Y-axis direction.

[0038] In one or more embodiments, a strip-shaped active via (VAB) may be disposed on an active contact to contact the pattern P13 of the third trace TR3 and the pattern P14 of the fourth trace TR4. For example, the pattern P13 of the third trace TR3 may be connected to the output pin of a first standard cell included in the integrated circuit 10, and the pattern P14 of the fourth trace TR4 may be connected to the input pin of a second standard cell included in the integrated circuit 10. In this case, the first standard cell and the second standard cell may be standard cells disposed adjacent to each other, or a filler cell may be disposed between the first standard cell and the second standard cell.

[0039] In the comparative example of the integrated circuit without forming a strip active via (VAB), the patterns of the second wiring layer M2 (as an upper layer on the first wiring layer M1) and the third wiring layer M3 (as an upper layer on the second wiring layer M2) may be required to electrically connect the pattern P13 of the third trace TR3 and the pattern P14 of the fourth trace TR4 to each other. Furthermore, a first via for connecting the first wiring layer M1 and the second wiring layer M2 to each other and a second via for connecting the second wiring layer M2 and the third wiring layer M3 to each other may also be required. Therefore, the integrated circuit 10 according to one or more embodiments can transmit signals via a strip active via (VAB) formed in the mid-process (MOL) layer, thus ensuring wiring space for the multiple wiring layers including the first wiring layer M1, the second wiring layer M2, and the third wiring layer M3.

[0040] exist Figure 1 and Figure 2 The diagram only shows a strip-shaped active via (VAB) extending along the active contact, but the integrated circuit 10 may also include a strip-shaped active via (VAB) extending in the X-axis direction along the pattern of the first wiring layer M1 or a strip-shaped active via (VAB) extending in the X-axis direction on the pattern of the first wiring layer M1.

[0041] Integrated circuit 10 may include a first power rail PR1 and a second power rail PR2 for supplying voltage to a semiconductor device. The first power rail PR1 may supply a first power supply voltage (e.g., source voltage VDD) to the semiconductor device, and the second power rail PR2 may supply a second power supply voltage (e.g., ground voltage VSS) to the semiconductor device. In one or more embodiments, the first power rail PR1 and the second power rail PR2 may be formed by a conductive pattern extending in the X-axis direction of the first wiring layer M1, and may be arranged alternately in the Y-axis direction.

[0042] Figure 3 It is a plan view used to describe the layout of an integrated circuit 10a according to one or more embodiments. Figure 4 It is along Figure 3 A cross-sectional view along line Y2-Y2'. (In the description) Figure 3 and Figure 4 At that time, and Figure 1 and Figure 2 Repeated descriptions of the same reference numerals may be omitted.

[0043] Reference Figure 3 and Figure 4The integrated circuit 10a may include a strip-shaped active via (VAB) that connects the first wiring layer M1 to an active contact selected from a plurality of active contacts. The strip-shaped active via (VAB) may extend along the active contact in the Y-axis direction and may be formed to contact at least two patterns that are continuously disposed or arranged in the first wiring layer M1 in the Y-axis direction.

[0044] The source / drain region S / D may be connected (e.g., contacted) to the lower portion of a strip-shaped active via VAB. The source / drain region S / D may include an epitaxially grown semiconductor layer. For example, the source / drain region S / D may include a semiconductor layer epitaxially grown from an active region. The source / drain region S / D may be formed in an embedded SiGe structure comprising an epitaxially grown silicon (Si) layer, an epitaxially grown silicon carbide (SiC) layer, and multiple epitaxially grown silicon germanium (SiGe) layers. A metal silicide layer may be formed on the bottom surface of an active contact on the top surface of each source / drain region S / D.

[0045] Figure 5 It is a plan view used to describe the layout of a standard cell C1 included in an integrated circuit according to one or more embodiments. Figure 6 yes Figure 5 A magnified perspective view of region A. Figure 7 It is along Figure 5 A sectional view along line X1-X1'. (In the description) Figure 5 At that time, and Figure 1 and Figure 2 Repeated descriptions of the same reference numerals may be omitted.

[0046] An integrated circuit configuring a chip or a functional block may include multiple standard cells. A standard cell can be a unit of layout included in the integrated circuit and can be defined by cell boundaries. A standard cell can be designed to perform a predefined function and may be referred to as a cell. The integrated circuit may include multiple standard cells of various types.

[0047] Multiple standard cells can be reused in integrated circuit designs. Standard cells can be designed based on manufacturing technologies and can be stored in cell libraries (e.g., Figure 16 In D10, standard cells stored in the standard cell library D10 can be set up based on design rules and can be connected to each other to design integrated circuits.

[0048] For example, a standard cell may include various basic circuits (such as inverters, AND gates, NAND gates, OR gates, XOR gates, and NOR gates (not limited to these)) that are frequently used in the digital circuit design of electronic devices (such as the design of central processing units (CPUs), graphics processing units (GPUs), and system-on-a-chip (SoCs) (not limited to these)). Optionally or additionally, for example, a standard cell may include other circuits that are frequently used in a circuit block (such as flip-flops and latches).

[0049] Reference Figure 5 and Figure 6 Standard cell C1 can be a standard cell implementing an inverter, and can be one or more embodiments of standard cells included in an integrated circuit containing a "Middle-of-Line (MOL) pattern". Standard cell C1 can be defined by cell boundaries, and a first power rail PR1, a second power rail PR2, and a diffusion break can be formed in the cell boundaries. The diffusion break electrically isolates the active regions of standard cell C1 from those of other standard cells. Figure 5 The diagram illustrates a single diffusion interruption replaced by a gate line, but is not limited to this, and double diffusion interruptions can be formed at cell boundaries. The diffusion interruption may include a silicon-containing insulating layer (such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, or combinations thereof). For example, the diffusion interruption may include fluorinated silicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), or Tonen silazane (TOSZ).

[0050] The standard cell C1 may include a first active region RX1 and a second active region RX2 extending in the X-axis direction. In one or more embodiments, the second active region RX2 may be formed in a substrate SUB doped with P-type impurities, and the first active region RX1 may be formed in an N-well formed in the substrate SUB. The first active region RX1 may be configured with a gate line and a P-type transistor, and the second active region RX2 may be configured with a gate line and an N-type transistor.

[0051] Multiple active contacts extending in the Y-axis direction can be formed on the source / drain region S / D, which is formed in the first active region RX1 and the second active region RX2. Multiple active vias can be disposed on the multiple active contacts, and the active vias can electrically connect the active contacts to the first wiring layer M1. Therefore, the source / drain region S / D can be connected to the first wiring layer M1 through the active contacts and active vias.

[0052] Active vias may include square active vias (VA) and strip active vias (VAB), which connect an active contact to a pattern of the first wiring layer M1. In this case, a strip active via (VAB) can connect an active contact to two or more patterns of the first wiring layer M1, or it can connect two or more active contacts to a pattern of the first wiring layer M1.

[0053] For example, the traces forming the wiring pattern can be defined in the first wiring layer M1, and the strip-shaped active via VAB can be connected to the pattern in two or more adjacent traces among multiple traces (e.g., first trace TR1 to fifth trace TR5) disposed in the first wiring layer M1. Therefore, in order to connect the standard cell C1 to another standard cell that receives the output signal output from the standard cell C1 for operation, wiring can be formed to one of the patterns of the first trace TR1, second trace TR2, fourth trace TR4, and fifth trace TR5 of the standard cell C1, and the degree of freedom in wiring can be increased. Furthermore, the voltage drop characteristics of the wiring between the standard cell C1 and other standard cells can be enhanced.

[0054] The standard cell C1 may include multiple gate lines extending in the Y-axis direction. In one or more embodiments, the gate lines may include a metal-containing work function layer and a gap-filling metal layer. For example, the metal-containing work function layer may include at least one of titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd), and the gap-filling metal layer may include a W layer or an Al layer. In one or more embodiments, the gate lines may include a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN / W stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure.

[0055] A gate contact may be disposed on at least one of a plurality of gate lines, and the gate contact may electrically connect the gate line to the first wiring layer M1. Figure 6 An example of a pattern for forming a gate contact CB to contact the gate line and the first wiring layer M1 has been described, but the disclosure is not limited thereto, and a gate via may also be formed between the gate contact and the first wiring layer M1, so that the gate line and the first wiring layer M1 can be connected to each other through the gate contact and the gate via.

[0056] Reference Figure 5 and Figure 7The nanosheet stack NS can be formed in at least one of the first active region RX1 and the second active region RX2, and the nanosheet stack NS can extend in the Y-axis direction. The device insulating layer 11 can be formed between the substrate SUB and the nanosheet stack NS.

[0057] The nanosheet stack NS can be used as a channel for a transistor. For example, the nanosheet stack NS disposed in the first active region RX1 of the substrate SUB can be doped with N-type impurities and can be configured with a P-type transistor. In one or more embodiments, the nanosheet stack NS may include Si, Ge, or SiGe. In one or more embodiments, the nanosheet stack NS may include InGaAs, InAs, GaSb, InSb, or combinations thereof.

[0058] The nanosheet stack NS may include a plurality of nanosheets NS1 to NS3 stacked on top of each other in a vertical direction (Z-axis direction). In one or more embodiments, the nanosheet stack NS may include three nanosheets, but the disclosure is not limited thereto. For example, the nanosheet stack NS may include at least two nanosheets, and the number of nanosheets is not limited thereto.

[0059] The gate line can simultaneously cover the nanosheet stack NS around each of the multiple nanosheets NS1 to NS3. A multi-bridge channel (MBC) FET with the gate line surrounding the multiple nanosheets can be formed. A gate insulating layer can be disposed between the nanosheet stack NS and the gate line.

[0060] The standard cell C1 included in the integrated circuit according to one or more embodiments is not limited to Figure 7 As shown, a finned FET comprising one or more fins and a gate line formed in a first active region RX1 and a second active region RX2 can be formed, or, for example, a gate-all-around (GAA) FET in which nanowires formed in at least one of the first active regions RX1 and the second active region RX2 are surrounded by a gate line can be formed. A vertical GAA FET in which multiple nanowires are vertically stacked and surrounded by a gate line GL can be formed in at least one of the first active regions RX1 and the second active region RX2. In one example, a nanosheet-like active region surrounded by a gate line GL can be formed. Furthermore, for example, a negative capacitance (NC) FET can be formed in at least one of the first active regions RX1 and the second active region RX2. In addition to the transistors described above, various types of transistors (e.g., complementary FETs (CFETs), negative complementary FETs (NCFETs), carbon nanotube (CNT) FETs, bipolar junction transistors, and other three-dimensional (3D) transistors) can be formed in the standard cell C1.

[0061] Figure 8This is a plan view used to describe the layout of a standard cell C2 included in an integrated circuit according to one or more embodiments. In the description Figure 8 At that time, and Figure 5 Repeated descriptions of the same reference numerals may be omitted.

[0062] Reference Figure 8 The standard cell C2 can be a standard cell that implements an inverter, and can be one or more embodiments of a standard cell included in an integrated circuit according to one or more embodiments. In the standard cell C2, active vias can be disposed on a plurality of active contacts, and the active vias can electrically connect the active contacts to the first wiring layer M1.

[0063] Active vias may include square active vias VA and strip active vias VAB1 or VAB2, which connect an active contact to a pattern of the first wiring layer M1. In this case, strip active vias VAB1 or VAB2 may connect one active contact to two or more patterns of the first wiring layer M1, or two or more active contacts may connect to a pattern of the first wiring layer M1.

[0064] At this point, the strip-shaped active via VAB1 or VAB2 can be formed to contact one of the first power rail PR1 and the second power rail PR2. For example, the first active via VAB1 can electrically connect the first power rail PR1 to the pattern of the first trace TR1 of the first wiring layer M1, and the second active via VAB2 can electrically connect the second power rail PR2 to the pattern of the fifth trace TR5 of the first wiring layer M1. Therefore, the voltage drop (IR drop) characteristic of the first power supply voltage provided by the first power rail PR1 can be improved, and the voltage drop characteristic of the second power supply voltage provided by the second power rail PR2 can be improved. Figure 8 The standard unit C2 may include, but is not limited to, all of the first active via VAB1 and the second active via VAB2, and may include at least one of the first active via VAB1 and the second active via VAB2.

[0065] exist Figure 8 The diagram illustrates strip-shaped active vias VAB1 and VAB2 connected to the first power rail PR1 and the second power rail PR2, respectively, but the disclosure is not limited thereto. Integrated circuits according to one or more embodiments may include... Figure 8 The strip-shaped active vias VAB1 and VAB2 may also include the above-mentioned references. Figure 5 The described pattern of one or more strip active vias (VABs) connected to two or more traces positioned adjacent to each other.

[0066] Figure 9It is a plan view used to describe the layout of a standard cell C3 included in an integrated circuit according to one or more embodiments. Figure 10 yes Figure 9 An enlarged perspective view of region B. (In the description) Figure 9 At that time, and Figure 5 Repeated descriptions of the same reference numerals may be omitted.

[0067] Reference Figure 9 and Figure 10 The standard cell C3 may be a standard cell for implementing an inverter, and may be one or more embodiments of a standard cell included in an integrated circuit including a bar-shaped MOL pattern. The standard cell C3 may include multiple gate lines (e.g., first gate line to fourth gate line) GL1 to GL4 extending in the Y-axis direction.

[0068] Gate contacts may be disposed on each of the multiple gate lines GL1 to GL4, and the gate contacts may electrically connect the gate lines to the first wiring layer M1. Standard cell C3 may include a strip-shaped gate contact CBB. In this case, the strip-shaped gate contact CBB may extend along the gate line in the Y-axis direction and may connect the gate line to two or more patterns of the first wiring layer M1, or it may extend along the pattern of the first wiring layer M1 in the X-axis direction and may connect two or more gate lines to one pattern of the first wiring layer M1.

[0069] The traces forming the wiring pattern can be defined in the first wiring layer M1, and the strip gate contact CBB can be connected to the pattern in two or more adjacent traces of multiple traces (e.g., the first trace TR1 to the fifth trace TR5) disposed in the first wiring layer M1. For example, the strip gate contact CBB can be connected to the pattern M12 to M14 of the second trace TR2 to the fourth trace TR4.

[0070] In one or more embodiments, a strip gate contact CBB may be disposed on each of the plurality of gate lines GL1 to GL4 included in the standard cell C3. In one or more embodiments, each of the plurality of gate lines GL1 to GL4 may be connected to the same pattern (e.g., M12, M13, and M14) of the first wiring layer M1 through the strip gate contact CBB formed thereon. For example, the same input signal may be input to the plurality of gate lines GL1 to GL4, and the plurality of gate lines GL1 to GL4 may receive the input signal through the pattern M12 to M14 of the second trace TR2 to the fourth trace TR4 connected thereto.

[0071] Therefore, in order to connect standard cell C3 to another standard cell that outputs the "input signal input to standard cell C3", wiring can be formed in one of the patterns M12 to M14 connected to the second trace TR2 to the fourth trace TR4 of standard cell C3, and the degree of freedom of wiring can be increased. Furthermore, the voltage drop characteristics of the wiring between standard cell C3 and other standard cells can be enhanced. Figure 9 The diagram shows a bar-shaped gate contact CBB formed on each of the first gate line GL1 to the fourth gate line GL4, which are all gate lines included in the standard cell C3. However, the disclosure is not limited to this, and the bar-shaped gate contact CBB may be formed on only a portion of the multiple gate lines GL1 to GL4 included in the standard cell C3.

[0072] exist Figure 9 The diagram only shows the bar-type gate contact CBB, but is not limited thereto, and the integrated circuit according to one or more embodiments may also include... Figure 5 strip-shaped active via VAB and Figure 8 At least one of the strip-shaped active vias VAB1 or VAB2.

[0073] Figure 11 This is a block diagram of a memory device 100 according to one or more embodiments.

[0074] Reference Figure 11 The integrated circuit according to one or more embodiments may be a memory device 100. The memory device 100 may be a static random access memory (RAM) (SRAM), dynamic RAM (DRAM), mobile DRAM, flash memory, electrically erasable programmable read-only memory (EEPROM), resistive RAM (PRAM), phase-change RAM (RRAM), or ferroelectric RAM (FRAM), but is not limited thereto. Hereinafter, for ease of description, the memory device 100 will be described based on SRAM.

[0075] The memory device 100 can receive commands, addresses, clock signals, and data, and can output data. For example, the memory device 100 can receive a command instructing writing, an address, and data as write data, and can store the data in the address-corresponding area of ​​the memory cell block 20. Furthermore, the memory device 100 can receive an address and a read command, and can output the read data stored in the address-corresponding area of ​​the memory cell block 20 as data to the outside of the memory device 100.

[0076] The memory device 100 may include a memory cell block 20 and peripheral circuitry. The memory cell block 20 may include a plurality of bit cells (e.g., ...). Figure 12(21). Multiple bit cells 21 can be arranged at intervals in multiple memory columns and multiple memory rows. Multiple bit cells 21 can be located at the points where multiple word lines WL and multiple bit lines BL intersect. That is, each of the multiple bit cells 21 can be connected to at least one of the multiple word lines WL and can be connected to at least one of the multiple bit lines BL.

[0077] Each of the plurality of bit cells 21 may be a memory cell. For example, each of the plurality of bit cells 21 may be an SRAM cell, or, for example, a volatile memory cell (such as DRAM). In one or more embodiments, each of the plurality of bit cells 21 may be a non-volatile memory cell (such as flash memory or resistive RAM (RRAM)). In embodiments, examples in which each of the plurality of bit cells 21 is an SRAM cell may be described primarily, but embodiments are not limited thereto.

[0078] The peripheral circuitry can receive address, command, and clock signals from outside the memory device 100, and can transmit data to or receive data from devices outside the memory device 100. The peripheral circuitry may include row driver 31, column driver 33, and control block 35. The peripheral circuitry can write data to or read data from memory cell block 20.

[0079] The row driver 31 can be connected to the memory cell block 20 via multiple word lines WL. The row driver 31 can activate at least one of the multiple word lines WL based on the row address ADDR_R. For example, the row driver 31 can select at least one word line WL from the multiple word lines WL. Therefore, bit cells connected to the activated word line can be selected from a plurality of bit cells 21.

[0080] The column driver 33 can be connected to the memory cell block 20 via multiple bit lines BL. The column driver 33 can select at least one bit line from the multiple bit lines BL based on the column address ADDR_C. The bit line BL and the complementary bit line BLB can be connected to at least one of the multiple bit cells 21, so when the column driver 33 selects the bit line BL and the complementary bit line BLB, the bit cell 21 connected to the bit line BL and the complementary bit line BLB can be selected.

[0081] The column driver 33 can perform read or write operations based on the control signal CTRL. The column driver 33 may include a read driver for performing read operations and a write driver for performing write operations.

[0082] The read driver can sense the current and / or voltage received through multiple bit lines BL, and thus can identify the values ​​stored in the bit cells connected to the active word lines among the multiple bit cells 21, and can output data based on the identified values. The write driver can apply current and / or voltage to the multiple bit lines BL based on data received from outside the memory device 100, and can write values ​​into the bit cells connected to the active word lines among the multiple bit cells 21.

[0083] Control block 35 can receive commands, addresses, and clock signals to generate row address ADDR_R, column address ADDR_C, and control signal CTRL. For example, control block 35 can decode commands to identify read commands and generate row address ADDR_R, column address ADDR_C, and control signal CTRL to read data from memory cell block 20. Furthermore, control block 35 can decode commands to identify write commands and generate row address ADDR_R, column address ADDR_C, and control signal CTRL to write data into memory cell block 20.

[0084] In a memory device 100 that is an integrated circuit according to one or more embodiments, a control block 35 can provide a control signal CTRL and a column address ADDR_C to a column driver 33, and can provide a row address ADDR_R to a row driver 31. Therefore, multiple signal lines for providing signals output from the control block 35 may be required. Consequently, it may be necessary to ensure wiring space for transmitting the control signal CTRL in multiple wiring layers and improve voltage drop characteristics.

[0085] In the memory device 100 according to one or more embodiments, in the peripheral circuitry, such as row driver 31, column driver 33, and control block 35, Figure 1 , Figure 3 and Figure 5 Strip-shaped active via VAB, Figure 8 The strip-shaped active via VAB1 or VAB2, or Figure 9 A bar-type gate contact (CBB) can be provided, thus ensuring wiring space in the wiring layer and improving the voltage drop characteristics of signals input to / output from the semiconductor device or power supply voltage supplied to the semiconductor device.

[0086] Figure 12 This is a circuit diagram used to describe bit cell 21 of an integrated circuit according to one or more embodiments.

[0087] Reference Figure 12 Bit cell 21 can be an SRAM unit cell. Bit cell 21 may include a first inverter INV1, a second inverter INV2, a first transmission element PG1, and a second transmission element PG2.

[0088] The first inverter INV1 and the second inverter INV2 can output data with opposite phases. Specifically, the first inverter INV1 may include a first pull-up element PU1 and a first pull-down element PD1. The first pull-up element PU1 may be a PMOS transistor, and the first pull-down element PD1 may be an NMOS transistor, but the disclosure is not limited thereto.

[0089] The second inverter INV2 may include a second pull-up element PU2 and a second pull-down element PD2. The second pull-up element PU2 may be a PMOS transistor, and the second pull-down element PD2 may be an NMOS transistor, but the disclosure is not limited thereto.

[0090] The sources of the first pull-down element PD1 and the second pull-down element PD2 can be connected to a first voltage (e.g., ground voltage), and the sources of the first pull-up element PU1 and the second pull-up element PU2 can be connected to a second voltage higher than the first voltage (e.g., source voltage VDD). The drains of the first pull-up element PU1 and the first pull-down element PD1 can be connected to a first node N1, and the drains of the second pull-up element PU2 and the second pull-down element PD2 can be connected to a second node N2. Furthermore, the input of the first inverter INV1 can be connected to the second node N2, which serves as the output node of the second inverter INV2, and the input of the second inverter INV2 can be connected to the first node N1, which serves as the output node of the first inverter INV1.

[0091] The gate of the first transmission element PG1 can be connected to the word line WL, the drain of the first transmission element PG1 can be connected to the bit line BL, and the source of the first transmission element PG1 can be connected to the first node N1. The gate of the second transmission element PG2 can be connected to the word line WL, the drain of the second transmission element PG2 can be connected to the complementary bit line BLB, and the source of the second transmission element PG2 can be connected to the second node N2. Here, the inverted signal of the signal on the bit line BL can be applied to the complementary bit line BLB.

[0092] Bit unit 21 can operate as follows. When the potential of word line WL is logic high, the first transmission element PG1 and the second transmission element PG2 can be turned on, and the signals of bit line BL and complementary bit line BLB can be transmitted to the first inverter INV1 and the second inverter INV2 respectively. Therefore, the operation of writing or reading data can be performed.

[0093] Figure 13 This is a plan view illustrating the layout of a portion of a control block 35 of a memory device 100 according to one or more embodiments. Figure 13 In, for example, control block 35 can be described, and Figure 13The description can be similarly applied to other components of the peripheral circuitry of the memory device 100.

[0094] Reference Figure 13 The control block 35 of the memory device 100 may include a plurality of active regions and a plurality of gate lines. The plurality of active regions are formed on a substrate and extend in the X-axis direction, and the plurality of gate lines are formed and extend in the Y-axis direction. A plurality of active contacts may be formed to contact the source / drain regions formed in the plurality of active regions, and active vias may be formed on each of the plurality of active contacts.

[0095] Furthermore, multiple wiring layers forming wiring for connecting semiconductor devices to each other can be formed as stacked in the control block 35 of the memory device 100. Figure 13 The first routing layer M1 shown can be the layer closest to the substrate (i.e., the bottommost layer) among multiple routing layers.

[0096] Multiple traces for setting the pattern can be defined in a first wiring layer M1 based on design rules. These traces in the first wiring layer M1 can extend in the X-axis direction and can be separated from each other in the Y-axis direction. Furthermore, the multiple traces for setting the pattern can be defined in a second wiring layer M2 disposed on the first wiring layer M1. The second wiring layer M2 can be a wiring layer disposed on the first wiring layer M1, and can be a wiring layer that is the second lowest wiring layer among multiple wiring layers. The multiple traces in the second wiring layer M2 can extend in the Y-axis direction and can be separated from each other in the X-axis direction. The first wiring layer M1 and the second wiring layer M2 can be connected to each other through at least one first via.

[0097] A power rail PR providing the power supply voltage VDDP used in the control block 35 and a power line PL providing the external power supply voltage VDDPE from the outside to the control block 35 can be formed in the control block 35. For example, the power rail PR and the power line PL can be formed as a pattern of the first wiring layer M1.

[0098] Furthermore, a strip-shaped active via VAB' extending in the Y-axis direction can be formed in the control block 35. For example, a power line PL providing an external power supply voltage VDDPE can be formed as a pattern of the first wiring layer M1, and the strip-shaped active via VAB' can connect the power line PL to a pattern M1P of the first wiring layer M1 adjacent to the power line PL. The pattern M1P of the first wiring layer M1 can be additionally operated as the power line PL through the strip-shaped active via VAB', and the voltage drop characteristics of the power line PL can be improved. Figure 13 The diagram only shows a strip-shaped active via VAB' connected to the power line PL to transmit voltage, but the disclosure is not limited thereto. As stated above... Figure 5As described in the standard unit C1, the control block 35 can be configured to connect active contacts to multiple patterns for transmitting signals formed in different traces of the first wiring layer M1.

[0099] Gate contacts for connecting gate lines to the first wiring layer M1 can be formed on each of the plurality of gate lines. Figure 13 The image only shows a square gate contact pattern for connecting a gate line to the first wiring layer M1, but the disclosure is not limited thereto. As described above... Figure 9 As described in the standard unit C3, the control block 35 may include a strip gate contact that connects a gate line to a plurality of patterns of the first wiring layer M1, and furthermore, the control block 35 may include a strip gate contact that connects a plurality of gate lines to a pattern of the first wiring layer M1.

[0100] Figure 14A and Figure 14B This is a plan view used to describe a portion of the row driver 31 of a memory device 100 according to one or more embodiments. Figure 14A and Figure 14B In, for example, line driver 31 can be described, and Figure 14A and Figure 14B The description can be similarly applied to other components of the peripheral circuitry of the memory device 100.

[0101] Reference Figure 14A The row driver 31 of the memory device 100 may include a plurality of active regions and a plurality of gate lines. The plurality of active regions are formed on a substrate and extend in the X-axis direction, and the plurality of gate lines are formed and extend in the Y-axis direction. A plurality of active contacts may be formed to contact the source / drain regions formed in the plurality of active regions, and active vias may be formed on each of the plurality of active contacts.

[0102] Furthermore, multiple wiring layers having wiring for connecting semiconductor devices to each other can be formed and stacked in the row driver 31 of the memory device 100. Figure 14A The first routing layer M1 shown can be the layer closest to the substrate (i.e., the bottommost layer) among multiple routing layers.

[0103] A pattern extending in the X-axis direction may be formed in the first wiring layer M1 based on design rules, or a pattern extending in the Y-axis direction may be formed in the second wiring layer M2 disposed on the first wiring layer M1 based on design rules. The first wiring layer M1 and the second wiring layer M2 may be connected to each other through at least one first via V1.

[0104] A power rail PR that provides the power supply voltage VDDWL used in the row driver 31 may be formed in the row driver 31. For example, the power rail PR may be formed as a pattern of the first wiring layer M1.

[0105] A strip-shaped active via (VAB) extending in the Y-axis direction can be formed in the row driver 31. For example, the power rail PR can be formed as a pattern of the first wiring layer M1, and the strip-shaped active via (VAB) can connect multiple patterns of the first wiring layers M1 arranged continuously in the Y-axis direction, including the power rail PR (e.g., first pattern M1P1 and second pattern M1P2). Therefore, the width of the power rail PR can be significantly increased, and thus the strip-shaped active via (VAB) can be provided to improve the voltage drop characteristics of the power rail PR.

[0106] exist Figure 14A The diagram only shows a strip-shaped active via VAB'' connected to the power rail PR to transmit voltage, but the disclosure is not limited thereto. As described above... Figure 5 As described in the standard unit C1, the line driver 31 can be configured to connect active contacts to multiple patterns for transmitting signals formed in different traces of the first wiring layer M1.

[0107] Reference Figure 14B A strip-shaped gate contact CBB' extending in the X-axis direction can be formed in the row driver 31. For example, the strip-shaped gate contact CBB' can be formed to connect multiple gate lines GL1 and GL2 arranged continuously in the X-axis direction to each other. That is, the strip-shaped gate contact CBB' can extend along the pattern of the first wiring layer M1. Therefore, multiple gate lines GL1 and GL2 can be connected to a pattern of the first wiring layer M1 through the strip-shaped gate contact CBB', and thus the voltage drop characteristics of the first wiring layer M1 connected to the multiple gate lines GL1 and GL2 can be improved.

[0108] exist Figure 14B The diagram only shows a strip-shaped gate contact CBB' of a pattern extending in the X-axis direction and connecting multiple gate lines GL1 and GL2 to the first wiring layer M1, but the disclosure is not limited thereto. As described above... Figure 9 As described in the standard unit C3, the row driver 31 may include strip gate contacts of multiple patterns that connect a gate line to the first wiring layer M1.

[0109] Figure 14A The text shows a strip-shaped active via VAB'', and... Figure 14B The diagram shows a bar-shaped gate contact CBB', but according to one or more embodiments, both the bar-shaped active via VAB'' and the bar-shaped gate contact CBB' can be formed in the peripheral circuitry of the memory device 100.

[0110] Figure 15 This is a block diagram illustrating a system-on-chip (SoC) 110 according to one or more embodiments.

[0111] According to one or more embodiments, SoC 110 may be a semiconductor device and may include at least one of the aforementioned integrated circuits. In SoC 110, complex blocks performing various functions (such as intellectual property (IP)) may be implemented in a single chip, and according to embodiments, SoC 110 may efficiently provide a variety of channel lengths and may have high efficiency and reliability.

[0112] Reference Figure 15 The SoC 110 may include a modem 112, a display controller 113, a memory 114, an external memory controller 115, a central processing unit (CPU) 116, a transaction unit 117, a power management integrated circuit (PMIC) 118, and a graphics processing unit (GPU) 119, and the functional blocks of the SoC 110 can communicate with each other via a system bus 111.

[0113] The CPU 116, located at the top layer and used to control the operation of SoC 110, can control the operation of other functional blocks 112 to 119. Modem 112 can demodulate signals received from outside SoC 110, or modulate signals generated within SoC 110 to transmit modulated signals externally. External memory controller 115 can control the sending of data to or receiving of data from external memory devices connected to SoC 110. For example, programs and / or data stored in external memory devices can be provided to CPU 116 or GPU 119 based on the control of external memory controller 115. GPU 119 can execute program instructions associated with graphics processing. GPU 119 can receive graphics data through external memory controller 115, or send graphics data obtained through processing by GPU 119 to the outside of SoC 110 through external memory controller 115. Transaction unit 117 can monitor data transactions of functional blocks, and PMIC 118 can control the power supplied to functional blocks based on the control of transaction unit 117. Display controller 113 can control a display (or display device) external to SoC 110, and thus can send data generated in SoC 110 to the display. Memory 114 may include non-volatile memory such as EEPROM or flash memory, or may include volatile memory such as DRAM or SRAM.

[0114] Figure 16 This is a flowchart illustrating a method for manufacturing an integrated circuit according to one or more embodiments.

[0115] Reference Figure 16 The standard cell library D10 may include information about standard cells (e.g., functional information, characteristic information, and layout information). The standard cell library D10 may include data defining the layout of the standard cells. For example, the data may include definitions of the above references. Figure 5 , Figure 8 and Figure 9 The data describes the structure of each of the standard cells C1, C2, and C3, and furthermore, the data may include data defining the structure of each of the standard cells, including strip active vias or strip gate contacts.

[0116] Operations S10 and S20 can be operations for designing an integrated circuit (IC) and can generate layout data D30 from register transfer level (RTL) data D11. In operation S10, a logic synthesis operation can be performed to generate netlist data D20 from the RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis module) can perform logic synthesis based on the RTL data D11 written in a hardware description language (HDL) (such as Verilog and VHSIC hardware description language (VHDL)) with reference to a standard cell library D10, and thus generate netlist data D20 including bitstreams or netlists. The standard cell library D10 can perform the same function and can include data defining the structure of each of the standard cells with different layouts; furthermore, with reference to the standard cell library D10, standard cells can be included in the integrated circuit (IC).

[0117] In operation S20, a layout and routing (P&R) operation can be performed to generate layout data D30 from netlist data D20. Layout data D30 may have a format such as GDSII, and furthermore, layout data D30 may include geometric information about interconnects and standard cells.

[0118] For example, a semiconductor design tool (e.g., a P&R module) can place multiple standard cells based on netlist data D20 and a standard cell library D10. The semiconductor design tool can select a layout defined by netlist data D20 from the standard cell layouts and can place the selected standard cell layout.

[0119] In operation S20, wiring operations for generating interconnects can also be performed. Interconnects can electrically connect the output and input pins of standard cells to other standard cells, and for example, interconnects may include multiple vias and conductive wiring formed in at least one wiring layer. In one or more embodiments, referring to the above... Figure 5 , Figure 8 and Figure 9 The wiring lines and vias formed when each of the described standard cells C1, C2 and C3 is connected to another standard cell can be generated.

[0120] The integrated circuit design operations, including S10 and S20, can be performed by a computing system used to design integrated circuits, including processors and memory. For example, a synthesis program for performing operation S10 and a P&R program for performing operation S20 can be loaded into the memory of the computing system, and the processor can execute the program, thereby performing the operations to design the integrated circuit.

[0121] In operation S30, optical proximity correction (OPC) can be performed. OPC can correct distortions such as refraction caused by the properties of light during photolithography in the semiconductor process of manufacturing integrated circuit ICs. Therefore, OPC can be referred to as an operation to form a pattern with a desired shape, and the pattern of the mask can be determined by applying OPC to the layout data D30. In one or more embodiments, the layout of the integrated circuit IC can be modified restrictively in operation S30, and the operation of modifying the integrated circuit IC restrictively in operation S30 can be a post-processing for optimizing the structure of the integrated circuit IC, and can be referred to as design modification.

[0122] In operation S40, the operation of manufacturing a mask can be performed. For example, when OPC is applied to layout data D30, the pattern of the mask can be defined to form a pattern formed in multiple layers, and at least one mask (or photomask) can be manufactured to form a pattern in each of the multiple layers.

[0123] In operation S50, operations for manufacturing an integrated circuit (IC) can be performed. For example, multiple layers can be patterned using at least one mask manufactured in operation S40, and thus, an integrated circuit (IC) can be manufactured. Operation S50 may include operations S51, S53, and S55.

[0124] In operation S51, a front-end process (FEOL) can be performed. FEOL can refer to the process of forming various components (e.g., transistors, capacitors, and resistors) in a substrate during the manufacturing process of an integrated circuit (IC). For example, the FEOL process may include operations such as wafer planarization and cleaning, trench formation, well formation, gate line formation, and source and drain regions formation.

[0125] In operation S53, a mid-stage process (MOL) can be performed. MOL can refer to a process for forming interconnecting components used to connect various elements generated by the FEOL process to each other in a standard cell. For example, the MOL process may include operations for forming active contacts in an active region, operations for forming gate contacts on gate lines, and operations for forming active vias on the active contacts. Specifically, the MOL process may include forming the aforementioned... Figures 1 to 14BThe operation of the strip gate contact CBB or CBB' or the strip active via VAB, VAB1, VAB2, VAB' or VAB'' is described. The layer on which the device is set by the MOL process can be defined as the MOL layer.

[0126] In operation S55, back-end process (BEOL) technology can be performed. BEOL can refer to the process of connecting various components (e.g., transistors, capacitors, and resistors) to each other in the manufacturing process of an integrated circuit (IC). For example, the BEOL process may include operations such as siliconizing the source and drain regions, adding dielectrics, performing planarization, forming vias, forming multiple wiring layers, forming multiple vias between the wiring layers, and forming a passivation layer. Subsequently, the integrated circuit IC can be packaged in a semiconductor package and used as a component for various applications.

[0127] Exemplary embodiments have been described above in the accompanying drawings and specification. Embodiments have been described using the terminology described herein, but this is for descriptive purposes only and not for limiting the meaning or scope of the disclosure as defined in the following claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments may be implemented from the disclosure. Accordingly, the spirit and scope of the disclosure are to be defined based on the spirit and scope of the following claims.

[0128] In the above embodiments, an active via that connects one active contact to at least two patterns or at least two active contacts to one pattern is called a strip active via. Similarly, in the above embodiments, a gate contact that connects one gate line to at least two patterns or at least two gate lines to one pattern is called a strip gate contact. However, according to one or more embodiments, the shape or form of the active via and gate contact may not be limited to strip, but may have different shapes or forms for the same connection purpose (e.g., a horizontally extending form). Furthermore, in order to contact at least two patterns, at least two active contacts, or at least two gate lines, a strip active via or a strip gate contact may be stacked vertically with at least two patterns, at least two active contacts, or at least two gate lines.

[0129] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

Claims

1. An integrated circuit, comprising: The first wiring layer includes multiple patterns, each extending in a first horizontal direction; Active contact element; as well as An active via connects an active contact to at least two of the plurality of patterns and extends along the active contact.

2. The integrated circuit as claimed in claim 1, wherein, The integrated circuit includes a first standard unit and a second standard unit. Multiple traces extending in a first horizontal direction and arranged in a second horizontal direction are in a first wiring layer, wherein the second horizontal direction intersects the first horizontal direction. The active vias respectively contact at least two patterns on at least two of the plurality of traces, and One of the at least two patterns is connected to the output pin of the first standard unit, and the other of the at least two patterns is connected to the input pin of the second standard unit.

3. The integrated circuit as described in claim 1, further comprising: The source / drain region is connected to the bottom of the active via.

4. The integrated circuit as claimed in claim 1, wherein, The first wiring layer includes: The first power rail is configured to provide a first power supply voltage; and The second power rail is configured to provide a second power supply voltage, and The active via is connected to one of the first power rail and the second power rail.

5. The integrated circuit of claim 1, further comprising: Gate lines extend in a second horizontal direction, which intersects with the first horizontal direction; as well as The nanosheet-shaped active region is surrounded by gate lines.

6. The integrated circuit of claim 5, further comprising: Gate contact, connecting the first wiring layer and the gate line.

7. The integrated circuit according to any one of claims 1 to 6, further comprising: A second wiring layer is disposed on the first wiring layer and includes at least one pattern extending in a second horizontal direction, which intersects the first horizontal direction. as well as The via layer connects the first wiring layer and the second wiring layer.

8. The integrated circuit according to any one of claims 1 to 6, wherein, The integrated circuit includes: Memory cell blocks; and The peripheral circuitry is configured to input data into or output data from memory cell blocks, and The integrated circuit is a static random access memory.

9. The integrated circuit as claimed in claim 8, wherein, Active vias are formed in the peripheral circuit.

10. An integrated circuit, comprising: Wiring layer, comprising multiple patterns, each extending in a first horizontal direction; The first gate line and the second gate line each extend in a second horizontal direction, and the second horizontal direction intersects with the first horizontal direction; as well as A first gate contact connects a first gate line to at least two of the plurality of patterns, or connects a first gate line, a second gate line, and a pattern of the plurality of patterns.

11. The integrated circuit of claim 10, wherein, The first gate contact is a strip-shaped gate contact that extends along the first gate line to overlap with the at least two patterns in the vertical direction.

12. The integrated circuit of claim 11, comprising: The second gate contact connects the second gate line to at least two of the plurality of patterns.

13. The integrated circuit of claim 10, further comprising: in, The first gate contact is a strip-shaped gate contact extending in a first horizontal direction and connecting the first gate line and the second gate line.

14. The integrated circuit of claim 10, further comprising: An active contact extends in the second horizontal direction; as well as An active via extends along an active contact in a second horizontal direction and connects the active contact to the at least two patterns or at least two other patterns in the wiring layer.

15. The integrated circuit according to any one of claims 10 to 14, wherein, The integrated circuit includes: Memory cell blocks; and The peripheral circuitry is configured to input data into or output data from memory cells. Wherein, the integrated circuit is a static random access memory, and The first gate contact is formed in the peripheral circuit.

16. An integrated circuit, comprising: Wiring layer, comprising multiple patterns, each extending in a first horizontal direction; Active contact element; as well as Active vias connect active contacts to the wiring layer. The active via overlaps with the first and second patterns among the plurality of patterns in the vertical direction and extends along the active contact.

17. The integrated circuit of claim 16, further comprising: Gate lines extend in a second horizontal direction, which intersects with the first horizontal direction; as well as Gate contacts connect the gate line and the wiring layer. The gate contact is stacked vertically with the third and fourth patterns among the plurality of patterns in the wiring layer.

18. The integrated circuit of claim 17, wherein, The gate contact is disposed on the gate line and extends along the gate line.

19. The integrated circuit of claim 16, wherein, A first pattern is included in a first trace, and a second pattern is included in a second trace. The first and second traces each extend in a first horizontal direction and are arranged spaced apart from each other in the second horizontal direction in a wiring layer. The first and second traces are configured to transmit signals. An active via connects the first pattern of the first trace and the second pattern of the second trace.

20. The integrated circuit of claim 19, wherein, The wiring layer includes power rails configured to provide power supply voltage, and One of the first and second patterns is a power rail.

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