Semiconductor device and method of manufacturing the same, electronic device

Abstract

This application provides a semiconductor device and its fabrication method, and an electronic device. The semiconductor device includes: a first interconnect layer, at least one memory cell, and a second interconnect layer stacked sequentially along a first direction; each memory cell includes a plurality of first transistors connected to the first interconnect layer and a plurality of second transistors connected to the second interconnect layer. The memory cell further includes: a first connection structure and a second connection structure, wherein the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple two inverters in the memory cell; the second connection structure penetrates the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of a third transistor to the second interconnect layer, wherein the third transistor is a first transistor in the first semiconductor structure that does not constitute an inverter.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With Moore's Law continuously evolving, and following the Gate-All-Around (GAA) technology node, further miniaturizing transistors is a hot research topic in the industry. Stacked FETs, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. They are considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] Currently, miniaturizing static random access memory (SRAM) based on planar transistors is extremely difficult. Stacked transistor designs, especially complementary field-effect transistors (CFETs), have become a feasible path to maintain the integration density of SRAM cells. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method, as well as an electronic device, which can achieve further integration by reducing the area of ​​SRAM cells.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a semiconductor device, including: a first interconnect layer, at least one memory cell, and a second interconnect layer stacked sequentially along a first direction; each memory cell includes a first semiconductor structure, a first isolation layer, and a second semiconductor structure arranged sequentially along the first direction; wherein the first semiconductor structure includes two first standard cells arranged along a second direction, each first standard cell including two first transistors arranged along a third direction and the two first transistors sharing a drain structure; the second semiconductor structure includes two second transistors; the two second transistors are respectively stacked with a first transistor in a different first standard cell along the first direction, and the two second transistors are staggered along the second direction; the first direction is perpendicular to... In the second direction, the third direction is perpendicular to the first and second directions; all first transistors in the first semiconductor structure are electrically connected to the first interconnect layer, and all second transistors in the second semiconductor structure are electrically connected to the second interconnect layer; the memory cell further includes: a first connection structure and a second connection structure, wherein the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple two inverters in the memory cell; the second connection structure at least penetrates the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of the third transistor to the second interconnect layer, wherein the third transistor is a first transistor in the first semiconductor structure that does not constitute an inverter.

[0007] This application provides a method for fabricating a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a plurality of fin structures, each fin structure including a first part, a second part and a third part, the second part being used to isolate the first part and the third part; depositing an oxide material on the substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the second part and the third part, and the first part is exposed outside the shallow trench isolation structure; forming a first semiconductor structure based on the first part, wherein the first semiconductor structure includes two first standard cells arranged along a second direction, each first standard cell including two first transistors arranged along a third direction and the two first transistors sharing a drain structure; forming a first interconnect layer above the first semiconductor structure, wherein all the first transistors in the first semiconductor structure are electrically connected to the first interconnect layer; bonding and flipping the first interconnect layer to a carrier wafer; removing the substrate and thinning the shallow trench isolation structure to expose the third part, wherein the thinned shallow trench isolation structure encloses the second part, and the thinned shallow trench isolation structure and the second part together constitute the first isolation layer; A second semiconductor structure is formed in the third part of the fin-like structure, wherein the first semiconductor structure and the second semiconductor structure are stacked along a first direction; the second first direction is perpendicular to the second direction, and the third third direction is perpendicular to both the first and second directions; the second semiconductor structure includes two transistors; the two transistors are stacked along the first direction with a first transistor in a different first standard cell, and the two transistors are staggered along the second direction; the first semiconductor structure, the first isolation layer, and the second semiconductor structure constitute a memory cell; a second interconnect layer is formed above the second semiconductor structure, wherein all transistors in the second semiconductor structure are electrically connected to the second interconnect layer; wherein the fabrication method further includes: forming a first connection structure and a second connection structure in the memory cell; the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple the two inverters in the memory cell; the second connection structure penetrates the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of a third transistor to the second interconnect layer, wherein the third transistor is a first transistor in the first semiconductor structure that does not constitute an inverter.

[0008] This application provides an electronic device, including: a circuit board and the aforementioned semiconductor device.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, at least one memory cell has a first interconnect layer and a second interconnect layer disposed on its front and back sides along the vertical direction, respectively. All front-side transistors (i.e., the first transistors) within the memory cell are interconnected with the first interconnect layer, and all back-side transistors (i.e., the second transistors) are interconnected with the first interconnect layer. Within each memory cell, two complementary transistor layers are interleaved into two pairs of inverters via a first connection structure. A second connection structure penetrates the film layer, connecting the source transistors in the front-side transistors that are not involved in the inverters to the second interconnect layer. This folds the traditional planar SRAM cell into a three-dimensional stacked SRAM cell, reducing the cell area of ​​the SRAM cell. Furthermore, the two front-side transistors arranged along the third direction share a common drain structure, with only the non-shared source structure led out to the second interconnect layer on the back side, thereby reducing the metal line length and lowering the voltage drop.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is an equivalent circuit diagram of a semiconductor device according to an exemplary embodiment.

[0014] Figure 2 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 1 .

[0015] Figure 3 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 2 .

[0016] Figure 4 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 3 .

[0017] Figure 5 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 4 .

[0018] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 1 .

[0019] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 2 .

[0020] Figure 8 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 3 .

[0021] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 4 .

[0022] Figures 10 to 19 This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an exemplary embodiment.

[0023] The reference numerals and names in the figure are as follows:

[0024] M1, First pull-down transistor; M2, First pull-up transistor; M3, Second pull-down transistor; M4, Second pull-up transistor; M5, First transmission gate transistor; M6, First transmission gate transistor; QB, First memory node; Q, Second memory node; WL, Word line; BL, Bit line; BLB, Inverted phase line; VDD, Positive power supply line; VSS, Ground line;

[0025] 1. First interconnect layer; 2. Memory cell; 3. Second interconnect layer; 21. First semiconductor structure; 22. First isolation layer; 23. Second semiconductor structure; 24. Metal gate structure; 25. Dielectric structure; 26. Source / drain metal; 27. First dielectric wall; 28. Second dielectric wall; 29. ​​Second part of fin structure; 30. Third part of fin structure; 31. Substrate; 32. Shallow trench isolation structure; 33. Pseudo-gate structure; 34. Source / drain structure; 35. Dielectric layer; 36. Carrier wafer; 37. First part of fin structure; 41. Gate via; 42. Source / drain via; 51. Through-layer via structure; 52. Source / drain contact metal; 53. Cross-coupling structure; 54. Second connection structure. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] As technology nodes enter the sub-nanometer era in the future, it will be very difficult to miniaturize SRAM based on planar transistors. Stacked transistor designs based on CFETs can achieve an area scaling of nearly 50% through three-dimensional stacking.

[0030] However, existing stacked transistor designs typically employ a combination of a back-side power delivery network (BSPDN) and front-side signal lines. This impacts the connectivity within the SRAM cells, as well as the integrity of signal and / or power line connections. Furthermore, the layout of the front-side signal lines tends to be crowded, hindering further scaling of the SRAM cells.

[0031] To address the aforementioned technical problems, embodiments of this application provide a semiconductor device and its fabrication method, as well as an electronic device, which can achieve further integration by reducing the area of ​​SRAM cells.

[0032] In a first aspect, embodiments of this application provide a semiconductor device. Figure 1 This is a schematic diagram of the equivalent circuit of a semiconductor device according to an exemplary embodiment. See also... Figure 1As shown, the semiconductor device can be an SRAM cell with six transistors. This SRAM cell includes a first inverter, a second inverter, and a pair of transmission gate transistors. The first inverter consists of a first pull-down (PD) transistor (denoted as M1) and a first pull-up (PU) transistor (denoted as M2), sharing the same gate node and forming a first memory node QB. The second inverter consists of a second pull-down transistor (denoted as M3) and a second pull-up transistor (denoted as M4), sharing the same gate node and forming a second memory node Q. The gates of the first and second inverters are cross-coupled to form a latch. The pair of transmission gate transistors includes a first transmission gate (PG) transistor (denoted as M5) and a second transmission gate transistor (denoted as M6). Transistors M5 and M6 are located outside the first and second inverters, respectively. The gate of transistor M5 is connected to the word line WL, and one end of its source or drain is connected to the anti-phase line BLB, while the other end is connected to the first memory node QB. The gate of transistor M6 is connected to the word line WL, and one end of its source or drain is connected to the bit line BL, while the other end is connected to the second memory node Q. Meanwhile, the sources of transistors M1 and M3 are connected to the ground line VSS, and the sources of transistors M2 and M4 are connected to the positive power supply line VDD.

[0033] Figure 2 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 1 . Figure 3 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 2 . Figure 4 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 3 . Figure 5 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 4 Wherein, AA' is a cross-section of the semiconductor device along the length direction of the source region (layout Y direction); BB' is a cross-section of the semiconductor device along the length direction of the gate region (layout Y direction); CC' is a cross-section of the semiconductor device along the length direction of the drain region (layout Y direction); DD' is a cross-section of the semiconductor device along the channel direction (layout Y direction). Figure X (Direction) of the cross section.

[0034] Figures 2 to 5Image (a) shows a front view of the layout of the semiconductor device, which includes a front channel structure, a front metal gate structure, a front source / drain metal, a front gate via, a front source / drain via, a first dielectric wall, and a first interconnect structure. Here, the first interconnect structure includes source / drain contact metal and a through-hole structure. The front view shows a first interconnect layer including a ground line VSS and a bit line WL. The front view also shows two first standard cells arranged along the Y direction of the layout. The first first standard cell (i.e., the first sub-standard cell) includes a layer along the layout... Figure X A transmission gate transistor arranged in the direction (equivalent to) Figure 1 The transistor M5 in the middle) and a pull-down transistor (equivalent to Figure 1 Transistor M1 in the middle). The second first standard unit (i.e., the second sub-standard unit) includes the edge plate. Figure X A pull-down transistor arranged in the direction (equivalent to) Figure 1 (transistor M3) and a transmission gate transistor (equivalent to) Figure 1 (Transistor M6 in the transistor).

[0035] Figures 2 to 5 Image (a) shows a rear view of the layout of the semiconductor device. The rear view shows the rear channel structure, the rear metal gate structure, the rear source / drain metal, the rear source / drain via, the second dielectric wall, the first interconnect structure, and the second interconnect structure. Here, the first interconnect structure includes source / drain contact metal, a cross-coupling structure, and a through-hole structure. The rear view shows the second interconnect layer including bit line BL, positive power line VDD, and reverse bit line BLB. The rear view also shows two second standard cells arranged along the Y direction of the layout. The first second standard cell (i.e., the third sub-standard cell) includes a pull-up transistor (equivalent to...). Figure 1 The second standard unit (i.e., the fourth sub-standard unit) includes a pull-up transistor (equivalent to transistor M2). Figure 1 (Transistor M4 in the first sub-standard unit). Here, transistor M1 in the first sub-standard unit and transistor M2 in the third sub-standard unit are stacked, and transistor M3 in the second sub-standard unit and transistor M4 in the fourth sub-standard unit are stacked.

[0036] Understandably, both the first interconnect layer 1 and the second interconnect layer 3 provide at least two layout options, which can be combined to form Figures 2 to 5 At least four types of semiconductor devices are shown.

[0037] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 1 . Figure 7 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 2 . Figure 8This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 3 . Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Figure 4 . Figure 6 Figures (a) to (d) show the semiconductor device along... Figure 2 The diagram shows cross-sectional views of sections AA', BB', CC', and DD'. Figure 7 Figures (a) to (d) show the semiconductor device along... Figure 3 The diagram shows cross-sectional views of sections AA', BB', CC', and DD'. Figure 8 Figures (a) to (d) show the semiconductor device along... Figure 4 The diagram shows cross-sectional views of sections AA', BB', CC', and DD'. Figure 9 Figures (a) to (d) show the semiconductor device along... Figure 5 The diagram shows cross-sectional views of sections AA', BB', CC', and DD'. (See attached diagram.) Figures 6 to 9 As shown, the semiconductor device in this embodiment may include: a first interconnect layer 1, at least one memory cell 2, and a second interconnect layer 3 stacked sequentially along a first direction (i.e., a stacking direction). Each memory cell 2 includes a first semiconductor structure 21, a first isolation layer 22, and a second semiconductor structure 23 stacked sequentially along the first direction.

[0038] In some embodiments, the first semiconductor structure 21 includes two first standard units arranged along a second direction (layout Y direction), namely a first sub-standard unit and a second sub-standard unit. The first sub-standard unit includes units arranged along a third direction (layout Y direction). Figure X The first sub-standard cell comprises two first transistors arranged in a third direction, namely a first transmission gate transistor (transistor M5) and a first pull-down transistor (transistor M1). Transistor M5 and transistor M1 share a common drain structure. The second sub-standard cell includes two first transistors arranged in a third direction, namely a second pull-down transistor (transistor M3) and a second transmission gate transistor (transistor M6). Transistor M3 and transistor M6 share a common drain structure.

[0039] In some embodiments, the second semiconductor structure 23 includes two second standard units arranged along a second direction, namely a third sub-standard unit and a fourth sub-standard unit. The third sub-standard unit includes a second transistor, which is a first pull-up transistor (i.e., transistor M2). The fourth sub-standard unit includes a second transistor, which is a second pull-up transistor (i.e., transistor M4). Transistors M2 and M1 are stacked along a first direction, and transistors M4 and M3 are stacked along a first direction. Transistors M2 and M4 are staggered along a second direction. The first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first and second directions.

[0040] In some embodiments, transistors M5, M1, M3, and M6 in the first semiconductor structure 21 are all electrically connected to the first interconnect layer 1 through source-drain vias 42 or gate vias 41. Transistors M2 and M4 in the second semiconductor structure 23 are all electrically connected to the second interconnect layer 3 through source-drain vias 42 or gate vias 41.

[0041] In some embodiments, transistor M5 is connected to the first interconnect layer 1 through a gate via 41, and transistor M1 is connected to the first interconnect layer 1 through a source-drain via 42. Transistor M3 is connected to the first interconnect layer 1 through a source-drain via 42, and transistor M6 is connected to the first interconnect layer 1 through a gate metal. Transistor M2 is connected to the second interconnect layer 3 through a source-drain via 42, and transistor M4 is connected to the second interconnect layer 3 through a source-drain via 42.

[0042] In some embodiments, the source structures in transistors M1 and M3 are connected to the first interconnect layer 1 via source-drain vias 42. The source structures in transistors M2 and M4 are connected to the second interconnect layer 3 via source-drain vias 42. Here, the gate via 41 and / or the source-drain via 42 can be metal via structures, such as through-silicon vias (TSVs).

[0043] In some embodiments, memory cell 2 may further include a first connection structure and a second connection structure 54. The first connection structure is used to couple transistor M2 and transistor M1 into an inverter (i.e., a first inverter), or transistor M4 and transistor M3 into an inverter (i.e., a second inverter). The first connection structure is also used to cross-couple the first inverter and the second inverter.

[0044] In some embodiments, the first connection structure includes at least one of the following: a structure that forms a common metal gate structure for the pull-up transistor and the pull-down transistor (a through-hole structure 51); a structure that forms a drain connection for the pull-up transistor and the pull-down transistor (a source-drain contact metal 52); and a structure that cross-couples the first inverter and the second inverter (a cross-coupling structure 53).

[0045] In some embodiments, a first inverter and a second inverter can be formed through a through-hole structure 51 and source / drain contact metals 52. In some embodiments, when transistor M2 and transistor M1 (or transistor M4 and transistor M3) share a common metal gate structure, it is not necessary to fabricate the through-hole structure 51. In some embodiments, when the drain structures of transistor M2 and transistor M1 (or transistor M4 and transistor M3) are already connected, it is not necessary to provide source / drain contact metals 52. In some embodiments, when the metal gate structure of the first inverter and the drain structure of the second inverter can be connected through a metal structure in the interconnect layer, it is not necessary to provide cross-coupling structure 53.

[0046] In some embodiments, the source / drain contact metal 52 has at least one.

[0047] In some embodiments, there is one source-drain contact metal 52. The drain structures of transistor M3 and transistor M4 are directly connected. The first end of the source-drain contact metal 52 is connected to the drain structure of transistor M1, and the second end extends along a first direction and is connected to the drain structure of transistor M2.

[0048] In some embodiments, there are two source-drain contact metals 52. The first end of the first source-drain contact metal 52 is connected to the drain structure of transistor M1, and the second end of the first source-drain contact metal 52 extends along a first direction and is connected to the drain structure of transistor M2. The first end of the second source-drain contact metal 52 is connected to the drain structure of transistor M3, and the second end of the second source-drain contact metal 52 extends along the first direction and is connected to the drain structure of transistor M4.

[0049] In some embodiments, the through-hole structure 51 has at least one.

[0050] In some embodiments, there is one through-hole structure 51. The metal gate structure 24 of transistor M3 is directly connected to the metal gate structure 24 of transistor M4. The first end of the through-hole structure 51 is connected to the metal gate structure 24 of transistor M1, and the second end extends along the first direction and is connected to the metal gate structure 24 of transistor M2.

[0051] In some embodiments, there are two through-hole structures 51. The first end of the first through-hole structure 51 is connected to the metal gate structure 24 of transistor M1, and the second end of the first through-hole structure 51 extends along a first direction and is connected to the metal gate structure 24 of transistor M2. The first end of the second through-hole structure 51 is connected to the metal gate structure 24 of transistor M3, and the second end of the first through-hole structure 51 extends along the first direction and is connected to the metal gate structure 24 of transistor M4.

[0052] In some embodiments, a first isolation layer 22 is disposed between the first semiconductor structure 21 and the second semiconductor structure 23. The two ends of the through-hole structure 51 penetrate the first isolation layer 22 to realize the gate interconnection of the stacked transistors.

[0053] In some embodiments, the cross-coupling structure 53 has at least one.

[0054] In some embodiments, there is one cross-coupling structure 53. When the metal gate structure 24 of transistor M2 and the drain structure of transistor M4 are connected through a metal structure (such as metal M0 or metal M1) in the interconnect layer, the first end of the cross-coupling structure 53 is connected to the metal gate structure 24 of transistor M4, and the second end is connected to the drain structure of transistor M2. Here, the first and second ends of the cross-coupling structure are the two ends of the cross-coupling structure 53 along a third direction. Here, the metal structure in the interconnect layer can be the metal structure in the first interconnect layer 1 and / or the metal structure in the second interconnect layer 3, which is not limited in this embodiment.

[0055] Understandably, the metal layer structure and its metal layer vias can short-circuit the common gate of the first inverter and the common drain of the second inverter, while the cross-coupling structure 53 short-circuits the common drain of the first inverter and the common gate of the second inverter, thereby cross-coupling the two sets of vertical inverters to form a latch, realizing the three-dimensional stacking and functional latching of SRAM cells without additional area.

[0056] In some embodiments, there are two cross-coupling structures 53. The first end of the first cross-coupling structure 53 is connected to the metal gate structure 24 of transistor M4, and the second end is connected to the drain structure of transistor M2. The first end of the second cross-coupling structure 53 is connected to the metal gate structure 24 of transistor M2, and the second end is connected to the drain structure of transistor M4. Here, the first and second ends of the cross-coupling structure are the two ends of the cross-coupling structure 53 along a third direction.

[0057] In some embodiments, the second connection structure 54 is used to electrically connect the first transistor (i.e., transistor M5 and transistor M6) that does not form an inverter in the first semiconductor structure 21, i.e., the third transistor, to the second interconnect layer 3.

[0058] In some embodiments, there are two second connection structures 54. The first connection structure 54 has a first end connected to the second interconnect layer 3, and a second end penetrating the dielectric structure 25 in the second semiconductor structure 23, the first isolation layer 22, and the dielectric structure 25 in the transistor M5, and connected to the source of the transistor M5. The second connection structure 54 has a first end connected to the second interconnect layer 3, and a second end penetrating the dielectric structure 25 in the second semiconductor structure 23, the first isolation layer 22, and the dielectric structure 25 in the transistor M6, and connected to the source of the transistor M6. Here, the first end and the second end of the second connection structure 54 are the two ends of the second connection structure 54 along a first direction.

[0059] In some embodiments, the first second connection structure 54 is located above transistor M5, and the second second connection structure 54 is located above transistor M6. The first second connection structure 54 and the second second connection structure 54 are staggered along a second direction.

[0060] In some embodiments, transistors M2 and M1 are arranged back-to-back; transistors M4 and M3 are arranged back-to-back. In some embodiments, the second connection structure 54 is formed using similar etching, deposition, or other processes as the source / drain metals 26 in transistors M2 and M4. The second connection structure 54 may be contained within the source / drain metals 26. The second connection structure 54 may be a source / drain metal 26 with a deeper dimension.

[0061] In some embodiments, a first dielectric wall 27 and / or a second dielectric wall 28.

[0062] In some embodiments, the first dielectric wall 27 is located between transistor M1 and an adjacent structure along a second direction, and / or, the first dielectric wall 27 is located between transistor M3 and an adjacent structure along a second direction. Exemplarily, the first dielectric wall 27 may be located between transistor M1 and transistor M6. The first dielectric wall 27 may also be located between transistor M1 and an adjacent semiconductor device. The second dielectric wall 28 may be located between transistor M3 and transistor M5. The second dielectric wall 28 may also be located between transistor M3 and an adjacent semiconductor device.

[0063] In some embodiments, the second dielectric wall 28 is located on both sides of the second semiconductor structure 23 along a second direction. For example, the second dielectric wall 28 may be located simultaneously between transistor M2 and an adjacent semiconductor device, and between transistor M4 and an adjacent semiconductor device.

[0064] In some embodiments, transistors M5, M1, M3, and M6 in the first semiconductor structure 21 are N-type transistors. The first interconnect layer 1 includes a word line WL and a ground line VSS. The word line WL is connected to the metal gate structure 24 of transistor M5 and to the metal gate structure 24 of transistor M6. The ground line VSS is connected to the source structure of transistor M1 and to the source structure of transistor M3.

[0065] In some embodiments, the connection between the word line WL and the metal gate structure 24 is achieved through the gate via 41, and the connection between the ground line VSS and the source structure is achieved through the source-drain via 42.

[0066] In some embodiments, transistors M2 and M4 in the second semiconductor structure 23 are P-type transistors. The second interconnect layer 3 includes a positive power line VDD, a bit line BL, and an anti-phase line BLB. The positive power line VDD is connected to the source structure of transistor M2 and to the source of transistor M4. The bit line BL and the anti-phase line BLB are each connected to a second connection structure 54. In some embodiments, the bit line BL may be connected to the second connection structure 54 connecting transistor M5. The anti-phase line BLB may be connected to the second connection structure 54 connecting transistor M6.

[0067] In some embodiments, the connection between the positive power line VDD and the source structure is achieved through the source-drain via 42, and the connection between the bit line BL, the anti-phase line BLB and the second connection structure 54 is achieved through the source-drain via 42.

[0068] In some embodiments, the first interconnect layer 1 includes a first word line, a first ground line, and a second word line arranged along a second direction; or, the first interconnect layer 1 includes a second ground line, a third word line, and a third ground line arranged along a second direction.

[0069] In some embodiments, see Figure 3 As shown, the first interconnect layer 1 includes three metal lines arranged along a second direction: a word line WL (i.e., the first word line), a ground line VSS (i.e., the first ground line), and a word line WL (i.e., the second word line), all three extending along the third direction. Along the second direction, the two word lines WL are located on opposite sides of the memory cell 2, and the ground line VSS is located at the intersection of the first and second sub-standard cells in the memory cell 2. The first word line is connected to the metal gate structure 24 in transistor M5. The first ground line is connected to the source structures in transistors M1 and M3, respectively. The second word line is connected to the metal gate structure 24 in transistor M6.

[0070] It is important to note that the third-direction extension length of the ground line VSS can be set according to the number of memory cells. However, the third-direction extension length of the word line WL is less than the length of each transistor along the third direction. For example, in... Figures 2 to 5 In the cross section shown in (a), there is a ground line VSS, but no word line WL. Thus, the word lines WL of two adjacent memory cells along the third direction are not connected, which ensures that two adjacent memory cells have independent signal input methods.

[0071] In some embodiments, see Figure 2 As shown, the first interconnect layer 1 includes three metal lines arranged along a second direction: a ground line VSS (i.e., the second ground line), a word line WL (i.e., the third word line), and a ground line VSS (i.e., the third ground line), all three extending along the third direction. Along the second direction, the two ground lines VSS are located on opposite sides of the memory cell 2, and the word line WL is located at the intersection of the first and second sub-standard cells in the memory cell 2. The second ground line is connected to the source structure in transistor M1. The third word line is connected to the metal gate structure 24 in transistors M5 and M6, respectively, and the third ground line is connected to the source structure in transistor M3.

[0072] In some embodiments, the second interconnect layer 3 includes a first positive power line, a first bit line, a first anti-phase line, and a second positive power line arranged along the second direction; or, the second interconnect layer 3 includes a second bit line BL, a third positive power line, and a second anti-phase line arranged along the second direction.

[0073] In some embodiments, see Figure 5 As shown, the second interconnect layer 3 includes four metal lines arranged along a second direction: a positive power line VDD (i.e., the first positive power line), a bit line BL (i.e., the first bit line), an anti-phase line BLB (i.e., the first anti-phase line), and a positive power line VDD (i.e., the second positive power line), all extending along a third direction. Along the second direction, the positive power line VDD, bit line BL, anti-phase line BLB, and positive power line VDD are spaced apart. The first positive power line is connected to the source structure of transistor M2. The first bit line is connected to the second connection structure 54 connecting transistor M5. The first anti-phase line is connected to the second connection structure 54 connecting transistor M6. The second positive power line is connected to the source structure of transistor M4.

[0074] In some embodiments, see Figure 4As shown, the second interconnect layer 3 includes three metal lines arranged along the second direction: a bit line BL (i.e., the second bit line), a positive power supply line VDD (i.e., the third positive power supply line), and an anti-phase line BLB (i.e., the second anti-phase line), all three extending along the third direction. Along the second direction, the bit line BL and the anti-phase line BLB are located on opposite sides of the memory cell 2, and the positive power supply line VDD is located at the intersection of the third and fourth sub-standard cells in the memory cell 2. The second bit line is connected to the second connection structure 54 connecting transistor M5. The third positive power supply line is connected to the source structures in transistors M2 and M4, respectively. The second anti-phase line is connected to the second connection structure 54 connecting transistor M6.

[0075] Understandably, in the above embodiments, placing the P-type transistor close to the positive power supply line VDD can reduce wiring length, lower resistance, and reduce voltage drop.

[0076] It should be noted that the above embodiments illustrate a semiconductor device where the first transistor is an N-type transistor and the second transistor is a P-type transistor. In an alternative, the polarities of the first and second transistors can be interchanged. In this case, only the source and drain structures of each transistor need to be interchanged on the layout coordinates to maintain the current direction, voltage bias, and logic function without changing the interconnect layers or additional area.

[0077] It should be noted that, for ease of explanation, the source / drain metals mentioned in the embodiments of this application are abbreviations, specifically referring to the source metal and / or drain metal. Furthermore, the source / drain structures and source / drain vias are similar, and the term "source / drain" is an abbreviation for "source and / or drain".

[0078] Secondly, embodiments of this application provide a method for fabricating a semiconductor device. The method for fabricating the semiconductor device in this application is used to fabricate the semiconductor device described in any of the embodiments of the first aspect. The method for fabricating the semiconductor device may include the following steps.

[0079] Step 1: Provide a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a plurality of fin structures, each fin structure including a first part, a second part and a third part, the second part being used to isolate the first part and the third part.

[0080] Step 2: Deposit oxide material on the substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the second and third portions, and the first portion is exposed outside the shallow trench isolation structure.

[0081] Step 3: Based on the first part, a first semiconductor structure is formed, wherein the first semiconductor structure includes two first standard units arranged along the second direction, each first standard unit includes two first transistors arranged along the third direction and the two first transistors share a drain structure.

[0082] Step 4: A first interconnect layer is formed above the first semiconductor structure, wherein all the first transistors in the first semiconductor structure are electrically connected to the first interconnect layer.

[0083] Step 5: Combine and flip the first interconnect layer with the carrier wafer.

[0084] Step 6: Remove the substrate and thin the shallow trench isolation structure to expose the third part, wherein the thinned shallow trench isolation structure wraps the second part, and the thinned shallow trench isolation structure and the second part together form the first isolation layer.

[0085] Step 7: Based on the third part of the fin structure, a second semiconductor structure is formed, wherein the second semiconductor structure includes two second transistors; the two second transistors are stacked along a first direction with a first transistor in a different first standard cell, and the two second transistors are staggered along a second direction; the first semiconductor structure, the first isolation layer, and the second semiconductor structure constitute a memory cell. The first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first and second directions.

[0086] Step 8: Form a first connection structure and a second connection structure in the memory cell; the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple the two inverters in the memory cell; the second connection structure passes through the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of the third transistor to the second interconnect layer, wherein the third transistor is the first transistor in the first semiconductor structure that does not form an inverter.

[0087] Step 9: A second interconnect layer is formed above the second semiconductor structure, wherein all transistors in the second semiconductor structure are electrically connected to the second interconnect layer. Furthermore, the second interconnect layer is connected to both the first interconnect structure and the second interconnect structure.

[0088] It should be noted that steps one through nine above are not exclusive, and other steps can be performed before, after, or between any of the steps shown in the operation; furthermore, the order of steps one through nine above can be adjusted according to actual needs.

[0089] In this embodiment, a semiconductor substrate can be fabricated using standard semiconductor fabrication processes. The fabrication process may include substrate fabrication and fin structure formation. Here, multiple fin structures can be formed on the substrate. Each fin structure includes a first portion, a second portion, and a third portion. The first, second, and third portions are formed from different material layers. The second portion forms a first isolation layer, which isolates the first and third portions. The second portion may be formed from an insulating layer material. The first portion is used to fabricate a first semiconductor structure, and the second portion is used to fabricate a second semiconductor structure.

[0090] In some embodiments, different fin structures can lead to different types of transistors subsequently fabricated. In some embodiments, when the fin structure is a columnar structure, the transistor type can be a fin field-effect transistor (FET). In some embodiments, when the fin structure is a nanosheet stacked structure, the transistor type can be a gate-around-the-ring (GROUP) FET or a forked-plate (FIP) transistor. In some embodiments, when the fin structure is a bulk structure, the transistor type can be a planar FET.

[0091] In some embodiments, after obtaining the semiconductor substrate, an oxide material can be deposited on the substrate to form a shallow trench isolation structure. Here, the shallow trench isolation structure encloses the second and third portions of the fin structure, while the first portion of the fin structure is exposed outside the shallow trench isolation structure.

[0092] In some embodiments, after forming the shallow trench isolation structure, a first semiconductor structure can be fabricated using standard semiconductor fabrication processes based on the first portion of the fin structure. Here, the first semiconductor structure includes two first standard cells arranged along a second direction, each first standard cell including two first transistors arranged along a third direction, and the two first transistors sharing a common drain structure.

[0093] In some embodiments, the fabrication process of each first transistor may include: epitaxially growing a source / drain structure based on a first portion of the fin structure; forming a metal gate structure and a dielectric structure in the first transistor; enclosing the source / drain structure in the dielectric structure; forming vias in the dielectric structure to expose the source / drain structure; and depositing metal material in the vias to form source / drain metal.

[0094] In some embodiments, after forming the first semiconductor structure, a first interconnect layer may be formed above the first semiconductor structure, the first interconnect layer including metal lines. All first transistors in the first semiconductor structure can be electrically connected to the metal lines in the first interconnect layer. The connection method can be referred to the description in any embodiment of the first aspect, and for the sake of brevity, it will not be repeated here.

[0095] In some embodiments, after forming the first interconnect layer, the first interconnect layer can be bonded to the carrier wafer, and then the carrier wafer can be flipped so that the substrate is on top.

[0096] In some embodiments, after the substrate is placed on top, the substrate can be removed and the shallow trench isolation structure thinned to expose the third portion of the fin structure. Here, the thinned shallow trench isolation structure encloses the second portion, and the thinned shallow trench isolation structure and the second portion together form the first isolation layer.

[0097] In some embodiments, after thinning the shallow trench isolation structure, a second semiconductor structure can be fabricated using standard semiconductor fabrication processes based on the third portion of the fin structure. Here, the second semiconductor structure includes two second standard cells arranged along a second direction, each second standard cell including a second transistor, and the two second transistors in the two second standard cells are staggered along the second direction. The first semiconductor structure, the first isolation layer, and the second semiconductor structure constitute a memory cell. The first semiconductor structure and the second semiconductor structure are stacked along a first direction.

[0098] In some embodiments, the fabrication process of each second transistor may include: epitaxially growing a source / drain structure based on a third portion of the fin structure; forming a metal gate structure and a dielectric structure in the second transistor; enclosing the source / drain structure with the dielectric structure; and forming vias in the dielectric structure to expose the source / drain structure. In some embodiments, after exposing the source / drain structure, source / drain metal may be formed above the source / drain structure. Here, the source / drain metal is located on the back side of the wafer.

[0099] In some embodiments, after forming the second semiconductor structure, a second interconnect layer may be formed on top of the second semiconductor structure. The second interconnect layer includes metal lines. All transistors in the second semiconductor structure are electrically connected to the metal lines in the second interconnect layer. The connection method can be found in the description of any embodiment of the first aspect, and for the sake of brevity, will not be repeated here.

[0100] In some embodiments, the fabrication method may further include: forming a first connection structure and a second connection structure in a memory cell; the first connection structure is used to couple a first transistor and a second transistor stacked along a first direction into an inverter, and to cross-couple the two inverters in the memory cell. The second connection structure extends through the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of a third transistor to the second interconnect layer. The third transistor is the first transistor in the first semiconductor structure that does not form an inverter.

[0101] In some embodiments, the first connection structure includes at least one of a source / drain contact metal, a cross-coupling structure, and a through-hole structure. The first end of the source / drain contact metal is connected to the drain structure of a first transistor in the inverter, and the second end extends along a first direction and is connected to the drain structure of a second transistor in the same inverter. The first end of the cross-coupling structure is connected to the metal gate structure of a second transistor in one inverter, and the second end is connected to the drain structure of a second transistor in another inverter; the first and second ends of the cross-coupling structure are the two ends of the cross-coupling structure along a third direction. The first end of the through-hole structure is connected to the metal gate structure of a first transistor in the inverter, and the second end extends along a first direction and is connected to the metal gate structure of a second transistor in the same inverter.

[0102] In some embodiments, forming a first connection structure in a memory cell may include at least one of the following: removing the dielectric structure and a first isolation layer between a first transistor and a second transistor in the same inverter, forming a via and filling it with a metal material to form source-drain contact metal; forming a dielectric layer over the second transistor, and forming a trench in the dielectric layer and filling it with a metal material to form a cross-coupling structure; forming a through-hole in the first isolation layer and filling it with a metal material to form a through-hole structure.

[0103] Understandably, an interlayer dielectric and a first isolation layer are disposed between the first transistor and the second transistor in the same inverter. By selectively etching the dielectric structure and the first isolation layer between the first transistor and the second transistor, contact holes connecting the drain structures of the first transistor and the second transistor can be formed. Then, filling the contact holes with metal can form source-drain contact metals.

[0104] Understandably, depositing a new dielectric layer (such as an inter-metal dielectric, IMD) over the second transistor, followed by etching trenches and filling them with metal, can form a cross-coupled structure connecting the gate structure of one inverter and the drain structure of another. Here, the cross-coupled structure can directly or indirectly connect to the drain structure. In one example, the cross-coupled structure can indirectly connect to the drain structure via source-drain metals.

[0105] Understandably, forming a vertical through-hole on the first isolation layer and filling it with metal can form a through-hole structure that connects the gate structures of the first transistor and the second transistor.

[0106] In some embodiments, forming a second interconnect structure in a memory cell may include: sequentially etching a second semiconductor structure, a first isolation layer, and a dielectric structure in a first transistor to form a deep hole and filling it with a metal material to form the second interconnect structure.

[0107] Understandably, the third part of the fin-like structure is cut off, and then the second semiconductor structure, the first isolation layer, and the dielectric structure in the first transistor are sequentially etched at the cut location to form a deep hole. Afterwards, a metal material is filled into the deep hole to form a second connection structure connecting the source structure in the first transistor and the second interconnect layer.

[0108] In some embodiments, the method may further include: depositing a dielectric material over a shallow trench isolation structure to form a dielectric wall, wherein the dielectric wall includes a first dielectric wall and / or a second dielectric wall. The first dielectric wall is located along a second direction between a first transistor in the inverter and an adjacent structure; the second dielectric wall is located along the second direction on both sides of the second semiconductor structure.

[0109] The following examples illustrate the semiconductor devices and their fabrication methods in the embodiments of this application.

[0110] Figures 10 to 19 This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an exemplary embodiment. Wherein, Figures 10 to 19 (a) shows the semiconductor device along Figure 2 The cross-sectional view of the AA' section shown; Figures 10 to 19 (b) shows the semiconductor device along Figure 2 The cross-sectional view of the BB' section shown; Figures 10 to 19 (c) shows the semiconductor device along Figure 2 The cross-sectional view of the CC' section is shown. Figures 10 to 19 (d) in the figure shows the semiconductor device along Figure 2 The cross-sectional view of the DD' section is shown. See also... Figures 10 to 19 to form Figure 6 Taking the semiconductor device shown as an example, the method for fabricating the semiconductor device may include the following steps.

[0111] The first step involves providing a silicon-on-insulator (SiI) substrate, then etching the upper silicon layer of the SiI substrate, followed by etching the buried oxide layer in between, and finally etching a portion of the lower silicon layer to form a semiconductor substrate, resulting in the following: Figure 10 The structure shown.

[0112] Here, the etched upper silicon forms the first part 37 of the fin structure in the semiconductor substrate, the etched buried oxide layer forms the second part 29 of the fin structure in the semiconductor substrate, a portion of the lower silicon forms the third part 30 of the fin structure in the semiconductor substrate after etching, and a portion of the lower silicon that is not etched forms the substrate 31 in the semiconductor substrate.

[0113] In some embodiments, the method of forming the semiconductor substrate is not limited in this application. For example, a semiconductor substrate can be formed by depositing a multilayer structure on a silicon wafer and then etching the multilayer structure. The etched multilayer structure forms a fin-like structure.

[0114] The second step involves depositing oxide material on substrate 31 to form a shallow trench isolation structure 32. Then, a pseudo-gate structure 33, spanning the first portion 37 of the fin-like structure, is formed above the shallow trench isolation structure 32, resulting in... Figure 11 The structure shown is as described.

[0115] The third step involves forming the source / drain structure 34 based on the first part 37 of the fin-like structure, resulting in the following: Figure 12 The structure shown is as described.

[0116] Here, the source-drain structure 34 can be an N-type structure.

[0117] Step four: Remove the dummy gate structure 33 and deposit metal material at the location where the dummy gate structure 33 was removed to form a metal gate structure 24, thus obtaining the first transistor. Then, a gate removal process is used to remove a portion of the metal gate structure 24, and insulating material is deposited at the location where the portion of the metal gate structure 24 was removed to form a dielectric wall, resulting in... Figure 13 The structure shown.

[0118] Here, the dielectric wall within the first semiconductor structure 21 is the first dielectric wall 27, which is located along the second direction between the first transistor in the inverter and the adjacent structure.

[0119] Step 5: Deposit dielectric material over the first transistor to form a dielectric layer 35. Then, etch the dielectric layer 35 to form source / drain metal vias exposing the source / drain structure 34, and deposit metal material within these vias to form source / drain metal 26, resulting in... Figure 14 The structure shown.

[0120] Step 6: After forming the source / drain metals 26, a first interconnect layer 1 connected to the first transistor is formed using standard back-end processes in semiconductor fabrication, resulting in the following... Figure 15 The structure shown.

[0121] Step 7: Bond the first interconnect layer 1 to the carrier wafer 36, then flip the carrier wafer 36 and remove the substrate 31 to expose the shallow trench isolation structure 32. Next, thin the shallow trench isolation structure to expose the third portion 30 of the fin structure; use a fin-cutting process to remove the third portion 30 of the fin structure in the non-second transistor region, and then form a pseudo-gate structure 33 spanning the third portion 30 of the fin structure based on the remaining third portion 30. Then, based on the third portion 30 of the fin structure, epitaxially form a source / drain structure 34, and deposit a dielectric structure 25 encapsulating the source / drain structure 34. After the source / drain structure 34 is formed, remove the pseudo-gate structure 33, and sequentially form a through-hole structure 51 and a metal gate structure 24. Then, use a gate-cutting process to remove a portion of the metal gate structure 24, and deposit insulating material at the location where the portion of the metal gate structure 24 was removed to form a dielectric wall; resulting in... Figure 16 The structure shown.

[0122] Here, the dielectric wall within the second semiconductor structure 23 is the second dielectric wall 28, which is located on both sides of the second semiconductor structure 23 along the second direction.

[0123] Step 8: Form a second connection structure 54 connecting the source structure within the first transistor, resulting in the following... Figure 17 The structure shown.

[0124] Here, the second connection structure 54 penetrates the dielectric structure 25 in the second semiconductor structure 23, the first isolation layer 22, and the dielectric structure 25 in the first transistor.

[0125] Step 9: Deposit dielectric material to form dielectric layer 35 on the back side of the wafer. Then, through an etching process, sequentially etch the dielectric layer 35, dielectric structure 25, and other structures to form source / drain metal vias and source / drain contact metal vias. Next, deposit metal material within the source / drain metal vias and source / drain contact metal vias to simultaneously form the source / drain metal 26 and source / drain contact metal 52 of the second transistor, resulting in... Figure 18 The structure shown.

[0126] Here, the source-drain contact metal via connects the source-drain metal via to the drain structure of the first transistor.

[0127] Step 10: Through etching, trenches are formed in the dielectric layer 35 on the back side of the wafer, and metal material is deposited in the trenches to form a cross-coupling structure 53, resulting in... Figure 19 The structure shown.

[0128] Step 11: Form a second interconnect layer 3 above the dielectric layer 35 on the back side of the wafer, to obtain... Figure 6 The structure shown.

[0129] This completes the fabrication of the semiconductor device.

[0130] In this embodiment, the front-side transistor is fabricated using a standard process, followed by wafer bonding and wafer flipping. The front-end structure of the back-side transistor is formed according to the normal process, followed by the fabrication of source / drain metals. This process is divided into two parts: one part involves forming contacts from the back side to the front-side source / drain epitaxial layer, requiring the formation of a high aspect ratio second connection structure to bring the bit line output from the back side to the front side; the other part involves conventionally forming contacts from the back-side to the back-side source / drain epitaxial layer. In the above process steps, the source / drain contact metals, cross-coupling structures, and through-hole structures form the cross-coupling of the two inverters. Finally, the back-end metal interconnects of the back-side transistor are formed, and the SRAM cell fabrication is complete.

[0131] This application's embodiments can be applied to next-generation integrated circuit SRAM processes, representing a novel stacked transistor SRAM design scheme with significant potential for advanced node process applications. It is compatible with different flip-chip stacked transistor process implementations, such as non-self-aligned and self-aligned flip-chip stacked transistors, and with processes based on two-flip and three-flip operations. Furthermore, the material used in the middle of the front and back transistors is not limited to the silicon-on-insulator substrate used in this embodiment; isolation can also be achieved through MDI, bulk substrates, and other methods.

[0132] Furthermore, the semiconductor devices provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM).

[0133] Taking TEM as an example, embodiments of this application can use TEM slicing to inspect the aforementioned semiconductor device. See also Figures 6 to 9 As shown, the unique first connection structure and second connection structure described in this application can be observed, and there are at least two ways to lay out the interconnection layers on the front and back sides respectively.

[0134] It should be noted that the process described in this application is universal, and the architecture of the transistor (e.g., planar field-effect transistor, fin field-effect transistor, all-ring gate field-effect transistor, etc.) does not affect the implementation of this application.

[0135] Thirdly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board.

[0136] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: A first interconnect layer, at least one memory cell, and a second interconnect layer are stacked sequentially along a first direction; each memory cell includes a first semiconductor structure, a first isolation layer, and a second semiconductor structure stacked sequentially along the first direction. The first semiconductor structure includes two first standard units arranged along a second direction, each first standard unit including two first transistors arranged along a third direction and the two first transistors sharing a drain structure; the second semiconductor structure includes two second transistors; the two second transistors are stacked with a first transistor in a different first standard unit along the first direction, and the two second transistors are staggered along the second direction; the first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first direction and the second direction; All first transistors in the first semiconductor structure are electrically connected to the first interconnect layer, and all second transistors in the second semiconductor structure are electrically connected to the second interconnect layer; The memory cell further includes: a first connection structure and a second connection structure, wherein the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple the two inverters in the memory cell; the second connection structure at least penetrates the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of the third transistor to the second interconnect layer, wherein the third transistor is the first transistor in the first semiconductor structure that does not constitute the inverter.

2. The semiconductor device according to claim 1, characterized in that, The first connection structure includes at least one of source / drain contact metal, cross-coupling structure, and through-hole structure; Wherein, the first end of the source-drain contact metal is connected to the drain structure of the first transistor in the inverter, and the second end extends along the first direction and is connected to the drain structure of the second transistor in the same inverter. The first end of the cross-coupling structure is connected to the metal gate structure of the second transistor in one of the inverters, and the second end is connected to the drain structure of the second transistor in another inverter. The first end and the second end of the cross-coupling structure are the two ends of the cross-coupling structure along the third direction. The first end of the through-hole structure is connected to the metal gate structure of the first transistor in the inverter, and the second end extends along the first direction and is connected to the metal gate structure of the second transistor in the same inverter.

3. The semiconductor device according to claim 1, characterized in that, The memory cell further includes: a first dielectric wall and / or a second dielectric wall; Wherein, the first dielectric wall is located between the first transistor and the adjacent structure in the inverter along the second direction; the second dielectric wall is located on both sides of the second semiconductor structure along the second direction.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor; The first interconnect layer includes word lines and ground lines, wherein the word lines are connected to the metal gate structure of the third transistor, and the ground lines are connected to the source structure of the first transistor in the inverter. The second interconnect layer includes a positive power line, a bit line, and an anti-phase line, wherein the positive power line is connected to the source structure of the second transistor in the inverter, and the bit line and the anti-phase line are each connected to a second interconnect structure.

5. The semiconductor device according to claim 4, characterized in that, The first interconnect layer includes a first word line, a first ground line, and a second word line arranged along the second direction; or, the first interconnect layer includes a second ground line, a third word line, and a third ground line arranged along the second direction. The second interconnect layer includes a first positive power line, a first bit line, a first anti-phase line, and a positive power ground line arranged along the second direction; or, the second interconnect layer includes a second bit line, a third positive power line, and a second anti-phase line arranged along the second direction.

6. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor are positioned opposite each other; the second connection structure and the source / drain metal in the second transistor are formed using the same deposition process.

7. A method for fabricating a semiconductor device, characterized in that, For fabricating a semiconductor device as described in any one of claims 1 to 6, comprising: A semiconductor substrate is provided, wherein the semiconductor substrate includes a substrate and a plurality of fin structures, each of the fin structures including a first portion, a second portion and a third portion, the second portion being used to isolate the first portion and the third portion; An oxide material is deposited on the substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure encloses the second portion and the third portion, and the first portion is exposed outside the shallow trench isolation structure; Based on the first part, a first semiconductor structure is formed, wherein the first semiconductor structure includes two first standard units arranged along a second direction, each of the first standard units includes two first transistors arranged along a third direction and the two first transistors share a drain structure; A first interconnect layer is formed above the first semiconductor structure, wherein all the first transistors in the first semiconductor structure are electrically connected to the first interconnect layer; The first interconnect layer is bonded to the wafer carrier and flipped; The substrate is removed and the shallow trench isolation structure is thinned to expose the third portion, wherein the thinned shallow trench isolation structure encloses the second portion, and the thinned shallow trench isolation structure and the second portion together form the first isolation layer; Based on the third portion of the fin-like structure, a second semiconductor structure is formed, wherein the first semiconductor structure and the second semiconductor structure are stacked along a first direction, and the second semiconductor structure includes two transistors; the two transistors are respectively stacked with a first transistor in a different first standard cell along the first direction, and the two transistors are staggered along the second direction; the first semiconductor structure, the first isolation layer, and the second semiconductor structure constitute a memory cell; the first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first and second directions; A second interconnect layer is formed above the second semiconductor structure, wherein all transistors in the second semiconductor structure are electrically connected to the second interconnect layer; The fabrication method further includes: forming a first connection structure and a second connection structure in the memory cell; the first connection structure is used to couple a first transistor and a second transistor stacked along the first direction into an inverter, and to cross-couple the two inverters in the memory cell; the second connection structure penetrates the dielectric structure and the first isolation layer in the second semiconductor structure, and is used to electrically connect the source structure of the third transistor to the second interconnect layer, wherein the third transistor is the first transistor in the first semiconductor structure that does not constitute the inverter.

8. The preparation method according to claim 7, characterized in that, A first connection structure is formed in the memory cell, comprising at least one of the following: Remove the dielectric structure and the first isolation layer between the first transistor and the second transistor in the same inverter to form a via and fill it with metal material to form source-drain contact metal; A dielectric layer is formed above the second transistor, and trenches are formed in the dielectric layer and filled with a metallic material to form a cross-coupled structure; Through holes are formed in the first isolation layer and filled with metallic material to form a through-hole structure.

9. The preparation method according to claim 7, characterized in that, A second connection structure is formed in the memory cell, including: The dielectric structure in the second semiconductor structure, the first isolation layer, and the dielectric structure in the first transistor are sequentially etched to form a deep hole and filled with metal material to form a second connection structure.

10. An electronic device, characterized in that, Includes circuit boards and semiconductor devices as described in any one of claims 1 to 6.

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