A three-terminal capacitorless dynamic random access memory cell, method of making and use thereof

Abstract

This invention discloses a three-terminal capacitor-free dynamic random access memory cell, its fabrication method, and its application, belonging to the field of semiconductor memory technology. This invention achieves vertical stacking of dual transistors, allowing adjacent memory cells to share the write transistor drain region and write bit line. With the same feature size, this invention occupies an area of ​​8F. 2 The area overhead and interconnect complexity of the storage array of the present invention are lower than those of the existing planar 2T0C storage array, effectively reducing the unit area overhead and increasing the integration density of the storage array.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, specifically relating to a three-terminal capacitorless dynamic random access memory cell, its fabrication method, and its application. Background Technology

[0002] Traditional silicon-based dynamic random access memories (DRAMs) use a 1-transistor-1-capacitor (1T1C) structure as their storage cells. With the continuation of Moore's Law, capacitor miniaturization has become a bottleneck for the continued shrinking of DRAMs. Simultaneously, the short-channel effect of transistors leads to charge leakage, prompting the international development of a novel capacitor-free DRAM concept. This cell typically employs a dual-transistor capacitor-free (2T0C) structure based on oxide semiconductor materials. The 2T0C cell uses the gate capacitance of the read transistor as the storage capacitor, eliminating the need for separate capacitor fabrication. Furthermore, thanks to the ultra-low off-state current of oxide semiconductor transistors, this cell effectively reduces storage charge leakage current, achieving extremely long data retention times. Existing capacitor-free DRAM cells have two word lines and two bit lines, resulting in complex cell interconnections, high hardware overhead, and challenges in layout and routing during array integration. Connecting the source of the read transistor to the gate of the write transistor eliminates the read word lines, forming a three-terminal 2T0C cell, thus reducing the complexity of the memory array interconnection. However, in existing three-terminal 2T0C cells, the transistors are on the same plane, occupying a large area and limiting the improvement of storage density. Summary of the Invention

[0003] The purpose of this invention is to propose a three-terminal capacitor-free dynamic random access memory cell structure, its fabrication method, and a three-dimensional integrated array, which can improve circuit integration density.

[0004] The technical solution of the present invention is as follows:

[0005] A three-terminal capacitorless dynamic random access memory cell includes a substrate, a write transistor, and a read transistor. An active layer for the write transistor is disposed on the substrate, and a gate dielectric layer for the write transistor is disposed on the active layer. A gate layer for the write transistor is disposed on the gate dielectric layer. A first dielectric layer covers the gate layer, the gate dielectric layer, and the active layer. A groove is provided within the first dielectric layer to expose the upper surface of the gate layer, and grooves are provided to expose the upper surfaces of the active layers on both sides of the gate layer, namely a gate groove, a source groove, and a drain groove. An internal interconnect layer is filled in the gate groove and the source groove. A write bitline layer is filled in the drain end groove. A write bitline layer and a read transistor gate layer are respectively disposed on the first dielectric layer. The write bitline layer covers the write bitline layer of the drain end groove of the write transistor, and the read transistor gate layer covers the cell internal interconnection layer of the source end groove of the write transistor. A read transistor gate dielectric layer is disposed on the read transistor gate layer. The read transistor active layer covers the read transistor gate dielectric layer and covers the cell internal interconnection layer of the write transistor gate groove, and is not connected to the write bitline layer. A second dielectric layer is disposed on the read transistor active layer, the first dielectric layer, and the write bitline layer. A groove is provided in the second dielectric layer to expose the upper surface of the drain end of the read transistor active layer. A read bitline layer is disposed on the groove and the second dielectric layer.

[0006] Furthermore, the active layer of the write transistor and the active layer of the read transistor are single-layer or multi-layer composite oxide semiconductor material thin films such as IGZO, IAZO, IGO, ITO, and ZnO.

[0007] Furthermore, the write transistor gate dielectric layer, the read transistor gate dielectric layer, the first dielectric layer, and the second dielectric layer are single-layer or multi-layer AlO. x HfO x SiO x TaO x ZrO x Composite dielectric thin films.

[0008] Furthermore, the materials of the write transistor gate layer, read transistor gate layer, write bit line layer, read bit line layer, and internal interconnect layer of the unit are single-layer or multi-layer conductor materials such as Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, and ITO.

[0009] Furthermore, the thickness range of the write transistor active layer, the read transistor active layer, the write transistor gate dielectric layer, and the read transistor gate dielectric layer is 5nm-1000nm.

[0010] Furthermore, a method for fabricating a three-terminal capacitorless dynamic random access memory cell is provided, the specific steps of which include:

[0011] 1) The active layer of the write transistor is formed on the substrate by deposition, photolithography and etching;

[0012] 2) A write transistor gate dielectric layer is formed on the active layer of the write transistor by deposition, photolithography and etching;

[0013] 3) The write transistor gate layer is formed on the write transistor gate dielectric layer by deposition, photolithography and etching;

[0014] 4) A first dielectric layer is formed by thin film deposition technology to cover the substrate, the active layer of the write transistor, the gate dielectric layer of the write transistor, and the gate layer of the write transistor;

[0015] 5) The gate of the write transistor and the upper surface of the active layer on both sides of the gate of the write transistor are exposed by photolithography and etching, respectively, and the gate groove, source groove and source groove of the write transistor are formed in the first dielectric layer.

[0016] 6) Deposit filling trenches; wherein, the cell internal interconnect layer is filled in the write transistor gate trench and the write transistor source trench; and the write bit line layer is filled in the write transistor drain trench;

[0017] 7) The read transistor gate layer and write bit line layer are formed on the first dielectric layer by deposition, photolithography and etching, and the read transistor gate layer and write bit line layer are not connected to each other. The write bit line layer covers the write bit line layer of the write transistor source end groove, and the read transistor gate layer covers the cell internal interconnect layer of the write transistor source end groove.

[0018] 8) The read transistor gate dielectric layer is formed on the read transistor gate layer by deposition, photolithography and etching, and is not connected to the write bit line layer;

[0019] 9) An active layer for read transistors is formed on the gate dielectric layer of the read transistor through deposition, photolithography and etching, and is not connected to the write bit line layer;

[0020] 10) Deposit a second dielectric layer covering the active layer of the read transistor, the first dielectric layer, and the write bit line layer;

[0021] 11) By photolithography and etching the second dielectric layer, the drain terminal of the active layer of the read transistor is exposed to form a groove;

[0022] 12) Deposit on the second dielectric layer and fill the grooves to form a read line layer.

[0023] Furthermore, an array integrating three-terminal capacitorless dynamic random access memory cells is provided. The array is composed of periodically arranged basic cell groups, each basic cell group consisting of two three-terminal capacitorless dynamic random access memory cells. The two write transistors are symmetrically distributed and share the same write transistor drain region. The basic cell groups are isolated by isolation slots. The write bit lines and read bit lines of all cells in the same row of the array are connected along the array row direction. The write word lines of all cells in the same column of the array are connected along the array row direction.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] This invention enables vertical stacking of dual transistors, allowing adjacent memory cells to share the write transistor drain region and write bit line. With the same feature size, this invention occupies an area of ​​8F. 2 The area overhead and interconnect complexity of the storage array of the present invention are lower than those of the existing planar 2T0C storage array, effectively reducing the cell area overhead and increasing the integration density of the storage array. Attached Figure Description

[0026] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0027] Figure 1 This is a schematic diagram of the three-terminal capacitorless dynamic random access memory cell structure of the present invention. In the diagram, 1 is the substrate, 2 is the active layer of the write transistor, 3 is the gate dielectric layer of the write transistor, 4 is the gate layer of the write transistor, 5 is the dielectric layer, 6 is the internal interconnect layer of the cell, 7 is the gate layer of the read transistor, 8 is the write bit line layer, 9 is the gate dielectric layer of the read transistor, 10 is the active layer of the write transistor, and 11 is the read bit line layer.

[0028] Figure 2 This is a circuit diagram of the three-terminal capacitorless dynamic random access memory cell of the present invention.

[0029] Figures 3-13 The diagram shows the structure obtained in each step of the preparation method provided by this invention.

[0030] Figure 14 The layout of the 2×2 array composed of the cells provided in this invention is provided.

[0031] Figure 15 for Figure 1-14 Legend of the diagram. Detailed Implementation

[0032] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

[0034] The accompanying drawings illustrate various structural schematics according to examples of this disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positions, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0035] like Figure 1 and Figure 2 As shown, the three-terminal capacitorless dynamic random access memory cell structure of the present invention includes: a substrate 1; a write transistor active layer 2 disposed on the upper surface of the substrate; a write transistor gate dielectric layer 3 disposed on the upper surface of the write transistor active layer; a write transistor gate layer 4 disposed on the upper surface of the write transistor dielectric layer; a first dielectric layer 5 covering the gate layer, the gate dielectric layer, and the write transistor active layer, and having a groove exposing the upper surface of the write transistor gate layer, and grooves exposing the upper surface of the active layer on both sides of the write transistor gate layer, which are not connected to each other, and are respectively the write transistor source end groove and the write transistor drain end groove; and an internal interconnect layer 6 filling the write transistor gate groove. The following layers are provided: a write transistor source end recess; a write bit line layer 8, filling the write transistor drain end recess and disposed on the first dielectric layer; a read transistor gate layer 7, disposed on the upper surface of the first dielectric layer, covering the internal interconnect layer of the write transistor source end recess unit; a read transistor gate dielectric layer 9, covering the read transistor gate layer; a read transistor active layer 10, covering the read transistor gate dielectric layer; a second dielectric layer 5, covering the above-mentioned read transistor active layer, write bit line layer and the first dielectric layer, and having a recess that exposes the upper surface of the drain end of the read transistor active layer; and a read bit line layer 11, filling the recess exposed on the upper surface of the read transistor active layer and disposed on the upper surface of the second dielectric layer.

[0036] The present invention provides a method for fabricating a three-terminal capacitor-free dynamic random access memory cell structure, combined with Figure 3-13 The specific process is as follows.

[0037] 1) Use a silicon substrate, such as Figure 3 As shown.

[0038] 2) A write transistor active layer with a thickness of 5-1000 nm is formed on the substrate by deposition, photolithography, and etching. The active layer material is a single-layer or multi-layer composite oxide semiconductor material, such as IGZO, IAZO, IGO, ITO, ZnO, etc. Figure 4 As shown.

[0039] 3) A write transistor gate dielectric layer with a thickness of 5-1000 nm is formed on the active layer of the write transistor through deposition, photolithography, and etching. The gate dielectric layer is a single-layer or multi-layer composite dielectric material thin film, such as AlO. x HfO x SiO x TaO x ZrO x etc., such as Figure 5 As shown.

[0040] 4) A write transistor gate layer is formed on the write transistor gate dielectric layer by deposition, photolithography, and etching. The thickness is 5-1000 nm. The gate layer is a single-layer or multi-layer conductor material, such as Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, etc. Figure 6 As shown.

[0041] 5) A first dielectric layer is formed using thin-film deposition technology to cover the substrate, the active layer of the write transistor, the gate dielectric layer of the write transistor, and the gate layer of the write transistor. The thickness of the first dielectric layer is 20-1000 nm, and the material is a single-layer or multi-layer composite dielectric thin film, such as AlO. x HfO x SiO x TaO x ZrO x etc., such as Figure 7 As shown.

[0042] 6) Grooves are formed in the first dielectric layer by photolithography and etching, exposing the gate of the write transistor and the upper surfaces of the active layers on both sides of the gate, respectively. The grooves are then filled with deposited material. The cell interconnect layer is filled in the gate groove and the source groove of the write transistor; the write bit line layer is filled in the drain groove of the write transistor. Figure 8 As shown.

[0043] 7) The read transistor gate layer and write bit line layer are formed by deposition, photolithography, and etching. The read transistor gate layer and write bit line layer are not connected to each other. The write bit line layer covers the write bit line layer of the write transistor source end recess, and the read transistor gate layer covers the internal interconnect layer of the write transistor source end recess. The thickness of the gate layer and write bit line layer is 5-1000nm, and the materials are single-layer or multi-layer conductor materials, such as Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, etc. Figure 9 As shown.

[0044] 8) A read transistor gate dielectric layer with a thickness of 5-1000 nm is formed on the read transistor gate layer through deposition, photolithography, and etching. The read transistor gate layer is a single-layer or multi-layer conductive material, such as Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, etc. Figure 10 As shown.

[0045] 9) A read transistor active layer with a thickness of 5-1000 nm is formed on the read transistor gate dielectric layer through deposition, photolithography, and etching. The active layer material is a single-layer or multi-layer composite oxide semiconductor material, such as IGZO, IAZO, IGO, ITO, ZnO, etc., and it is not connected to the write bit line layer; Figure 11 As shown

[0046] 10) Deposit a second dielectric layer covering the read transistor dielectric layer, the first dielectric layer, and the write bit line layer. The second dielectric layer and the first dielectric layer have the same material thickness, such as... Figure 12 As shown.

[0047] 11) A groove is formed in the second dielectric layer by photolithography and etching to expose the drain terminal of the active layer of the read transistor;

[0048] 12) Deposit and fill the grooves on the second dielectric layer, and form a read line layer with a thickness of 5-1000 nm by photolithography and etching. The gate layer is a single-layer or multi-layer conductor material, such as Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, etc. Figure 13 As shown.

[0049] This invention proposes a 2×2 array of storage cells, such as... Figure 14 As shown, two adjacent memory cells in the array form a basic cell group. Within each basic cell group, two write transistors are symmetrically distributed and share the same write transistor drain region. The basic cell groups are isolated by isolation slots. The write bit lines and read bit lines of all cells in the same row of the array are connected along the array row direction; the write word lines of all cells in the same column of the array are connected along the array row direction.

[0050] The area overhead of this invention is 8F. 2 Compared to the traditional 2T0C planar unit which occupies an area of ​​20F 2 Compared to other methods, this significantly reduces area overhead and increases array integration density.

[0051] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A three-terminal capacitorless dynamic random access memory cell, comprising a substrate, a write transistor, and a read transistor, characterized in that, A write transistor active layer is disposed on the substrate, and a write transistor gate dielectric layer is disposed on the write transistor active layer; a write transistor gate layer is disposed on the write transistor gate dielectric layer, and a first dielectric layer covers the write transistor gate layer, the write transistor gate dielectric layer, and the write transistor active layer. A groove is provided within the first dielectric layer to expose the upper surface of the write transistor gate layer, and grooves are provided to expose the upper surfaces of the active layers on both sides of the write transistor gate layer, namely a write transistor gate groove, a write transistor source groove, and a write transistor drain groove; an internal interconnect layer is filled in the write transistor gate groove and the write transistor source groove; a write bit line layer is filled in the write transistor drain groove. A write bit line layer and a read transistor gate layer are respectively disposed on the dielectric layer, wherein the write bit line layer covers the write bit line layer of the write transistor drain end groove, and the read transistor gate layer covers the cell internal interconnect layer of the write transistor source end groove; a read transistor gate dielectric layer is disposed on the read transistor gate layer, a read transistor active layer covers the read transistor gate dielectric layer, and the read transistor active layer covers the cell internal interconnect layer of the write transistor gate groove, and is not connected to the write bit line layer; a second dielectric layer is disposed on the read transistor active layer, the first dielectric layer, and the write bit line layer, and a groove is provided in the second dielectric layer to expose the upper surface of the drain end of the read transistor active layer; a read bit line layer is disposed on the groove and the second dielectric layer.

2. The three-terminal capacitorless dynamic random access memory cell as described in claim 1, characterized in that, The active layers of the write transistor and the active layers of the read transistor are single-layer or multi-layer IGZO, IAZO, IGO, ITO, and ZnO composite oxide semiconductor thin films.

3. The three-terminal capacitorless dynamic random access memory cell as described in claim 1, characterized in that, The write transistor gate dielectric layer, read transistor gate dielectric layer, first dielectric layer, and second dielectric layer are single-layer or multi-layer AlO. x HfO x SiO x TaO x ZrO x Composite dielectric thin film.

4. The three-terminal capacitorless dynamic random access memory cell as described in claim 1, characterized in that, The materials of the write transistor gate layer, read transistor gate layer, write bit line layer, read bit line layer, and internal interconnect layer of the unit are single-layer or multi-layer Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, and ITO conductor materials.

5. The three-terminal capacitorless dynamic random access memory cell as described in claim 1, characterized in that, The thickness range of the write transistor active layer, read transistor active layer, write transistor gate dielectric layer, and read transistor gate dielectric layer is 5nm-1000nm.

6. The method for fabricating a three-terminal capacitorless dynamic random access memory cell as described in claim 1, specifically comprising the following steps: 1) The active layer of the write transistor is formed on the substrate by deposition, photolithography and etching; 2) A write transistor gate dielectric layer is formed on the active layer of the write transistor by deposition, photolithography and etching; 3) The write transistor gate layer is formed on the write transistor gate dielectric layer by deposition, photolithography and etching; 4) A first dielectric layer is formed by thin film deposition technology to cover the substrate, the active layer of the write transistor, the gate dielectric layer of the write transistor, and the gate layer of the write transistor; 5) The gate of the write transistor and the upper surface of the active layer on both sides of the gate of the write transistor are exposed by photolithography and etching, respectively, and the gate groove, source groove and source groove of the write transistor are formed in the first dielectric layer. 6) Deposit filling trenches; wherein, the cell internal interconnect layer is filled in the write transistor gate trench and the write transistor source trench; and the write bit line layer is filled in the write transistor drain trench; 7) The read transistor gate layer and write bit line layer are formed on the first dielectric layer by deposition, photolithography and etching, and the read transistor gate layer and write bit line layer are not connected to each other. The write bit line layer covers the write bit line layer of the write transistor source end groove, and the read transistor gate layer covers the cell internal interconnect layer of the write transistor source end groove. 8) The read transistor gate dielectric layer is formed on the read transistor gate layer by deposition, photolithography and etching, and is not connected to the write bit line layer; 9) An active layer for read transistors is formed on the gate dielectric layer of the read transistor through deposition, photolithography and etching, and is not connected to the write bit line layer; 10) Deposit a second dielectric layer covering the active layer of the read transistor, the first dielectric layer, and the write bit line layer; 11) By photolithography and etching the second dielectric layer, the drain terminal of the active layer of the read transistor is exposed to form a groove; 12) Deposit on the second dielectric layer and fill the grooves to form a read line layer.

7. A three-terminal capacitorless dynamic random access memory array, characterized in that, The array is composed of periodically arranged basic unit groups, each basic unit group consisting of two three-terminal capacitorless dynamic random access memory cells as described in claim 1. The two write transistors are symmetrically distributed and share the same write transistor drain region. The basic unit groups are isolated by isolation slots. The write bit lines and read bit lines of all cells in the same row of the array are connected along the array row direction. The write word lines of all cells in the same column of the array are connected along the array row direction.

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