Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and its manufacturing method, as well as an electronic device, are disclosed. The semiconductor device includes: a plurality of vertically stacked memory cells; bit lines extending vertically through different layers of memory cells; a plurality of word lines distributed in different layers, the word lines and bit lines being distributed along a first direction parallel to the substrate; each word line includes a vertically spaced first horizontal portion and a second horizontal portion of an integral structure, and a connecting portion disposed between the first horizontal portion and the second horizontal portion, the first horizontal portion and the second horizontal portion extending along a second direction parallel to the substrate; a transistor includes a semiconductor layer disposed between the first horizontal portion and the second horizontal portion; the semiconductor layer forms a first annular structure with an opening direction parallel to the first direction, and the connecting portion is disposed on two opposite sides of the semiconductor layer along the second direction. The solution provided by the embodiments of this disclosure can avoid the semiconductor layer being affected by word lines of adjacent memory cells along a direction perpendicular to the substrate, thereby improving transistor performance.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device.

[0006] This application provides a semiconductor device, including:

[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0008] Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate;

[0009] Multiple word lines are distributed on different layers. The word lines and bit lines are distributed along a first direction parallel to the substrate. Each word line includes a first horizontal portion and a second horizontal portion spaced apart along a direction perpendicular to the substrate, and a connecting portion disposed between the first horizontal portion and the second horizontal portion to connect them. The first horizontal portion and the second horizontal portion extend along a second direction parallel to the substrate. The first horizontal portion, the second horizontal portion, and the connecting portion are an integral structure. The first direction and the second direction intersect.

[0010] The memory cell includes a transistor, and the transistor includes a semiconductor layer connecting the bit line; the semiconductor layer is disposed between the first horizontal portion and the second horizontal portion; the semiconductor layer forms a first annular structure with the opening direction parallel to the first direction, the first horizontal portion is distributed on the side of the semiconductor layer away from the substrate, the second horizontal portion is distributed on the side of the semiconductor layer facing the substrate, and the connecting portion is distributed on both sides of the semiconductor layer disposed opposite to each other along the second direction.

[0011] In some embodiments, the semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along the first direction and the second direction; a first isolation layer is disposed between adjacent semiconductor layers along the second direction, and the two sides of the first isolation layer disposed opposite to each other along the second direction are covered by the connection portion, the side of the first isolation layer away from the substrate is connected to the first horizontal portion, and the side of the first isolation layer facing the substrate is connected to the second horizontal portion.

[0012] In some embodiments, the first horizontal portion and the second horizontal portion are provided with a recessed structure located between adjacent bit lines along the second direction on the side facing the bit line.

[0013] In some embodiments, the semiconductor layer has first protrusions on both sides disposed opposite to each other along the second direction, and the distance between the two sides disposed opposite to each other along the second direction decreases sequentially from the location of the first protrusions away from the bit line.

[0014] In some embodiments, the semiconductor layer includes two ends disposed opposite each other along the first direction, and the bit line contacts at least one of the ends of the semiconductor layer and an inner sidewall adjacent to the end.

[0015] In some embodiments, the bit line forms a second annular structure or a solid structure extending in a direction perpendicular to the substrate, and the second annular structure or solid structure includes a plurality of second protrusions corresponding one-to-one with the plurality of memory cells, the second protrusions extending into the first annular structure formed by the semiconductor layer of the transistor of the corresponding memory cell and filling the opening of the first annular structure facing the bit line.

[0016] In some embodiments, the transistor further includes a first electrode forming a cylindrical structure with an opening away from the semiconductor layer, and the bottom wall of the cylindrical structure is connected to the end of the first annular structure away from the bit line. The bottom wall of the cylindrical structure is provided with a third protrusion that extends into the first annular structure and connects to the inner sidewall of the first annular structure and fills the opening of the first annular structure away from the bit line.

[0017] In some embodiments, a second insulating layer is filled within the space enclosed by the inner wall of the first annular structure, the first electrode, and the bit line.

[0018] In some embodiments, the transistor further includes a gate insulating layer disposed between the word line and the semiconductor layer and surrounding the semiconductor layer, and the gate insulating layers of a plurality of transistors in the same column distributed along a second direction are disconnected from each other, the gate insulating layers of a plurality of transistors distributed at the same position in different layers are connected to form an integral structure on the side facing the bit line, and the integral structure formed by the plurality of gate insulating layers is connected to the sidewall of the bit line.

[0019] In some embodiments, the semiconductor device further includes a third isolation layer disposed between adjacent bit lines along a second direction and extending through multiple layers, the third isolation layer being connected to the bit lines, the connection portion, and the first isolation layer.

[0020] In some embodiments, the storage cell further includes a capacitor, the capacitor including a second capacitor electrode and a dielectric layer disposed between the second capacitor electrode and a first electrode, the dielectric layer being distributed on the inner bottom wall, inner side wall and outer side wall of the cylindrical structure, the second capacitor electrode filling the cylindrical structure and filling the region between adjacent first electrodes along a second direction, and being distributed on the outer side wall of the cylindrical structure parallel to the substrate.

[0021] This disclosure provides a method for manufacturing a semiconductor device, including:

[0022] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0023] A first trench and a second trench are formed that penetrate the stacked structure along a direction perpendicular to the substrate. The first trench and the second trench extend along a second direction parallel to the substrate, and the first trench and the second trench are spaced apart along a first direction parallel to the substrate. The first direction and the second direction intersect. A first dummy layer is formed that fills the first trench and the second trench.

[0024] A plurality of first holes and a plurality of second holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction. The first holes penetrate the first trench along the first direction and the size of the first holes along the first direction is larger than the size of the first trench along the first direction. The plurality of second holes are spaced apart along the second direction. The second holes penetrate the second trench along the first direction and the size of the second holes along the first direction is larger than the size of the second trench along the first direction. A second insulating layer is formed covering the bottom wall and sidewalls of the first holes and the second holes, and a second dummy layer is formed filling the first holes and the second holes.

[0025] The first dummy layer in the second trench is etched away to form a plurality of third holes spaced apart by the second holes. The first sacrificial layer is etched along a direction parallel to the substrate based on the plurality of third holes to form a plurality of first grooves and to form a third dummy layer that fills the first grooves and the third holes.

[0026] The second insulating layer and the second dummy layer are etched away to expose the first hole and the second hole. The first sacrificial layer is etched away based on the first hole and the second hole to form a channel that extends in the second direction between adjacent first insulating layers and between the third dummy layer and the first trench.

[0027] Word lines and multiple semiconductor layers are formed in the channel. The word lines include first horizontal portions and second horizontal portions spaced apart along a direction perpendicular to the substrate, and a connecting portion disposed between the first horizontal portions and the second horizontal portions to connect the first horizontal portions and the second horizontal portions. The first horizontal portions and the second horizontal portions extend along a second direction parallel to the substrate, and the first horizontal portions, the second horizontal portions and the connecting portion are an integral structure. The semiconductor layer is disposed between the first horizontal portions and the second horizontal portions. The semiconductor layer forms a first annular structure with an opening direction parallel to the first direction. The first horizontal portions are distributed on the side of the semiconductor layer away from the substrate, the second horizontal portions are distributed on the side of the semiconductor layer facing the substrate, and the connecting portions are distributed on two opposite sides of the semiconductor layer along the second direction.

[0028] In some embodiments, forming word lines and multiple semiconductor layers in the channel includes:

[0029] A first barrier layer is formed covering the inner wall of the first hole, the second hole, and the channel; and a second sacrificial layer is formed to fill the channel. The second sacrificial layer in the channel is etched based on the first hole and the second hole, such that the second sacrificial layer in the channel forms a plurality of sacrificial sub-layers spaced apart along a second direction, forming a fourth dummy layer filling the channel.

[0030] The first dummy layer in the first trench is etched away to form a plurality of fourth holes spaced apart by the first hole. The sacrificial sublayer is etched away based on the fourth holes and the fourth dummy layer is etched away, while a portion of the fourth dummy layer is retained to form a second groove, wherein the retained fourth dummy layer is connected to the first hole and the second hole.

[0031] The first barrier layer in the channel is removed by etching based on the fourth hole and the second groove;

[0032] A first conductive film is formed covering the inner wall of the channel and the sidewall of the fourth dummy layer parallel to the substrate and the sidewall opposite to the second direction. The first conductive film is etched based on the fourth hole so that the first conductive film on the sidewall of the second groove is removed at a distance less than or equal to a first preset length from the opening of the second groove, thereby forming a first conductive layer.

[0033] A gate insulating structure layer and a semiconductor structure layer are formed that sequentially cover the inner wall of the channel and the sidewall of the fourth dummy layer that is parallel to the sidewall of the substrate and opposite to the sidewall of the fourth dummy layer along the second direction.

[0034] A bit line extending perpendicular to the substrate direction is formed in the fourth hole, the bit line extending into the second groove of the multilayer and connecting to the multilayer semiconductor structure layer;

[0035] The third dummy layer in the third hole and the first groove is etched away to expose the first conductive layer. The exposed first conductive layer is etched to form the word line. The semiconductor structure layer is etched so that the semiconductor structure layer opens on the side away from the bit line to form a plurality of semiconductor layers.

[0036] In some embodiments, the method further includes:

[0037] The first capacitor electrode, which covers the sidewall of the first groove and extends into the channel and is connected to the semiconductor layer, is located in the first groove.

[0038] Replace the fourth virtual layer with the first isolation layer;

[0039] The inner wall of the first capacitor electrode, the outer wall parallel to the substrate, and the two outer walls opposite to each other along the second direction are exposed to form a second capacitor electrode distributed on the inner wall of the first capacitor electrode, the outer wall parallel to the substrate, and the two outer walls opposite to each other along the second direction.

[0040] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0041] This application includes a semiconductor device and a method for manufacturing the same, and an electronic device. The semiconductor device includes: a plurality of memory cells stacked in different layers along a direction perpendicular to a substrate; bit lines extending through the memory cells in different layers along a direction perpendicular to the substrate; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate; each word line includes a first horizontal portion and a second horizontal portion spaced apart along a direction perpendicular to the substrate, and a connecting portion disposed between the first horizontal portion and the second horizontal portion connecting the first horizontal portion and the second horizontal portion, the first horizontal portion and the second horizontal portion extending along a second direction parallel to the substrate, the first horizontal portion, the second horizontal portion and the connecting portion being an integral structure; the first direction and the second direction intersect; each memory cell includes a transistor, the transistor including a semiconductor layer connecting the bit lines; the semiconductor layer is disposed between the first horizontal portion and the second horizontal portion; the semiconductor layer forms a first annular structure with an opening direction parallel to the first direction, the first horizontal portion being distributed on the side of the semiconductor layer away from the substrate, the second horizontal portion being distributed on the side of the semiconductor layer facing the substrate, and the connecting portion being distributed on two opposite sides of the semiconductor layer along the second direction. The solution provided in this embodiment of the present disclosure, by setting a first horizontal portion and a second horizontal portion that are set opposite to each other, can avoid the semiconductor layer of the memory cell being affected by the word lines of adjacent memory cells along the direction perpendicular to the substrate, thereby improving transistor performance. In addition, the presence of a surrounding channel can increase the transistor's on-state current.

[0042] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0044] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0045] Figures 1A to 1F These are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' direction parallel to the substrate, the BB' direction, the CC' direction perpendicular to the substrate, the DD' direction, the EE' direction, and the FF' direction; Figure 1G This is a cross-sectional view along the A1A1' direction parallel to the substrate; Figure 1H for Figure 1A A magnified view of a portion of the image. Figure 1I for Figure 1C A magnified view of a portion of the image. Figure 1J for Figure 1D A magnified view of a portion of the image;

[0046] Figures 2A to 2F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the first and second holes are provided in some embodiments;

[0047] Figures 3A to 3C These are cross-sectional views along the AA', BB', and DD' directions after the formation of the first groove, provided in some embodiments.

[0048] Figures 4A to 4F Cross-sectional views along the AA', BB', CC', DD', EE' and FF' directions after forming the channel and the first transverse groove, respectively, according to some embodiments;

[0049] Figures 5A to 5F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the first barrier layer and the second sacrificial layer are provided in some embodiments;

[0050] Figures 6A to 6F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after forming the sacrificial sublayer and the fourth dummy layer, respectively, provided in some embodiments;

[0051] Figures 7A to 7F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the second groove is formed, provided in some embodiments;

[0052] Figures 8A to 8D Cross-sectional views along the AA', CC', DD', and FF' directions respectively, after etching to remove the first barrier layer in the channel provided in some embodiments;

[0053] Figures 9A to 9E Cross-sectional views along the AA', BB', CC', DD', and FF' directions after the formation of the first conductive layer are provided in some embodiments;

[0054] Figures 10A to 10F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the gate insulating structure layer and the semiconductor structure layer;

[0055] Figures 11A to 11DThese are cross-sectional views along the AA', BB', DD', and EE' directions after the bit lines are formed, provided in some embodiments.

[0056] Figures 12A to 12C Cross-sectional views along the AA', BB', and DD' directions after the exposed semiconductor structure layer is provided in some embodiments;

[0057] Figures 13A to 13C Cross-sectional views along the AA', BB', and DD' directions after the formation of the first capacitor electrode are provided in some embodiments;

[0058] Figures 14A to 14E Cross-sectional views along the AA', BB', CC', EE', and FF' directions after exposing the first and second holes, respectively, provided in some embodiments;

[0059] Figures 15A to 15E Cross-sectional views along the AA', BB', CC', EE', and FF' directions after the formation of the first isolation layer are provided in some embodiments;

[0060] Figures 16A to 16D Cross-sectional views along the AA', BB', EE', and FF' directions after the first hole is exposed, provided in some embodiments;

[0061] Figures 17A to 17E The following are cross-sectional views along the AA', BB', DD', EE', and FF' directions after the first capacitor electrode 41 is exposed, respectively, according to some embodiments. Detailed Implementation

[0062] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0063] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0064] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0065] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0066] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0067] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0068] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0069] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0070] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0071] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0072] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0073] Figures 1A to 1F These are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' direction, BB' direction, CC' direction, DD' direction, EE' direction, and FF' direction, which are parallel to the substrate 1. Figure 1G This is a cross-sectional view along the A1A1' direction parallel to substrate 1. Figure 1H for Figure 1A A magnified view of a portion of the image. Figure 1I for Figure 1C A magnified view of a portion of the image. Figure 1J for Figure 1D A magnified view of a portion of the image.

[0074] like Figures 1A to 1J As shown, this disclosure provides a semiconductor device, including:

[0075] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;

[0076] Bit line 30 extends through the memory cells in different layers along a direction perpendicular to the substrate 1;

[0077] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X parallel to the substrate 1. Each word line 40 includes a first horizontal portion 40a and a second horizontal portion 40b spaced apart along a direction perpendicular to the substrate 1, and a connecting portion 40c disposed between the first horizontal portion 40a and the second horizontal portion 40b to connect them. The first horizontal portion 40a and the second horizontal portion 40b extend along a second direction Y parallel to the substrate 1. The first horizontal portion 40a, the second horizontal portion 40b, and the connecting portion 40c can be an integral structure. The first direction X and the second direction Y intersect.

[0078] The memory cell includes a transistor, and the transistor includes a semiconductor layer 23 connecting the bit line; the semiconductor layer 23 is disposed between the first horizontal portion 40a and the second horizontal portion 40b; the semiconductor layer 23 forms a first annular structure with the opening direction parallel to the first direction X, the first horizontal portion 40a is distributed on the side of the semiconductor layer 23 away from the substrate 1, the second horizontal portion 40b is distributed on the side of the semiconductor layer 23 facing the substrate 1, and the connecting portion 40c is distributed on both sides of the semiconductor layer 23 that are disposed opposite to each other along the second direction Y.

[0079] The solution provided in this embodiment of the present disclosure, by setting a first horizontal portion and a second horizontal portion that are set opposite to each other, can avoid the semiconductor layer of the memory cell being affected by the word lines of adjacent memory cells along the direction perpendicular to the substrate, thereby improving transistor performance. In addition, the presence of a surrounding channel can increase the transistor's on-state current.

[0080] In some embodiments, the semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along the first direction X and the second direction Y; a first isolation layer 19 is disposed between adjacent semiconductor layers 23 along the second direction Y, and the two sides of the first isolation layer 19 disposed opposite to each other along the second direction Y are covered by the connection portion 40c, the side of the first isolation layer 19 facing away from the substrate 1 is connected to the first horizontal portion 40a, and the side facing the substrate 1 is connected to the second horizontal portion 40b. The solution provided in this embodiment can isolate the semiconductor layers 23 by means of the first isolation layer 19, without removing parasitic MOS by cutting the channel material, achieving a larger channel width, increasing on-state current, and avoiding damage to the channel by eliminating the need for a cutting process, thus improving transistor performance.

[0081] In some embodiments, such as Figure 1G As shown, the first horizontal portion 40a and the second horizontal portion 40b are provided with a recessed structure on the side facing the bit line 30, located between adjacent bit lines 30 along the second direction Y. In other words, the first horizontal portion 40a and the second horizontal portion 40b have protrusions at the positions corresponding to the bit lines 30. Figure 1G Only the first horizontal section 40a is shown in the figure; the structure of the second horizontal section 40b can be referenced from that of the first horizontal section 40a.

[0082] In some embodiments, such as Figure 1H As shown, the semiconductor layer 23 has first protrusions on both sides that are opposite each other along the second direction Y. From the position of the first protrusion away from the bit line 30, the distance between the two sides of the semiconductor layer 23 that are opposite each other along the second direction Y decreases sequentially.

[0083] In some embodiments, the semiconductor layer 23 includes two ends disposed opposite each other along the first direction X, and the bit line 30 contacts at least one of the ends of the semiconductor layer 23 and an inner sidewall adjacent to the end.

[0084] In some embodiments, the bit line 30 forms a second annular structure or a solid structure extending perpendicular to the substrate 1, and the second annular structure or solid structure includes a plurality of second protrusions corresponding one-to-one with the plurality of memory cells. The second protrusions extend into the first annular structure formed by the semiconductor layer 23 of the transistor of the corresponding memory cell, filling the opening of the first annular structure facing the bit line 30. Figure 1H and Figure 1J As shown, bit line 30 can extend into the first annular structure, thereby increasing the contact area between bit line 30 and semiconductor layer 23.

[0085] In some embodiments, the transistor further includes a first electrode (which also serves as a first capacitor electrode 41 of a capacitor), the first electrode forming a cylindrical structure with an opening away from the semiconductor layer 23, and the bottom wall of the cylindrical structure being connected to the end of the first annular structure away from the bit line 30, and the bottom wall of the cylindrical structure having a third protrusion extending into the first annular structure and connecting to the inner sidewall of the first annular structure and filling the opening of the first annular structure away from the bit line 30, such as... Figure 1H and Figure 1J As shown in the figure. In the solution provided in this embodiment, the first electrode can extend into the first annular structure, thereby increasing the contact area between the first electrode and the semiconductor layer 23.

[0086] In some embodiments, the space enclosed by the inner sidewall of the first annular structure, the first electrode, and the bit line 30 is filled with a second insulating layer 6.

[0087] In some embodiments, the transistor further includes a gate insulating layer 24 disposed between the first horizontal portion 40a and the second horizontal portion 40b and surrounding the semiconductor layer 23, and the gate insulating layers 24 of a plurality of transistors in the same column distributed along the second direction Y are disconnected, and the gate insulating layers 24 of a plurality of transistors distributed at the same position in different layers are connected on the side facing the bit line 30 to form an integral structure.

[0088] In some embodiments, the semiconductor device may further include a third isolation layer 21 disposed between adjacent bit lines 30 along the second direction Y, the third isolation layer 21 being connected to the bit lines 30, the connection portion 40c, and the first isolation layer 19.

[0089] In some embodiments, the storage cell may further include a capacitor, which may include a second capacitor electrode 42 and a dielectric layer 43 disposed between the second capacitor electrode 42 and a first electrode. The dielectric layer 43 is distributed on the inner bottom wall, inner side wall and outer side wall of the cylindrical structure. The second capacitor electrode 42 fills the cylindrical structure and the area between adjacent first electrodes along the second direction Y, and is distributed on the outer side wall of the cylindrical structure parallel to the substrate 1.

[0090] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0091] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0092] 1) Form the first hole K1 and the second hole K2;

[0093] A protective layer film is grown on the substrate 1 to form a protective layer 9; the protective layer film may be silicon germanium (SiGe) or the like, which can protect the substrate 1;

[0094] A first insulating film and a first sacrificial layer film are sequentially and alternately deposited on the protective layer 9 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0095] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a first trench T1 and a second trench T2 that penetrate the stacked structure. The first trench T1 extends along the second direction Y, and the second trench T2 extends along the second direction Y. The first trench T1 and the second trench T2 are distributed at intervals along the first direction X.

[0096] After depositing the first dummy layer film, it is ground flat to form the first dummy layer 71 that fills the first trench T1 and the second trench T2;

[0097] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a first hole K1 and a second hole K2 penetrating the stacked structure. The first hole K1 and the second hole K2 can be strip-shaped holes extending along a first direction X. A plurality of first holes K1 are spaced apart along a second direction Y, and a plurality of second holes K2 are spaced apart along a second direction Y. The first holes K1 penetrate the first trench T1 along the first direction X, and the second holes K2 penetrate the second trench T2 along the first direction X. The first holes K1 and the second holes K2 are spaced apart along the first direction X. The plurality of first holes K1 divide the first dummy layer 71 in the first trench T1 into multiple segments, and the plurality of second holes K2 divide the first dummy layer 71 in the second trench T2 into multiple segments.

[0098] After sequentially depositing the second insulating film and the second dummy layer film, the layers are smoothed to form a second insulating layer 12 covering the inner walls of the first hole K1 and the second hole K2, and a second dummy layer 72 filling the first hole K1 and the second hole K2; as shown. Figures 2A to 2F As shown, Figures 2A to 2F The images are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the first hole K1 and the second hole K2, respectively, provided in some embodiments.

[0099] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0100] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to twelfth insulating films are similar and will not be described in detail.

[0101] In some embodiments, the first sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0102] In some embodiments, the first dummy layer film and the second dummy layer film may be films with an etching selectivity ratio to the first insulating film and the first sacrificial layer film, such as polysilicon. The materials of the subsequent third to seventh dummy layer films are similar to those of the first dummy layer film, and will not be described in detail here.

[0103] 2) Form the first groove A1;

[0104] A third insulating film is deposited to form a third insulating layer 13 covering the aforementioned structure;

[0105] The third insulating layer 13 is etched to expose the first dummy layer 71 in the second trench T2. The first dummy layer 71 in the second trench T2 is removed by etching to form a plurality of third holes K3. The third holes K3 are located between adjacent second holes K2, and the sidewalls of the third holes K3 expose the second insulating layer 12.

[0106] Based on the third hole K3, the first sacrificial layer 10 is etched along a direction parallel to the substrate 1 to form a plurality of first grooves A1. The bottom wall of the first groove A1 is the first sacrificial layer 10, the sidewall perpendicular to the substrate 1 is the second insulating layer 12 in the adjacent second hole K2 along the second direction Y, and the sidewall parallel to the substrate 1 is two adjacent layers of first insulating layer 11. The first sacrificial layer 10 is etched to a position flush or approximately flush with the two sidewalls of the second hole K2 that are opposite each other along the first direction X. Figures 3A to 3C As shown, Figures 3A to 3C These are cross-sectional views along the AA', BB', and DD' directions after the formation of the first groove A1 provided in some embodiments. When etching the first sacrificial layer 10 based on the third hole K3 along a direction parallel to the substrate 1, etching can be performed in two opposite directions. Based on the same third hole, two first grooves A1 are formed in the same layer, and subsequently, the first capacitor electrodes 41 of two capacitors are formed in the two first grooves A1 respectively.

[0107] 3) Form channel B1 and the first transverse groove L1;

[0108] After depositing the third dummy layer film, it is ground flat. The third dummy layer film fills the first groove A1 and the third hole K3 to form the third dummy layer 73.

[0109] The second insulating layer 12 and the second dummy layer 72 are etched away, exposing the first hole K1 and the second hole K2. Based on the first hole K1 and the second hole K2, the first sacrificial layer 10 is etched away, forming a channel B1 extending along the second direction Y and a first transverse trench L1 extending along the second direction Y. The channel B1 communicates with the first hole K1 and the second hole K2. Figures 4A to 4F As shown, Figures 4A to 4F The following are cross-sectional views along the directions AA', BB', CC', DD', EE', and FF' after forming the channel B1 and the first transverse groove L1, respectively, according to some embodiments.

[0110] 4) Forming the first barrier layer 8 and the second sacrificial layer 7;

[0111] A first barrier layer film and a second sacrificial layer film are deposited sequentially. The first barrier layer film covers the inner walls of the first hole K1, the second hole K2, the channel B1, and the first transverse trench L1. The second sacrificial layer film fills the channel B1 but does not completely fill the first hole K1 and the second hole K2, forming a first barrier layer 8 and a second sacrificial layer 7. Figures 5A to 5F As shown, Figures 5A to 5F The images are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the first barrier layer 8 and the second sacrificial layer 7, respectively, according to some embodiments.

[0112] In some embodiments, the first barrier layer film may be an aluminum oxide, copper-doped silicon nitride, or a film layer that has a certain etching selectivity with the first insulating film.

[0113] In some embodiments, the second sacrificial layer film may be a film layer with a certain etching selectivity ratio to the first barrier layer film, such as SiN.

[0114] 5) Formation of a sacrificial sublayer and a fourth dummy layer 74;

[0115] The second sacrificial layer 7 in the first hole K1 and the second hole K2 is removed by etching. Based on the first hole K1 and the second hole K2, the second sacrificial layer 7 in the channel B1 and the first transverse trench L1 is etched, so that the second sacrificial layer 7 in the channel B1 and the first transverse trench L1 forms a plurality of sacrificial sub-layers distributed at intervals along the second direction Y. At this time, the area where the second sacrificial layer 7 is connected to the first hole K1 and the second hole K2 is removed, so that the second sacrificial layer 7 is broken into a plurality of sacrificial sub-layers.

[0116] A fourth dummy layer film is deposited, which fills the channel B1 and covers the bottom and sidewalls of the first hole K1 and the second hole K2, and fills the first transverse trench L1; the fourth dummy layer film in the first hole K1 and the second hole K2 is etched away to form a fourth dummy layer 74 disposed in the channel B1 and the first transverse trench L1; Figures 6A to 6F As shown, Figures 6A to 6F These are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the sacrificial sublayer and the fourth dummy layer 74, as provided in some embodiments.

[0117] 6) Form the second groove A2;

[0118] The first barrier layer 8 in the first hole K1 and the second hole K2 is removed by etching;

[0119] A fourth insulating film is deposited to form a fourth insulating layer 14, which covers the inner walls of the first hole K1 and the second hole K2.

[0120] After depositing the fifth dummy layer film, it is ground flat. The fifth dummy layer film fills the first hole K1 and the second hole K2 to form the fifth dummy layer 75.

[0121] A fifth insulating film is deposited to form a fifth insulating layer 15 covering the aforementioned structure;

[0122] The fifth insulating layer 15 is etched to expose the first dummy layer 71 in the first trench T1. The first dummy layer 71 in the first trench T1 is removed by etching to form a plurality of fourth holes K4. The fourth holes K4 are located between adjacent first holes K1, and the sidewalls of the fourth holes K4 expose the second insulating layer 12.

[0123] Based on the etching of the fourth hole K4, the first barrier layer 8 is exposed on the sidewall of the fourth hole K4;

[0124] Based on the etching of the fourth hole K4, the sacrificial sublayer in the channel B1 is removed, and the fourth dummy layer 74 is etched. The area where the fourth dummy layer 74 is connected to the fourth hole K4 is etched, and a portion of the fourth dummy layer 74 is retained to form the second groove A2. The retained fourth dummy layer 74 is connected to the fourth insulating layer 14 in the first hole K1 and the second hole K2. Figures 7A to 7F As shown, Figures 7A to 7F These are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the second groove A2 is formed, as provided in some embodiments.

[0125] 7) Etch away the first barrier layer 8 in channel B1;

[0126] Based on the fourth hole K4 and the second groove A2, the first barrier layer 8 in the channel B1 is removed by lateral etching, such as Figures 8A to 8D As shown, Figures 8A to 8D These are cross-sectional views along the AA', CC', DD', and FF' directions respectively, after etching away the first barrier layer 8 in channel B1 provided in some embodiments.

[0127] 8) Form the first conductive layer 40';

[0128] A first conductive film is deposited, which covers the inner wall of the channel B1, as well as the bottom wall and sidewall of the fourth hole K4. At this time, the first conductive film covers the sidewall of the fourth dummy layer 74 parallel to the substrate 1 and the sidewall opposite to each other along the second direction Y, as well as the surfaces of the two first insulating layers 11 constituting the channel B1 facing the channel B1. The first conductive film on the bottom wall of the fourth hole K4 is etched away.

[0129] A third sacrificial layer film is deposited, which sequentially covers the inner wall of the channel B1, as well as the bottom and side walls of the fourth hole K4;

[0130] The third sacrificial layer film on the bottom and sidewalls of the fourth hole K4 is etched away, while the third sacrificial layer film in the channel B1 (including the third sacrificial layer film in the second groove A2) is retained, exposing the first conductive film in the fourth hole K4; and the third sacrificial layer film in the second groove A2 is etched for a first predetermined length.

[0131] The first conductive film on the sidewall of the fourth hole K4 is etched away, and the first conductive film exposed in the second groove A2 is etched away for a first predetermined length to form a first conductive layer 40'; that is, the first conductive film on the sidewall of the second groove A2 adjacent to the fourth hole K4 is etched away.

[0132] Etching removes the third sacrificial layer film in channel B1, such as... Figures 9A to 9E As shown, Figures 9A to 9E Cross-sectional views along the AA', BB', CC', DD', and FF' directions are provided in some embodiments after the formation of the first conductive layer 40'. A cross-sectional view along the EE' direction can be found in [reference needed]. Figure 7E .

[0133] In some embodiments, the first conductive film on the bottom wall of the fourth hole K4 may not be removed before depositing the third sacrificial layer film, or the first conductive film on the bottom wall of the fourth hole K4 may be etched away while the first conductive film on the sidewall of the fourth hole K4 is being etched away.

[0134] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0135] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0136] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0137] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0138] The materials of the subsequent second to fourth conductive films are similar to those of the first conductive film, and will not be described in detail here.

[0139] 9) Forming a gate insulating structure layer 24' and a semiconductor structure layer 23';

[0140] A gate insulating film, a semiconductor film, and a fourth sacrificial layer film are deposited sequentially. The fourth sacrificial layer film fills the second groove A2. The fourth sacrificial layer film in the fourth hole K4 is etched away, and the semiconductor film in the fourth hole K4 is etched away, forming a gate insulating structure layer 24', a semiconductor structure layer 23', and a second isolation layer 6.

[0141] Based on the fourth hole K4, the second isolation layer 6 is etched laterally for a first preset length, so that there is a first preset distance between the second isolation layer 6 and the opening of the second groove A2, in order to increase the contact area between the subsequently formed bit line 30 and the semiconductor structure layer 23', such as... Figures 10A to 10F As shown, Figures 10A to 10F These are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the gate insulating structure layer 24' and the semiconductor structure layer 23'.

[0142] In an exemplary embodiment of this disclosure, the material of the semiconductor structure layer 23' may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0143] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0144] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0145] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0146] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0147] In exemplary embodiments of this disclosure, the material of the gate insulating structure layer 24' may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0148] 10) Forming bit line 30;

[0149] A second conductive film is deposited, covering the bottom and sidewalls of the fourth hole K4 and filling the cavity formed by the etching of the second isolation layer 6 in the second groove A2. The second conductive film on the bottom wall of the fourth hole K4 is then etched away to form a bit line 30. In this embodiment, the bit line 30 is a ring structure. In some implementations, the second conductive film on the bottom wall of the fourth hole K4 may not need to be removed.

[0150] After depositing the fifth insulating film, it is ground smooth. The fifth insulating film fills the fourth hole K4 to form the fifth insulating layer 15, as shown. Figures 11A to 11D As shown, Figures 11A to 11D These are cross-sectional views along the AA', BB', DD', and EE' directions after the bit line 30 is formed, provided in some embodiments.

[0151] In some embodiments, the second conductive film can fill the fourth hole K4 to form bit line 30, i.e., bit line 30 is a solid structure. The aforementioned annular bit line 30 can be subsequently divided into two independent bit lines, such that adjacent memory cells along the first direction X are connected to different bit lines.

[0152] 11) Expose semiconductor structure layer 23';

[0153] A sixth insulating film is deposited to form a sixth insulating layer 16 covering the structure formed above;

[0154] The sixth insulating layer 16 is etched to expose the third dummy layer 73 in the third hole K3; the third dummy layer 73 in the third hole K3 and the first groove A1 is etched away to expose the first conductive layer 40'.

[0155] The first conductive layer 40' is etched to expose the gate insulating structure layer 24'; a seventh insulating film is deposited, the seventh insulating film is etched, and the seventh insulating film covering the end of the first conductive layer 40' is retained to form the seventh insulating layer 17; at this time, the first conductive layer 40' forms the word line 40;

[0156] The gate insulating structure layer 24' and the semiconductor structure layer 23' are etched to expose the second isolation layer 6. The second isolation layer 6 is etched along a direction parallel to the substrate 1 for a second predetermined length to expose a portion of the surface of the semiconductor structure layer 23' facing the second isolation layer 6, thereby increasing the contact area between the subsequently formed first capacitor electrode 41 and the semiconductor structure layer 23'. Figures 12A to 12C As shown, Figures 12A to 12C The images shown are cross-sectional views along the AA', BB', and DD' directions after the semiconductor structure layer 23' has been exposed, as provided in some embodiments. At this time, the semiconductor structure layer 23' forms multiple semiconductor layers 23.

[0157] 12) Form the first capacitor electrode 41;

[0158] A third conductive film and a fifth sacrificial layer film are deposited sequentially. The third conductive film covers the inner wall of the third hole K3 and the first groove A1 and fills the cavity formed after the second isolation layer 6 is etched. The fifth sacrificial layer film fills the third hole K3 and the first groove A1. The third conductive film and the fifth sacrificial layer film in the third hole K3 are etched away to form the first capacitor electrode 41 and the fifth sacrificial layer 5.

[0159] After sequentially depositing the sixth sacrificial layer film and the sixth dummy layer film, the surface is smoothed. The sixth sacrificial layer film covers the bottom and sidewalls of the third hole K3, and the sixth dummy layer film fills the third hole K3, forming the sixth sacrificial layer 4 and the sixth dummy layer 76. Figures 13A to 13C As shown, Figures 13A to 13C These are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first capacitor electrode 41.

[0160] 13) Exposing the first hole K1 and the second hole K2;

[0161] Deposit an eighth insulating film to form an eighth insulating layer covering the aforementioned structure;

[0162] The eighth insulating layer is etched to expose the fifth dummy layer 75 in the first hole K1 and the second hole K2, and the fifth dummy layer 75 is removed by etching; the fourth insulating layer 14 in the first hole K1 and the second hole K2 is exposed.

[0163] The fourth insulating layer 14 is removed by etching, and the fourth dummy layer 74 (including the fourth dummy layer 74 in the channel B1 and the first lateral trench L1) is removed by lateral etching based on the first hole K1 and the second hole K2. At this time, the first hole K1, the second hole K2, the channel B1, and the first lateral trench L1 are connected, as shown below. Figures 14A to 14E As shown, Figures 14A to 14E The images are cross-sectional views along the AA', BB', CC', EE', and FF' directions after exposing the first hole K1 and the second hole K2, respectively, according to some embodiments.

[0164] 14) Form the first isolation layer 19;

[0165] A ninth insulating film is deposited, which covers the inner walls of the first hole K1 and the second hole K2, fills the area between adjacent sacrificial sublayers in channel B1 and the area between adjacent sacrificial sublayers in the first transverse trench L1, and etches away the ninth insulating film in the first hole K1 and the second hole K2 to form a first isolation layer 19; that is, at this time, the fourth dummy layer 74 between adjacent sacrificial sublayers is replaced by the first isolation layer 19.

[0166] A seventh dummy layer film is deposited, which fills the first hole K1 and the second hole K2 to form the seventh dummy layer 77, as shown. Figures 15A to 15E As shown, Figures 15A to 15E These are cross-sectional views along the AA', BB', CC', EE', and FF' directions after the formation of the first isolation layer 19, provided in some embodiments.

[0167] 15) First hole K1 is exposed;

[0168] A tenth insulating film is deposited to form a tenth insulating layer 20 covering the aforementioned structure;

[0169] Etch the tenth insulating layer 20 to expose the seventh dummy layer 77 in the first hole K1, then etch away the seventh dummy layer 77 in the first hole K1 to expose the first hole K1, as shown. Figures 16A to 16D As shown, Figures 16A to 16D These are cross-sectional views along the AA', BB', EE', and FF' directions after the first hole K1 is exposed, provided in some embodiments.

[0170] 16) Expose the first capacitor electrode 41;

[0171] After depositing the eleventh insulating film, it is ground smooth, and the eleventh insulating film fills the first hole K1 to form the third isolation layer 21.

[0172] A twelfth insulating film is deposited, which covers the aforementioned structure to form a twelfth insulating layer 22;

[0173] The twelfth insulating layer 22 is etched to expose a plurality of second holes K2 distributed along the second direction Y, and to expose the area between the plurality of second holes K2 distributed along the second direction Y;

[0174] The seventh dummy layer 77 in the second hole K2 is removed by etching; the fifth sacrificial layer 5, the sixth sacrificial layer 4, and the sixth dummy layer 76 are also removed by etching; and the first insulating layer 11 between adjacent second holes K2 along the second direction Y is removed, exposing the inner sidewalls (including two sidewalls parallel to the substrate 1 and an inner sidewall intersecting the substrate 1) and two outer sidewalls parallel to the substrate 1 of the first capacitor electrode 41, as well as two outer sidewalls perpendicular to the substrate 1 and arranged opposite each other along the second direction. That is, the first capacitor electrode 41 forms a suspended structure, which can maximize the facing area between the subsequently formed second capacitor electrode 42 and the first capacitor electrode 41. Figures 17A to 17E As shown, Figures 17A to 17E The following are cross-sectional views along the AA', BB', DD', EE', and FF' directions after the first capacitor electrode 41 is exposed, respectively, according to some embodiments.

[0175] 17) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0176] A dielectric layer film and a fourth conductive film are deposited sequentially. The dielectric layer film covers the inner sidewall of the first capacitor electrode 41 and the outer sidewall parallel to the substrate 1, with two outer sidewalls arranged opposite each other along the second direction Y. The fourth conductive film fills the region between the second hole K2 and the adjacent second hole K2 along the second direction Y, forming a dielectric layer 43 and a second capacitor electrode 42. Figures 1A to 1F As shown.

[0177] In some embodiments, the dielectric layer 43 may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0178] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0179] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers; Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; Multiple word lines are distributed on different layers. The word lines and bit lines are distributed along a first direction parallel to the substrate. Each word line includes a first horizontal portion and a second horizontal portion spaced apart along a direction perpendicular to the substrate, and a connecting portion disposed between the first horizontal portion and the second horizontal portion to connect them. The first horizontal portion and the second horizontal portion extend along a second direction parallel to the substrate. The first horizontal portion, the second horizontal portion, and the connecting portion are an integral structure. The first direction and the second direction intersect. The memory cell includes a transistor, and the transistor includes a semiconductor layer connecting the bit line; the semiconductor layer is disposed between the first horizontal portion and the second horizontal portion. The semiconductor layer forms a first annular structure with the opening direction parallel to the first direction. The first horizontal portion is distributed on the side of the semiconductor layer away from the substrate, the second horizontal portion is distributed on the side of the semiconductor layer facing the substrate, and the connecting portion is distributed on both sides of the semiconductor layer that are opposite to each other along the second direction.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: a multilayer memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along the first direction and the second direction; a first isolation layer is disposed between adjacent semiconductor layers along the second direction, and the two sides of the first isolation layer disposed opposite to each other along the second direction are covered by the connecting portion, the side of the first isolation layer away from the substrate is connected to the first horizontal portion, and the side of the first isolation layer facing the substrate is connected to the second horizontal portion.

3. The semiconductor device according to claim 2, characterized in that, The first horizontal portion and the second horizontal portion are provided with a recessed structure located between adjacent bit lines along the second direction on the side facing the bit line.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor layer has first protrusions on both sides that are disposed opposite to each other along the second direction. From the location of the first protrusions away from the bit line, the distance between the two sides of the semiconductor layer disposed opposite to each other along the second direction decreases sequentially.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor layer includes two ends disposed opposite each other along the first direction, and the bit line contacts at least one of the ends of the semiconductor layer and an inner sidewall adjacent to the end.

6. The semiconductor device according to claim 1, characterized in that, The bit line forms a second annular structure or a solid structure extending in a direction perpendicular to the substrate, and the second annular structure or solid structure includes a plurality of second protrusions corresponding one-to-one with the plurality of memory cells. The second protrusions extend into the first annular structure formed by the semiconductor layer of the transistor of the corresponding memory cell and fill the opening of the first annular structure facing the bit line.

7. The semiconductor device according to claim 6, characterized in that, The transistor further includes a first electrode, which forms a cylindrical structure with an opening away from the semiconductor layer. The bottom wall of the cylindrical structure is connected to the end of the first annular structure away from the bit line. The bottom wall of the cylindrical structure is provided with a third protrusion, which extends into the first annular structure and connects to the inner wall of the first annular structure, filling the opening of the first annular structure away from the bit line.

8. The semiconductor device according to claim 7, characterized in that, The space enclosed by the inner wall of the first annular structure, the first electrode, and the bit line is filled with a second insulating layer.

9. The semiconductor device according to claim 2, characterized in that, The transistor further includes a gate insulating layer disposed between the word line and the semiconductor layer and surrounding the semiconductor layer, and the gate insulating layers of multiple transistors in the same column distributed along the second direction are disconnected from each other, the gate insulating layers of multiple transistors distributed at the same position in different layers are connected to form an integral structure on the side facing the bit line, and the integral structure formed by the multiple gate insulating layers is connected to the sidewall of the bit line.

10. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a third isolation layer disposed between adjacent bit lines along a second direction, the third isolation layer being connected to the bit lines, the connection portion, and the first isolation layer.

11. The semiconductor device according to claim 7, characterized in that, The storage cell further includes a capacitor, which includes a second capacitor electrode and a dielectric layer disposed between the second capacitor electrode and a first electrode. The dielectric layer is distributed on the inner bottom wall, inner side wall and outer side wall of the cylindrical structure. The second capacitor electrode fills the cylindrical structure and the area between adjacent first electrodes along a second direction, and is distributed on the outer side wall of the cylindrical structure parallel to the substrate.

12. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A first trench and a second trench are formed that penetrate the stacked structure along a direction perpendicular to the substrate. The first trench and the second trench extend along a second direction parallel to the substrate, and the first trench and the second trench are spaced apart along a first direction parallel to the substrate. The first direction and the second direction intersect. A first dummy layer is formed that fills the first trench and the second trench. A plurality of first holes and a plurality of second holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along the second direction. The first holes penetrate the first trench along the first direction and the size of the first holes along the first direction is larger than the size of the first trench along the first direction. Multiple second holes are spaced apart along the second direction, the second holes penetrate the second groove along the first direction, and the size of the second holes along the first direction is larger than the size of the second groove along the first direction; A second insulating layer is formed covering the bottom and sidewalls of the first and second holes, and a second dummy layer is formed filling the first and second holes; The first dummy layer in the second trench is etched away to form a plurality of third holes spaced apart by the second holes. The first sacrificial layer is etched along a direction parallel to the substrate based on the plurality of third holes to form a plurality of first grooves and to form a third dummy layer that fills the first grooves and the third holes. The second insulating layer and the second dummy layer are etched away to expose the first hole and the second hole. The first sacrificial layer is etched away based on the first hole and the second hole to form a channel that extends in the second direction between adjacent first insulating layers and between the third dummy layer and the first trench. Word lines and multiple semiconductor layers are formed in the channel. The word lines include first horizontal portions and second horizontal portions spaced apart along a direction perpendicular to the substrate, and a connecting portion disposed between the first horizontal portions and the second horizontal portions to connect the first horizontal portions and the second horizontal portions. The first horizontal portions and the second horizontal portions extend along a second direction parallel to the substrate, and the first horizontal portions, the second horizontal portions and the connecting portion are an integral structure. The semiconductor layer is disposed between the first horizontal portions and the second horizontal portions. The semiconductor layer forms a first annular structure with an opening direction parallel to the first direction. The first horizontal portions are distributed on the side of the semiconductor layer away from the substrate, the second horizontal portions are distributed on the side of the semiconductor layer facing the substrate, and the connecting portions are distributed on two opposite sides of the semiconductor layer along the second direction.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The formation of word lines and multiple semiconductor layers in the channel includes: A first barrier layer is formed covering the inner wall of the first hole, the second hole, and the channel; and a second sacrificial layer is formed to fill the channel. The second sacrificial layer in the channel is etched based on the first hole and the second hole, such that the second sacrificial layer in the channel forms a plurality of sacrificial sub-layers spaced apart along a second direction, forming a fourth dummy layer filling the channel. The first dummy layer in the first trench is etched away to form a plurality of fourth holes spaced apart by the first hole. The sacrificial sublayer is etched away based on the fourth holes and the fourth dummy layer is etched away, while a portion of the fourth dummy layer is retained to form a second groove, wherein the retained fourth dummy layer is connected to the first hole and the second hole. The first barrier layer in the channel is removed by etching based on the fourth hole and the second groove; A first conductive film is formed covering the inner wall of the channel and the sidewall of the fourth dummy layer parallel to the substrate and the sidewall opposite to the second direction. The first conductive film is etched based on the fourth hole so that the first conductive film on the sidewall of the second groove is removed at a distance less than or equal to a first preset length from the opening of the second groove, thereby forming a first conductive layer. A gate insulating structure layer and a semiconductor structure layer are formed that sequentially cover the inner wall of the channel and the sidewall of the fourth dummy layer that is parallel to the sidewall of the substrate and opposite to the sidewall of the fourth dummy layer along the second direction. A bit line extending perpendicular to the substrate direction is formed in the fourth hole, the bit line extending into the second groove of the multilayer and connecting to the multilayer semiconductor structure layer; The third dummy layer in the third hole and the first groove is etched away to expose the first conductive layer. The exposed first conductive layer is etched to form the word line. The semiconductor structure layer is etched so that the semiconductor structure layer opens on the side away from the bit line to form a plurality of semiconductor layers.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: The first capacitor electrode, which covers the sidewall of the first groove and extends into the channel and is connected to the semiconductor layer, is located in the first groove. Replace the fourth virtual layer with the first isolation layer; The inner wall of the first capacitor electrode, the outer wall parallel to the substrate, and the two outer walls opposite to each other along the second direction are exposed to form a second capacitor electrode distributed on the inner wall of the first capacitor electrode, the outer wall parallel to the substrate, and the two outer walls opposite to each other along the second direction.

15. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 11, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 12 to 14.

Images