Memory and method of manufacturing the same, and electronic device
By optimizing the memory structure and process flow, the problem of channel layer material loss due to high-temperature processing was solved, improving memory performance and reducing manufacturing difficulty and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248722A_ABST
Abstract
Description
Technical Field
[0001] This article relates to the field of semiconductor technology, and in particular to a memory, its manufacturing method, and electronic devices. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing. This means that even the slightest difference in the manufacturing process can affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] This application provides a memory, a method for manufacturing the same, and an electronic device.
[0005] In a first aspect, embodiments of this application provide a memory, including multiple memory cell layers vertically stacked on a substrate, multiple bit lines connected to the multiple memory cell layers, and multiple word lines; the memory cell layers include multiple memory cells arranged in an array; each memory cell includes a transistor, a capacitor, and a support structure supporting the capacitor; wherein, the transistor includes a gate pillar, the gate pillar having a first columnar boss structure extending radially outward, the outer surface of the gate pillar being surrounded by a dielectric material layer, and the outer surface of the dielectric material layer surrounding the outer wall of the first columnar boss structure being surrounded by a channel layer; the support structure is columnar and has a second columnar boss structure extending radially outward, the axis of the support structure being parallel to the axis of the gate pillar; the capacitor includes a first electrode plate, a dielectric layer, and a second electrode plate, wherein the first electrode plate surrounds the outer surface of the support structure, the dielectric layer surrounds the outer surface of the first electrode plate, and the outer surface of the dielectric layer surrounding the outer surface of the second columnar boss structure is covered by the second electrode plate; the outer wall of the channel layer is in contact with the outer wall of the second electrode plate, and one end opposite to the capacitor is in contact with the bit line; the word line is formed by connecting multiple vertically stacked gate pillars.
[0006] Secondly, embodiments of this application provide a method for manufacturing a memory. The memory includes word lines, bit lines, and multiple memory cell layers stacked vertically on a substrate. Each memory cell layer includes multiple memory cells arranged in an array. Word lines extend along a first direction perpendicular to the substrate, connecting multiple memory cells in different layers. Word lines extend along a second direction parallel to the substrate, connecting multiple memory cells in the same layer. Each memory cell includes a capacitor and a transistor. The manufacturing method includes: alternately fabricating a first isolation layer and a second isolation layer on a substrate to obtain a stacked structure; etching the stacked structure along the first direction to form capacitor holes penetrating the stacked structure, and forming capacitors and support structures supporting the capacitors in the capacitor holes; arranging multiple capacitors in an array along the second direction and a third direction parallel to the substrate; etching the stacked structure along the first direction to form transistor holes penetrating the stacked structure, and forming transistors in each transistor hole; arranging multiple transistors in an array along the second direction and the third direction, corresponding one-to-one with multiple capacitors; the channel layers of the transistors are respectively contacted and connected to the second plates of the capacitors and the bit lines; the gates of multiple transistors located in the same transistor hole are connected to form word lines to form memory cells.
[0007] Thirdly, embodiments of this application provide an electronic device, including a memory as described in any embodiment of this application or a memory formed by a manufacturing method as described in any embodiment of this application.
[0008] This application includes a memory, a method for manufacturing the same, and an electronic device. The memory includes multiple memory cell layers vertically stacked on a substrate, multiple bit lines connected to the multiple memory cell layers, and multiple word lines. Each memory cell layer includes multiple memory cells arranged in an array. Each memory cell includes a transistor, a capacitor, and a support structure supporting the capacitor. The transistor includes a gate pillar with a first columnar boss structure extending radially outward. The outer surface of the gate pillar is surrounded by a dielectric material layer, and the outer surface of the dielectric material layer surrounding the outer wall of the first columnar boss structure is surrounded by a channel layer. The support structure is columnar and has a second columnar boss structure extending radially outward, with the axis of the support structure parallel to the axis of the gate pillar. The capacitor includes a first electrode plate, a dielectric layer, and a second electrode plate. The first electrode plate surrounds the outer surface of the support structure, the dielectric layer surrounds the outer surface of the first electrode plate, and the outer surface of the dielectric layer surrounding the outer surface of the second columnar boss structure is covered by the second electrode plate. The outer wall of the channel layer is in contact with the outer wall of the second electrode plate, and one end opposite to the capacitor is in contact with the bit line. The word line is formed by connecting multiple vertically stacked gate pillars. In the memory of this application embodiment, the channel layer of the transistor surrounds the outer wall of the first columnar boss structure, and the second plate of the capacitor surrounds the outer surface of the second columnar boss structure, so that the contact area between the second plate and the channel layer of the transistor is far away from the gate pillar and the support structure of the capacitor, resulting in a better morphology. This can reduce the loss of channel layer material performance caused by high-temperature processing during the production process, help improve the performance of the memory, and reduce the difficulty of the manufacturing process.
[0009] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description
[0010] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0011] Figure 1 This is a schematic diagram of the memory structure in an embodiment of this application;
[0012] Figure 2A This is a schematic cross-sectional view of the memory along the AA' direction in an embodiment of this application;
[0013] Figure 2B This is a schematic cross-sectional view of the memory along the BB' direction in an embodiment of this application;
[0014] Figure 3This is a cross-sectional schematic diagram of the stacked structure in one embodiment of the memory manufacturing method of this application;
[0015] Figure 4 This is a schematic cross-sectional view of the structure after forming capacitor holes in one embodiment of the memory manufacturing method of this application.
[0016] Figure 5 This is a schematic cross-sectional view of the memory manufacturing method in one embodiment of the present application after forming the first annular groove;
[0017] Figure 6 This is a schematic cross-sectional view of the structure after electrode material deposition in one embodiment of the memory manufacturing method of this application.
[0018] Figure 7 This is a schematic cross-sectional view of the memory manufacturing method in one embodiment of the present application after filling with sacrificial material;
[0019] Figure 8 This is a schematic cross-sectional view of the memory manufacturing method in one embodiment of the present application after removing the electrode material from the inner wall of the capacitor hole;
[0020] Figure 9 This is a schematic cross-sectional view of the memory manufacturing method in one embodiment of the present application after removing the sacrificial material;
[0021] Figure 10 This is a schematic cross-sectional view of the structure after the dielectric layer is formed in one embodiment of the memory manufacturing method of this application;
[0022] Figure 11 This is a schematic cross-sectional view of the memory manufacturing method in one embodiment of the present application after the first electrode plate has been formed;
[0023] Figure 12 This is a schematic cross-sectional view of the support structure after it has been formed in one embodiment of the memory manufacturing method of this application.
[0024] Figure 13 This is a schematic cross-sectional view of the structure after forming transistor holes in one embodiment of the memory manufacturing method of this application;
[0025] Figure 14 This is a schematic cross-sectional view of the structure after forming the second annular groove in one embodiment of the memory manufacturing method of this application;
[0026] Figure 15 This is a schematic cross-sectional view of the structure after electrode material is deposited in the second annular groove in one embodiment of the memory manufacturing method of this application.
[0027] Figure 16 This is a schematic cross-sectional view of the structure after the trench layer is formed in one embodiment of the memory manufacturing method of this application;
[0028] Figure 17 This is a schematic cross-sectional view of the structure after forming a dielectric material layer in one embodiment of the memory manufacturing method of this application.
[0029] Figure 18 This is a schematic cross-sectional view of the structure after the gate pillars are formed in one embodiment of the memory manufacturing method of this application;
[0030] Figure 19 This is a schematic flowchart of one embodiment of the memory manufacturing method in this application.
[0031] Figure 20 This is a schematic diagram of the process for preparing a capacitor in one embodiment of the memory manufacturing method of this application;
[0032] Figure 21 This is a schematic flowchart illustrating the process of forming a second electrode plate in one embodiment of the memory manufacturing method described in this application.
[0033] Figure 22 This is a schematic diagram illustrating the process of forming a transistor in one embodiment of the memory manufacturing method described in this application.
[0034] Figure label:
[0035] 110-Substrate; 120-Memory cell layer; 130-Memory cell; 131-Capacitor; 1311-First electrode plate; 1312-Dielectric layer; 1313-Second electrode plate; 132-Transistor; 1321-Channel layer; 1322-Dielectric material layer; 1323-Gate pillar; 133-Support structure; 140-Bit line; 141-Connection portion; 320-First isolation layer; 330-Second isolation layer; 410-Capacitor hole; 510-First annular groove; 610-Electrode material; 710-Sacrificial material; 1310-Transistor hole; 1410-Second annular groove; 1710-Dielectric material layer. Detailed Implementation
[0036] The embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this application and the features thereof can be combined arbitrarily with each other.
[0037] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this application pertains.
[0038] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values shown in the drawings.
[0039] The ordinal numbers “first,” “second,” “third,” etc., used in this application are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0040] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms used herein and may be appropriately replaced as needed.
[0041] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0042] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.
[0043] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this application, the "source electrode" and "drain electrode" can be interchanged.
[0044] In this application, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0045] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0046] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as breaks or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
[0047] In related technologies, memory is formed by vertically stacking multiple layers of memory cells. The channel layer of the transistor in the memory cell is closely attached to the cylindrical surface of the gate pillar, and the connection area between the capacitor plate and the channel layer is close to the gate pillar and the capacitor's supporting structure. Because the memory manufacturing process involves high-temperature processing steps, and the channel layer material suffers performance degradation under high temperatures, this morphology places higher demands on the memory manufacturing process and adversely affects memory performance.
[0048] Therefore, embodiments of this application provide a memory. Figure 1 A schematic diagram of the memory structure in this embodiment is shown, as follows: Figure 1 As shown, the memory includes multiple memory cell layers 120 vertically stacked on a substrate 110, multiple bit lines (not shown) connected to the multiple memory cell layers 120, and multiple word lines (…). Figure 1 (Not shown in the image). The storage cell layer 120 includes multiple arrayed storage cells 130. Figure 2A A schematic diagram of the memory interface along the AA' direction is shown. Figure 2B This shows a cross-sectional schematic diagram of the memory along the BB' direction, as shown below. Figure 2A and Figure 2BAs shown, the storage cell 130 includes a transistor 132, a capacitor 131, and a support structure 133 supporting the capacitor. The transistor 132 includes a gate pillar 1323, which has a first columnar boss structure extending radially outward. A dielectric material layer 1322 surrounds the outer surface of the gate pillar 1323, and a channel layer 1321 surrounds the outer surface of the dielectric material layer 1322 surrounding the outer wall of the first columnar boss structure. The support structure 133 is columnar and has a second columnar boss structure extending radially outward. The axis of the support structure 133 is parallel to the axis of the gate pillar 1323. The capacitor 132 includes a first electrode 1311, a dielectric layer 1312, and a second electrode 1313. The first electrode 1311 surrounds the outer surface of the support structure 133, the dielectric layer 1312 surrounds the outer surface of the first electrode 1311, and the outer surface of the dielectric layer surrounding the outer surface of the second columnar boss structure is covered by the second electrode 1313. The outer wall of the second electrode 1313 is in contact with the outer wall of the channel layer 1321. One end of the channel layer 1321 opposite to the capacitor 132 is connected to the bit line 140. The word line is formed by connecting multiple vertically stacked gate pillars 1323.
[0049] In this embodiment, the first columnar boss structure and the second columnar boss structure are in a plane parallel to the substrate 110 (i.e., Figure 1 The cross-sectional shape of the plane composed of D2 and D3 can be a hollow square or polygon, etc. The structure of the first columnar boss structure and the second columnar boss structure can be the same or different. This embodiment does not limit this.
[0050] In some optional embodiments of this example, the first columnar boss structure is a cylindrical structure, and the channel layer 1321 can be a cylindrical structure with the axis of the cylindrical structure parallel to the axis of the gate pillar 1323.
[0051] As an example, the cross-sectional shape of the first and second columnar boss structures in a plane parallel to the substrate 110 can be annular. The gate pillar 1323 can be a stepped columnar structure formed of a gate material (e.g., IZO). The axis of the gate pillar 1323 can be perpendicular to the substrate 110. When multiple memory cells 130 are stacked vertically on the substrate 110, the gate pillars 1323 in each memory cell 130 are connected together and can serve as word lines. The outer surface of the gate pillar 1323 (e.g., it can include a cylindrical surface parallel to the axis and an annular plane perpendicular to the axis and an outer wall parallel to the axis in the first columnar boss structure) is surrounded by a dielectric material layer 1322. Among them, a cylindrical channel layer 1321 is surrounded on the outer surface of the dielectric material layer surrounding the outer wall of the first columnar boss structure (i.e., the cylindrical surface of the first columnar boss structure). In this configuration, the channel layer 1321 can be located at a position far from the axis of the gate pillar 1323.
[0052] The support structure 133 is made of a support material and has a structure similar to the gate pillar 1323. Its outer surface (e.g., it may include a cylindrical surface and an annular plane perpendicular to the axis and an outer wall parallel to the axis in the second columnar boss structure) is surrounded by a first electrode plate 1311 made of electrode material. The outer surface of the first electrode plate 1311 is surrounded by a dielectric layer 1312 made of dielectric material. The outer surface of the dielectric layer 1312 surrounding the outer surface of the second columnar boss structure (e.g., it may include an annular plane perpendicular to the axis and an outer wall parallel to the axis of the second columnar boss structure) is surrounded by a second electrode plate 1313. Thus, the second electrode plate 1313 is an integral structure formed by connecting a double-layer annular plane perpendicular to the axis and a cylindrical surface (i.e., an outer wall) parallel to the axis.
[0053] In this embodiment, the capacitor 131 and the transistor 132 are connected by the outer wall of the second electrode plate 1313 and the outer wall of the channel layer 1321 in contact. The end of the channel layer 1321 opposite to the capacitor 131 can be connected to the bit line 140. The end connected to the second electrode plate 1313 can serve as the first electrode of the transistor 132, and the end connected to the bit line 140 can serve as the second electrode of the transistor 132.
[0054] like Figure 2B As shown, the bit line 140 can adopt a ring structure composed of straight lines and curves. Each bit line 140 can connect two columns of memory cells 130. The two columns of memory cells 130 are located on both sides of the bit line 140 and are mirror-distributed, so that the bit line 140 simultaneously contacts and connects to the channel layer 1321 of the transistors 132 in the two columns of memory cells 130. A connection portion 141 can be provided on the bit line 140 near the edge of the memory cell layer 120. The connection portion 141 is perpendicular to the substrate 110 (i.e., Figure 1D1) runs through each memory cell layer 120 to connect the bit lines of different layers.
[0055] In some alternative implementations of this embodiment, transistor 132 may be a junctionless transistor to improve memory performance.
[0056] In this embodiment, the key dimensions of each component of the memory can be determined according to actual needs and specific process conditions.
[0057] In some optional embodiments of this example, the critical dimension of capacitor 131 (e.g., the outer surface diameter of the second electrode 1313) can be larger than the critical dimension of transistor 132 (e.g., the outer surface diameter of the channel layer 1321) in order to increase the capacitor area, improve the capacitor capacity, and thus improve the performance of the memory cell.
[0058] In this embodiment, the connection area between the transistor and the capacitor in the memory cell is located on the protruding part of the first columnar boss structure and the second columnar boss structure, which increases the lateral distance between the connection area and the gate pillar and the support structure. This morphology can reduce the loss of channel layer material performance caused by high temperature operation during processing, help improve the overall performance of the memory, and reduce the difficulty of the memory manufacturing process.
[0059] In related technologies, at the bottom of the holes where vertically stacked capacitors and transistors are located, the side of the substrate facing the memory cell usually has a recessed area. This is caused by substrate wear during the memory manufacturing process. However, in this embodiment, the side of the substrate near the memory cell is flat, which avoids substrate wear during the manufacturing process, thereby reducing the production cost of the memory.
[0060] In some embodiments, the dielectric layers of the vertically stacked capacitors are a continuous, monolithic structure. This allows for the formation of the dielectric layers for multiple capacitors in a single deposition process, simplifying the manufacturing process, and the monolithic structure can further improve memory performance.
[0061] In some embodiments, the dielectric material layers of the vertically stacked transistors are a continuous, monolithic structure. This allows for the formation of dielectric material layers for multiple transistors in a single deposition process, simplifying the manufacturing process, and the monolithic structure can further improve memory performance.
[0062] In some embodiments, the dielectric material layer and / or the dielectric layer may be made of a high-k (High-k or high-k) material to improve the performance of the dielectric material layer and / or the dielectric layer. Here, the dielectric material layer and the dielectric layer may be made of different high-k materials or the same high-k material, and this application does not limit this.
[0063] In this embodiment, the material of the supporting structure is a spin-on dielectric (SOD), such as silicon dioxide (SiO2), low-k materials (e.g., polyimide, organosilicon), high-k materials (e.g., barium strontium titanate (BST), lead zirconate titanate (PZT)), or organic materials (e.g., SOD based on organic polymers, such as polymethyl methacrylate (PMMA)). Compared with other materials such as polycrystalline silicon, the cost and processing difficulty of spin-on dielectric layers are lower.
[0064] In this embodiment, the channel layer is made of a metal oxide material, such as IGZO (Indium Gallium Zinc Oxide), to improve the performance of the channel layer.
[0065] Figures 3 to 18 These are all cross-sectional structural diagrams of the memory during the manufacturing process. The following will be combined with... Figures 3 to 18 The manufacturing process of the memory in this embodiment will be described by way of example. First, through... Figures 3 to 12 The process shown can realize the capacitor manufacturing process; then through Figures 12 to 18 It can realize the transistor fabrication process.
[0066] like Figure 3 As shown, D1 represents the first direction, and D3 represents the third direction. A stacked structure can be obtained by alternately fabricating a first isolation layer 320 and a second isolation layer 330 on the upper surface of the substrate 110. As an example, the material of the first isolation layer 320 can be silicon nitride (SiN), and the material of the second isolation layer 330 can be silicon oxide (SiO2). The number of layers in the stacked structure can be determined according to the number of memory cell layers in the memory. Figure 3 The number of stacked structures is merely an example. The thickness of the first isolation layer 320 and the second isolation layer 330 can be determined according to actual needs, for example, it can be 20-55nm. The thicknesses of the two can be the same or different, and this application does not limit this.
[0067] Combination Figure 1 As an example, each storage cell layer may include an adjacent first isolation layer 320 and a second isolation layer 330.
[0068] like Figure 4 As shown, etching along the first direction of the stacked structure yields capacitor holes 410. The etching method can be wet etching, dry etching, or other etching methods; this application does not limit the specific method used.
[0069] like Figure 5As shown, etching the first isolation layer 320 along the radial direction of the capacitor hole 410 can form a first annular groove 510 in the capacitor hole 410, and the center line of the first annular groove 510 coincides with the center line of the capacitor hole 410.
[0070] like Figure 6 As shown, electrode material 610 (e.g., titanium nitride) is deposited in capacitor hole 410, such that the inner wall of capacitor hole 410 and the inner surface of first annular groove 510 are covered by electrode material 610.
[0071] like Figure 7 As shown, the first annular groove 510 is filled with sacrificial material 710, such that the sacrificial material 710 completely fills the first annular groove 510.
[0072] like Figure 8 As shown, by removing the electrode material 610 deposited on the inner wall of the capacitor hole 410, the second plates of adjacent capacitor layers can be separated to obtain the second plates of multiple capacitors stacked vertically.
[0073] Figures 5 to 8 The formation process of the second electrode plate is shown.
[0074] like Figure 9 As shown, after the second plate of multiple capacitors is formed, the sacrificial material 710 in the first annular groove 510 can be removed.
[0075] like Figure 10 As shown, by depositing a first dielectric material, a dielectric layer 1312 of the capacitor can be formed on the inner wall of the capacitor hole 410 and the inner surface of the second electrode plate. Here, the dielectric layers 1312 of the multiple vertically stacked capacitors are a continuous, integral structure.
[0076] like Figure 11 As shown, by depositing electrode material 610, the first electrode plate of the capacitor can be formed, thus completing the process of fabricating multiple vertically stacked capacitors in the capacitor holes. The first electrode plates of the multiple vertically stacked capacitors obtained are an integral structure.
[0077] like Figure 12 As shown, a spin-coated dielectric layer can be deposited in the capacitor hole 410 to form a support structure 133 that supports the capacitor.
[0078] Figures 10 to 12 The formation process of the capacitor's dielectric layer, first electrode, and supporting structure is shown. Figures 3 to 12 This illustrates the capacitor manufacturing process.
[0079] like Figure 13 As shown, after the capacitor is fabricated, the stacked structure can be etched along the first direction to form transistor holes 1310.
[0080] like Figure 14 As shown, the second annular groove 1410 can be obtained by etching the first isolation layer 320 radially along the transistor hole 1310. Here, the second electrode of the capacitor needs to be exposed in the second annular groove 1410. Therefore, the second electrode may be damaged to some extent during the etching process.
[0081] like Figure 15 As shown, electrode material 610 is deposited in the second annular groove 1410, which can repair the exposed second electrode plate, for example, by increasing the thickness of the second electrode plate or repairing the damaged part of the second electrode plate.
[0082] like Figure 16 As shown, depositing channel layer material in the second annular groove 1410 can form a cylindrical channel layer 1321 in the second annular groove 1410.
[0083] like Figure 17 As shown, a dielectric material layer 1322 of a transistor can be formed by depositing a second dielectric material. Here, the dielectric material layers of multiple vertically stacked transistors are a monolithic structure formed in a single deposition.
[0084] like Figure 18 As shown, by depositing gate material in the transistor hole, a gate pillar 1323 of the transistor can be formed, thereby obtaining a transistor composed of a gate pillar 1323, a dielectric material layer 1322 and a channel layer 1321.
[0085] Figures 13 to 18 The transistor fabrication process is illustrated. A capacitor located in the same first isolation layer is connected to the channel layer of the corresponding transistor via a second electrode, thus forming a memory cell. The side of the channel layer opposite the capacitor can be connected to a bit line, and multiple memory cells arranged along the extension direction of the bit line can be connected to the same bit line. Multiple memory cells in the same layer form a memory cell layer. The gate pillars of multiple transistors located in the same transistor hole are an integral structure, which can serve as word lines to connect memory cells in different layers, thereby assembling multiple memory cells into a memory.
[0086] Currently, in the manufacturing process of memory, the fabrication of capacitors and transistors are carried out simultaneously, with different steps for capacitors and transistors performed concurrently or overlapping. This process is highly complex and presents numerous technological challenges, some of which are difficult to overcome. This negatively impacts both the manufacturing cost and performance assurance of memory.
[0087] Therefore, embodiments of this application provide a method for manufacturing a memory, such as... Figure 19As shown, the process may include the following steps.
[0088] Step 1910: Alternately prepare the first isolation layer and the second isolation layer on the substrate to obtain a stacked structure.
[0089] In this embodiment, the substrate can be a silicon substrate, the first isolation layer can be made of silicon nitride, and the second isolation layer can be made of silicon oxide. The stacked structure obtained in this step can be referred to... Figure 3 .
[0090] The memory may include word lines, bit lines, and multiple memory cell layers stacked vertically on a substrate; each memory cell layer includes multiple memory cells arranged in an array; word lines are formed by connecting the gate pillars of multiple vertically stacked memory cells, connecting multiple memory cells in different layers; bit lines extend along a second direction parallel to the substrate, connecting multiple memory cells in the same layer; each memory cell includes a capacitor and a transistor.
[0091] Step 1920: Etch the stacked structure along the first direction to form a capacitor hole that penetrates the stacked structure, and form a capacitor in the capacitor hole.
[0092] Among them, multiple capacitors are along the second direction (e.g.) Figure 1 D2) and a third direction parallel to the substrate (e.g. Figure 1 The array is arranged in the D3 direction. The first direction can be... Figure 1 D1 in the middle.
[0093] In this embodiment, capacitor holes are first formed in the stacked structure, and then capacitors are fabricated in the capacitor holes through processes such as etching and deposition. This step can correspond to... Figures 5 to 12 .
[0094] As an example, the second direction can be the length or width direction of the substrate, while the third direction can be the width or length direction of the substrate.
[0095] Step 1930: Etch the stacked structure along the first direction to form transistor holes that penetrate the stacked structure, and form transistors in each transistor hole.
[0096] In this array, multiple transistors are arranged in a second direction and a third direction, and each corresponds to a capacitor. The channel layer of the transistors is connected to the second plate and bit line of the capacitors respectively. The gate pillars of the transistors located in the same transistor hole are connected to form word lines, thus forming a memory cell.
[0097] In this embodiment, after the capacitor fabrication is completed, transistor holes can be etched into the stacked structure, and then transistors are formed in the transistor holes through etching, deposition, and other processes. The transistors can be junctionless transistors. This step can correspond to... Figures 13 to 18 .
[0098] Transistor holes and capacitor holes can be arranged adjacently so that the second plate of the capacitor can be connected to the channel layer of the transistor. Two parallel rows of memory cells can be mirrored relative to the bit line, and the transistors are close to the bit line so that the trench layer of multiple memory cells and the side opposite to the capacitor can be connected to the bit line.
[0099] In this embodiment, a capacitor is first fabricated in a stacked structure, and then a transistor connected to the capacitor is formed in the stacked structure. Compared with the method of fabricating capacitors and transistors simultaneously in related technologies, the method of manufacturing memory in this embodiment simplifies the process flow and reduces process costs and process difficulty.
[0100] The following is for reference. Figure 20 , Figure 20 A flowchart illustrating the preparation of a capacitor is shown in one embodiment of the method for manufacturing the memory of this application, as follows: Figure 20 As shown, the process may include the following steps.
[0101] Step 2010: Etch back the first isolation layer along the radial direction of the capacitor hole in the capacitor hole to form a first annular groove parallel to the substrate in the capacitor hole.
[0102] The capacitor in this embodiment can be applied to the memory in the above embodiments, and this step can correspond to... Figure 5 .
[0103] Step 2020: Deposit electrode material to form a second electrode plate on the surface of the first annular groove.
[0104] In this embodiment, electrode material can be deposited on the surface of the first annular groove to obtain the second electrode plate of the capacitor. The second electrode plate is formed by connecting a double-layer annular plane parallel to the substrate and a cylindrical surface perpendicular to the substrate. This step can correspond to... Figures 6 to 9 .
[0105] Step 2030: Deposit the first dielectric material to form the dielectric layer of the capacitor on the inner wall of the capacitor hole and the inner surface of the second electrode plate.
[0106] In this embodiment, the inner surface of the second electrode plate refers to the surface exposed in the second annular groove, while the outer surface is the surface in contact with the first and second isolation layers. Since the inner wall of the capacitor aperture is in contact with the inner surface of the second electrode plate, the dielectric layer obtained through deposition is a continuous, integral structure, which helps improve the capacitor's performance. This step can correspond to... Figure 10 .
[0107] Step 2040: Deposit electrode material to form the first electrode plate of the capacitor on the inner surface of the dielectric layer of the capacitor, thereby obtaining the capacitor.
[0108] This step can correspond to Figure 11 .
[0109] Step 2050: Deposit a spin-coated dielectric layer in the capacitor holes, so that the spin-coated dielectric layer fills the capacitor holes and the first annular groove, to obtain a support structure for supporting the capacitor.
[0110] This step can correspond to Figure 12 .
[0111] In this embodiment, the first isolation layer is etched back to form a first annular groove, and then an electrode material and dielectric material are deposited to form a capacitor. The second electrode plate of the capacitor is located in the first annular groove, and the cylindrical surface of the second electrode plate is farther from the center of the capacitor hole, which helps to improve the morphology of the capacitor-transistor connection area.
[0112] In some optional embodiments of this example, step 2020 described above may be adopted. Figure 21 The process shown forms the second electrode plate, as... Figure 21 As shown, the process may include the following steps.
[0113] Step 2110: Deposit electrode material in the capacitor hole so that the inner wall of the capacitor hole and the surface of the first annular groove are covered by the electrode material.
[0114] This step can correspond to Figure 6 .
[0115] Step 2120: Fill the first annular groove with sacrificial material.
[0116] As an example, the sacrificial material can be an oxide. This step can correspond to... Figure 7 .
[0117] Step 2130: Remove the electrode material deposited on the inner wall of the capacitor hole to obtain the second electrode plate.
[0118] This step can correspond to Figure 8
[0119] Step 1240: Remove the sacrificial material from the first annular groove.
[0120] This step can correspond to Figure 9 .
[0121] In this embodiment, after depositing the electrode material, sacrificial material can be filled into the first annular groove, and then the electrode material on the inner wall of the capacitor hole can be removed, thereby separating the second plates of the capacitors of different layers; then the sacrificial material is removed. Compared with directly removing the electrode material on the inner wall of the capacitor hole, this embodiment can avoid damage to the silicon substrate during the capacitor fabrication process, keeping the surface of the silicon substrate near the memory cell flat, which helps to reduce material loss during memory processing.
[0122] In some embodiments, the first dielectric material is a high dielectric constant material; the sacrificial material is an oxide material.
[0123] The following is for reference. Figure 22 , Figure 22 The flowchart illustrating the formation of a transistor in one embodiment of the memory manufacturing method of this application is shown. The transistor in this embodiment is a junctionless transistor, such as... Figure 7 As shown, the process may include the following steps.
[0124] Step 2210: Etch back the first isolation layer along the radial direction of the transistor hole in the transistor hole to form a second annular groove parallel to the substrate in the transistor hole, and expose the second electrode plate at least partially in the second annular groove.
[0125] In this embodiment, the second annular groove and the first annular groove are located in the same first isolation layer and are connected, so that the cylindrical surface of the second electrode plate is exposed in the second annular groove for connection with the channel layer of the transistor. This step can correspond to Figure 14 .
[0126] Step 2220: Deposit channel layer material in the second annular groove to form a channel layer in the second annular groove.
[0127] The channel layer is a cylindrical structure parallel to the first direction.
[0128] As an example, the channel layer material can be IGZO. This step can correspond to... Figure 16 .
[0129] Step 2230: Deposit a second dielectric material to form a dielectric material layer of the transistor on the inner wall of the transistor hole, the surface of the second annular groove, and the inner surface of the channel layer.
[0130] In this embodiment, the inner surface of the channel layer refers to the surface near the center of the transistor hole. The inner wall of the transistor hole, the second annular groove, and the inner surface of the channel layer are continuous, and the dielectric material obtained by deposition is also continuous, which helps to improve the performance of the transistor. This step can correspond to... Figure 17 .
[0131] The second dielectric material can be the same as or different from the first dielectric material; no restrictions are imposed on this in the application.
[0132] Step 2240: Deposit gate material in the transistor hole so that the gate material fills the transistor hole and the second annular groove to obtain the transistor.
[0133] This step can correspond to Figure 18 .
[0134] In this embodiment, gate pillars can be formed in transistor holes by depositing a gate material (e.g., IZO), thereby obtaining a transistor composed of gate pillars, a dielectric material layer, and a channel layer. Since the channel layer is far from the center of the gate pillar, it helps to improve the morphology of the connection region between the channel layer and the capacitor, and also reduces the performance loss of the channel layer material caused by high-temperature operation during manufacturing, thereby improving the performance of the transistor.
[0135] In some optional embodiments of this example, after step 2210 and before step 2220, the process may further include: step 2211, depositing electrode material to form a cylindrical electrode material layer in the second annular groove.
[0136] This step can correspond to Figure 15 In this embodiment, the etching process of the second annular groove occurs after the capacitor fabrication is completed, which may cause some damage to the second electrode plate of the capacitor. To address this issue, this embodiment can deposit an electrode material before depositing the channel layer material, which can repair the second electrode plate, reduce the adverse effects of the transistor fabrication process on the capacitor performance, and thus improve the overall performance of the memory.
[0137] In an optional example, after step 2220, the electrode material exposed in the second annular groove can be removed so that the channel layer completely covers the electrode material before proceeding with subsequent steps.
[0138] This application also provides an electronic device, including the memory in any of the above embodiments or the memory formed by the manufacturing method of the memory described in any of the above embodiments. The electronic device may be: a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0139] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0140] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A memory, comprising: The memory comprises a plurality of layers of memory cells vertically stacked on a substrate, a plurality of bit lines connected to the plurality of layers of memory cells, and a plurality of word lines; each layer of memory cells comprises a plurality of memory cells arranged in an array; The memory cell comprises a transistor, a capacitor, and a support structure supporting the capacitor; wherein, The transistor comprises a gate pillar having a first columnar boss structure extending radially outward, an outer surface of the gate pillar is surrounded by a dielectric material layer, and an outer surface of the dielectric material layer surrounding an outer wall of the first columnar boss structure is surrounded by a channel layer; The support structure is columnar and has a second columnar boss structure extending radially outward, and an axis of the support structure is parallel to an axis of the gate pillar; The capacitor comprises a first electrode plate, a dielectric layer, and a second electrode plate, wherein the first electrode plate surrounds an outer surface of the support structure, the dielectric layer surrounds an outer surface of the first electrode plate, and an outer surface of the dielectric layer surrounding an outer surface of the second columnar boss structure is covered by the second electrode plate; An outer wall of the channel layer is in contact with an outer wall of the second electrode plate, and an end opposite to the capacitor is in contact with the bit line; The word line is connected by a plurality of the gate pillars vertically stacked.
2. The memory of claim 1, wherein, A side of the substrate close to the layers of memory cells is planar.
3. The memory according to claim 1, wherein, A material of the support structure is a spin-on dielectric layer; and / or, A material of the channel layer is a metal oxide; and / or, A material of the dielectric material layer and / or the dielectric layer is a high dielectric constant material.
4. The memory of claim 1, wherein, The transistor is a junctionless transistor.
5. The memory of claim 1, wherein, The first columnar boss structure is a cylindrical structure, and the channel layer is a cylindrical structure, and an axis of the cylindrical structure is parallel to an axis of the gate pillar.
6. A method of fabricating a memory, the memory comprising word lines, bit lines, and a plurality of layers of memory cells vertically stacked on a substrate; the layers of memory cells comprising a plurality of arrayed memory cells. The word line extends in a first direction perpendicular to the substrate and connects a plurality of memory cells of different layers; The bit line extends in a second direction parallel to the substrate and connects a plurality of memory cells of the same layer; the memory cell comprises a capacitor and a transistor; and the manufacturing method comprises: Alternately preparing a first isolation layer and a second isolation layer on a substrate to obtain a stacked structure; Etching the stacked structure in a first direction perpendicular to the substrate to form a capacitor hole penetrating through the stacked structure, and forming the capacitor and a support structure supporting the capacitor in the capacitor hole; a plurality of the capacitors are arranged in an array in a second direction parallel to the substrate and a third direction parallel to the substrate; Etching the stacked structure in the first direction to form a transistor hole penetrating through the stacked structure, and forming the transistor in each transistor hole; a plurality of the transistors are arranged in an array in the second direction and the third direction and correspond to a plurality of the capacitors one by one; a channel layer of the transistor is in contact with a second electrode plate of the capacitor and the bit line; a gate of a plurality of the transistors in the same transistor hole is connected as the word line to form the memory cell.
7. The production method according to claim 6, wherein The memory is the memory according to any one of claims 1 to 7, and Forming the capacitor in the capacitor hole includes: The first isolation layer is etched back along the radial direction of the capacitor hole to form a first annular groove parallel to the substrate in the capacitor hole. Deposit electrode material to form the second electrode plate on the surface of the first annular groove; A first dielectric material is deposited to form the dielectric layer of the capacitor on the inner wall of the capacitor hole and the inner surface of the second electrode plate. The electrode material is deposited to form the first electrode of the capacitor on the inner surface of the dielectric layer of the capacitor, thereby obtaining the capacitor; A spin-coated dielectric layer is deposited in the capacitor hole, such that the spin-coated dielectric layer fills the capacitor hole and the first annular groove, thereby obtaining a support structure for supporting the capacitor.
8. The manufacturing method according to claim 7, wherein Depositing electrode material to form a second electrode plate on the surface of the first annular groove includes: The electrode material is deposited in the capacitor hole such that the inner wall of the capacitor hole and the surface of the first annular groove are both covered by the electrode material; The first annular groove is filled with sacrificial material; The electrode material deposited on the inner wall of the capacitor hole is removed to obtain the second electrode plate; Remove the sacrificial material from the first annular groove.
9. The production method according to any one of claims 6 to 8, characterized by, Forming the transistor in each of the transistor holes includes: The first isolation layer is etched back along the radial direction of the transistor hole to form a second annular groove parallel to the substrate in the transistor hole, and the second electrode plate is at least partially exposed in the second annular groove; Deposit channel layer material in the second annular groove to form the channel layer, wherein the channel layer is a cylindrical structure parallel to the first direction; A second dielectric material is deposited to form the dielectric material layer on the inner wall of the transistor hole, the inner surface of the second annular groove, and the inner surface of the channel layer; A gate material is deposited in the transistor hole such that the gate material fills the transistor hole and the second annular groove to obtain the transistor.
10. The manufacturing method according to claim 9, wherein After forming a second annular groove parallel to the substrate in the transistor hole, and before forming the channel layer in the second annular groove, the method further includes: Electrode material is deposited to form a cylindrical electrode material layer in the second annular groove.
11. An electronic device, comprising: Includes the memory as described in any one of claims 1 to 5, or includes the memory formed by the manufacturing method as described in any one of claims 6 to 10.