Semiconductor device and semiconductor memory device including capacitor structure

Abstract

A semiconductor device and a semiconductor memory device are provided. The semiconductor device includes: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction; and a first support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the first support member includes a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in a first direction perpendicular to the second direction, the second support portion being located between the plurality of lower electrodes, each of the plurality of lower electrodes including a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion being a flat surface extending in the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices and semiconductor memory devices including capacitor structures. Background Technology

[0002] Semiconductor devices are core components used in electronic devices to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, memory devices can be used to store and retrieve data, while non-memory devices can be used to control or amplify electrical signals. Semiconductor devices are key components in electronic devices and can be used in various fields, including computers, communication equipment, and consumer electronics.

[0003] With industrial development, the performance and functional requirements of electronic devices are increasing daily. Therefore, there is a need for high-performance characteristics in semiconductor devices, and the integration density of semiconductor devices is constantly increasing to meet these demands. For example, there is a need for technologies that can increase the integration density of Dynamic Random Access Memory (DRAM) devices and form capacitors with excellent electrical characteristics. Therefore, DRAM devices can improve their electrical characteristics by minimizing electrode losses during the capacitor formation process. Summary of the Invention

[0004] The exemplary embodiments of this disclosure provide a semiconductor device with improved electrical characteristics and reliability.

[0005] The objectives of this invention are not limited to those described above, and those skilled in the art can clearly understand from the description of this disclosure other objectives not explicitly described herein.

[0006] According to some aspects of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction; and a first support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the first support member may include a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in a first direction perpendicular to the second direction, the second support portion being located between the plurality of lower electrodes, wherein each of the plurality of lower electrodes may include a protrusion and a recessed portion, the protrusion being located above a lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion may be a flat surface extending in the second direction.

[0007] According to some aspects of this disclosure, a semiconductor device may be provided, the semiconductor device comprising: a substrate; a plurality of lower electrodes located on the substrate and spaced apart from each other in a second direction, each of the plurality of lower electrodes extending in a first direction perpendicular to the second direction; a support member disposed on an upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes; and a mask pattern disposed in the first direction between at least one of the plurality of lower electrodes and the support member.

[0008] According to some aspects of this disclosure, a semiconductor device may be provided, the semiconductor device including a substrate, a capacitor structure, and a support member, the substrate including a plurality of transistors, the capacitor structure disposed on the substrate and connected to the plurality of transistors, wherein the capacitor structure may include a plurality of lower electrodes, an upper electrode, and a dielectric film, the plurality of lower electrodes each being connected to a corresponding transistor among the plurality of transistors, the upper electrode being disposed on the plurality of lower electrodes, the dielectric film being disposed between the plurality of lower electrodes and the upper electrode in a first direction, the support member being disposed on an upper surface of the plurality of lower electrodes and a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein the support member may include a first support portion and a second support portion, the first support portion overlapping the plurality of lower electrodes in the first direction, the second support portion being located between the plurality of lower electrodes, each of the plurality of lower electrodes including a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion, the recessed portion being located below the lower surface of the second support portion, and the upper surface of the protrusion being a flat surface extending in a second direction perpendicular to the first direction.

[0009] According to some aspects of this disclosure, during the process of forming a support covering the upper region of the lower electrode, a mask pattern formed on the lower electrode can minimize the loss of the lower electrode, thereby improving the electrical characteristics of the semiconductor device. Attached Figure Description

[0010] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 It is a plan view used to describe a semiconductor device according to an example embodiment; Figure 2 According to the example embodiment, along Figure 1 A cross-sectional view taken from line AA; Figure 3 According to the example embodiment Figure 2 A magnified view of region R; Figures 4 to 8 It is a diagram used to describe a semiconductor device according to an example embodiment; Figures 9 to 11 It is a diagram used to describe a semiconductor device according to an example embodiment; Figure 12 and Figure 13 It is a diagram used to describe a semiconductor device according to an example embodiment; Figure 14 and Figure 15 These are diagrams used to describe semiconductor devices according to example embodiments; and Figures 16 to 23 This is a diagram illustrating a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0011] In the following description, various aspects of this disclosure will be described with reference to the accompanying drawings. Throughout the description, the same reference numerals may refer to the same parts.

[0012] Reference Figures 1 to 3 A semiconductor device according to an example embodiment is described.

[0013] Figure 1 This is a plan view used to describe a semiconductor device according to an example embodiment. For example, Figure 1 This can correspond to a plan view provided to illustrate the layout of the lower electrode and the first support of a semiconductor device. Figure 2 According to the example embodiment, along Figure 1 The cross-sectional view taken from line AA. Figure 3 According to the example embodiment Figure 2 A magnified view of region R. For ease of description, Figure 1 The configuration other than the first support member 150 and the lower electrode 130 is omitted.

[0014] refer to Figure 1 and Figure 2 The semiconductor device may include a substrate 100, an interlayer insulating film 105, a contact plug 110, a landing pad 120, an etch stop film 125, a first support 150, a second support 152, and a capacitor structure C_ST.

[0015] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0016] The semiconductor device may include multiple transistors in the substrate 100. The semiconductor device may be a combination of multiple transistors and a memory device including at least one data storage structure. The semiconductor device may be dynamic random access memory (DRAM) or ferroelectric RAM (FeRAM).

[0017] An interlayer insulating film 105 may be disposed on a substrate 100. A landing pad 120 may be disposed on top of the interlayer insulating film 105. A contact plug 110 may be disposed within the interlayer insulating film 105. The contact plug 110 may be connected to the landing pad 120. For example, the contact plug 110 may electrically connect a corresponding transistor disposed within the substrate 100 to the landing pad 120.

[0018] For example, the interlayer insulating film 105 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and combinations thereof. For example, the contact plug 110 may include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. For example, the landing pad 120 may include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. The landing pad 120 may include tungsten (W).

[0019] An etch stop film 125 may be disposed on the interlayer insulating film 105. The etch stop film 125 may be disposed on the landing pad 120. The etch stop film 125 may expose at least a portion of the landing pad 120. For example, the etch stop film 125 may include an opening exposing at least a portion of the landing pad 120.

[0020] For example, the etch stop film 125 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon carbon oxide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbon nitride (SiOCN). In this disclosure, compounds such as silicon carbon oxide (SiCO) indicate the presence of silicon (Si), carbon (C), and oxygen (O), but the ratio between silicon (Si), carbon (C), and oxygen (O) is not specified.

[0021] A capacitor structure C_ST can be disposed on the substrate 100. The capacitor structure C_ST can store signals received from the transistors in the substrate 100. The capacitor structure C_ST can be used as a data storage element electrically connected to the transistors. For example, the capacitor structure C_ST can store charge under the control of the transistors.

[0022] The capacitor structure C_ST may include a lower electrode 130, a dielectric film 160, a conductive film 170, and an upper electrode 180. In an embodiment, the capacitor structure C_ST may include a plurality of lower electrodes 130. For example, each of the plurality of lower electrodes 130 may be connected to a corresponding transistor.

[0023] The lower electrode 130 may be disposed on the substrate 100. The lower electrode 130 may be disposed on the landing pad 120. The landing pad 120 may be disposed between the substrate 100 and the lower electrode 130. The lower electrode 130 may be electrically connected to the landing pad 120. A portion of the lower electrode 130 may be disposed in the etch stop film 125. For example, the lower electrode 130 may be formed to pass through the etch stop film 125 and be connected to the landing pad 120.

[0024] The lower electrode 130 may have a cylindrical shape. The lower electrode 130 may extend in a first direction D1. The first direction D1 may refer to a direction perpendicular or substantially perpendicular to the upper surface of the substrate 100.

[0025] The plurality of lower electrodes 130 can be configured as a hexagonal honeycomb structure. For example, each of the plurality of lower electrodes 130 can be disposed at each vertex and center of a hexagon, and the regular hexagonal structure in which each lower electrode 130 is disposed can be repeated. The lower electrodes 130 can be arranged to be spaced apart from each other along the second direction D2, and can be arranged in a zigzag shape along the third direction D3. However, the aspects of the invention are not limited to the above, and from a plan view, the lower electrodes 130 can have various shapes such as circular, elliptical, rectangular, square, and rhomboid. The second direction D2 and the third direction D3 are parallel to the upper surface of the substrate 100 and perpendicular to each other.

[0026] For example, the lower electrode 130 may include conductive metal materials (e.g., cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), etc.), noble metal materials (e.g., platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), conductive oxide films (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo, etc.), and metal silicide films. However, the aspects of the present invention are not limited to the above.

[0027] The first support member 150 may cover the upper portion of the plurality of lower electrodes 130. For example, the first support member 150 may be disposed on the upper surface of the plurality of lower electrodes 130 and on a portion of the side surfaces of the plurality of lower electrodes 130 extending from the upper surface. For example, the side surfaces of the lower electrodes 130 may include a portion facing the first support member 150. Thus, the first support member 150 may connect to and support lower electrodes 130 adjacent to each other.

[0028] The first support member 150 may include: a first support portion 150A, which overlaps with a plurality of lower electrodes 130 in a first direction D1; and a second support portion 150B, which is located between the plurality of lower electrodes 130. The thickness of the second support portion 150B may be greater than the thickness of the first support portion 150A. Thickness may refer to the distance from the upper surface to the lower surface of the component in the first direction D1.

[0029] The second support member 152 may be spaced apart from the first support member 150 in the first direction D1. For example, the second support member 152 may be located below the first support member 150. The first support member 150 and the second support member 152 may overlap each other in the first direction D1.

[0030] The second support 152 may surround the middle portion of the plurality of lower electrodes 130. For example, the second support 152 may be positioned at a vertical level corresponding to the middle portion of the plurality of lower electrodes 130. The second support 152 may be positioned between adjacent lower electrodes 130 to surround a portion of the side surface of each lower electrode 130. The side surface of the lower electrode 130 may include a portion facing the second support 152. Figure 2 A support member (e.g., a second support member 152) is shown disposed in the middle portion of the plurality of lower electrodes 130, but aspects of the invention are not limited thereto. Two or more supports may be disposed below the first support member 150 surrounding the plurality of lower electrodes 130.

[0031] Each of the first support member 150 and the second support member 152 may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), and tantalum oxide (TaO). In some aspects, the first support member 150 and the second support member 152 may include the same material, but aspects of the invention are not limited thereto. For example, the first support member 150 and the second support member 152 may include different materials.

[0032] The dielectric film 160 may be disposed on the upper surface of the first support 150 and extend along the contour of the upper surface of the first support 150.

[0033] Furthermore, the dielectric film 160 can be disposed on the lower electrode 130, the first support 150, and the second support 152. For example, the dielectric film 160 can be disposed on the side surface of the lower electrode 130, the lower surface of the first support 150, and the upper surface of the second support 152. The side surface of the lower electrode 130 can refer to the side portion of the lower electrode 130 located between the first support 150 and the second support 152, but not surrounded by either the first support 150 or the second support 152. The dielectric film 160 can extend along the contour of the side surface of the lower electrode 130, the lower surface of the first support 150, and the upper surface of the second support 152.

[0034] Furthermore, the dielectric film 160 may be disposed on the lower electrode 130, the etch stop film 125, and the second support 152. For example, the dielectric film 160 may be disposed on the side surface of the lower electrode 130, the lower surface of the second support 152, and the upper surface of the etch stop film 125. The side surface of the lower electrode 130 may refer to the side portion of the lower electrode 130 located between the second support 152 and the etch stop film 125, but not surrounded by the second support 152 or the etch stop film 125. The dielectric film 160 may extend along the contours of the side surface of the lower electrode 130, the lower surface of the second support 152, and the upper surface of the etch stop film 125.

[0035] For example, dielectric film 160 may include a high-k material, including silicon oxide, silicon nitride, silicon oxynitride, and metals. Although dielectric film 160 is shown as a single layer, this is only for ease of description, and aspects of the invention are not limited thereto. Unlike the illustration, dielectric film 160 may include multiple films.

[0036] A conductive film 170 may be disposed on a dielectric film 160. The conductive film 170 may extend along the contour of the dielectric film 160. The conductive film 170 may cover the dielectric film 160. For example, the dielectric film 160 may be disposed between the first support 150 and the conductive film 170. Furthermore, the dielectric film 160 may be disposed between the second support 152 and the conductive film 170. Additionally, the dielectric film 160 may be disposed between the lower electrode 130 and the conductive film 170. Furthermore, the dielectric film 160 may be disposed between the etch stop film 125 and the conductive film 170.

[0037] For example, the conductive film 170 may include at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), although aspects of the invention are not limited thereto.

[0038] The upper electrode 180 can be disposed on the conductive film 170. For example, the upper electrode 180 can fill the empty space between the lower electrodes 130. The upper electrode 180 can fill the remaining space between the plurality of lower electrodes 130 after the dielectric film 160 and the conductive film 170 have been formed.

[0039] Furthermore, the upper electrode 180 may be disposed on the first support member 150. For example, the upper electrode 180 may cover the dielectric film 160 and the conductive film 170 disposed on the first support member 150.

[0040] The upper electrode 180 may be electrically connected to the conductive film 170. For example, the upper electrode 180 may comprise at least one of an elemental semiconductor material film and a compound semiconductor material film. The upper electrode 180 may include doped n-type or p-type impurities.

[0041] Each of the plurality of lower electrodes 130 may include: a protrusion 130A located above the lower surface 150B_BS of the second support portion 150B; and a recessed portion 130B located below the lower surface 150B_BS of the second support portion 150B. For example, the protrusion 130A may be located at a vertical height higher than the lower surface 150B_BS of the second support portion 150B, while the recessed portion 130B may be located at a vertical height lower than the lower surface 150B_BS of the second support portion 150B.

[0042] Vertical height can refer to the vertical height in the first direction D1. Vertical height can refer to the distance from the reference height to the surface of a particular component in the first direction D1. The reference height can be the vertical height corresponding to the upper or lower surface of any component with a flat surface (e.g., substrate 100 or landing pad 120).

[0043] The side surfaces of the protrusion 130A and the embedded portion 130B can be aligned in the vertical direction (e.g., the first direction D1). For example, the first width W1 of the protrusion 130A in the second direction D2 can be the same as or substantially the same as the second width W2 of the embedded portion 130B in the second direction D2. The first width W1 of the protrusion 130A can refer to the average width of the protrusion 130A measured at all vertical heights in the second direction D2. Similarly, the second width W2 of the embedded portion 130B can refer to the average width of the embedded portion 130B measured at all vertical heights in the second direction D2.

[0044] The upper surface 130A_TS of the protrusion 130A can be a flat surface or a non-curved surface. For example, the upper surface 130A_TS of the protrusion 130A can include a flat surface. A flat surface can refer to a non-curved surface that retains its shape in its deposited state because a mask pattern formed on the surface prevents the surface from being etched or substantially etched. The protrusion 130A of the lower electrode 130 can be an area exposed to the outside by a patterning process. Prior to the patterning process, a mask pattern formed by a region selective deposition (ASD) process can be included on the upper surface of the lower electrode (e.g., Figures 9 to 11 The mask pattern formed on the upper surface of the lower electrode can be formed such that the upper surface of the lower electrode is less affected by the patterning process, so that the upper surface of the lower electrode can have a flat or substantially flat surface.

[0045] Figures 4 to 8 This is a diagram used to describe a semiconductor device according to an example embodiment. For reference, Figures 4 to 8 It can be with Figure 2 The diagram corresponds to a magnified view of region R. For ease of description, the main description will be related to the above. Figures 1 to 3 The differences in configuration.

[0046] The second support portion 150B may include a gap VD. (See reference) Figure 4 A void VD can be formed in the second support portion 150B, and the void VD can have an elliptical shape with its major axis located in the first direction D1. However, the invention is not limited to the above, and the void VD can be formed in various shapes. For example, the void VD can have an elliptical shape with its major axis located in any direction (e.g., in the second direction D2). The void VD can be formed when a portion of the interior of the second support portion 150B remains unfilled during the process of forming the first support member 150.

[0047] The first support member 150 may extend along the contour of the upper region of the plurality of lower electrodes 130. For example, the vertical height of the upper surface of the first support portion 150A and the vertical height of the upper surface of the second support portion 150B may be different from each other. (See reference) Figures 5 to 8 The vertical height of the uppermost portion of the upper surface of the first support portion 150A may be higher than the vertical height of the lowermost portion of the upper surface of the second support portion 150B. For example, the first support member 150 may have an upwardly projecting convex shape in the region where the first support member 150 and the lower electrode 130 overlap in the vertical direction (e.g., the first direction D1). Furthermore, the first support member 150 may have a downwardly projecting concave shape in the region between the lower electrodes 130.

[0048] In some examples, the protrusion 130A of the lower electrode 130 can have various shapes.

[0049] refer to Figure 6 The protrusion 130A may gradually decrease in width towards its upper portion. For example, the third width W3 of the upper surface 130A_TS of the protrusion 130A may be narrower than the fourth width W4 of the lower surface 130A_BS of the protrusion 130A. The lower surface 130A_BS of the protrusion 130A may refer to the cross-section of the lower electrode 130 at a vertical height corresponding to the lower surface 150B_BS of the second support portion 150B. Furthermore, each of the third width W3 and the fourth width W4 may refer to the width of the semiconductor device in the second direction D2. The third width W3 may refer to the distance between two side surfaces facing each other in the second direction D2 on the upper surface 130A_TS of the protrusion 130A, and the fourth width W4 may refer to the distance between the two side surfaces of the lower electrode 130 facing each other in the second direction D2 at the same vertical height as the lower surface 150B_BS of the second support portion 150B.

[0050] refer to Figure 7 The side surface 130A_SS of the protrusion 130A may have a concave shape. More specifically, the protrusion 130A may have a structure in which the side surface 130A_SS of the protrusion 130A curves inward into the protrusion 130A, causing the width of the protrusion 130A to gradually decrease and then gradually increase in the upward direction. For example, the fifth width W5 of the protrusion 130A at any vertical height between the upper surface 130A_TS and the lower surface 130A_BS of the protrusion 130A may be narrower than the third width W3 of the upper surface 130A_TS and the fourth width W4 of the lower surface 130A_BS of the protrusion 130A.

[0051] refer to Figure 8 The side surfaces 130A_SS of the protrusion 130A and 130B_SS of the embedded portion 130B may be misaligned in the first direction D1. For example, the side surfaces 130A_SS of the protrusion 130A and 130B_SS of the embedded portion 130B may not be on the same plane and may be arranged to be spaced apart from each other by a predetermined distance in the second direction D2. The first width W1 of the protrusion 130A may be narrower than the second width W2 of the embedded portion 130B.

[0052] Figures 9 to 11 This is a diagram used to describe a semiconductor device according to an example embodiment. For reference, Figures 9 to 11 It can be with Figure 2 The corresponding magnified image of region R. Besides the mask pattern MS. Figures 9 to 11 Semiconductor devices can be used with reference Figures 1 to 8 The semiconductor devices described are the same. For ease of description, the main description will be the same as... Figures 1 to 8 The above configurations are different from the configurations mentioned above.

[0053] The semiconductor device may also include a mask pattern MS disposed between at least one of the plurality of lower electrodes 130 and the first support member 150. For example, the mask pattern MS may be disposed between the lower surface of the first support portion 150A of the first support member 150 and the upper surface 130A_TS of the protrusion 130A.

[0054] The mask pattern MS may include a nitride film, an oxide film, a polycrystalline silicon film, a photoresist film, or a combination thereof. The mask pattern MS may include at least one of a spin-on hard mask (SOH) and an amorphous carbon layer (ACL). The mask pattern MS may include a material having different etch selectivity than an oxide layer.

[0055] The width of the lower surface MS_BS of the mask pattern MS and the width of the upper surface 130A_TS of the protrusion 130A can correspond to each other. For example, the width of the lower surface MS_BS of the mask pattern MS can be the same as or substantially the same as the width of the upper surface 130A_TS of the protrusion 130A.

[0056] In some embodiments, the mask pattern MS can have various shapes.

[0057] refer to Figure 9 The side surface MS_SS of the mask pattern MS can be vertically aligned with the side surface of at least one lower electrode 130. More specifically, the side surface MS_SS of the mask pattern MS can be aligned with the side surface 130A_SS of the protrusion 130A in a vertical direction (e.g., a first direction D1).

[0058] The mask pattern MS can have a curved shape. The side surface MS_SS of the mask pattern MS can have a convex shape. More specifically, refer to... Figure 10 The mask pattern MS can have the following structure: the side surface MS_SS of the mask pattern MS_SS bends outwards towards the mask pattern MS, causing the width of the mask pattern MS to gradually increase and then gradually decrease in the upward direction. The upper surface of the mask pattern MS can have a convex shape. (Reference) Figure 11 The width of the mask pattern MS in the second direction D2 can gradually decrease towards its upper part. For example, the mask pattern MS can be a semi-elliptic, but the invention is not limited thereto.

[0059] refer to Figures 9 to 11 The aspects of semiconductor devices including mask patterns MS described herein can be referenced. Figures 3 to 8The shape of the protrusion 130A of the lower electrode 130 is described in combination. For example, refer to Figures 9 to 11 Each of the mask patterns described in the reference can be set to a mask pattern MS. Figures 3 to 8 Each of them is described above the lower electrode 130.

[0060] Figure 12 and Figure 13 This is a diagram used to describe a semiconductor device according to an example embodiment. For reference, Figure 12 This is a schematic layout diagram illustrating a semiconductor device according to an example embodiment. Figure 13 It is according to the example embodiment along Figure 12 The cross-sectional view of line BB.

[0061] refer to Figure 12 and Figure 13 A semiconductor device may include multiple active regions ACT. The active regions ACT may be defined by a device isolation film 305 formed in a substrate 300. The substrate 300 may correspond to... Figure 2 The substrate 100. The active regions ACT can be strip-shaped. Multiple active regions ACT can be spaced apart from each other. The device isolation film 305 can have a shallow trench isolation (STI) structure with excellent device isolation characteristics.

[0062] For example, each device isolation film in device isolation film 305 may include at least one of silicon oxide film, silicon nitride film, and silicon oxynitride film, but is not limited thereto. Although it is shown that each device isolation film in device isolation film 305 is formed of an insulating film, this is only for ease of description, and aspects of the invention are not limited thereto.

[0063] Word lines WL can intersect with the active region ACT. Word lines WL can extend in the second direction D2. Multiple word lines WL can be spaced apart from each other in the third direction D3. Multiple word lines WL can be arranged at equal intervals. The width of each word line WL or the spacing between adjacent word lines WL can be determined according to design rules.

[0064] In some examples, the word line WL may be disposed on the gate trench formed in the substrate 300 and the device isolation film 305. The word line WL may include a gate insulating film, a gate electrode, and a gate overlay pattern.

[0065] The gate electrode may include at least one of the following: metal, metal alloy, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, doped semiconductor material, conductive metal oxynitride, and conductive metal oxide.

[0066] Multiple bit lines BL can be set on the word line WL, extending perpendicularly to the word line WL in the third direction D3. The multiple bit lines BL can extend parallel to each other. The multiple bit lines BL can be arranged at equal intervals. The width of each bit line BL or the spacing between adjacent bit lines BL can be determined according to design rules.

[0067] Bit line BL may include a first unit conductive film 322, a second unit conductive film 324, and a third unit conductive film 326. The first unit conductive film 322, the second unit conductive film 324, and the third unit conductive film 326 may be stacked sequentially on the substrate 300 and the device isolation film 305. Figure 13 The bit line BL is shown to be a three-layer film, but the invention is not limited thereto.

[0068] Each of the first unit conductive film 322, the second unit conductive film 324, and the third unit conductive film 326 may include at least one of the following: a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a metal, and a metal alloy.

[0069] Bit line cover film 330 may be disposed on bit line BL. Bit line cover film 330 may extend along the upper surface of the third unit conductive film 326. For example, bit line cover film 330 may include at least one of silicon nitride film, silicon oxynitride film, silicon carbon nitride film, and silicon oxycarbon nitride film. Bit line cover film 330 is shown as a single film, but aspects of the invention are not limited thereto.

[0070] A direct contact DC can be formed between the bit line BL and the substrate 300. The direct contact DC electrically connects the bit line BL to the substrate 300. The bit line BL can be formed on the direct contact DC. For example, the direct contact DC can be formed at the point where the bit line BL intersects with the middle portion of the active region ACT having an elongated island shape.

[0071] For example, direct contact with DC may include at least one of doped semiconductor materials, conductive silicide compounds, conductive metal nitrides, and metals.

[0072] The bit line BL may include a second unit conductive film 324 and a third unit conductive film 326 in the region overlapping with the upper surface of the DC that is in direct contact. The bit line BL may also include a first unit conductive film 322, a second unit conductive film 324, and a third unit conductive film 326 in the region that does not overlap with the upper surface of the DC that is in direct contact.

[0073] The unit insulating film 310 can be formed on the substrate 300 and the device isolation film 305. Specifically, the unit insulating film 310 can be formed on the device isolation film 305 and the substrate 300 at locations where there is no direct contact with DC. The unit insulating film 310 can be formed between the substrate 300 and the bit line BL, and between the device isolation film 305 and the bit line BL.

[0074] The cell line spacer SP can be disposed on the sidewalls of the bit line capping film 330 and the bit line BL. At the portion of the bit line BL that directly contacts the DC, the cell line spacer SP can be formed on the substrate 300 and the device isolation film 305. The cell line spacer SP can be disposed on the bit line BL, the bit line capping film 330, and the sidewall directly contacting the DC.

[0075] However, in the remaining portion of the bit line BL where no direct contact with DC is formed, cell line spacers SP can be disposed on the cell insulating film 310. Cell line spacers SP can be disposed on the sidewalls of the bit line cover film 330 and the bit line BL.

[0076] The unit line spacer SP can be a single-layer film, but as shown in the figure, the unit line spacer SP can be a multilayer film including a first unit line spacer 342, a second unit line spacer 344, a third unit line spacer 346, and a fourth unit line spacer 348. For example, the first unit line spacer 342, the second unit line spacer 344, the third unit line spacer 346, and the fourth unit line spacer 348 can include, but are not limited to, one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film (SiON), silicon oxycarbon nitride film (SiOCN), air, and combinations thereof.

[0077] Embedded contacts BC can be positioned between adjacent bit lines BL in the second direction D2. Embedded contacts BC can connect to the active region ACT. Embedded contacts BC can connect the active region ACT to the capacitor structure C_ST. This arrangement allows for a small contact area between the embedded contacts BC and the active region ACT. Therefore, the landing pad LP can be configured to increase the contact area with the active region ACT, and also increase the contact area with the capacitor structure C_ST.

[0078] For example, the embedded contact BC may include at least one of the following: a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

[0079] A landing pad LP can be formed on the buried contact BC. The landing pad LP can be electrically connected to the buried contact BC. The landing pad LP can be positioned between the active region ACT and the buried contact BC. The landing pad LP can be positioned between the buried contact BC and the lower electrode 130. Because the contact area is increased through the landing pad LP, the contact resistance between the active region ACT and the lower electrode 130 can be reduced.

[0080] For example, the landing pad LP may include at least one of the following: doped semiconductor material, conductive silicide compound, conductive metal nitride, conductive metal carbide, metal and metal alloy.

[0081] A pad isolation insulating film 360 can be disposed between landing pads LP. The pad isolation insulating film 360 can electrically isolate multiple landing pads LP from each other. For example, the pad isolation insulating film 360 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a silicon oxycarbonitride film.

[0082] The etch stop film 125 may be disposed on the upper surface of the landing pad LP and the upper surface of the pad isolation insulating film 360. For example, the etch stop film 125 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), silicon oxynitride (SiON), and silicon boron nitride (SiBN).

[0083] The capacitor structure C_ST can be set on the landing pad LP. The capacitor structure C_ST can be connected to the landing pad LP. For example, the capacitor structure C_ST can be electrically connected to the embedded contact BC.

[0084] The capacitor structure C_ST may include a lower electrode 130, a dielectric film 160, a conductive film 170, and an upper electrode 180. A first support 150 may be disposed on the upper surface of the lower electrode 130 and a portion of a side surface extending from the upper surface of the lower electrode 130. A second support 152 may surround the middle portion of the lower electrode 130. The description of the capacitor structure C_ST, the first support 150, and the second support 152 can be compared with... Figures 1 to 11 The same as those described in the text.

[0085] Furthermore, the mask pattern MS can be disposed between the lower electrode 130 and the first support 150. A description of the mask pattern MS can be found in the above reference. Figures 9 to 11 The description is the same.

[0086] Figure 14 and Figure 15 This is a diagram used to describe a semiconductor device according to an example embodiment. For reference, Figure 15 According to the example embodiment, along Figure 14The cross-sectional view taken from line CC.

[0087] refer to Figure 14 and Figure 15 The semiconductor device may include a substrate 400, a lower insulating film 410, a bit line BL, a word line WL, a gate insulating film 430, a channel layer 450, a landing pad LP, and a capacitor structure C_ST. According to some aspects, the semiconductor device may be a memory device including a vertical channel transistor VCT. A vertical channel transistor may refer to a structure in which the channel length of the channel layer 450 extends from the substrate 400 along a first direction D1, which is the vertical direction.

[0088] A lower insulating film 410 can be disposed on a substrate 400. Multiple bit lines BL can be disposed on the lower insulating film 410. The multiple bit lines BL can extend in a second direction D2. The multiple bit lines BL can be configured to be spaced apart from each other in a third direction D3.

[0089] Multiple bit lines BL may include at least one of doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, and RuTiN), conductive metal silicides, and conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), and LSCo), but the present invention is not limited thereto.

[0090] Multiple bit lines BL can comprise single-layer or multi-layer materials as described above. In some aspects, multiple bit lines BL can comprise graphene, carbon nanotubes, or combinations thereof.

[0091] A molding etch stop film 415 can be disposed on bit line BL. A molding pattern 420 can be disposed on the molding etch stop film 415. The molding etch stop film 415 and the molding pattern 420 can extend in a third direction D3. Multiple molding patterns 420 can be configured to be spaced apart from each other in a second direction D2.

[0092] A channel layer 450 may be disposed on a bit line BL. The channel layer 450 may be disposed between molding patterns 420. The channel layer 450 may include a horizontal portion contacting the bit line BL and a vertical portion extending from the horizontal portion in a first direction D1. The vertical portion may include a first vertical portion disposed at one end of the horizontal portion and a second vertical portion disposed at the other end of the horizontal portion. The first vertical portion and the second vertical portion may be spaced apart from each other in a second direction D2. In some examples, unlike the illustration, the horizontal portions of the channel layer may be separate.

[0093] The channel layer 450 may include an oxide semiconductor. For example, the oxide semiconductor may include InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, InGaO, or combinations thereof. The channel layer 450 may include a single layer or multiple layers of oxide semiconductor. Furthermore, the channel layer 450 may be, for example, polycrystalline or amorphous, but is not limited thereto. In some examples, the channel layer 450 may include graphene, carbon nanotubes, or combinations thereof.

[0094] A gate insulating film 430 may be disposed on the channel layer 450. The gate insulating film 430 may be disposed between the channel layer 450 and the word line WL. The channel layer 450 and the word line WL may be spaced apart from each other by the gate insulating film 430.

[0095] The gate insulating film 430 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a higher dielectric constant than that of a silicon oxide film, or a combination thereof.

[0096] The word line WL can be disposed on the gate insulating film 430. The word line WL can extend in the third direction D3. The word line WL can extend along the vertical portion of the channel layer 450 in the first direction D1.

[0097] In some examples, the upper surface of the word line WL may be set higher than the upper surface of the channel layer 450. For example, the distance from the upper surface of the bit line BL to the upper surface of the word line WL may be greater than the distance from the upper surface of the bit line BL to the upper surface of the vertical portion of the channel layer 450. However, the invention is not limited to the above. For example, the upper surface of the word line WL may be disposed in the same plane as the upper surface of the channel layer 450, or may be set lower than the upper surface of the channel layer 450.

[0098] The word line (WL) may include a conductive material. For example, the word line (WL) may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy.

[0099] Gate isolation pattern 470 may be disposed between word lines WL. The word lines WL may be spaced apart from each other by gate isolation pattern 470. For example, word lines WL disposed on a first vertical portion of channel layer 450 and word lines WL disposed on a second vertical portion of channel layer 450 may be spaced apart from each other by gate isolation pattern 470 in a second direction D2. Gate isolation pattern 470 may include insulating material.

[0100] Landing pads LP can be disposed on molded pattern 420 and gate isolation pattern 470. Landing pads LP may include protrusions extending toward channel layer 450. The protrusions of landing pads LP may contact vertical portions of channel layer 450. Landing pads LP may be electrically connected to channel layer 450.

[0101] The landing pad LP may include a conductive material. The landing pad LP may include at least one of the following: doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy.

[0102] An etch stop film 125 may be disposed on the upper surface of the landing pads LP and on the upper surface of the contact interlayer insulating film disposed between the landing pads LP. For example, the etch stop film 125 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), silicon oxynitride (SiON), and silicon boron nitride (SiBN).

[0103] The capacitor structure C_ST can be disposed on the landing pad LP. The capacitor structure C_ST can be connected to the landing pad LP. For example, the channel layer 450 and the capacitor structure C_ST can be electrically connected to each other through the landing pad LP.

[0104] The capacitor structure C_ST may include a lower electrode 130, a dielectric film 160, a conductive film 170, and an upper electrode 180. A first support 150 may be disposed on the upper surface of the lower electrode 130 and a portion of a side surface extending from the upper surface of the lower electrode 130. A second support 152 may surround the middle portion of the lower electrode 130. The description of the capacitor structure C_ST, the first support 150, and the second support 152 can be compared with... Figures 1 to 11 The same as those described in [the text].

[0105] Although not shown, a mask pattern MS may be disposed between the lower electrode 130 and the first support 150. A description of the mask pattern MS can be found in the above reference. Figures 9 to 11 The description is the same.

[0106] Figures 16 to 23 This is a diagram illustrating a method of manufacturing a semiconductor device according to an example embodiment. For reference, Figure 16 It is a plan view showing an intermediate stage in the manufacturing of semiconductor devices. Figures 17 to 23 It is according to the example embodiment along Figure 16 The cross-sectional view taken by line AA. For ease of description, Figure 16 The configuration except for the second support 152 and the lower electrode 130 is omitted.

[0107] refer to Figure 16 and Figure 17 Contact plugs 110, landing pads 120, and interlayer insulating films 105 can be formed on substrate 100. Figure 17 The contact plug 110, landing pad 120, and interlayer insulating film 105 can correspond to Figure 2 The contact plug 110, landing pad 120, and interlayer insulating film 105 are provided. An etch stop film 125, a first sacrificial film SC_1, a second support 152, a second sacrificial film SC_2, and a third sacrificial film SC_3 can be sequentially stacked on the interlayer insulating film 105 and the landing pad 120.

[0108] The first sacrificial film SC_1, the second sacrificial film SC_2, and the third sacrificial film SC_3 may comprise the same or similar materials. Each of the first sacrificial film SC_1, the second sacrificial film SC_2, and the third sacrificial film SC_3 may comprise silicon oxide or metal oxide. In an example embodiment, the first sacrificial film SC_1 and the second sacrificial film SC_2 may comprise silicon oxide or metal oxide, and the third sacrificial film SC_3 may comprise metal nitride or silicon nitride. However, the invention is not limited to the above.

[0109] Figure 17 An aspect employing three sacrificial film layers is shown, but the invention is not limited thereto. For example, it may include two sacrificial film layers, or four or more sacrificial film layers.

[0110] The lower electrode 130 can be formed through the third sacrificial film SC_3, the second sacrificial film SC_2, the second support 152, the first sacrificial film SC_1, and the etch stop film 125. The lower electrode 130 can be formed by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD).

[0111] refer to Figure 18 A mask pattern MS can be formed on the lower electrode 130. No mask pattern MS can be formed on the third sacrificial film SC_3. The mask pattern MS can be formed using a region-selective deposition (ASD) process. The ASD process may include inducing material deposition on the upper surface of the lower electrode 130 by pre-defining surfaces with different chemical activities.

[0112] refer to Figure 19 The portion of the third sacrificial film SC_3 exposed by the mask pattern MS can be removed by an etching process, thereby exposing the upper region of the lower electrode 130. For example, the etching process can be a dry etching process. The lower electrode 130 can have etch selectivity relative to the third sacrificial film SC_3. At least a portion of the mask pattern MS can be retained in the process of removing the third sacrificial film SC_3.

[0113] refer to Figure 20 A first support 150 may be formed on the upper region of the lower electrode 130 and on the remaining upper surface of the third sacrificial film SC_3. The upper surface of the first support 150 may be formed parallel to or substantially parallel to the upper surface of the substrate 100. However, the invention is not limited to the above. The first support 150 may extend along the shape of the lower electrode 130 exposed to the outside and along the contour of the upper surface of the third sacrificial film SC_3. The first support 150 may include a high vertical height portion and a low vertical height portion. The first support 150 may include: a relatively high vertical height portion located in the region overlapping with the lower electrode 130 in the first direction D1; and a relatively low vertical height portion located in the region overlapping with the third sacrificial film SC_3 in the first direction D1.

[0114] refer to Figure 21 The first sacrificial film SC_1, the second sacrificial film SC_2, and the third sacrificial film SC_3 can be removed by an etching process. For example, a wet etching process can be used to remove the first sacrificial film SC_1, the second sacrificial film SC_2, and the third sacrificial film SC_3. However, the invention is not limited to the above.

[0115] refer to Figure 22 A dielectric film 160 can be formed on the lower electrode 130, the first support 150, and the second support 152. The dielectric film 160 can be formed along the side surface of the lower electrode 130 exposed between the first support 150 and the second support 152, the lower surface of the first support 150, and the upper surface of the second support 152. Furthermore, the dielectric film 160 can be formed along the side surface of the lower electrode 130 exposed between the second support 152 and the etch stop film 125, the lower surface of the second support 152, and the upper surface of the etch stop film 125. Additionally, the dielectric film 160 can be formed along the contour of the upper surface of the first support 150. The upper surface of the dielectric film 160 can be formed parallel to or substantially parallel to the upper surface of the substrate 100. However, the invention is not limited to the above. The dielectric film 160 formed on the first support 150 may include a high vertical height portion and a low vertical height portion. The dielectric film 160 may include: a relatively high vertical height portion located in a region that overlaps with the lower electrode 130 in the first direction D1; and a relatively low vertical height portion located in a region that does not overlap with the lower electrode 130 in the first direction D1.

[0116] For example, the dielectric film 160 can be formed using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or PEALD.

[0117] refer to Figure 23 A conductive film 170 can be formed on the dielectric film 160. The conductive film 170 can be formed along the contour of the dielectric film 160. For example, the conductive film 170 can be formed along the contour of the dielectric film 160 disposed on the lower electrode 130, the first support 150, the second support 152, and the etch stop film 125. The upper surface of the conductive film 170 can be formed parallel to or substantially parallel to the upper surface of the substrate 100. However, the aspects of the invention are not limited to the above. The conductive film 170 formed on the dielectric film 160 may include a high vertical height portion and a low vertical height portion. The conductive film 170 may include: a relatively high vertical height portion located in a region overlapping with the lower electrode 130 in the first direction D1; and a relatively low vertical height portion located in a region not overlapping with the lower electrode 130 in the first direction D1.

[0118] The conductive film 170 can be formed using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or PEALD.

[0119] refer to Figure 2 An upper electrode 180 can be formed on the conductive film 170 to form a capacitor structure C_ST, thereby providing a reference. Figures 1 to 8 The semiconductor device is described. Furthermore, if the mask pattern MS remains on the lower electrode 130, a reference can be provided. Figures 9 to 11 The semiconductor device described.

[0120] While the concept of the invention has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made in the invention without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; A plurality of lower electrodes, the plurality of lower electrodes being located on the substrate and spaced apart from each other in a second direction; and A first support member is disposed on the upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein The first support member includes a first support portion and a second support portion. The first support portion overlaps with the plurality of lower electrodes in a first direction perpendicular to the second direction, and the second support portion is located between the plurality of lower electrodes. Each of the plurality of lower electrodes includes a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion and the recessed portion being located below the lower surface of the second support portion. The upper surface of the protrusion is a flat surface and extends in the second direction.

2. The semiconductor device according to claim 1, wherein, The side surface of the protrusion and the side surface of the embedded portion are aligned in the first direction.

3. The semiconductor device according to claim 1, wherein, The upper surface of the protrusion is narrower in the second direction than the lower surface of the protrusion is narrower in the second direction.

4. The semiconductor device according to claim 1, wherein, The side surface of the protrusion has a concave shape.

5. The semiconductor device according to claim 1, wherein, The second support portion includes a gap located within the second support portion.

6. The semiconductor device according to claim 1, wherein, The width of the protrusion in the second direction is narrower than the width of the embedded portion in the second direction.

7. The semiconductor device of claim 1, further comprising a mask pattern disposed in the first direction between the first support and the upper surface of the protrusion.

8. The semiconductor device according to claim 7, wherein, The width of the lower surface of the mask pattern and the width of the upper surface of the protrusion correspond to each other.

9. The semiconductor device according to claim 7, wherein, The side surface of the mask pattern is aligned with the side surface of the protrusion in the first direction.

10. The semiconductor device according to claim 7, wherein, The mask pattern has a curved shape.

11. The semiconductor device according to claim 7, wherein, The side surfaces of the mask pattern have a convex shape.

12. The semiconductor device according to claim 7, wherein, The width of the mask pattern in the second direction gradually decreases towards the upper part of the mask pattern.

13. The semiconductor device according to claim 1, wherein, The vertical height of the uppermost part on the upper surface of the first support portion is higher than the vertical height of the lowermost part on the upper surface of the second support portion.

14. The semiconductor device according to claim 1, further comprising: A plurality of landing pads are disposed between the substrate and the plurality of lower electrodes in the first direction, and each of the plurality of landing pads is connected to a corresponding lower electrode among the plurality of lower electrodes; The upper electrode is disposed on the plurality of lower electrodes; and A dielectric film is disposed between the plurality of lower electrodes and the upper electrode in the first direction.

15. The semiconductor device of claim 1, further comprising a second support member disposed on a side surface of the plurality of lower electrodes.

16. A semiconductor device, the semiconductor device comprising: Substrate; A plurality of lower electrodes are located on the substrate and spaced apart from each other in a second direction, each of the plurality of lower electrodes extending in a first direction perpendicular to the second direction; A support member is disposed on the upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes; and A mask pattern disposed in the first direction between at least one of the plurality of lower electrodes and the support member.

17. The semiconductor device according to claim 16, wherein, The mask pattern is disposed between the lower surface of a portion of the support and the upper surface of the at least one lower electrode.

18. The semiconductor device according to claim 16, wherein, The side surface of the mask pattern is aligned with the side surface of the at least one lower electrode in the first direction.

19. The semiconductor device according to claim 16, wherein, The side surface of the mask pattern has a convex shape in the second direction.

20. A semiconductor memory device, the semiconductor memory device comprising: Substrate, the substrate comprising a plurality of transistors; A capacitor structure, disposed on the substrate and connected to the plurality of transistors, the capacitor structure comprising: Multiple lower electrodes, each of which is connected to a corresponding transistor in the plurality of transistors; Upper electrode, the upper electrode being disposed on the plurality of lower electrodes; and A dielectric film disposed in a first direction between the plurality of lower electrodes and the upper electrode; and A support member is disposed on the upper surface of the plurality of lower electrodes and on a portion of a side surface extending from the upper surface of the plurality of lower electrodes, wherein: The support member includes a first support portion and a second support portion, wherein the first support portion overlaps with the plurality of lower electrodes in the first direction, and the second support portion is located between the plurality of lower electrodes. Each of the plurality of lower electrodes includes a protrusion and a recessed portion, the protrusion being located above the lower surface of the second support portion and the recessed portion being located below the lower surface of the second support portion. The upper surface of the protrusion is a flat surface and extends in a second direction perpendicular to the first direction.

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