Semiconductor structure and method of manufacturing the same
CN122248729APending Publication Date: 2026-06-19NAN YA TECH
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2025-12-23
- Publication Date
- 2026-06-19
AI Technical Summary
Technical Problem
Defects in the manufacturing and integration of DRAM memory cells increase structural complexity and affect performance.
Method used
A low-k dielectric layer is covered by three insulating oxide layers, including a low-k dielectric layer, a first insulating oxide layer, a second insulating oxide layer, and a third insulating oxide layer, which are formed by atomic layer deposition technology. The oxygen content of each layer gradually increases to improve etch resistance and reduce dielectric constant.
Benefits of technology
This improves the etch resistance of DRAM memory cells, reduces the dielectric constant of bit line spacers, reduces bit line parasitic capacitance, and enhances electrical performance and yield.
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Smart Images
Figure CN122248729A_ABST
Abstract
This invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor substrate, a bitline structure, and bitline spacers. The bitline structure is located on the semiconductor substrate. The bitline spacers include a low-k dielectric layer and first, second, and third insulating oxide layers. The low-k dielectric layer covers the sidewalls of the bitline structure. The first insulating oxide layer covers the low-k dielectric layer and has a first oxygen content. The second insulating oxide layer covers the first insulating oxide layer and has a second oxygen content. The third insulating oxide layer covers the second insulating oxide layer and has a third oxygen content. The third oxygen content is higher than the second oxygen content, and the second oxygen content is higher than the first oxygen content. The first, second, and third insulating oxide layers improve the etch resistance of the bitline spacers, thus protecting the low-k dielectric layer from damage in subsequent etching processes and reducing the parasitic capacitance of the bitlines. Therefore, this semiconductor structure can exhibit good electrical performance.
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