Semiconductor structure, method for manufacturing a semiconductor structure, and electronic device
By incorporating a fluorine-containing semiconductor layer in an oxide-channel 3D memory architecture, the problem of transistor turn-off difficulty caused by oxide-channel materials is solved, improving memory performance and reliability, and achieving positive shifts in carrier mobility and threshold voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Oxide channel materials make transistors difficult to turn off, resulting in poor gate control and affecting memory performance and reliability.
In an oxide channel 3D memory architecture, a fluorine-containing semiconductor layer is formed by setting a first hole and a first receiving trench surrounding and connecting the first hole in a semiconductor structure, and setting a fluorine-containing metal oxide semiconductor material on the inner wall, and doping fluorine ions to occupy oxygen vacancies.
It improves the performance and reliability of oxide channel 3D memory devices, enhances carrier mobility and threshold voltage stability, and strengthens gate control capabilities.
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Figure CN122248731A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a method for fabricating the semiconductor structure, and an electronic device. Background Technology
[0002] Memory is a storage device used in modern information technology to store information. With the development of integrated circuit technology, the types of memory have become increasingly diverse. Currently, memory is widely used in various electronic products such as personal computers, laptops, and mobile phones.
[0003] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] Based on this, this disclosure provides a semiconductor structure for improving the performance and reliability of memory devices, a method for fabricating the semiconductor structure, and an electronic device.
[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a method for fabricating a semiconductor structure, comprising:
[0006] A stacked structure is formed, which includes multiple alternating layers of first dielectric layers and multiple layers of second dielectric layers;
[0007] A patterned stacked structure is used to form the first hole;
[0008] A first dielectric layer is patterned in the first hole to form a first receiving groove;
[0009] A fluorine-containing material layer, a semiconductor material layer, a gate dielectric layer, and a conductive layer are sequentially stacked in the first receiving groove and the first hole, and the resulting stacked structure is heat-treated to obtain a fluorine-containing semiconductor layer.
[0010] A patterned stacked structure forms a first groove located on at least one side of a first receiving groove; wherein a plurality of first holes are arranged in a row along a first direction, and the first groove extends along the first direction and penetrates the stacked structure;
[0011] A first dielectric layer is patterned along the direction close to the first hole based on the first trench, and a fluorine-containing material layer and a fluorine-containing semiconductor layer are patterned in the first accommodating trench to form a second accommodating trench; the second accommodating trench exposes the gate dielectric layer.
[0012] Oxygen vacancies in oxide channel materials cause a series of problems: the negative correlation between carrier mobility and threshold voltage Vth in oxide channel FETs (Field-Effect Transistors) leads to a negative shift in Vth while increasing the on-state current, resulting in difficulty in turning off the transistor and deterioration of gate control. Therefore, the semiconductor structure fabrication method in the above embodiments of this disclosure, based on the oxide channel 3D memory architecture, proposes a solution to improve the performance and reliability of the memory by doping with fluorine (F). Specifically, this disclosure sequentially stacks a fluorine-containing material layer, a semiconductor material layer, a gate dielectric layer, and a conductive layer within the first accommodating trench and the first hole formed in the semiconductor structure, and performs heat treatment on the resulting structure so that the oxygen vacancies in the semiconductor material layer are occupied by fluorine ions in the fluorine-containing material layer to obtain a fluorine-containing semiconductor layer, thereby realizing a semiconductor structure fabrication method that can improve and enhance the performance and reliability of oxide channel memory devices.
[0013] In some embodiments, the method for fabricating a semiconductor structure further includes:
[0014] A first isolation layer covering the gate dielectric layer is formed within the second receiving groove;
[0015] In some embodiments, the method for fabricating a semiconductor structure further includes:
[0016] Based on the first trench, a second dielectric layer is patterned along the direction close to the first hole until a fluorine-containing material layer is exposed, and the fluorine-containing material layer is patterned to form a third accommodating trench; the third accommodating trench exposes a fluorine-containing semiconductor layer;
[0017] A second isolation layer is formed within the third receiving groove, at least partially covering the fluorine-containing semiconductor layer.
[0018] In some embodiments, the first trench is located on one side of the first receiving groove; the preparation method further includes:
[0019] Source / drain electrodes and / or bit lines that at least partially cover the fluorine-containing semiconductor layer are formed in the third accommodating trench.
[0020] In some embodiments, the first groove is also located between two adjacent columns of first holes, and the two adjacent columns of first holes are symmetrically arranged with the first groove as the center.
[0021] The preparation method also includes: forming an isolation structure in the first trench.
[0022] In some embodiments, heat treatment of the resulting structure includes performing an annealing process on the resulting structure;
[0023] The annealing temperature range for the annealing process includes 350℃~400℃.
[0024] In some embodiments, the doping concentration of fluorine ions in the fluorine-containing material layer is greater than 4 × 10⁻⁶. 12 / cm 2 .
[0025] In some embodiments, before sequentially stacking the fluorine-containing material layer, the semiconductor material layer, the gate dielectric layer, and the conductive layer in the first receiving groove and the first hole, the preparation method further includes:
[0026] A sacrificial layer is formed on the inner wall of the first receiving groove in a conformal manner;
[0027] The fluorine-containing material layer covers the sacrificial layer.
[0028] In some embodiments, the method for fabricating a semiconductor structure includes at least one of the following features:
[0029] The materials for the sacrificial layer include polycrystalline silicon;
[0030] The materials used for the fluorinated layer include fluorosilicate glass;
[0031] The materials used in the semiconductor layer include metal oxide semiconductor materials.
[0032] A second aspect of this disclosure provides a semiconductor structure, including:
[0033] A stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately; the stacked structure has a first hole penetrating each of the first dielectric layers and the second dielectric layers, and a first receiving groove located in the first dielectric layer and surrounding the first hole;
[0034] A fluorine-containing semiconductor layer is located on the inner wall of the first hole between adjacent first receiving trenches; the material of the fluorine-containing semiconductor layer includes fluorine-containing metal oxide semiconductor materials;
[0035] A gate dielectric layer covers the fluorine-containing semiconductor layer and the inner wall of the first accommodating trench;
[0036] A conductive layer covers the gate dielectric layer and is located on the side of the gate dielectric layer away from the fluorine-containing semiconductor layer.
[0037] To address the issues of transistor turn-off difficulties and gate control degradation caused by the introduction of oxide channel materials, the semiconductor structure in the above embodiments of this disclosure, based on the oxide channel 3D memory architecture, proposes to provide a first hole and a first receiving trench surrounding and communicating with the first hole in the semiconductor structure, and to provide a fluorine-containing semiconductor layer comprising a metal oxide semiconductor material in which fluorine ions occupy oxygen vacancies on the inner wall of the first hole located between adjacent first receiving trenches, thereby realizing a semiconductor structure that can improve and enhance the performance and reliability of oxide channel 3D memory devices.
[0038] In some embodiments, the stacked structure further includes a first trench located at least on one side of the first receiving groove and penetrating each of the first dielectric layers and each of the second dielectric layers, and a second receiving groove located on the side of the first trench near the first hole and within the first dielectric layer; the second receiving groove exposes at least a portion of the gate dielectric layer located in the first receiving groove.
[0039] Among them, multiple first holes are arranged in a row along a first direction, and the first groove extends along the first direction;
[0040] The semiconductor structure further includes a first isolation layer that at least partially covers the gate dielectric layer in the second accommodating trench.
[0041] In some embodiments, the stacked structure further includes a third accommodating trench located on the side of the first trench near the first hole and within the second dielectric layer; the third accommodating trench exposes a fluorine-containing semiconductor layer;
[0042] The semiconductor structure also includes a second isolation layer that at least partially covers the fluorine-containing semiconductor layer.
[0043] In some embodiments, the first trench is located on one side of the first accommodating trench; the semiconductor structure further includes source / drain electrodes and / or bit lines that at least partially cover a fluorine-containing semiconductor layer within a third accommodating trench.
[0044] In some embodiments, the first groove is located on one side of the first receiving groove and between two adjacent columns of first holes; the two adjacent columns of first holes are symmetrically arranged with the first groove as the center.
[0045] The semiconductor structure also includes an isolation structure disposed in the first trench.
[0046] According to some embodiments, a third aspect of this disclosure provides an electronic device including the semiconductor structure of the first aspect described above, or a semiconductor structure prepared based on the method for preparing the semiconductor structure of the second aspect. Attached Figure Description
[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0048] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0049] Figure 2 This is a three-dimensional schematic diagram of the structure obtained in S10 of one embodiment;
[0050] Figure 3 and Figure 4 This is a three-dimensional structural diagram of the structure obtained by the preparation process of S20 in one embodiment;
[0051] Figure 5 This is a three-dimensional schematic diagram of the structure obtained in S30 of one embodiment;
[0052] Figure 6 This is a three-dimensional structural diagram of a structure formed after polycrystalline silicon deposition in one embodiment;
[0053] Figure 7 This is a three-dimensional structural diagram of a structure obtained by forming a sacrificial layer on the inner wall of a first receiving groove, as provided in one embodiment.
[0054] Figures 8-12 This is a three-dimensional structural diagram of the structure obtained by the preparation process of S40 in one embodiment;
[0055] Figure 13 for Figure 12 A larger view of a portion of the structure shown;
[0056] Figure 14 and Figure 15 This is a three-dimensional structural diagram of the structure obtained from the preparation process of S50 in one embodiment;
[0057] Figures 16 to 20 This is a three-dimensional structural diagram of the structure obtained by the preparation process of S60 in one embodiment;
[0058] Figure 21 This is a three-dimensional structural diagram of the structure formed by the first trench and the second receiving groove in one embodiment;
[0059] Figure 22 for Figure 21 A larger view of a portion of the structure shown;
[0060] Figure 23 This is a three-dimensional structural diagram of the structure obtained before the formation of the first isolation layer covering the gate dielectric layer in the second receiving groove, as provided in one embodiment.
[0061] Figure 24 This is a three-dimensional structural diagram of a structure obtained by forming a first isolation layer covering the gate dielectric layer in a second receiving groove, as provided in one embodiment.
[0062] Figure 25 This is a flowchart of a method for fabricating a semiconductor structure provided in yet another embodiment;
[0063] Figure 26 and Figure 27 This is a three-dimensional structural diagram of the structure obtained from the preparation process of S2502 in one embodiment;
[0064] Figure 28 This is a three-dimensional structural diagram of the structure obtained in S2504 provided in one embodiment;
[0065] Figure 29 for Figure 28 A larger view of a portion of the structure shown;
[0066] Figure 30 This is a three-dimensional structural diagram of the structure obtained after partially removing the second isolation layer in the third receiving groove to expose the source / drain contact area, as provided in one embodiment.
[0067] Figure 31 A three-dimensional structural schematic diagram of a semiconductor structure prepared by a semiconductor structure preparation method provided in one embodiment is shown.
[0068] Figure 32 for Figure 31 A larger view of a portion of the structure shown;
[0069] Figure 33 for Figure 31 The diagram shows a three-dimensional structure with different layers as the top cross-section.
[0070] Explanation of reference numerals in the attached figures:
[0071] 100. Stacked structure; 110. First dielectric layer; 120. Second dielectric layer; 210. First via; 220. First accommodating trench; 130. Fluorine-containing material layer; 140. Semiconductor material layer; 150. Gate dielectric layer; 160. Conductive layer; 170. Fluorine-containing semiconductor layer; 230. First trench; 240. Second accommodating trench; 180. First isolation layer; 250. Third accommodating trench; 190. Second isolation layer; 300. Source / drain electrode and / or bit line; 191. Polysilicon layer; 192. Sacrificial layer; D1. First orientation; 400. Substrate; 510. Hard mask layer; 520. Anti-reflective layer; 530. Photoresist layer; 500. Isolation structure. Detailed Implementation
[0072] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0074] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0075] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0076] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0077] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0078] Please see Figure 1 This disclosure provides a method for preparing a semiconductor structure, comprising the following steps: S10-S60.
[0079] S10: Form a stacked structure 100, which includes multiple layers of first dielectric layers 110 and multiple layers of second dielectric layers 120 stacked alternately.
[0080] For example, a stacked structure 100 is formed on a substrate. The substrate can be made of any combination of semiconductor materials, insulating materials, conductive materials, or such materials. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0081] Please see Figure 2 , Figure 2 This is a three-dimensional schematic diagram of the structure obtained in S10. (Example) Figure 2As shown, a stacked structure 100 can be formed on a substrate 400 using a deposition process. The stacked structure 100 includes alternating layers of first dielectric layers 110 and second dielectric layers 120. The first dielectric layers 110 provide support, ensuring the stability of the semiconductor structure throughout the fabrication process. The etching ratios of the second dielectric layers 120 and the first dielectric layers 110 are different. The first dielectric layer 110 can be silicon oxide, etc., and the second dielectric layer 120 can be silicon nitride, etc. The deposition process can include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD). As a further example, the second dielectric layer 120 can be prepared by plasma-enhanced chemical vapor deposition (PECVD), and the first dielectric layer 110 can be prepared by low-pressure chemical vapor deposition (LPCVD).
[0082] S20: Patterned stacked structure 100 forms the first hole 210.
[0083] Optionally, patterning can be achieved through an etching process. For an example, please refer to... Figure 3 and Figure 4 . Figure 3 and Figure 4 This is a schematic diagram of the three-dimensional structure of the structure obtained during the preparation process of S20. Please refer to [the diagram first]. Figure 3 , Figure 3 The diagram illustrates the preparatory work before forming the first aperture 210: first, a hard mask layer 510 is formed on the stacked structure 100; then, an anti-reflective layer 520 is formed above the hard mask layer 510; and finally, a photoresist layer 530 is formed on the anti-reflective layer 520. The hard mask layer 510 is a carbon layer, and the anti-reflective layer 520 is a SION layer. Forming the anti-reflective layer 520 between the photoresist and the hard mask layer 510 optimizes the photoresist exposure effect and reduces rough edges. Specifically, the SION layer, as an anti-reflective layer 520, effectively reduces light reflection and interference during photolithography, reduces standing wave effects, and thus ensures a more precise and uniform photoresist exposure effect. This makes the photoresist edges smoother after development, reducing roughness. Subsequently, after patterning the stacked structure 100, a layer is formed as shown... Figure 4The structure shown has a first hole 210 that extends through the entire stacked structure 100 up to the substrate 400.
[0084] S30: Pattern the first dielectric layer 110 based on the first hole 210 to form the first receiving groove 220.
[0085] For example, please refer to Figure 5 . Figure 5 This is a three-dimensional structural diagram of the structure obtained in S30. Specifically, the first dielectric layer 110 is laterally patterned based on the first hole 210, thereby forming a first receiving groove 220 within the first dielectric layer 110 and surrounding the first hole 210.
[0086] S40: A fluorine-containing material layer 130, a semiconductor material layer 140, a gate dielectric layer 150 and a conductive layer 160 are sequentially stacked in the first receiving groove 220 and the first hole 210, and the resulting structure is heat-treated to obtain a fluorine-containing semiconductor layer 170.
[0087] Oxygen vacancies in oxide channel materials cause a series of problems: the negative correlation between carrier mobility and threshold voltage Vth in oxide channel FETs (Field-Effect Transistors) leads to a negative shift in Vth while increasing the on-state current, resulting in difficulty in turning off the transistor and deterioration of gate control. Therefore, the semiconductor structure fabrication method in the above embodiments of this disclosure, based on the oxide channel 3D memory architecture, proposes a solution to improve the performance and reliability of the memory by doping with fluorine (F). Specifically, this disclosure sequentially stacks a fluorine-containing material layer 130, a semiconductor material layer 140, a gate dielectric layer 150, and a conductive layer 160 within the first accommodating trench 220 and the first hole 210 formed in the semiconductor structure, and performs heat treatment on the resulting structure so that the oxygen vacancies in the semiconductor material layer 140 are occupied by fluorine ions in the fluorine-containing material layer 130 to obtain a fluorine-containing semiconductor layer 170, thereby realizing a semiconductor structure fabrication method that can improve and enhance the performance and reliability of oxide channel 3D memory devices.
[0088] S50: A patterned stacked structure forms a first groove located on at least one side of the first receiving groove; wherein a plurality of first holes are arranged in a row along a first direction, and the first groove extends along the first direction and penetrates the stacked structure.
[0089] Wherein, the first direction D1 is a direction parallel to the substrate 400.
[0090] S60: Based on the first trench, a first dielectric layer is patterned along the direction close to the first hole, and a fluorine-containing material layer and a fluorine-containing semiconductor layer are patterned in the first accommodating trench to form a second accommodating trench; the second accommodating trench exposes the gate dielectric layer.
[0091] Specifically, this disclosure, based on existing three-dimensional structures, optimizes the process by doping F into the semiconductor material layer. This achieves positive shifts in carrier mobility and threshold voltage, improving the performance of oxide-channel 3D memory devices and enhancing device stability. Specifically, before depositing the semiconductor material layer, an F-doped thin film (i.e., a fluorine-containing material layer) is deposited. The F-doped film is then annealed at a specific temperature in contact with the semiconductor material layer. This allows F ions from the doped film to diffuse into the semiconductor material layer, reducing oxygen vacancies and thus improving carrier mobility and positive threshold voltage shift. This enhances gate control capability and device stability.
[0092] In some embodiments, before sequentially stacking the fluorine-containing material layer 130, the semiconductor material layer, the gate dielectric layer 150, and the conductive layer 160 in the first receiving groove 220 and the first hole 210, the preparation method further includes: forming a sacrificial layer 192 on the inner wall of the first receiving groove 220; wherein the fluorine-containing material layer 130 covers the sacrificial layer 192.
[0093] For example, please refer to Figure 6 and Figure 7 . Figure 6 This is a schematic diagram of the three-dimensional structure formed after the deposition of polycrystalline silicon layer 191; Figure 7 A three-dimensional structural diagram of the structure obtained by forming a sacrificial layer on the inner wall of the first receiving groove.
[0094] First, a polysilicon layer 191 is deposited in the formed first hole 210 and first accommodating trench 220. Further, the polysilicon layer 191 fills the first accommodating trench 220. (See reference...) Figure 6 , Figure 6 This is a three-dimensional structural diagram of the structure formed after the polysilicon layer 191 is deposited. Subsequently, the polysilicon layer 191 is partially removed, resulting in a portion of the polysilicon layer located on the inner wall of the first receiving trench 220 within the first dielectric layer 110, which is the sacrificial layer 192. Please refer to [reference needed]. Figure 7 , Figure 7 A three-dimensional structural diagram showing the structure obtained by forming a sacrificial layer 192 on the inner wall of the first receiving tank 220. In subsequent processes, a fluorine-containing material layer 130 covers the sacrificial layer 192.
[0095] In this embodiment, a support material is formed by depositing a polysilicon layer in the first hole and the first accommodating groove. Subsequently, the polysilicon layer is partially removed, and the portion of the polysilicon layer located on the inner wall of the first accommodating groove in the first dielectric layer is the sacrificial layer, which can ensure that the first accommodating groove will not collapse when constructing structures in other areas.
[0096] In some embodiments, please refer to Figures 8-12 , Figures 8-12 This is a three-dimensional structural diagram of the structure obtained during the preparation process of S40.
[0097] For example, Figures 8-11 This is a three-dimensional structural diagram of the structure obtained by sequentially stacking a fluorine-containing material layer 130, a semiconductor material layer 140, a gate dielectric layer 150, and a conductive layer 160 within the first receiving groove 220 and the first hole 210. Specifically, after forming the fluorine-containing material layer 130 in the first receiving groove 220 and the first hole 210, the following is obtained: Figure 8 The diagram shows a three-dimensional structure; a fluorine-containing material layer 130 is formed in the first receiving groove 220 and the first hole 210, and then a semiconductor material layer 140 is stacked to obtain... Figure 9 The diagram shows a three-dimensional structure; a fluorine-containing material layer 130 and a semiconductor material layer 140 are sequentially stacked in the first receiving groove 220 and the first hole 210, followed by a gate dielectric layer 150, to obtain... Figure 10 The diagram shows a three-dimensional structural schematic; after sequentially stacking a fluorine-containing material layer 130, a semiconductor material layer 140, a gate dielectric layer 150, and a conductive layer 160 within the first receiving groove 220 and the first hole 210, the following is obtained: Figure 11 The diagram shows a three-dimensional structural schematic. The conductive layer 160 is a combination of a gate and a word line. The portion of the conductive layer within the first hole 210 facing the channel region of the fluorine-containing semiconductor layer can be considered as the gate; the remaining portions of the conductive layer 160 connecting the gates within the same first hole 210 can be considered as word lines.
[0098] Furthermore, a fluorine-containing material layer 130, a semiconductor material layer 140, a gate dielectric layer 150, and a conductive layer 160 are sequentially stacked within the first receiving groove 220 and the first hole 210, and the resulting structure is heat-treated to obtain... Figure 12 A three-dimensional structural diagram of the structure shown.
[0099] For example, the structure obtained after forming the fluorine-containing material layer 130, the semiconductor material layer 140, the gate dielectric layer 150 and the conductive layer 160 is subjected to heat treatment, including performing an annealing process on the obtained structure; wherein the annealing temperature range of the annealing process includes 350°C to 400°C.
[0100] In addition, for example Figure 11 Before heat treatment, the structure shown may undergo chemical mechanical polishing (CMP) treatment. Specifically, the CMP process stops after reaching the second dielectric layer 120, followed by heat treatment, which occupies oxygen vacancies in the semiconductor material layer 140 with fluorine ions in the fluorine-containing material layer 130 to obtain the fluorine-containing semiconductor layer 170. Please also refer to... Figure 13 , Figure 13 for Figure 12 As shown in the enlarged view of the structure, it can be understood that when the sacrificial layer 192 is not formed in the first receiving tank 220 in the preceding steps, there is no sacrificial layer 192 in the first receiving tank 220 of the first medium layer 110. At this time, the outermost layer of the first receiving tank 220 is the fluorine-containing material layer 130.
[0101] In some embodiments, after annealing the resulting structure, the fluorine ion doping concentration in the fluorine-containing material layer 130 is greater than 4 × 10⁻⁶. 12 / cm 2 .
[0102] In some embodiments, please refer to Figure 14 and Figure 15 , Figure 14 and Figure 15 This is a three-dimensional structural diagram of the structure obtained during the preparation process of S50.
[0103] For example, please refer to... Figure 14 , Figure 14 The diagram illustrates the preparatory work before forming the first trench 230 located on at least one side of the first accommodating trench 220: firstly, a hard mask layer 510 is formed on the stacked structure 100, then an anti-reflective layer 520 is formed above the hard mask layer 510, and then a photoresist layer 530 is formed on the anti-reflective layer 520, wherein the hard mask layer 510 is a carbon layer and the anti-reflective layer 520 is a SION layer. Forming the anti-reflective layer 520 between the photoresist and the hard mask layer 510 can optimize the photoresist exposure effect and reduce rough boundaries. Specifically, the SION layer, as an anti-reflective layer 520, can effectively reduce light reflection and interference during photolithography, reduce standing wave effects, and thus ensure a more accurate and uniform photoresist exposure effect. This makes the photoresist boundary smoother after development, reducing roughness. Subsequently, after patterning the stacked structure 100, a layer such as... Figure 15 The structure shown has a plurality of first holes 210 arranged in a column along a first direction D1, and a first groove 230 extending along the column direction and penetrating the stacked structure 100. Figure 15 The diagram shows a first groove 230 formed on one side of the first receiving groove 220, but it can be understood that the first groove 230 can also be formed by simultaneously slotting on both opposite sides; the same process is performed on both sides.
[0104] In some embodiments, please refer to Figures 16 to 20 , Figures 16 to 20 This is a three-dimensional structural diagram of the structure obtained during the preparation process of S60.
[0105] For example, please refer to the following: Figure 16Based on the first trench 230, the first dielectric layer 110 is patterned along the direction close to the first hole 210, exposing the sacrificial layer 192 within the first receiving groove 220, forming Figure 16 A three-dimensional structural diagram of the structure shown. For further details, please refer to... Figure 17 Based on the first trench 230, the sacrificial layer 192 in the first receiving groove 220 is further patterned along the direction close to the first hole 210, exposing the fluorine-containing material layer 130 in the first receiving groove 220, forming Figure 17 A three-dimensional structural diagram of the structure shown.
[0106] In some embodiments, if a sacrificial layer is not formed in the first receiving groove 220 in the preceding steps, then after the first dielectric layer 110 is patterned based on the first trench 230 along the direction close to the first hole 210, the fluorine-containing material layer 130 in the first receiving groove 220 is exposed, and the process is directly formed. Figure 17 A three-dimensional structural diagram of the structure shown.
[0107] For example, Figure 18 It shows Figure 17 The diagram shows a three-dimensional structure with different layers as the top cross-section. Figure 18 It can be seen more clearly in the image that during this step, the first receiving trench 220 located in the first dielectric layer 110 has a conductive layer 160, a gate dielectric layer 150, a fluorine-containing semiconductor layer 170, and a fluorine-containing material layer 130 located at the center of the first receiving trench 220, respectively.
[0108] Please continue to refer to Figure 19 After exposing the fluorinated material layer 130 within the first receiving trench 220, the fluorinated material layer 130 within the first receiving trench 220 is further patterned along the direction close to the first hole 210 based on the first trench 230, thereby exposing the fluorinated semiconductor layer 170 within the first receiving trench 220, forming... Figure 20 The diagram shows a three-dimensional structural schematic. In this embodiment, after the fluorinated material layer 130 in the first receiving groove 220 is exposed, the fluorinated material layer 130 in the first receiving groove 220 is further patterned based on the first trench 230 in the direction close to the first hole 210, thereby removing the fluorinated material layer.
[0109] Please continue to refer to Figure 20 After exposing the fluorinated semiconductor layer 170 within the first accommodating trench 220, the fluorinated semiconductor layer 170 within the first accommodating trench 220 is further patterned along the direction close to the first hole 210 based on the first trench 230, forming a second accommodating trench 240; the second accommodating trench 240 exposes the gate dielectric layer 150, forming... Figure 20The diagram shows a three-dimensional structural schematic. In this embodiment, after exposing the fluorine-containing semiconductor layer 170 in the first accommodating trench 220, the fluorine-containing semiconductor layer 170 in the first accommodating trench 220 is further patterned based on the first trench 230 in the direction close to the first hole 210, thereby removing the parasitic transistor channel.
[0110] Optionally, in some embodiments, the first trench 230 and the second receiving groove 240 are formed as follows: Figure 21 The structure is shown. Optionally, the first trench 230 and the second accommodating trench 240 may be filled with the same material as the first dielectric layer 110; for example, silicon oxide may be used to fill the first trench 230 and the second accommodating trench 240. Please also refer to... Figure 22 , Figure 22 for Figure 21 A magnified view of a portion of the structure shown. From Figure 22 As can be seen, the fluorine-containing semiconductor layer 170 of the transistors in different layers has been broken. Specifically, the fluorine-containing semiconductor layer 170 is broken in the first dielectric layer 110. At this time, the parasitic channel and the fluorine-containing material layer outside the parasitic channel have been removed.
[0111] And further, please refer to Figure 23 , Figure 23 The preparation work before forming the first isolation layer 180 covering the gate dielectric layer 150 in the second accommodating trench 240 is shown: first, a hard mask layer 510 is formed on the stacked structure 100, then an anti-reflection layer 520 is formed above the hard mask layer 510, and then a photoresist layer 530 is formed on the anti-reflection layer 520, wherein the hard mask layer 510 is a carbon layer and the anti-reflection layer 520 is a SION.
[0112] In some embodiments, this disclosure provides another method for fabricating a semiconductor structure, the method further comprising: forming a first isolation layer 180 covering the gate dielectric layer 150 in the second accommodating trench 240.
[0113] For example, after patterning the stacked structure 100, a structure is formed as shown in the figure. Figure 24 The structure shown depicts a first isolation layer 180 forming a cover layer 150 over the gate dielectric layer 150 within the second receiving groove 240. Please refer to... Figure 24 . Figure 24 A three-dimensional structural diagram of the structure obtained to form the first isolation layer 180.
[0114] Please see Figure 25 In some embodiments, this disclosure provides another method for preparing a semiconductor structure, the method further comprising: S2502-S2504.
[0115] S2502: Based on the first trench 230, the second dielectric layer 120 is patterned in the direction close to the first hole 210 until the fluorine-containing material layer 130 is exposed, and the fluorine-containing material layer 130 is patterned to form a third accommodating trench 250; the third accommodating trench 250 exposes the channel region and source / drain contact region of the fluorine-containing semiconductor layer 170.
[0116] Please refer to Figure 26 and Figure 27 , Figure 26 and Figure 27 This is a three-dimensional structural diagram of the structure obtained during the preparation process of S2502. For example, after obtaining... Figure 24 Following the structure shown, the second dielectric layer 120 is patterned along the direction close to the first hole 210 based on the first trench 230 until the fluorine-containing material layer 130 is exposed, thereby obtaining... Figure 26 The structure shown. Figure 26 A three-dimensional structural diagram is shown, illustrating a structure in which a second dielectric layer 120 is patterned along a direction close to the first hole 210 based on a first trench 230, exposing a fluorinated material layer 130. Further, after exposing the fluorinated material layer 130, the fluorinated material layer 130 is patterned to form a third receiving groove 250, thereby obtaining... Figure 27 The structure shown has a third accommodating trench 250 that exposes the channel region and source / drain contact region of the fluorine-containing semiconductor layer 170.
[0117] S2504: A second isolation layer 190 covering the trench area is formed within the third receiving groove 250.
[0118] Please refer to Figure 28 and Figure 29 After forming a second isolation layer 190 covering the trench area within the third receiving groove 250, the following is obtained: Figure 28 The structure shown, in which Figure 29 for Figure 28 A partial enlarged view of the structure shown. Optionally, the same material as the first dielectric layer 110 can be used as the second isolation layer 190 to cover the channel region. For example, silicon oxide can be used to form the second isolation layer 190 covering the channel region in the third receiving tank 250, thereby protecting the channel. For example, the second isolation layer 190 can be formed by ALD deposition.
[0119] In some embodiments, the second isolation layer 190 is partially removed in the third receiving groove 250 to expose the source / drain contact area. Figure 30 A three-dimensional structural diagram of the structure obtained after partially removing the second isolation layer in the third receiving groove to expose the source / drain contact area.
[0120] In some embodiments, the first trench 230 is located on one side of the first accommodating trench 220; the method of fabricating the semiconductor structure further includes: forming a source / drain electrode and / or bit line 300 covering the source / drain contact region in the third accommodating trench 250.
[0121] In some embodiments, the first trench 230 is also located between two adjacent columns of first holes 210, and the two adjacent columns of first holes 210 are symmetrically arranged with the first trench 230 as the center; the method for fabricating the semiconductor structure further includes forming an isolation structure 500 in the first trench 230.
[0122] Please refer to the following at the same time Figure 31 , Figure 32 and Figure 33 , Figure 31 A three-dimensional structural schematic diagram of the semiconductor structure obtained by the semiconductor structure fabrication method of this disclosure is shown. Specifically, after obtaining... Figure 30 Following the structure shown, source / drain electrodes and / or bit lines 300 covering the source / drain contact area are formed in the third receiving trench 250. Subsequently, an isolation structure 500 is formed in the first trench 230, resulting in the structure shown. Figure 31 The structure shown is an insulating material. Optionally, the isolation structure 500 fills the first trench 230, and the isolation structure 500 can be polycrystalline silicon. Figure 32 for Figure 31 A magnified view of a portion of the structure shown. Figure 33 for Figure 31 The diagram shows a three-dimensional structure with different layers as the top cross-section.
[0123] In some embodiments of the semiconductor structure fabrication method, the material of the sacrificial layer 192 includes polycrystalline silicon.
[0124] In other embodiments, the material of the fluorinated material layer 130 includes fluorosilicate glass (FSG).
[0125] In some other embodiments, the material of the semiconductor layer includes a metal oxide semiconductor material.
[0126] In some embodiments, the material of the sacrificial layer 192 includes polycrystalline silicon and / or the material of the fluorinated material layer 130 includes fluorosilicate glass (FSG) and / or the material of the semiconductor material layer includes metal oxide semiconductor material.
[0127] In some embodiments, the metal oxide semiconductor material includes IGZO; the gate dielectric layer 150 includes a high-k material layer.
[0128] This disclosure optimizes the process by doping F into metal-oxide-semiconductor materials, thereby achieving positive shifts in carrier mobility and threshold voltage, improving the performance of oxide-channel 3D memory devices, and providing device stability.
[0129] Furthermore, by depositing an F-doped thin film before IGZO deposition, and then annealing the F-doped thin film layer with the IGZO material at a certain temperature, the F in the F-doped thin film diffuses into the IGZO, reducing oxygen vacancies in the material. This achieves the purpose of improving carrier mobility and positively shifting the threshold voltage, thereby increasing gate control capability and device stability.
[0130] It is understood that the semiconductor structure fabrication method disclosed herein may also include a step of forming a capacitor, which can be performed with reference to relevant technologies and will not be described in detail here.
[0131] In some embodiments, please refer to Figure 31 , Figure 31 The semiconductor structures described herein are some embodiments of the semiconductor structure, which can be prepared using the preparation methods described in the above embodiments. Specific features of each component in the semiconductor structure can also be found in the relevant descriptions of the aforementioned preparation methods.
[0132] Please refer to Figure 31 The semiconductor structure includes: a stacked structure 100, comprising alternating layers of first dielectric layers 110 and second dielectric layers 120; the stacked structure 100 has a first hole 210 penetrating each of the first dielectric layers 110 and the second dielectric layers 120, and a first receiving trench 220 located within the first dielectric layer 110 and surrounding the first hole 210; a fluorinated semiconductor layer 170 located on the inner wall of the first hole 210 between adjacent first receiving trenches 220; the material of the fluorinated semiconductor layer 170 includes a metal oxide semiconductor material in which fluorine ions occupy oxygen vacancies; a gate dielectric layer 150 covering the fluorinated semiconductor layer 170 and the inner wall of the first receiving trench 220; and a conductive layer 160 disposed in the first receiving trench 220 and the first hole 210 and covering the gate dielectric layer 150.
[0133] Oxygen vacancies in oxide channel materials cause a series of problems: the negative correlation between carrier mobility and threshold voltage Vth in oxide channel FETs (Field-Effect Transistors) leads to a negative shift in Vth while increasing the on-state current, resulting in difficulty in turning off the transistor and deterioration of gate control. Therefore, the semiconductor structure in the above embodiments of this disclosure, based on the oxide channel 3D memory architecture, proposes a solution to improve the performance and reliability of the memory by doping with fluorine (F). Specifically, this disclosure provides a semiconductor structure that improves the performance and reliability of oxide channel 3D memory devices by setting a first hole 210 and a first receiving trench 220 surrounding and communicating with the first hole 210 in the semiconductor structure, and setting a fluorine-containing semiconductor layer 170, which is a metal oxide semiconductor material in which fluorine ions occupy oxygen vacancies, on the inner wall of the first hole 210 located between adjacent first receiving trenches 220.
[0134] In some embodiments, the stacked structure 100 further includes a first trench 230 located on at least one side of the first receiving trench 220 and penetrating each of the first dielectric layers 110 and each of the second dielectric layers 120, and a second receiving trench 240 located on the side of the first trench 230 near the first hole 210 and within the first dielectric layer 110; the second receiving trench 240 exposes the gate dielectric layer 150 located at the bottom of the first receiving trench 220; wherein, a plurality of first holes 210 are arranged in a column along a first direction D1, and the first trench 230 extends along the column direction; the semiconductor structure further includes a first isolation layer 180 disposed in the second receiving trench 240 and covering the gate dielectric layer 150.
[0135] In some embodiments, the stacked structure 100 further has a third receiving trench 250 located on the side of the first trench 230 near the first hole 210 and within the second dielectric layer 120; the third receiving trench 250 exposes a fluorine-containing semiconductor layer 170; wherein the semiconductor structure further includes a second isolation layer 190 covering the trench region.
[0136] In some embodiments, the first trench 230 is located on one side of the first accommodating trench 220; the semiconductor structure further includes: source / drain electrodes and / or bit lines 300 disposed in the third accommodating trench 250 and at least partially covering the fluorine-containing semiconductor layer 170.
[0137] In some embodiments, the first trench 230 is located on one side of the first receiving trench 220 and between two adjacent columns of first holes 210; the two adjacent columns of first holes 210 are symmetrically arranged with the first trench 230 as the center; the semiconductor structure further includes an isolation structure disposed in the first trench 230.
[0138] According to some embodiments, this disclosure also provides an electronic device, including the semiconductor structure described in the above embodiments, or a semiconductor structure prepared based on the preparation method of the above semiconductor structure. The electronic device can be a mobile phone, computer, tablet computer, television, artificial intelligence device, etc.
[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure comprising multiple alternating layers of first dielectric layers and multiple layers of second dielectric layers; Pattern the stacked structure to form a first hole; The first dielectric layer is patterned in the first hole to form a first receiving groove; A fluorine-containing material layer, a semiconductor material layer, a gate dielectric layer, and a conductive layer are sequentially stacked in the first receiving groove and the first hole, and the resulting stacked structure is heat-treated to obtain a fluorine-containing semiconductor layer. The stacked structure is patterned to form a first groove located on at least one side of the first receiving groove; wherein a plurality of the first holes are arranged in a row along a first direction, and the first groove extends along the first direction and penetrates the stacked structure; Based on the first trench, the first dielectric layer is patterned in the direction close to the first hole, and the fluorine-containing material layer and the fluorine-containing semiconductor layer in the first receiving trench are patterned to form a second receiving trench; the second receiving trench exposes the gate dielectric layer.
2. The method for preparing the semiconductor structure according to claim 1, characterized in that, Also includes: A first isolation layer covering the gate dielectric layer is formed within the second receiving groove.
3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, Also includes: Based on the first trench, the second dielectric layer is patterned along the direction close to the first hole until the fluorine-containing material layer is exposed, and the fluorine-containing material layer is patterned to form a third receiving groove; The third accommodating groove exposes the fluorine-containing semiconductor layer; A second isolation layer is formed within the third accommodating groove, at least partially covering the fluorine-containing semiconductor layer.
4. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The first groove is located on one side of the first receiving groove; the preparation method further includes: Source / drain electrodes and / or bit lines that at least partially cover the fluorine-containing semiconductor layer are formed in the third accommodating groove.
5. The method for preparing a semiconductor structure as described in claim 4, characterized in that, The first groove is also located between two adjacent columns of the first holes, and the two adjacent columns of the first holes are symmetrically arranged with the first groove as the center. The preparation method further includes: forming an isolation structure in the first trench.
6. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The heat treatment of the obtained structure includes: performing an annealing process on the obtained structure; The annealing temperature range of the annealing process includes 350℃~400℃.
7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The fluorine ion doping concentration in the fluorine-containing material layer is greater than 4 × 10⁻⁶. 12 / cm 2 .
8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that, Before sequentially stacking the fluorine-containing material layer, the semiconductor material layer, the gate dielectric layer, and the conductive layer in the first receiving groove and the first hole, the preparation method further includes: A sacrificial layer is formed on the inner wall of the first receiving groove; The fluorine-containing material layer covers the sacrificial layer.
9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, Includes at least one of the following features: The material of the sacrificial layer includes polycrystalline silicon; The material of the fluorine-containing layer includes fluorosilicate glass; The semiconductor material layer is made of metal oxide semiconductor material.
10. A semiconductor structure, characterized in that, include: A stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately; the stacked structure has a first hole penetrating each of the first dielectric layers and the second dielectric layers, and a first receiving groove located in the first dielectric layer and surrounding the first hole; A fluorine-containing semiconductor layer is located on the inner wall of the first hole between adjacent first receiving trenches; the material of the fluorine-containing semiconductor layer includes a fluorine-containing metal oxide semiconductor material; A gate dielectric layer covers the fluorine-containing semiconductor layer and the inner wall of the first accommodating trench; A conductive layer covers the gate dielectric layer and is located on the side of the gate dielectric layer away from the fluorine-containing semiconductor layer.
11. The semiconductor structure as claimed in claim 10, characterized in that, The stacked structure further has a first trench located on at least one side of the first receiving groove and penetrating each of the first dielectric layers and each of the second dielectric layers, and a second receiving groove located on the side of the first trench near the first hole and within the first dielectric layer. The second receiving groove exposes at least a portion of the gate dielectric layer located in the first receiving groove; Among them, a plurality of the first holes are arranged in a row along the first direction, and the first groove extends along the first direction; The semiconductor structure further includes: a first isolation layer that at least partially covers the gate dielectric layer in the second accommodating trench.
12. The semiconductor structure as claimed in claim 11, characterized in that, The stacked structure also has a third receiving groove located on the side of the first trench near the first hole and within the second dielectric layer; The third accommodating groove exposes the fluorine-containing semiconductor layer; The semiconductor structure further includes a second isolation layer that at least partially covers the fluorine-containing semiconductor layer.
13. The semiconductor structure as described in claim 12, characterized in that, The first trench is located on one side of the first accommodating trench; the semiconductor structure further includes: source / drain electrodes and / or bit lines that at least partially cover the fluorine-containing semiconductor layer within the third accommodating trench.
14. The semiconductor structure as claimed in claim 12, characterized in that, The first groove is located on one side of the first receiving groove and between two adjacent columns of the first holes; the two adjacent columns of the first holes are symmetrically arranged with the first groove as the center. The semiconductor structure further includes an isolation structure disposed in the first trench.
15. An electronic device, characterized in that, Includes the semiconductor structure as described in any one of claims 10-14, or the semiconductor structure prepared based on the preparation method of the semiconductor structure as described in any one of claims 1-9.