Method of manufacturing a semiconductor device

Abstract

This disclosure relates to a method for manufacturing a semiconductor device. The method includes: forming a pad film to cover a first gate electrode and a second gate electrode; forming an insulating film on the pad film; exposing the pad film on each of the first and second gate electrodes by performing anisotropic dry etching on the insulating film, and forming a buried layer between the first and second gate electrodes; forming an interlayer insulating film on the buried layer; and forming contact holes in the interlayer insulating film, the buried layer, and the pad film, and forming plug electrodes in the contact holes.

Description

Cross-reference to related applications

[0001] The entire disclosure of Japanese Patent Application No. 2024-220866, filed on December 17, 2024, including the specification, drawings and abstract, is incorporated herein by reference. Technical Field

[0002] This invention relates to a method for manufacturing a semiconductor device, and to a technique that can be effectively applied to, for example, the manufacturing of semiconductor devices including flash memory. Background Technology

[0003] Electrically erasable programmable read-only memory (EEPROM) has been widely used as electrically writable and erasable non-volatile memory. Examples exist of using split-gate MONOS (metal oxide nitride oxide semiconductor) memory as EEPROM embedded in microcomputers.

[0004] The following technologies have been disclosed.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-56222

[0006] Patent document 1 describes a technology related to split-gate MONOS (metal oxide nitride oxide semiconductor) memory. Summary of the Invention

[0007] The inventors of this application have identified the following problems in semiconductor devices comprising multiple split-gate MONOS memories arranged in a matrix pattern.

[0008] A split-gate MONOS memory includes: a drain region and a source region formed in a semiconductor substrate; a control gate electrode formed on the semiconductor substrate via a gate insulating film; and a memory gate electrode formed on the semiconductor substrate via a charge-retaining film. An interlayer insulating film filling the gap between adjacent control gate electrodes is formed on the semiconductor substrate, and plug electrodes are formed in the interlayer insulating film. The plug electrodes electrically connect the drain region and a bit line. A plurality of plug electrodes are arranged at predetermined intervals between adjacent control gate electrodes along the extending direction of the control gate electrodes.

[0009] With the miniaturization of semiconductor devices, the distance between adjacent control gate electrodes is reduced. It has been confirmed that gaps are formed in the interlayer insulating film between adjacent control gate electrodes. Due to the formation of gaps between adjacent plug electrodes, adjacent bit lines are short-circuited. This is because a metal layer is also formed in the gaps due to the plug electrode formation step. Note that this problem is also discussed in Patent Document 1.

[0010] In this type of split-gate MONOS memory, there is an urgent need for a technology to prevent short circuits between adjacent bit lines. In other words, there is an urgent need for a technology that can improve the reliability of semiconductor devices.

[0011] Other issues and novel features will become apparent from the description and accompanying drawings in this specification.

[0012] A method of manufacturing a semiconductor device according to one embodiment includes the steps of: forming a first insulating film to cover a first gate electrode and a second gate electrode; and forming a second insulating film on the first insulating film. The method of manufacturing a semiconductor device further includes the steps of exposing the first insulating film located on each of the first and second gate electrodes by performing anisotropic dry etching on the second insulating film, and forming a buried layer between the first and second gate electrodes. The method of manufacturing a semiconductor device further includes the steps of: forming a third insulating film on the buried layer; and forming a contact hole in each of the third insulating film, the buried layer, and the first insulating film, and forming a conductive layer in the contact hole.

[0013] According to the embodiments, the reliability of semiconductor devices can be improved. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view showing the main parts of a semiconductor device according to an embodiment.

[0015] Figure 2 This is a plan view showing the main parts of a semiconductor device according to an embodiment.

[0016] Figure 3 This is a cross-sectional view illustrating the steps of manufacturing a semiconductor device according to an embodiment.

[0017] Figure 4 It shows from Figure 3 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0018] Figure 5 It shows from Figure 4 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0019] Figure 6 It shows from Figure 5 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0020] Figure 7 It shows from Figure 6 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0021] Figure 8 It shows from Figure 7A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0022] Figure 9 It shows from Figure 8 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0023] Figure 10 It shows from Figure 9 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0024] Figure 11 It shows from Figure 10 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0025] Figure 12 It shows from Figure 11 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0026] Figure 13 It shows from Figure 12 A cross-sectional view of the subsequent steps in manufacturing semiconductor devices.

[0027] Figure 14 This is a cross-sectional view showing the steps of manufacturing a semiconductor device according to the first modified example.

[0028] Figure 15 This is a cross-sectional view showing the steps of manufacturing a semiconductor device according to the second modified example. Detailed Implementation

[0029] In all the accompanying drawings, the same components used to describe the embodiments are indicated by the same reference numerals, and repeated descriptions thereof are omitted.

[0030] In the following embodiments, the term "N-type" refers to "N" conductivity type, and the term "P-type" refers to "P" conductivity type. The term "P-type impurity region" may be modified to the term "P-type semiconductor region," and the term "N-type impurity region" may be modified to the term "N-type semiconductor region."

[0031] The "X" and "Y" directions are along the main surface of the semiconductor substrate and are orthogonal to each other.

[0032] Example

[0033] The semiconductor device according to this embodiment includes a plurality of memory cells. Each of the memory cells is composed of a split-gate MONOS memory, and the memory cell array is composed of a plurality of memory cells. The plurality of memory cells constituting the memory cell array are arranged in a matrix pattern along the X and Y directions on the main surface of the semiconductor substrate SB. Figure 2 It is a plan view of a memory cell array. Figure 1These are cross-sectional views of a semiconductor device along bit line BL in region AR and a semiconductor device along source line SL in region BR.

[0034] like Figure 2 As shown, each of a plurality of control gate electrodes CG and a plurality of memory gate electrodes MG extends along the Y direction on the main surface of the semiconductor substrate SB. Each of a plurality of bit lines BL and a plurality of source lines SL extends along the X direction. The drain region DR in the memory cell is electrically connected to the bit line BL via a plug electrode PG. The source region SR in the memory cell is electrically connected to the source line SL via a plug electrode PG. In the plan view, the drain region DR is arranged along the X direction between two adjacent control gate electrodes CG and along the Y direction between two adjacent shallow trench isolation members ST. In the plan view, the source region SR is arranged along the X direction between two adjacent memory gate electrodes MG and extends along the Y direction.

[0035] At region AR, two adjacent memory cells in the X direction share the drain region DR and are symmetrical across the drain region DR. At region BR, two adjacent memory cells in the X direction share the source region SR and are symmetrical across the source region SR. To extend the source region SR in the Y direction, the source region SR is arranged between two adjacent shallow trench isolation elements ST along the X direction. Therefore, in the X direction, the distance D2 between two adjacent memory gate electrodes MG is greater than the distance D1 between two adjacent control gate electrodes CG (D2>D1).

[0036] like Figure 1As shown, the memory cell includes a drain region DR, a source region SR, a gate insulating film GI, a control gate electrode CG, an insulating film MZ, a memory gate electrode MG, and a cover insulating film CP. The drain region DR and the source region SR are arranged relative to each other in the semiconductor substrate SB at a predetermined spacing. A channel formation region is located between the drain region DR and the source region SR. The control gate electrode CG and the memory gate electrode MG are formed on the channel formation region. The control gate electrode CG is formed on the main surface of the semiconductor substrate SB via the gate insulating film GI. The memory gate electrode MG is formed on the main surface of the semiconductor substrate SB via the insulating film MZ. The insulating film MZ is L-shaped in cross-section and is arranged between the control gate electrode CG and the memory gate electrode MG, and between the memory gate electrode MG and the main surface of the semiconductor substrate SB. The insulating film MZ is formed between the semiconductor substrate SB and the memory gate electrode MG, but a different insulating film than the insulating film MZ may be formed between the control gate electrode CG and the memory gate electrode MG. A control gate electrode CG is disposed between the drain region DR and the memory gate electrode MG, and the memory gate electrode MG is disposed between the control gate electrode CG and the source region SR. A capping insulating film CP is formed on the control gate electrode CG. The stacked structure including the control gate electrode CG and the capping insulating film CP is referred to as the "gate electrode". Each of the drain region DR and the source region SR includes an N-type impurity region NM and an N-type impurity region NH. A silicide layer SC is formed on the drain region DR. Furthermore, the silicide layer SC is formed on the source region SR. Additionally, the silicide layer SC is formed on the memory gate electrode MG.

[0037] The main surface of the semiconductor substrate SB and the memory cells are covered by a pad film LN, an interlayer insulating film IL1, and an interlayer insulating film IL2. The pad film LN is formed on the gate electrode and the memory gate electrode MG to cover the memory cells. The interlayer insulating film IL1 is formed on the pad film LN. The interlayer insulating film IL2 is formed on the interlayer insulating film IL1.

[0038] At region AR, bit line BL is electrically connected to drain region DR via plug electrode PG. In the region between two adjacent gate electrodes, pad film LN, buried layer BZ, interlayer insulating film IL1, and interlayer insulating film IL2 are formed on drain region DR. Buried layer BZ, located on drain region DR, covers pad film LN and is formed between pad film LN and interlayer insulating film IL1. Plug electrode PG is formed in contact hole CH that penetrates interlayer insulating film IL2, interlayer insulating film IL1, buried layer BZ, and pad film LN. Bit line BL is formed on interlayer insulating film IL2. Note that pad film LN on the gate electrode is in contact with interlayer insulating film IL1. That is, buried layer BZ is not present on pad film LN on the gate electrode.

[0039] At region BR, the source line SL is electrically connected to the source region SR via a plug electrode PG. In the region between two adjacent memory gate electrodes MG, a pad film LN, an interlayer insulating film IL1, and an interlayer insulating film IL2 are formed on the source region SR. The plug electrode PG is formed in a contact hole CH penetrating the interlayer insulating films IL2, IL1, and LN. As described above, two memory cells share the source region SR and are symmetrical across it. The two memory cells are arranged on either side of the plug electrode PG connected to the source region SR. Two insulating films IF3A are formed on the source region SR, and the plug electrode PG is arranged between the two insulating films IF3A. One insulating film IF3A is selectively formed on the pad film LN formed on the sidewall of the memory gate electrode MG of one memory cell. The other insulating film IF3A is selectively formed on the pad film LN formed on the sidewall of the memory gate electrode MG of the other memory cell. The two insulating films IF3A on the source region SR are spaced apart from each other. As described later, the insulating film IF3A is formed by forming the buried layer BZ. The distance D2 between two adjacent memory gate electrodes MG in region BR is longer than the distance D1 between two adjacent gate electrodes in region AR. Therefore, the two insulating films IF3A on the source region SR are formed far apart from each other.

[0040] Next, we will refer to Figure 1 and Figures 3 to 13 A method for manufacturing a semiconductor device according to this embodiment is described.

[0041] First, such as Figure 3 As shown, an insulating film IF1, a silicon film SF, and an insulating film IF2 are formed on the main surface of a semiconductor substrate SB. The semiconductor substrate SB is made of, for example, p-type single-crystal silicon. The insulating film IF1 is made of, for example, a silicon oxide film. The insulating film IF1 may include a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The silicon film SF is made of, for example, a polycrystalline silicon film, and a polycrystalline silicon film is deposited on the insulating film IF1 using a CVD method. The insulating film IF2 is made of, for example, a silicon nitride film, and a silicon nitride film is deposited on the silicon film SF using a CVD method.

[0042] Next, as Figure 3 As shown, a mask layer MK1 with a desired pattern is formed on the insulating film IF2. The mask layer MK1 is composed of, for example, a photoresist film. The mask layer MK1 has a pattern corresponding to the gate electrode.

[0043] Next, as Figure 4As shown, the insulating film IF2, silicon film SF, and insulating film IF1 exposed from the mask layer MK1 are removed by using a dry etching method. A gate electrode consisting of a control gate electrode CG and a capping insulating film CP formed on the control gate electrode CG is formed on the gate insulating film G1.

[0044] At region AR, a first gate electrode and a second gate electrode are formed on the main surface of the semiconductor substrate SB in a left-to-right order. The first gate electrode has a first sidewall and a second sidewall opposite to the first sidewall, and each of the first and second sidewalls extends in the Y direction. The second gate electrode has a third sidewall and a fourth sidewall opposite to the third sidewall, and each of the third and fourth sidewalls extends in the Y direction. The second sidewall of the first gate electrode faces the third sidewall of the second gate electrode.

[0045] At region BR, a third gate electrode and a fourth gate electrode are formed on the main surface of the semiconductor substrate SB in a left-to-right order. The third gate electrode has a fifth sidewall and a sixth sidewall opposite to the fifth sidewall, and each of the fifth and sixth sidewalls extends in the Y direction. The fourth gate electrode has a seventh sidewall and an eighth sidewall opposite to the seventh sidewall, and each of the seventh and eighth sidewalls extends in the Y direction. The sixth sidewall of the third gate electrode faces the seventh sidewall of the fourth gate electrode.

[0046] Next, as Figure 5 As shown, an insulating film (also known as a charge-retaining film) MZ and a memory gate electrode MG are formed on the main surface of a semiconductor substrate SB. The insulating film MZ includes, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate electrode MG is made of, for example, a polycrystalline silicon film.

[0047] At region AR, a first memory gate electrode MG is formed on each of the first sidewall of the first gate electrode and the main surface of the semiconductor substrate SB via the insulating film MZ. A second memory gate electrode MG is formed on each of the fourth sidewall of the second gate electrode and the main surface of the semiconductor substrate SB via the insulating film MZ.

[0048] At region BR, a third memory gate electrode MG is formed on each of the sixth sidewall of the third gate electrode and the main surface of the semiconductor substrate SB via the insulating film MZ. A fourth memory gate electrode MG is formed on each of the seventh sidewall of the fourth gate electrode and the main surface of the semiconductor substrate SB via the insulating film MZ.

[0049] Next, as Figure 6As shown, a drain region DR and a source region SR are formed in a semiconductor substrate SB. In region AR, in the plan view, an N-type impurity region NM is formed in the semiconductor substrate SB in the region between the first gate electrode and the second gate electrode. In region BR, in the plan view, an N-type impurity region NM is formed in the semiconductor substrate SB in the region between the third memory gate electrode MG and the fourth memory gate electrode MG. The N-type impurity region NM is formed using methods such as ion implantation. That is, N-type impurities such as arsenic (As) or phosphorus (P) are introduced into the semiconductor substrate SB.

[0050] Next, in region AR, a sidewall insulating film SW is formed on each of the second sidewall of the first gate electrode and the third sidewall of the second gate electrode. In region BR, a sidewall insulating film SW is formed on each of the sidewalls of the third memory gate electrode MG and the fourth memory gate electrode MG.

[0051] Next, in region AR, in the plan view, an N-type impurity region NH is formed in the semiconductor substrate SB in the region between the sidewall insulating film SW on the second sidewall of the first gate electrode and the sidewall insulating film SW on the third sidewall of the second gate electrode. In region BR, in the plan view, an N-type impurity region NH is formed in the semiconductor substrate SB in the region between the sidewall insulating film SW on the sidewall of the third memory gate electrode MG and the sidewall insulating film SW on the sidewall of the fourth memory gate electrode MG. The N-type impurity region NH is formed by using methods such as ion implantation. That is, N-type impurities such as arsenic (As) or phosphorus (P) are introduced into the semiconductor substrate SB. The impurity concentration of the N-type impurity region NH is higher than the impurity concentration of the N-type impurity region NM.

[0052] In the above steps, at region AR, in the plan view, in the region between the first gate electrode and the second gate electrode, a drain region DR comprising an N-type impurity region NM and an N-type impurity region NH is formed in the semiconductor substrate SB. At region BR, in the plan view, in the region between the third memory gate electrode MG and the fourth memory gate electrode MG, a source region SR comprising an N-type impurity region NM and an N-type impurity region NH is formed in the semiconductor substrate SB.

[0053] Next, as Figure 7 As shown, a silicide layer SC is formed. In region AR, the silicide layer SC is formed on each of the drain region DR, the first memory gate electrode MG, and the second memory gate electrode MG. In region BR, the silicide layer SC is formed on each of the source region SR, the third memory gate electrode MG, and the fourth memory gate electrode MG. The silicide layer SC is composed of an alloy film of, for example, nickel (Ni) and platinum (Pt).

[0054] Next, as Figure 8 As shown, a pad film LN is formed on the main surface of the semiconductor substrate SB to cover the memory cell. The pad film LN covers the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode. Furthermore, the pad film LN covers the first memory gate electrode, the second memory gate electrode, the third memory gate electrode, and the fourth memory gate electrode. The pad film LN is composed of an insulating film such as silicon nitride and is deposited on the main surface of the semiconductor substrate SB using a CVD method.

[0055] Next, as Figure 9 As shown, an insulating film IF3 is formed on the liner film LN. The insulating film IF3 is composed of a silicon oxide film and is deposited on the liner film LN using a CVD method. Preferably, an O3-tetraethyl orthosilicate (TEOS) film with excellent step coverage is used as the insulating film IF3.

[0056] First, the region AR is described. The gap between the first and second gate electrodes, which are adjacent to each other, is filled with an insulating film IF3. That is, in the region between the first and second gate electrodes, relative to the main surface of the semiconductor substrate SB, the upper surface of the insulating film IF3 is equal to or higher than the upper surface of the cover insulating film CP. In the region between the first and second gate electrodes, the lowest portion of the upper surface of the insulating film IF3 is equal to or higher than the upper surface of the cover insulating film CP. The thickness T2 of the insulating film IF3 filling the region between the first and second gate electrodes is expressed by the following expression.

[0057] [Numerical Expression 1] T2 ≥ D1 / 2 – T1

[0058] In numerical expression 1, the term "D1" represents the distance between the first gate electrode and the second gate electrode, and the term "T1" represents the thickness of the pad film LN located on the first gate electrode. The term "T2" represents the thickness of the insulating film IF3 located on the first gate electrode. Note that in order to fill the area between the first gate electrode and the second gate electrode with the insulating film IF3, the thickness T1 of the pad film LN is made smaller than the thickness T2 of the insulating film IF3 (T1... <T2)。

[0059] As described above, the region between the first gate electrode and the second gate electrode is filled with an insulating film IF3, and therefore, the insulating film IF3 in the region between the first gate electrode and the second gate electrode has a thickness T3. The thickness T3 of the insulating film IF3 in the region between the first gate electrode and the second gate electrode is greater than the thickness T2 of the insulating film IF3 located on the first gate electrode or the second gate electrode (T3>T2). In this case, the thicknesses T1, T2, and T3 are the thicknesses in the vertical direction relative to the main surface of the semiconductor substrate SB.

[0060] Conversely, in region BR, the area between the adjacent third and fourth memory gate electrodes is not filled with insulating film IF3. In the region between the third and fourth memory gate electrodes, the upper surface of insulating film IF3 has a portion lower than the upper surface of the cover insulating film CP relative to the main surface of the semiconductor substrate SB. That is, the thickness of this portion of insulating film IF3 located on the source region SR is almost equal to the thickness T2 of insulating film IF3 on the third or fourth gate electrode.

[0061] Next, as Figure 10 As shown, anisotropic dry etching is performed on the insulating film IF3 to form the buried layer BZ and the insulating film IF3A.

[0062] The region AR will be described. In the step of performing anisotropic dry etching on the insulating film IF3, the insulating film IF3 located on the first gate electrode and the second gate electrode is etched to expose the pad film LN. Conversely, a buried layer BZ covering the pad film LN is formed in the region between the first gate electrode and the second gate electrode. This is because... Figure 9 As shown, the thickness T3 of the insulating film IF3 in the region between the first gate electrode and the second gate electrode is greater than the thickness T2 of the insulating film IF3 on either the first or second gate electrode. The buried layer BZ has a first portion, a second portion, and a third portion in the cross-sectional view. (As shown...) Figure 10 As shown, a first portion is formed on the pad film LN along the main surface of the semiconductor substrate SB. A second portion is formed along the pad film LN on the sidewall of the first gate electrode. A third portion is formed along the pad film LN on the sidewall of the second gate electrode. The second portion is connected to one end of the first portion, and the third portion is connected to the other end of the first portion. Each of the second and third portions extends in a vertical direction relative to the main surface of the semiconductor substrate SB. That is, a buried layer BZ located on the drain region DR and appearing concave in the cross-sectional view is formed on the pad film LN by an anisotropic dry etching step.

[0063] On the contrary, such as Figure 9As shown, in region BR, the area between the adjacent third memory gate electrode MG and fourth memory gate electrode MG is not filled with insulating film IF3, and therefore, no buried layer BZ is formed. Figure 10 As shown, an insulating film IF3A is formed on the pad film LN covering the sidewall of the third memory gate electrode MG. An insulating film IF3A is also formed on the pad film LN covering the sidewall of the fourth memory gate electrode MG. The two insulating films IF3A formed between the third and fourth memory gate electrodes MG are spaced far apart from each other. That is, a portion of the pad film LN located on the source region SR is exposed from the insulating film IF3A.

[0064] Next, as Figure 11 As shown, an interlayer insulating film IL1 is formed on a semiconductor substrate SB, thereby covering the memory cell, the pad film LN, the buried layer BZ, and the insulating film IF3A. The interlayer insulating film IL1 is composed of a silicon oxide film and is deposited on each of the pad film LN and the buried layer BZ using a CVD method. Preferably, an O3-TEOS film with excellent step coverage is used as the interlayer insulating film IL1.

[0065] At region AR, a buried layer BZ is formed in the region between the first gate electrode and the second gate electrode. Therefore, the region between the first gate electrode and the second gate electrode can be filled with an interlayer insulating film IL1 without forming voids in the interlayer insulating film IL1 located on the drain region DR.

[0066] At region BR, the distance between the third memory gate electrode MG and the fourth memory gate electrode MG is greater than the distance between the first gate electrode and the second gate electrode, and therefore, no voids are formed in the interlayer insulating film IL1 located on the source region SR.

[0067] Next, as Figure 12 As shown, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1. The interlayer insulating film IL2 is composed of a silicon oxide film and is deposited on the interlayer insulating film IL1 using a CVD method. A TEOS film having superior mechanical properties to the interlayer insulating film IL1 is preferably used as the interlayer insulating film IL2. Then, chemical mechanical polishing (CMP) is performed on the interlayer insulating film IL2 to flatten its upper surface.

[0068] Next, as Figure 13As shown, a plug electrode PG is formed. In region AR, the interlayer insulating film IL2, interlayer insulating film IL1, buried layer BZ, and pad film LN are etched. Then, a contact hole CH is formed penetrating the interlayer insulating film IL2, interlayer insulating film IL1, buried layer BZ, and pad film LN. The contact hole CH is formed on the drain region DR, and the plug electrode PG is formed in the contact hole CH. The plug electrode PG contacts the silicide layer SC formed on the upper surface of the drain region DR. In region BR, the interlayer insulating film IL2, interlayer insulating film IL1, and pad film LN are etched. Then, a contact hole CH is formed penetrating the interlayer insulating film IL2, interlayer insulating film IL1, and pad film LN. The contact hole CH is formed on the source region SR, and the plug electrode PG is formed in the contact hole CH. The plug electrode PG contacts the silicide layer SC formed on the upper surface of the source region SR. The plug electrode PG includes a barrier conductor film and a main body film. The barrier conductor film is composed of, for example, a titanium film, a titanium nitride film, or a stacked film of a titanium film and a titanium nitride film on the titanium film. The dominant conductor film is formed on the barrier conductor film and is composed of, for example, tungsten (W).

[0069] Next, as Figure 1 As shown, a wiring layer including bit line BL and source line SL is formed on the interlayer insulating film IL2. The wiring layer is made of, for example, a copper (Cu) film or an aluminum (Al) film. Bit line BL is electrically connected to drain region DR via plug electrode PG. Source line SL is electrically connected to source region SR via plug electrode PG.

[0070] Note that, as Figure 2 As shown, the second gate electrode at region AR and the third gate electrode at region BR are the same gate electrode. The second gate electrode and the third gate electrode can also be different gate electrodes. For example... Figure 2 As shown, the second memory gate electrode MG at region AR and the third memory gate electrode MG at region BR are the same memory gate electrode MG. Alternatively, the second memory gate electrode MG and the third memory gate electrode MG can be different memory gate electrodes MG.

[0071] The method for manufacturing a semiconductor device according to this embodiment has the following features.

[0072] A buried layer BZ is formed on the pad film LN in the region between the first gate electrode and the second gate electrode, and then the region between the first gate electrode and the second gate electrode is filled with an interlayer insulating film IL1. Since the buried layer BZ is formed before the interlayer insulating film IL1 is formed, the drain region DR and the region between the first gate electrode and the second gate electrode can be filled with the interlayer insulating film IL1 without any gaps. Therefore, short circuits between the multiple plug electrodes PG formed in the interlayer insulating film IL1 can be prevented.

[0073] <First Modification Example>

[0074] The first modification example is related to the above embodiment. Figure 10 Related modification examples. For example... Figure 14 As shown, after forming the insulating film IF3 and then the mask layer MK2, anisotropic dry etching is performed on the insulating film IF3. At region AR, the mask layer MK2 has an opening that exposes the buried layer BZ located on the drain region DR, the pad film LN located on a portion of the first gate electrode, and the pad film LN located on a portion of the second gate electrode. In the plan view, the drain region DR is arranged in the opening between a portion of the first gate electrode and a portion of the second gate electrode. Through the anisotropic dry etching step, in the plan view, the insulating film IF3 on each of the portion of the first gate electrode and the portion of the second gate electrode located in the opening is removed to expose the pad film LN. Furthermore, through the anisotropic dry etching step, a buried layer BZ similar to the buried layer BZ in the above embodiment is formed in the region between the first gate electrode and the second gate electrode.

[0075] Conversely, at region BR, the insulating film IF3 on the source region SR is covered by the mask layer MK2, and therefore, the pad film LN on the source region SR is not exposed. That is, the pad film LN on the source region SR has sufficient thickness to act as an etch stop. In the above embodiment, the thickness of the pad film LN can be reduced by exposing the pad film LN on the source region SR. Reducing the thickness of the pad film LN will not cause it to act as an etch stop during the etching step of forming the contact hole CH.

[0076] In the first modified example, the thickness of the pad film LN on the source region SR can be prevented from decreasing. Therefore, when forming the contact hole CH on the source region SR, the problem of the contact hole CH penetrating the source region SR can be prevented. In other words, a short circuit between the source region SR and the semiconductor substrate SB can be prevented.

[0077] <Second Modification Example>

[0078] The second modified example is a modified example related to the first modified example. The difference from the first modified example lies in the thickness of the pad film LN on each of the first and second gate electrodes. The pad film LN on the first gate electrode will be described here, but the pad film LN on the second gate electrode is treated similarly. In the anisotropic dry etching step for the insulating film IF3 in the first modified example, the anisotropic dry etching is completed when the pad film LN on the first gate electrode is exposed. Figure 15As shown, in the second modified example, anisotropic dry etching continues even after the insulating film IF3 has been completely etched to expose the pad film LN on the first gate electrode. During the anisotropic dry etching step, the thickness of the pad film LN located in the opening portion of the mask layer MK2 is reduced. That is, the thickness of the pad film LNA exposed from the mask layer MK2 is made smaller than the thickness of the pad film LN covered by the mask layer MK2. Through the anisotropic dry etching step, the pad film LNA is formed on the first gate electrode located in the opening portion of the mask layer MK2. The thickness of the pad film LNA located on the first gate electrode and exposed from the opening portion is smaller than the thickness of the pad film LN located on the first gate electrode and covered by the insulating film IF3. Therefore, in the step of filling the region between the first and second gate electrodes with the interlayer insulating film IL1, the formation of voids can be prevented.

[0079] In the foregoing, the invention made by the inventors of this invention has been specifically described based on the embodiments. However, it goes without saying that this invention is not limited to the above embodiments, and various modifications can be made within the scope of this invention.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: (a) A first gate electrode and a second gate electrode are formed on the main surface of a semiconductor substrate; (b) An impurity region is formed in the semiconductor substrate in the region between the first gate electrode and the second gate electrode; (c) Deposit a first insulating film on the main surface to cover the first gate electrode and the second gate electrode; (d) Deposit a second insulating film on the first insulating film; (e) The second insulating film is removed by anisotropic dry etching of the second insulating film to expose the first insulating film, and a buried layer is formed in the region between the first gate electrode and the second gate electrode, the buried layer covering the first insulating film and being constituted by the second insulating film; (f) Deposit a third insulating film on the main surface to cover the first gate electrode, the second gate electrode, and the buried layer; (g) In the region between the first gate electrode and the second gate electrode, a contact hole penetrating the third insulating film, the buried layer and the first insulating film is formed in the third insulating film, the buried layer and the first insulating film; as well as (h) A plug electrode electrically connected to the impurity region is formed by forming a conductive layer in the contact hole.

2. The method for manufacturing the semiconductor device according to claim 1, wherein step (a) comprises the following steps: (a1) Deposit a silicon film on the main surface; (a2) Deposit a fourth insulating film on the silicon film; as well as (a3) The first gate electrode and the second gate electrode are formed by processing the fourth insulating film and the silicon film. The first gate electrode includes a first control gate electrode formed by the silicon film and a first cover insulating film formed by the fourth insulating film. The second gate electrode includes a second control gate electrode formed by the silicon film and a second cover insulating film formed by the fourth insulating film.

3. The method for manufacturing the semiconductor device according to claim 2, further comprising the following step after step (h): (i) A wiring layer electrically connected to the plug electrode is formed on the third insulating film.

4. The method of manufacturing the semiconductor device according to claim 2, wherein in step (d), the first thickness of the second insulating film formed in the region between the first gate electrode and the second gate electrode is greater than the second thickness of the second insulating film formed on the first gate electrode.

5. The method of manufacturing the semiconductor device according to claim 2, wherein the fourth insulating film is composed of a first silicon nitride film.

6. The method for manufacturing the semiconductor device according to claim 2, The first insulating film is composed of a second silicon nitride film. The second insulating film is composed of a first silicon oxide film, and The third insulating film is composed of a second silicon oxide film.

7. The method of manufacturing the semiconductor device according to claim 6, wherein the second insulating film is composed of a first O3-TEOS film, and The third insulating film is composed of a second O3-TEOS film.

8. A method for manufacturing a semiconductor device, comprising the following steps: (a) A first gate electrode and a second gate electrode are formed on the main surface of a semiconductor substrate; the first gate electrode has a first sidewall and a second sidewall, and the second gate electrode has a third sidewall and a fourth sidewall; (b) A first memory gate electrode is formed on each of the first sidewall and the main surface of the first gate electrode via a first charge-retaining film, and a second memory gate electrode is formed on each of the fourth sidewall and the main surface of the second gate electrode via a second charge-retaining film; (c) A first impurity region is formed in the semiconductor substrate at a first region between the first gate electrode and the second gate electrode; (d) Deposit a first insulating film on the main surface to cover the first gate electrode, the first memory gate electrode, the second gate electrode, and the second memory gate electrode; (e) Deposit a second insulating film on the first insulating film; (f) Forming a mask layer that covers the first memory gate electrode and the second memory gate electrode, and the mask layer having an opening that exposes a first portion of the first gate electrode, the first region, and a second portion of the second gate electrode; (g) By performing anisotropic dry etching on the second insulating film, the first insulating film covering the first portion of the first gate electrode and the second portion of the second gate electrode is exposed in the opening portion of the mask layer, and a buried layer is formed in the first region, the buried layer covering the first insulating film and being constituted by the second insulating film. (h) A third insulating film is deposited on the main surface to cover the first gate electrode, the second gate electrode, and the buried layer; (i) A first contact hole is formed in the third insulating film, the buried layer, and the first insulating film at the first region; as well as (j) A first plug electrode electrically connected to the first impurity region is formed by forming a first conductive layer in the first contact hole. Each of the first gate electrode and the second gate electrode extends along the main surface of the semiconductor substrate in a first direction, and the first gate electrode and the second gate electrode are arranged in a second direction orthogonal to the first direction. Each of the first sidewall and the second sidewall of the first gate electrode extends in the first direction. The second sidewall of the first gate electrode faces the third sidewall of the second gate electrode, and Each of the third and fourth sidewalls of the second gate electrode extends in the first direction.

9. The method of manufacturing the semiconductor device according to claim 8, wherein in step (a), a third gate electrode having a fifth sidewall and a sixth sidewall and a fourth gate electrode having a seventh sidewall and an eighth sidewall are formed on the main surface. In step (b), a third memory gate electrode is formed on each of the sixth sidewall and the main surface of the third gate electrode via a third charge-retaining film, and a fourth memory gate electrode is formed on each of the seventh sidewall and the main surface of the fourth gate electrode via a fourth charge-retaining film. In step (c), a second impurity region is formed in the semiconductor substrate in the second region between the third memory gate electrode and the fourth memory gate electrode. In step (d), the first insulating film is deposited on the main surface to cover the third gate electrode, the third memory gate electrode, the fourth gate electrode, the fourth memory gate electrode, and the second region. In step (f), the mask layer covers the third memory gate electrode, the second region, and the fourth memory gate electrode. In step (h), the third insulating film covers the remaining second insulating film, the third memory gate electrode, and the fourth memory gate electrode in the second region. In step (i), a second contact hole is formed in each of the third insulating film, the second insulating film, and the first insulating film at the second region. In step (j), a second plug electrode electrically connected to the second impurity region is formed by forming a second conductive layer in the second contact hole. Each of the third gate electrode and the fourth gate electrode extends in the first direction of the main surface, and the third gate electrode and the fourth gate electrode are arranged in the second direction. Each of the fifth and sixth sidewalls of the third gate electrode extends in the first direction. Each of the seventh and eighth sidewalls of the fourth gate electrode extends in the first direction, and The sixth sidewall of the third gate electrode faces the seventh sidewall of the fourth gate electrode.

10. The method of manufacturing the semiconductor device according to claim 9, wherein step (a) comprises the following steps: (a1) Deposit a silicon film on the main surface; (a2) Deposit a fourth insulating film on the silicon film; as well as (a3) By processing the fourth insulating film and the silicon film, a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode are formed. The first gate electrode includes a first control gate electrode formed by the silicon film and a first cover insulating film formed by the fourth insulating film. The second gate electrode includes a second control gate electrode formed by the silicon film and a second cover insulating film formed by the fourth insulating film. The third gate electrode includes a third control gate electrode formed by the silicon film and a third cover insulating film formed by the fourth insulating film. The fourth gate electrode includes a fourth control gate electrode formed by the silicon film and a fourth cover insulating film formed by the fourth insulating film.

11. The method of manufacturing the semiconductor device according to claim 10, further comprising the following step after step (j): (k) A first wiring layer electrically connected to the first plug electrode is formed on the third insulating film located in the first region, and a second wiring layer electrically connected to the second plug electrode is formed on the third insulating film located in the second region. Each of the first wiring layer and the second wiring layer extends in the second direction.

12. The method of manufacturing the semiconductor device according to claim 10, In step (e), at the first region, the first thickness of the second insulating film is greater than the second thickness of the second insulating film formed on the first gate electrode.

13. The method of manufacturing the semiconductor device according to claim 10, The fourth insulating film is composed of a first silicon nitride film.

14. The method of manufacturing the semiconductor device according to claim 10, The first insulating film is composed of a second silicon nitride film. The second insulating film is composed of a first silicon oxide film, and The third insulating film is composed of a second silicon oxide film.

15. The method of manufacturing the semiconductor device according to claim 14, The second insulating film is composed of a first O3-TEOS film, and The third insulating film is composed of a second O3-TEOS film.

16. The method of manufacturing the semiconductor device according to claim 10, The first distance between the third memory gate electrode and the fourth memory gate electrode is greater than the second distance between the first gate electrode and the second gate electrode.

17. The method of manufacturing the semiconductor device according to claim 8, In step (g), the third thickness of the first insulating film located on each of the first gate electrode and the second gate electrode and exposed from the opening portion of the mask layer is less than the fourth thickness of the first insulating film covered by the mask layer.

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