Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and its manufacturing method, as well as an electronic device, are disclosed. The semiconductor device includes: a plurality of memory cells located on different layers, stacked and spaced apart along a direction perpendicular to a substrate; each memory cell includes a transistor, the transistor including a first electrode, a second electrode, a semiconductor layer located between the first electrode and the second electrode, and a gate electrode, wherein a gate insulating layer is provided between the semiconductor layer and the gate electrode; both the first electrode and the second electrode partially surround the semiconductor layer. The semiconductor device of this application embodiment has high storage density and a simple manufacturing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device has high storage density and a simple manufacturing process.

[0006] This application provides a semiconductor device, the semiconductor device comprising:

[0007] Multiple memory cells are stacked and spaced apart on different layers along a direction perpendicular to the substrate; each memory cell includes a transistor, the transistor including a first electrode, a second electrode, a semiconductor layer and a gate electrode located between the first electrode and the second electrode, and a gate insulating layer is provided between the semiconductor layer and the gate electrode;

[0008] Both the first electrode and the second electrode partially surround the semiconductor layer.

[0009] In some embodiments of this application, both the first electrode and the second electrode are arc-shaped and recessed in a direction away from the semiconductor layer between them.

[0010] In some embodiments of this application, both the first electrode and the second electrode are circular arcs, and the radius of curvature of the first electrode is the same as that of the second electrode.

[0011] In some embodiments of this application, the arc length of the first electrode is the same as the arc length of the second electrode.

[0012] In some embodiments of this application, the first electrode and the second electrode of the same transistor are spaced apart along a row direction parallel to the substrate;

[0013] The width of the first electrode in the row direction is the same as the width of the second electrode in the row direction.

[0014] In some embodiments of this application, the arc center of the first electrode of the same transistor is the same as the arc center of the second electrode.

[0015] In some embodiments of this application, the semiconductor layer at least partially surrounds the gate electrode, and the semiconductor layer extends in a direction perpendicular to the substrate.

[0016] In some embodiments of this application, the semiconductor layers of a plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected.

[0017] In some embodiments of this application, the gate insulating layers of the plurality of memory cells stacked along a direction perpendicular to the substrate are interconnected as a single structure.

[0018] In some embodiments of this application, the gate electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are an integral structure interconnected.

[0019] In some embodiments of this application, the memory cell further includes a capacitor; the capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the second electrode of the transistor located in the same memory cell;

[0020] The first capacitor electrode has a second upper surface and a second lower surface distributed along a direction perpendicular to the substrate, and a second sidewall connecting the second upper surface and the second lower surface.

[0021] In some embodiments of this application, the second electrode has a first upper surface and a first lower surface distributed along a direction perpendicular to the substrate, and a first sidewall connecting the first upper surface and the first lower surface;

[0022] The first sidewall is in contact with the second sidewall.

[0023] In some embodiments of this application, the second upper surface and the first upper surface are located on the same plane.

[0024] In some embodiments of this application, the second lower surface and the first lower surface are located on the same plane.

[0025] In some embodiments of this application, the first capacitor electrode at least partially surrounds the second capacitor electrode.

[0026] In some embodiments of this application, the first capacitor electrode is ring-shaped.

[0027] In some embodiments of this application, the second capacitor electrode is connected to an electrode signal line, the electrode signal line being configured to lead out the second capacitor electrode;

[0028] The electrode signal lines are made of tungsten.

[0029] In some embodiments of this application, the first capacitor electrodes of a plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected.

[0030] In some embodiments of this application, the dielectric layers of the plurality of memory cells stacked along a direction perpendicular to the substrate are an integral structure interconnected.

[0031] In some embodiments of this application, the second capacitor electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are an integral structure interconnected.

[0032] In some embodiments of this application, the semiconductor device further includes bit lines and word lines;

[0033] The bit line extends along a column direction parallel to the substrate and is connected to the first electrode of a column of memory cells spaced apart along the column direction;

[0034] The word line extends in a direction perpendicular to the substrate; the gate electrode is part of the word line, and the gate electrodes of the plurality of memory cells stacked in a direction perpendicular to the substrate are located in different regions of the word line.

[0035] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0036] Multiple first insulating layers and multiple second insulating layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0037] A transistor hole is formed through the stacked structure, and an annular conductive layer and a first sacrificial layer are formed on the sidewalls of the transistor hole located in the first insulating layer and the second insulating layer, respectively.

[0038] A semiconductor layer, a gate insulating layer, and a gate electrode are sequentially formed on the inner wall of the transistor hole;

[0039] Openings are formed on both sides of the transistor hole to expose the annular conductive layer.

[0040] The annular conductive layer is broken within the opening to form a first electrode and a second electrode spaced apart.

[0041] Remove the first sacrificial layer to expose the semiconductor layer between two adjacent conductive layers in different layers; remove at least a portion of the semiconductor layer between two adjacent conductive layers in different layers.

[0042] In some embodiments of this application, forming a transistor via through the stacked structure, and forming an annular conductive layer and a first sacrificial layer on the sidewalls of the transistor via located in the first insulating layer and the second insulating layer, respectively, includes:

[0043] The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure;

[0044] The first insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the first insulating layer, forming a first groove of the transistor hole extending into the first insulating layer.

[0045] An annular conductive layer is formed within the first groove;

[0046] The second insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the second insulating layer, forming a second groove of the transistor hole extending into the second insulating layer.

[0047] An annular first sacrificial layer is formed within the second groove.

[0048] In some embodiments of this application, forming openings on both sides of the transistor hole to expose the annular conductive layer includes:

[0049] A first through-hole and a second through-hole are formed in the stacked structure. The first through-hole and the second through-hole are located on both sides of the transistor hole along a column direction parallel to the substrate. The first through-hole and the second through-hole alternately expose the first insulating layer and the second insulating layer in a direction perpendicular to the substrate.

[0050] The exposed first insulating layer is etched in the first and second through holes to form an opening on each side of the transistor hole along the column direction, and the opening exposes a portion of the annular conductive layer.

[0051] In some embodiments of this application, the step of breaking the annular conductive layer within the opening to form a spaced-apart first electrode and second electrode includes:

[0052] The exposed area of ​​the annular conductive layer is etched within the opening, and a notch is formed on each side of the annular conductive layer along a column direction parallel to the substrate, the notch exposing the semiconductor layer; the two notches separate the conductive layer into a first electrode and a second electrode spaced apart along a row direction parallel to the substrate.

[0053] In some embodiments of this application, removing the first sacrificial layer to expose the semiconductor layer between two adjacent conductive layers located in different layers; removing at least a portion of the semiconductor layer between two adjacent conductive layers located in different layers includes:

[0054] The stacked structure is etched along a direction toward the substrate to form at least one etch window penetrating the stacked structure on at least one side of the transistor aperture; the etch window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture;

[0055] The exposed area of ​​the first sacrificial layer is etched within the etching window until the first sacrificial layer is removed, exposing at least a portion of the semiconductor layer located between two adjacent conductive layers of different layers.

[0056] The exposed area of ​​the semiconductor layer between two adjacent conductive layers in different layers is etched to remove at least a portion of the semiconductor layer between the two adjacent conductive layers in different layers, thereby breaking the semiconductor layer in the direction toward the substrate.

[0057] In some embodiments of this application, the etched window includes at least one of a via extending in a direction toward the substrate and a trench extending in a direction parallel to the substrate.

[0058] In some embodiments of this application, the etching of the stacked structure along a direction toward the substrate forms at least one etch window penetrating the stacked structure on at least one side of the transistor aperture; the etch window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, including:

[0059] The stacked structure is etched along the direction toward the substrate, forming trenches extending along the column direction parallel to the substrate on a first side of the transistor holes distributed along the row direction parallel to the substrate; the trenches alternately expose the first insulating layer and the second insulating layer in the direction toward the substrate.

[0060] Laterally etch the first insulating layer exposed on both sides in the trench to form bit line grooves extending along the column direction on both sides of the trench; the bit line grooves expose the first electrode;

[0061] A bit line connected to the first electrode is formed in the bit line groove;

[0062] Laterally etch the second insulating layer exposed on both sides in the trench, expand the trench along the direction toward the transistor hole, and expose at least a portion of the first sacrificial layer on one side of the expanded trench.

[0063] The trench, which expands in the direction of the transistor hole, serves as the etching window.

[0064] In some embodiments of this application, etching the stacked structure along a direction toward the substrate to form at least one etching window penetrating the stacked structure on at least one side of the transistor aperture; the etching window exposing at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, further includes:

[0065] After the first electrode and the second electrode are formed, a first etch barrier layer is formed in the opening of the first via and the second via, the first etch barrier layer covering the semiconductor layer that was originally exposed by the opening;

[0066] Laterally etch the exposed second insulating layer in the first and second vias, and expand both the first and second vias in the direction toward the transistor hole. The expanded first and second vias expose at least a portion of the first sacrificial layer.

[0067] Meanwhile, the trench, the first via, and the second via, which expand toward the transistor hole, serve as the etching window, and the trench, the first via, and the second via, which expand toward the transistor hole, respectively expose different regions of the first sacrificial layer on the sidewall of the same transistor hole.

[0068] In some embodiments of this application, the first through hole and the second through hole, which expand toward the direction of the transistor hole, are formed first, and then the trench, which expands toward the direction of the transistor hole, is formed.

[0069] In some embodiments of this application, the trench expanding toward the direction of the transistor hole is formed first, and then the first through hole and the second through hole expanding toward the direction of the transistor hole are formed.

[0070] In some embodiments of this application, when the first via and the second via expanding in the direction of the transistor aperture are formed first, and then the trench expanding in the direction of the transistor aperture is formed, the manufacturing method further includes: after forming the first via and the second via expanding in the direction of the transistor aperture, before etching the stacked structure to form the unexpanded trench,

[0071] A second sacrificial layer is filled in the first and second vias that expand in the direction toward the transistor hole;

[0072] And, after forming the trench that expands toward the transistor aperture, before etching the exposed area of ​​the first sacrificial layer within the etching window,

[0073] After removing the second sacrificial layer, the first and second vias, which expand toward the transistor hole, expose different areas of the first sacrificial layer on the sidewall of the same transistor hole.

[0074] In some embodiments of this application, the manufacturing method further includes: after forming the conductive layer,

[0075] The stacked structure is etched along the direction toward the substrate to form capacitor holes on a second side of the transistor holes distributed along a row direction parallel to the substrate; the capacitor holes alternately expose the first insulating layer and the second insulating layer in the direction toward the substrate.

[0076] Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole in the direction toward the transistor hole, and the expanded capacitor hole exposes the conductive layer.

[0077] A capacitor connected to the conductive layer is formed within the expanded capacitor hole.

[0078] In some embodiments of this application, the step of laterally etching the exposed first insulating layer within the capacitor hole to expand the capacitor hole along a direction toward the transistor hole, thereby exposing the conductive layer within the expanded capacitor hole, and forming a capacitor connected to the conductive layer within the expanded capacitor hole, includes:

[0079] Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole along the direction toward the transistor hole, forming a third groove of the capacitor hole; the third groove exposes the conductive layer located on the second side of the transistor hole;

[0080] A first capacitor electrode connected to the conductive layer is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate;

[0081] A dielectric layer and a second capacitor electrode are sequentially formed on the inner wall of the capacitor hole.

[0082] In some embodiments of this application, a first capacitor electrode connected to the conductive layer is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate, including:

[0083] A first electrode layer and a second etching barrier layer are sequentially formed on the inner wall of the expanded capacitor hole;

[0084] Remove the second etch barrier layer and the first electrode layer located on the sidewall of the second insulating layer of the capacitor hole, break the first electrode layer in a direction perpendicular to the substrate, and retain the first electrode layer located on the inner wall of the third groove to obtain the first capacitor electrode located on the inner wall of the third groove.

[0085] Remove the second etching barrier layer within the third groove.

[0086] In some embodiments of this application, the first capacitor electrode has a second upper surface and a second lower surface distributed along a direction perpendicular to the substrate, and a second sidewall connecting the second upper surface and the second lower surface;

[0087] The manufacturing process further includes: after forming the first capacitor electrode, but before forming a dielectric layer on the inner wall of the capacitor hole.

[0088] Laterally etch the exposed second insulating layer within the capacitor hole to expose at least a portion of at least one of the second upper surface and the second lower surface;

[0089] The step of sequentially forming a dielectric layer and a second capacitor electrode on the inner wall of the capacitor hole includes:

[0090] A dielectric layer and a second electrode layer are sequentially formed on the inner wall of the capacitor hole, both the dielectric layer and the second electrode layer surrounding the exposed areas of the second upper surface and the second lower surface; the second electrode layer includes second capacitor electrodes of a plurality of capacitors stacked and distributed along a direction perpendicular to the substrate;

[0091] An insulating material is filled into the capacitor hole, and the insulating material inside the capacitor hole is etched back; an electrode signal line is formed in the space formed after the insulating material is etched back; the electrode signal line is connected to the second capacitor electrode.

[0092] In some embodiments of this application, the capacitor hole is formed after the gate electrode is formed and before openings exposing the annular conductive layer are formed on both sides of the transistor hole.

[0093] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0094] The semiconductor device in this application embodiment stacks multiple memory cells along a direction perpendicular to the substrate, which can reduce the area occupied by multiple memory cells, achieve higher storage density, and simplify the manufacturing process.

[0095] The semiconductor device manufacturing method of this application first forms an annular first sacrificial layer in contact with the semiconductor layer on the sidewall of the transistor hole, then removes the annular first sacrificial layer to expose the semiconductor layer of the parasitic MOS region, and then removes the parasitic MOS. This method can remove the parasitic MOS in a simple step without damaging the semiconductor layer in the channel region, and can improve the morphology of the semiconductor layer in the channel region.

[0096] In addition, the semiconductor device manufacturing method of this application avoids the formation of insulating / metal layer stacks by first forming an annular conductive layer on the sidewall of the transistor hole and then breaking the annular conductive layer to form the first electrode and the second electrode, thus reducing the process difficulty.

[0097] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0098] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0099] Figure 1A A schematic diagram of the longitudinal section structure of a semiconductor device extending along the longitudinal direction, which is an exemplary embodiment of this application;

[0100] Figure 1B for Figure 1A The diagram shows a cross-sectional view of the semiconductor structure through the film layer between two adjacent memory cells.

[0101] Figure 1C for Figure 1A The diagram shows a cross-sectional view of the semiconductor structure passing through the memory cell.

[0102] Figure 2 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0103] Figure 3 A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a stacked structure, extending in the longitudinal section along the row direction;

[0104] Figure 4A A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a transistor hole, on a longitudinal section extending in the row direction;

[0105] Figure 4B for Figure 4A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0106] Figure 5A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first groove for a transistor hole in the longitudinal section extending in the row direction.

[0107] Figure 5B for Figure 5A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0108] Figure 6A This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method, which is an exemplary embodiment of this application, after forming an annular conductive layer.

[0109] Figure 6B for Figure 6A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0110] Figure 7A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming an annular first sacrificial layer;

[0111] Figure 7B for Figure 7A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0112] Figure 8A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the gate electrode, extending in the longitudinal direction;

[0113] Figure 8B for Figure 8A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0114] Figure 9A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a capacitor hole, extending in the longitudinal direction;

[0115] Figure 9B for Figure 9A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0116] Figure 10A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming the second groove of the capacitor hole in the longitudinal section extending in the row direction;

[0117] Figure 10B for Figure 10A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0118] Figure 11 This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a second etch barrier layer on the inner wall of a capacitor hole.

[0119] Figure 12A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first capacitor electrode on the inner wall of a capacitor hole.

[0120] Figure 12B for Figure 12A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0121] Figure 13A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method after removing the second etch barrier layer, which is an exemplary embodiment of this application.

[0122] Figure 13B for Figure 13A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0123] Figure 14 A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after exposing the second upper surface and the second lower surface of the first capacitor electrode in a longitudinal section extending along the row direction;

[0124] Figure 15A A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a capacitor, on a longitudinal section extending in the row direction;

[0125] Figure 15B for Figure 15A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0126] Figure 16A A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming electrode signal lines, extending in the longitudinal section along the running direction;

[0127] Figure 16B for Figure 16A The diagram shows a schematic of the longitudinal section of the semiconductor structure extending along the column direction.

[0128] Figure 16C for Figure 16A The semiconductor structure shown is a perspective view from a top angle;

[0129] Figure 17A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first through hole and a second through hole, on a longitudinal section extending along the column direction;

[0130] Figure 17B for Figure 17A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0131] Figure 18A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming openings on both sides of a transistor hole.

[0132] Figure 18B for Figure 18A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0133] Figure 19A A schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the first electrode and the second electrode, on a longitudinal section extending along the column direction;

[0134] Figure 19B for Figure 19A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0135] Figure 20A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the trench is formed, extending in the longitudinal direction;

[0136] Figure 20B for Figure 20A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0137] Figure 21AA schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the bit lines are formed, extending in the longitudinal direction;

[0138] Figure 21B for Figure 21A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0139] Figure 22 A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after exposing the first sacrificial layer in the trench, extending in the longitudinal direction;

[0140] Figure 23A A schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application after the removal of the first sacrificial layer;

[0141] Figure 23B for Figure 23A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0142] Figure 24A A schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of this application after removing the first sacrificial layer;

[0143] Figure 24B for Figure 24A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0144] Figure 25A A schematic diagram of the longitudinal section structure of another semiconductor device manufacturing method according to an exemplary embodiment of this application, after filling the first and second vias with a second sacrificial layer;

[0145] Figure 25B for Figure 25A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0146] Figure 26A A schematic diagram of the longitudinal section structure of another semiconductor device manufacturing method according to an exemplary embodiment of this application, after exposing the first sacrificial layer in the trench, extending in the longitudinal direction;

[0147] Figure 26B for Figure 26A A schematic diagram of the cross-sectional structure of the semiconductor structure shown;

[0148] Figure 27A A schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of this application after removing the second sacrificial layer;

[0149] Figure 27B for Figure 27A The diagram shows a cross-sectional view of the semiconductor structure. Detailed Implementation

[0150] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0151] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0152] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0153] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0154] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0155] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0156] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0157] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0158] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0159] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0160] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0161] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.

[0162] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0163] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0164] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0165] In this application, "cross section" refers to a cross section parallel to the substrate; "longitudinal section" refers to a cross section perpendicular to the substrate.

[0166] This application provides a semiconductor device. Figure 1A A schematic diagram of the longitudinal section structure of a semiconductor device extending along the longitudinal direction, which is an exemplary embodiment of this application; Figure 1B for Figure 1A The diagram shows a cross-sectional view of the semiconductor structure through the film layer between two adjacent memory cells. Figure 1C for Figure 1A The diagram shows a cross-sectional view of the semiconductor structure passing through the memory cell.

[0167] like Figures 1A to 1C As shown, the semiconductor device includes a plurality of memory cells 100 located on different layers, stacked and spaced apart along a direction perpendicular to the substrate 10;

[0168] Each memory cell 100 includes a transistor 20, which includes a first electrode 21, a second electrode 22, a semiconductor layer 23 located between the first electrode 21 and the second electrode 22, and a gate electrode 24. A gate insulating layer 25 is provided between the semiconductor layer 23 and the gate electrode 24.

[0169] Both the first electrode 21 and the second electrode 22 partially surround the semiconductor layer 23.

[0170] The semiconductor device in this application embodiment stacks multiple memory cells along a direction perpendicular to the substrate, which can reduce the area occupied by multiple memory cells, achieve higher storage density, and simplify the manufacturing process.

[0171] The semiconductor device manufacturing method of this application avoids the formation of insulating / metal layer stacks by first forming an annular conductive layer on the sidewall of the transistor hole and then breaking the annular conductive layer to form the first electrode and the second electrode, thus reducing the process difficulty.

[0172] In some embodiments of this application, such as Figure 1C As shown, both the first electrode 21 and the second electrode 22 are arc-shaped and are recessed in a direction away from the semiconductor layer 23 between them.

[0173] In some embodiments of this application, such as Figure 1C As shown, both the first electrode 21 and the second electrode 22 are circular arcs, and the radius of curvature of the first electrode 21 is the same as that of the second electrode 22.

[0174] In some embodiments of this application, such as Figure 1C As shown, the arc length of the first electrode 21 is the same as the arc length of the second electrode 22.

[0175] In some embodiments of this application, such as Figure 1A As shown, the first electrode 21 and the second electrode 22 of the same transistor 20 are spaced apart along a row direction parallel to the substrate 10.

[0176] In the description of this application, the row direction intersects the column direction; for example, the row direction and the column direction may be perpendicular to each other. Exemplarily, the row direction can be as follows: Figures 1A to 1C In the X direction, the column direction can be as follows: Figure 1B and Figure 1C The Y direction in the figure; the direction perpendicular to the substrate can be as follows: Figure 1A The Z direction is shown.

[0177] Multiple components distributed along the row direction can be referred to as a row component, for example, a row of storage cells. Multiple components distributed along the column direction can be referred to as a column component, for example, a column of storage cells.

[0178] In some embodiments of this application, such as Figure 1A As shown, the first electrode 21 and the second electrode 22 of the same transistor 20 are disposed on the same layer.

[0179] In some embodiments of this application, such as Figure 1C As shown, the width of the first electrode 21 in the row direction is the same as the width of the second electrode 22 in the row direction.

[0180] In some embodiments of this application, such as Figure 1C As shown, the arc center of the first electrode 21 of the same transistor 20 is the same as the arc center of the second electrode 22.

[0181] In some embodiments of this application, such as Figure 1A and Figure 1C As shown, the semiconductor layer 23 at least partially surrounds the gate electrode 24, and the semiconductor layer 23 extends in a direction perpendicular to the substrate 10.

[0182] In some embodiments of this application, such as Figure 1A As shown, the semiconductor layers 23 of a plurality of memory cells 100 stacked and distributed along a direction perpendicular to the substrate 10 are spaced apart and disconnected.

[0183] The semiconductor layers 23 of the multiple memory cells 100 stacked along a direction perpendicular to the substrate 10 are spaced apart and disconnected, which can eliminate parasitic MOS between adjacent layers and improve device stability.

[0184] In some embodiments of this application, such as Figure 1A As shown, the gate insulating layer 25 of the multiple memory cells 100 stacked along a direction perpendicular to the substrate 10 is an integral structure that is interconnected.

[0185] In some embodiments of this application, such as Figure 1A As shown, the gate electrodes 24 of the multiple memory cells 100 stacked along a direction perpendicular to the substrate 10 are interconnected as a single structure.

[0186] In some embodiments of this application, when fabricating transistor holes, transistor holes of other shapes, such as square ones, can be formed. By forming a surrounding conductive layer on the sidewall of the transistor hole and then breaking the conductive layer to form the first electrode and the second electrode, an electrode structure that partially surrounds the transistor can be formed, thereby avoiding the formation of insulating / metal layer stacks and reducing the difficulty of the process.

[0187] In some embodiments of this application, such as Figure 1A As shown, the storage cell 100 also includes a capacitor 30; the capacitor 30 includes a first capacitor electrode 31, a second capacitor electrode 32 and a dielectric layer 33 located between the first capacitor electrode 31 and the second capacitor electrode 32; the first capacitor electrode 31 is connected to the second electrode 22 of the transistor 20 located in the same storage cell 100.

[0188] The first capacitor electrode 31 has a second upper surface 311 and a second lower surface 312 distributed along a direction perpendicular to the substrate 10, and a second sidewall 313 connecting the second upper surface 311 and the second lower surface 312.

[0189] In some embodiments of this application, such as Figure 1A As shown, the second electrode 22 has a first upper surface 221 and a first lower surface 222 distributed along a direction perpendicular to the substrate 10, and a first sidewall 223 connecting the first upper surface 221 and the first lower surface 222.

[0190] The first sidewall 223 is in contact with the second sidewall 313.

[0191] In some embodiments of this application, such as Figure 1A As shown, the second upper surface 311 and the first upper surface 221 are located on the same plane.

[0192] In some embodiments of this application, such as Figure 1A As shown, the second lower surface 312 and the first lower surface 222 are located on the same plane.

[0193] In some embodiments of this application, such as Figure 1A and Figure 1C As shown, the first capacitor electrode 31 at least partially surrounds the second capacitor electrode 32.

[0194] In some embodiments of this application, such as Figure 1C As shown, the first capacitor electrode 31 is ring-shaped.

[0195] In some embodiments of this application, such as Figure 1A As shown, the second capacitor electrode 32 is connected to the electrode signal line 34, and the electrode signal line 34 is configured to lead out the second capacitor electrode 32.

[0196] The material of the electrode signal line 34 can be tungsten.

[0197] Using tungsten to form the electrode signal line 34 can avoid high temperature or strain problems.

[0198] In some embodiments of this application, such as Figure 1A As shown, the first capacitor electrodes 31 of a plurality of memory cells 100 stacked along a direction perpendicular to the substrate 10 are spaced apart and disconnected.

[0199] In some embodiments of this application, such as Figure 1A As shown, the dielectric layer 33 of the multiple memory cells 100 stacked along a direction perpendicular to the substrate 10 is an integral structure that is interconnected.

[0200] In some embodiments of this application, such as Figure 1A As shown, the second capacitor electrodes 32 of the multiple memory cells 100 stacked along a direction perpendicular to the substrate 10 are an integral structure that is interconnected.

[0201] In some embodiments of this application, such as Figure 1A As shown, the semiconductor device further includes a bit line BL and a word line WL;

[0202] Bit line BL extends along a column direction parallel to the substrate 10 and is connected to the first electrode 21 of a column of memory cells spaced apart along the column direction;

[0203] The word line WL extends in a direction perpendicular to the substrate 10; the gate electrode 24 is part of the word line WL, and the gate electrodes 24 of the multiple memory cells 100 stacked in a direction perpendicular to the substrate 10 are located in different regions of the word line WL.

[0204] In some embodiments of this application, such as Figure 1A As shown, the semiconductor device further includes a plurality of first insulating layers 41 and a plurality of second insulating layers 42 that are alternately stacked along a direction perpendicular to the substrate 10; the memory cell 100 is located in the first insulating layer 41, and two adjacent memory cells 100 stacked along a direction perpendicular to the substrate 10 are separated by the second insulating layer 42.

[0205] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0206] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0207] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0208] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0209] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0210] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0211] In some embodiments of this application, the material of the bit line can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0212] In some embodiments of this application, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0213] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0214] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0215] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0216] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0217] Low-K materials, such as silicon oxide.

[0218] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0219] In some embodiments of this application, the dielectric layer may be made of silicon oxide or a high-K dielectric material. High-K materials, in some embodiments, may include any one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0220] In some embodiments of this application, the semiconductor device may be a 3D memory, such as a 3D DRAM. The 3D memory may have a 1T1C structure.

[0221] This application also provides a method for manufacturing a semiconductor device, which can be used to obtain the semiconductor device described above.

[0222] Figure 2 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.

[0223] like Figure 2As shown, the manufacturing method includes:

[0224] Multiple first insulating layers and multiple second insulating layers are sequentially and alternately deposited on a substrate to obtain a stacked structure;

[0225] A transistor hole is formed through the stacked structure, and an annular conductive layer and a first sacrificial layer are formed on the sidewalls of the transistor hole located in the first insulating layer and the second insulating layer, respectively.

[0226] A semiconductor layer, a gate insulating layer, and a gate electrode are sequentially formed on the inner wall of the transistor hole;

[0227] Openings are formed on both sides of the transistor hole to expose the annular conductive layer.

[0228] The annular conductive layer is broken within the opening to form a first electrode and a second electrode spaced apart.

[0229] Remove the first sacrificial layer to expose the semiconductor layer between two adjacent conductive layers in different layers; remove at least a portion of the semiconductor layer between two adjacent conductive layers in different layers.

[0230] The semiconductor device manufacturing method of this application first forms an annular first sacrificial layer in contact with the semiconductor layer on the sidewall of the transistor hole, then removes the annular first sacrificial layer to expose the semiconductor layer of the parasitic MOS region, and then removes the parasitic MOS. This method can remove the parasitic MOS in a simple step without damaging the semiconductor layer in the channel region, and can improve the morphology of the semiconductor layer in the channel region.

[0231] In addition, the semiconductor device manufacturing method of this application avoids the formation of insulating / metal layer stacks by first forming an annular conductive layer on the sidewall of the transistor hole and then breaking the annular conductive layer to form the first electrode and the second electrode, thus reducing the process difficulty.

[0232] In some embodiments of this application, forming a transistor via through the stacked structure, and forming an annular conductive layer and a first sacrificial layer on the sidewalls of the transistor via located in the first insulating layer and the second insulating layer, respectively, includes:

[0233] The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure;

[0234] The first insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the first insulating layer, forming a first groove of the transistor hole extending into the first insulating layer.

[0235] An annular conductive layer is formed within the first groove;

[0236] The second insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the second insulating layer, forming a second groove of the transistor hole extending into the second insulating layer.

[0237] An annular first sacrificial layer is formed within the second groove.

[0238] In some embodiments of this application, forming openings on both sides of the transistor hole to expose the annular conductive layer includes:

[0239] A first through-hole and a second through-hole are formed in the stacked structure. The first through-hole and the second through-hole are located on both sides of the transistor hole along a column direction parallel to the substrate. The first through-hole and the second through-hole alternately expose the first insulating layer and the second insulating layer in a direction perpendicular to the substrate.

[0240] The exposed first insulating layer is etched in the first and second through holes to form an opening on each side of the transistor hole along the column direction, and the opening exposes a portion of the annular conductive layer.

[0241] In some embodiments of this application, the step of breaking the annular conductive layer within the opening to form a spaced-apart first electrode and second electrode includes:

[0242] The exposed area of ​​the annular conductive layer is etched within the opening, and a notch is formed on each side of the annular conductive layer along a column direction parallel to the substrate, the notch exposing the semiconductor layer; the two notches separate the conductive layer into a first electrode and a second electrode spaced apart along a row direction parallel to the substrate.

[0243] In some embodiments of this application, removing the first sacrificial layer to expose the semiconductor layer between two adjacent conductive layers located in different layers; removing at least a portion of the semiconductor layer between two adjacent conductive layers located in different layers includes:

[0244] The stacked structure is etched along a direction toward the substrate to form at least one etch window penetrating the stacked structure on at least one side of the transistor aperture; the etch window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture;

[0245] The exposed area of ​​the first sacrificial layer is etched within the etching window until the first sacrificial layer is removed, exposing at least a portion of the semiconductor layer located between two adjacent conductive layers of different layers.

[0246] The exposed area of ​​the semiconductor layer between two adjacent conductive layers in different layers is etched to remove at least a portion of the semiconductor layer between the two adjacent conductive layers in different layers, thereby breaking the semiconductor layer in the direction toward the substrate.

[0247] In some embodiments of this application, the etched window includes at least one of a via extending in a direction toward the substrate and a trench extending in a direction parallel to the substrate.

[0248] In some embodiments of this application, the etching of the stacked structure along a direction toward the substrate forms at least one etch window penetrating the stacked structure on at least one side of the transistor aperture; the etch window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, including:

[0249] The stacked structure is etched along the direction toward the substrate, forming trenches extending along the column direction parallel to the substrate on a first side of the transistor holes distributed along the row direction parallel to the substrate; the trenches alternately expose the first insulating layer and the second insulating layer in the direction toward the substrate.

[0250] Laterally etch the first insulating layer exposed on both sides in the trench to form bit line grooves extending along the column direction on both sides of the trench; the bit line grooves expose the first electrode;

[0251] A bit line connected to the first electrode is formed in the bit line groove;

[0252] Laterally etch the second insulating layer exposed on both sides in the trench, expand the trench along the direction toward the transistor hole, and expose at least a portion of the first sacrificial layer on one side of the expanded trench.

[0253] The trench, which expands in the direction of the transistor hole, serves as the etching window.

[0254] In some embodiments of this application, etching the stacked structure along a direction toward the substrate to form at least one etching window penetrating the stacked structure on at least one side of the transistor aperture; the etching window exposing at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, further includes:

[0255] After the first electrode and the second electrode are formed, a first etch barrier layer is formed in the opening of the first via and the second via, the first etch barrier layer covering the semiconductor layer that was originally exposed by the opening;

[0256] Laterally etch the exposed second insulating layer in the first and second vias, and expand both the first and second vias in the direction toward the transistor hole. The expanded first and second vias expose at least a portion of the first sacrificial layer.

[0257] Meanwhile, the trench, the first via, and the second via, which expand toward the transistor hole, serve as the etching window, and the trench, the first via, and the second via, which expand toward the transistor hole, respectively expose different regions of the first sacrificial layer on the sidewall of the same transistor hole.

[0258] In some embodiments of this application, the first through hole and the second through hole, which expand toward the direction of the transistor hole, are formed first, and then the trench, which expands toward the direction of the transistor hole, is formed.

[0259] In some embodiments of this application, the trench expanding toward the direction of the transistor hole is formed first, and then the first through hole and the second through hole expanding toward the direction of the transistor hole are formed.

[0260] In some embodiments of this application, when the first via and the second via expanding in the direction of the transistor aperture are formed first, and then the trench expanding in the direction of the transistor aperture is formed, the manufacturing method further includes: after forming the first via and the second via expanding in the direction of the transistor aperture, before etching the stacked structure to form the unexpanded trench,

[0261] A second sacrificial layer is filled in the first and second vias that expand in the direction toward the transistor hole;

[0262] And, after forming the trench that expands toward the transistor aperture, before etching the exposed area of ​​the first sacrificial layer within the etching window,

[0263] After removing the second sacrificial layer, the first and second vias, which expand toward the transistor hole, expose different areas of the first sacrificial layer on the sidewall of the same transistor hole.

[0264] In some embodiments of this application, the manufacturing method further includes: after forming the conductive layer,

[0265] The stacked structure is etched along the direction toward the substrate to form capacitor holes on a second side of the transistor holes distributed along a row direction parallel to the substrate; the capacitor holes alternately expose the first insulating layer and the second insulating layer in the direction toward the substrate.

[0266] Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole in the direction toward the transistor hole, and the expanded capacitor hole exposes the conductive layer.

[0267] A capacitor connected to the conductive layer is formed within the expanded capacitor hole.

[0268] In some embodiments of this application, the step of laterally etching the exposed first insulating layer within the capacitor hole to expand the capacitor hole along a direction toward the transistor hole, thereby exposing the conductive layer within the expanded capacitor hole, and forming a capacitor connected to the conductive layer within the expanded capacitor hole, includes:

[0269] Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole along the direction toward the transistor hole, forming a third groove of the capacitor hole; the third groove exposes the conductive layer located on the second side of the transistor hole;

[0270] A first capacitor electrode connected to the conductive layer is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate;

[0271] A dielectric layer and a second capacitor electrode are sequentially formed on the inner wall of the capacitor hole.

[0272] In some embodiments of this application, a first capacitor electrode connected to the conductive layer is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate, including:

[0273] A first electrode layer and a second etching barrier layer are sequentially formed on the inner wall of the expanded capacitor hole;

[0274] Remove the second etch barrier layer and the first electrode layer located on the sidewall of the second insulating layer of the capacitor hole, break the first electrode layer in a direction perpendicular to the substrate, and retain the first electrode layer located on the inner wall of the third groove to obtain the first capacitor electrode located on the inner wall of the third groove.

[0275] Remove the second etching barrier layer within the third groove.

[0276] In some embodiments of this application, the first capacitor electrode has a second upper surface and a second lower surface distributed along a direction perpendicular to the substrate, and a second sidewall connecting the second upper surface and the second lower surface;

[0277] The manufacturing process further includes: after forming the first capacitor electrode, but before forming a dielectric layer 33 on the inner wall of the capacitor hole.

[0278] Laterally etch the exposed second insulating layer within the capacitor hole to expose at least a portion of at least one of the second upper surface and the second lower surface;

[0279] The step of sequentially forming a dielectric layer and a second capacitor electrode on the inner wall of the capacitor hole includes:

[0280] A dielectric layer and a second electrode layer are sequentially formed on the inner wall of the capacitor hole. Both the dielectric layer 33 and the second electrode layer surround the exposed areas of the second upper surface and the second lower surface. The second electrode layer includes the second capacitor electrodes of a plurality of capacitors stacked and distributed along a direction perpendicular to the substrate.

[0281] An insulating material is filled into the capacitor hole, and the insulating material inside the capacitor hole is etched back; an electrode signal line is formed in the space formed after the insulating material is etched back; the electrode signal line is connected to the second capacitor electrode.

[0282] In some embodiments of this application, the capacitor hole is formed after the gate electrode is formed and before openings exposing the annular conductive layer are formed on both sides of the transistor hole.

[0283] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0284] like Figures 3 to 23B As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0285] S10: A substrate 10 is provided, and a plurality of first insulating layers 41 and a plurality of second insulating layers 42 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure composed of a plurality of first insulating layers 41 and a plurality of second insulating layers 42, such as Figure 3 As shown.

[0286] In some embodiments of this application, the materials forming the first insulating layer and the second insulating layer can be low-K dielectric materials, i.e., dielectric materials with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon oxide (SiO2) or other silicon-containing films, but the materials of the first insulating layer and the second insulating layer are different. For example, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0287] For example only. Figure 3 The stacked structure shown includes three first insulating layers 41 and three second insulating layers 42. In other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 41 and second insulating layers 42.

[0288] S20: A transistor hole K3 is formed in the stacked structure, penetrating the stacked structure.

[0289] For example, step S20 may include:

[0290] S21: Etch the stacked structure along the direction toward the substrate 10 to form a transistor hole K3 penetrating the stacked structure, such as... Figure 4A and Figure 4B As shown; where, Figure 4B The cross section in the middle passes through the second insulating layer 42;

[0291] S22: Laterally etch the first insulating layer 41 within the transistor hole K3, expanding the transistor hole K3 along the direction toward the first insulating layer 41 to form a first groove T1 extending into the first insulating layer 41, such as... Figure 5A and Figure 5B As shown; where, Figure 5B The cross section passes through the first insulating layer 41.

[0292] In some embodiments of this application, such as Figure 4A As shown, the transistor hole K3 formed in step 21 extends in a direction perpendicular to the substrate 10.

[0293] In some embodiments of this application, multiple transistor holes K3 can be formed simultaneously in the stacked structure, with the multiple transistor holes K3 spaced apart in the row and column directions parallel to the substrate, for example, in an array distribution.

[0294] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. Exemplarily, the row direction can be as follows: Figure 4BThe column direction can be as shown in the X direction, where the column direction is as follows: Figure 4B Y direction shown.

[0295] S30: An annular conductive layer 43 and a first sacrificial layer 51 are formed on the sidewalls of the transistor hole K3 located on the first insulating layer 41 and the second insulating layer 42, respectively.

[0296] For example, step S30 may include steps S31 to S33 described below.

[0297] S31: An annular conductive layer 43 is formed within the first groove T1, such as... Figure 6A and Figure 6B As shown. Among them, Figure 6B The cross section passes through the first insulating layer 41.

[0298] For example, step S31 may include:

[0299] S311: A conductive layer 43 is deposited on the inner wall of the transistor hole K3 to fill the first groove T1;

[0300] S312: By etching, such as wet etching, the conductive layer 43 on the sidewall and bottom wall of the transistor hole K3 is removed, leaving only the conductive layer in the first groove T1, thus forming an annular conductive layer 43.

[0301] like Figure 6B As shown, the annular structure of the conductive layer 43 can be a circular ring, or in other embodiments, a square ring or other annular shape.

[0302] For example, the material of the conductive layer can be metals such as nickel, aluminum, copper, cobalt, and titanium, or their compounds, or materials with similar properties.

[0303] For example, the conductive layer 43 can be formed by atomic layer deposition (ALD) process, for example, the conductive layer 43 of TiN material can be deposited by ALD process at 430°C.

[0304] S32: Laterally etch the second insulating layer 42 inside the transistor hole K3 to expand the transistor hole K3 along the direction toward the second insulating layer 42, forming a second groove T2 extending into the transistor hole K3 of the second insulating layer 42;

[0305] S33: An annular first sacrificial layer 51 is formed within the second groove T2, such as Figure 7A and Figure 7B As shown. Among them, Figure 7B The cross section passes through the second insulating layer 42.

[0306] like Figure 7A As shown, in step S31, the second insulating layer 42 on the surface of the stacked structure is also etched away.

[0307] For example, step S33 may include:

[0308] S331: A first sacrificial layer 51 is deposited on the inner wall of transistor hole K3 to fill the second groove T2 and cover the annular conductive layer 43;

[0309] S332: The first sacrificial layer 51 located on the sidewall of the annular conductive layer 43 of the transistor hole K3 is removed by etching, leaving only the first sacrificial layer 51 located in the second groove T2, that is, the annular first sacrificial layer 51.

[0310] like Figure 7B As shown, the annular structure of the first sacrificial layer 51 can be a circular ring, or in other embodiments, a square ring or other annular shape.

[0311] like Figure 7A As shown, the annular conductive layer 43 and the annular first sacrificial layer 51 are alternately distributed along a direction perpendicular to the substrate 10.

[0312] For example, such as Figure 7A As shown, the diameter of the second groove T2 is larger than the diameter of the first groove T1. In other embodiments, the diameter of the second groove T2 may be less than or equal to the diameter of the first groove T1.

[0313] S40: A semiconductor layer 23, a gate insulating layer 25, and a gate electrode 24 are sequentially deposited on the inner wall of the transistor hole K3, such as... Figure 8A and Figure 8B As shown. Among them, Figure 8B The cross section passes through the second insulating layer 42.

[0314] For example, an IGZO semiconductor layer 23 can be deposited using an ALD process.

[0315] For example, step S40 may include:

[0316] S41: A semiconductor layer 23, a gate insulating layer 25, and a gate electrode layer covering the inner wall of the transistor hole K3 are sequentially deposited on the substrate.

[0317] S42: The semiconductor layer 23, gate insulating layer 25 and gate electrode layer on the substrate surface are removed by chemical mechanical polishing (CMP) process, exposing the first insulating layer 41 on the substrate surface. Only the semiconductor layer 23, gate insulating layer 25 and gate electrode layer on the inner wall of transistor hole K3 are retained. The remaining gate electrode layer is the gate electrode 24.

[0318] S43: Deposit a second insulating layer 42 on the substrate surface covering each transistor hole K3 to protect the semiconductor layer 23, gate insulating layer 25 and gate electrode 24 from being etched in subsequent etching steps.

[0319] S50: A capacitor 30 connected to the annular conductive layer 43 is formed on one side of the transistor hole K3.

[0320] For example, step S50 may include steps S51 to S53 as described below.

[0321] S51: The stacked structure is etched along the direction toward the substrate 10, for example, by dry etching, to form capacitor holes K4 on the second side distributed along the row direction of transistor holes K3, as shown. Figure 9A and Figure 9B As shown. Among them, Figure 9B The cross section passes through the first insulating layer 41.

[0322] like Figure 9A and Figure 9B As shown, the capacitor hole K4 alternately exposes the first insulating layer 41 and the second insulating layer 42 in the direction toward the substrate 10, that is, the capacitor hole K4 does not expose the annular conductive layer 43 and the annular first sacrificial layer 51 on the sidewall of the transistor hole K3.

[0323] In some embodiments of this application, such as Figure 9A As shown, the capacitor hole K4 formed in step 50 extends in a direction perpendicular to the substrate 10.

[0324] S52: Laterally etch the exposed first insulating layer 41 inside the capacitor hole K4, expanding the capacitor hole K4 along the direction toward the transistor hole K3 to form the third groove T3 of the capacitor hole K4; the third groove T3 exposes the conductive layer 43 located on the second side of the transistor hole K3, such as Figure 10A and Figure 10B As shown. Among them, Figure 10B The cross section passes through the first insulating layer 41.

[0325] S53: A capacitor 30 connected to the conductive layer 43 is formed within the expanded capacitor hole K4.

[0326] For example, step S53 may include the following steps S531 to S533.

[0327] S531: A first capacitor electrode 31 connected to the conductive layer 43 is formed on the inner wall of the third groove T3; the first capacitor electrodes 31 located in different layers are spaced apart in a direction perpendicular to the substrate 10.

[0328] For example, step S531 may include:

[0329] S5311: Sequentially deposit a first electrode layer 31' and a second etch barrier layer 62 on the substrate, covering the inner wall of the expanded capacitor hole K4, as shown. Figure 11 As shown;

[0330] S5312: Remove the second etch barrier layer 62 and the first electrode layer 31' located on the sidewall of the second insulating layer 42 of the capacitor hole K4. Break the first electrode layer 31' in a direction perpendicular to the substrate 10. The first electrode layer 31' located on the inner wall of the third groove T3 is retained. The first electrode layer 31' located on the inner wall of the third groove T3 is the first capacitor electrode 31. Figure 12A and Figure 12B As shown; where, Figure 12B The cross section passes through the second etch barrier layer 62.

[0331] S5313: Remove the second etching barrier layer 62 within the third groove T3, such as Figure 13A and Figure 13B As shown.

[0332] like Figure 13A As shown, the first capacitor electrode 31 has a second upper surface 311 and a second lower surface 312 spaced apart along a direction perpendicular to the substrate 10, and a second sidewall 313 connecting the second upper surface 311 and the second lower surface 312. The second sidewall 313 is in contact with the annular conductive layer 43. Figure 13B The cross section passes through the second upper surface 311 or the second lower surface 312 of the first capacitor electrode 31.

[0333] S532: Laterally etch the exposed second insulating layer 42 within the capacitor hole K4 to expose at least a portion of at least one of the second upper surface 311 and the second lower surface 312 of the first capacitor electrode 31, such as... Figure 14 As shown.

[0334] Exposing at least a portion of at least one of the second upper surface 311 and the second lower surface 312 of the first capacitor electrode 31 can allow for a larger contact area between the subsequently formed dielectric layer and the second capacitor electrode and the first capacitor electrode 31.

[0335] S533: A dielectric layer 33 and a second capacitor electrode 32 are sequentially formed on the inner wall of the capacitor hole K4, as follows: Figure 15A and Figure 15B As shown. Among them, Figure 15B The cross section passes through the first insulating layer 41.

[0336] For example, step S533 may include:

[0337] A dielectric layer 33 and a second electrode layer are sequentially formed on the inner wall of the capacitor hole K4. Both the dielectric layer 33 and the second electrode layer surround the exposed areas of the second upper surface 311 and the second lower surface 312 of the first capacitor electrode 31. The second electrode layer includes a plurality of second capacitor electrodes 32 stacked and distributed along a direction perpendicular to the substrate 10. A first capacitor electrode 31, a second capacitor electrode 32, and a dielectric layer 33 constitute a capacitor 30.

[0338] For example, the plurality of second capacitor electrodes 32 distributed along the direction perpendicular to the substrate can be an integral structure.

[0339] For example, step S53 may also include:

[0340] S534: An insulating material is filled into the capacitor hole K4, and the insulating material is etched back; an electrode signal line 34 is formed in the space formed after the insulating material is etched back; the electrode signal line 34 is connected to the uppermost second capacitor electrode 32 in the direction away from the substrate; a second insulating layer 42 is formed on the substrate surface to cover the electrode signal line 34, such as... Figures 16A to 16C As shown.

[0341] For example, the material of the electrode signal line 34 can be a conductive metal material, such as tungsten (W) or other conductive metal materials.

[0342] S60: Openings are formed on both sides of the transistor hole K3 to expose the annular conductive layer 43; the annular conductive layer 43 is broken in the opening P1 to form a first electrode 21 and a second electrode 22 that are spaced apart.

[0343] For example, step S60 may include:

[0344] S61: A first through-hole K1 and a second through-hole K2 are formed through the stacked structure. The first through-hole K1 and the second through-hole K2 are located on both sides of the column direction of the transistor hole K3, respectively. The first through-hole K1 and the second through-hole K2 alternately expose the first insulating layer 41 and the second insulating layer 42 in a direction perpendicular to the substrate 10. Figure 17A and Figure 17B As shown; where, Figure 17B The cross section in the middle passes through the first insulating layer 41;

[0345] S62: The exposed first insulating layer 41 is etched within the first through-hole K1 and the second through-hole K2, forming an opening P1 on each side of the transistor hole K3 along the column direction. The opening P1 exposes a portion of the annular conductive layer 43, such as... Figure 18A and Figure 18B As shown; where, Figure 18B The cross section in the middle passes through the first insulating layer 41;

[0346] S63: The annular conductive layer 43 is broken within the opening P1 to form a first electrode 21 and a second electrode 22 spaced apart, as shown. Figure 19A and Figure 19B As shown; where, Figure 19B The cross section passes through the first insulating layer 41.

[0347] For example, step S63 may include:

[0348] The exposed area of ​​the annular conductive layer 43 is etched within the opening P1, and a notch P2 is formed on both sides of the column direction of the annular conductive layer 43, exposing the semiconductor layer 23. The two notches P2 separate the conductive layer 43 into a first electrode 21 and a second electrode 22 that are spaced apart along the row direction. Insulating material is filled into the first through hole K1, the second through hole K2 and the notch P2.

[0349] like Figure 19B As shown, a first electrode 21, a second electrode 22, and a semiconductor layer 23, a gate electrode 24, and a gate insulating layer 25 between them constitute a transistor 20.

[0350] S70: The stacked structure is etched along the direction toward the substrate 10 to form at least one etch window through the stacked structure on at least one side of the transistor hole K3; the etch window exposes at least a portion of the first sacrificial layer 51 located on the outer sidewall of the transistor hole K3.

[0351] For example, step S70 may include steps S71 to S73 described below.

[0352] S71: The stacked structure is etched along the direction toward the substrate 10, forming a trench T4 extending in a column direction parallel to the substrate 10 on the first side where the transistor holes K3 are distributed in the row direction; the trench T4 alternately exposes the first insulating layer 41 and the second insulating layer 42 in the direction toward the substrate 10, as shown. Figure 20A and Figure 20B As shown.

[0353] The first and second sides of the transistor hole K3 are opposite sides, for example, opposite sides distributed along the row direction.

[0354] S72: Laterally etch the first insulating layer 41 exposed on both sides within the trench T4, forming bit line grooves extending along the column direction on both sides of the trench T4; the bit line grooves expose the first electrode 21; bit lines BL connected to the first electrode 21 are formed within the bit line grooves, such as... Figure 21A and Figure 21B As shown.

[0355] like Figure 21B As shown, the bit line BL extends along the column direction.

[0356] S73: Laterally etch the second insulating layer 42 exposed on both sides within the trench T4, expanding the trench T4 along the direction toward the transistor hole K3, exposing at least a portion of the first sacrificial layer 51 on one side of the expanded trench T4; using the trench T4 expanding in the direction toward the transistor hole K3 as the etching window, such as... Figure 22 As shown.

[0357] S80: Remove the first sacrificial layer 51 to expose the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers; remove at least a portion of the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers.

[0358] For example, step S80 may include:

[0359] S81: Etch the exposed area of ​​the first sacrificial layer 51 within the etching window (i.e., trench T4) until the first sacrificial layer 51 is removed, exposing at least a portion of the semiconductor layer 23 located between two adjacent conductive layers 43 of different layers, such as... Figure 23A and Figure 23B As shown; where, Figure 23B The cross section passes through the second insulating layer 42.

[0360] S82: Etch the exposed area of ​​the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers to remove at least a portion of the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers, i.e. remove the parasitic MOS, and disconnect the semiconductor layer 23 in the direction toward the substrate 10.

[0361] S83: Fill the space between the trench T4 and the conductive layer 43 located in different layers with insulating material to obtain, as shown below. Figures 1A to 1C The semiconductor device shown.

[0362] The above embodiment uses the expanded trench T4 as the etching window, i.e., only one etching window, to achieve the purpose of removing parasitic MOS. In other embodiments, more etching windows can be designed, for example, two or three.

[0363] This embodiment uses the design of three etching windows as an example for illustration. The semiconductor device manufacturing method of this embodiment includes the following process.

[0364] Steps S100 to S600 are the same as steps S10 to S60 in the above embodiments.

[0365] S700: The stacked structure is etched along the direction toward the substrate 10 to form at least one etch window through the stacked structure on at least one side of the transistor hole K3; the etch window exposes at least a portion of the first sacrificial layer 51 located on the outer wall of the transistor hole K3.

[0366] For example, step S700 may include steps S710 to S730 described below.

[0367] S710: A first etch barrier layer 61 is formed in the opening P1 of the first via K1 and the second via K2. The first etch barrier layer 61 covers the semiconductor layer that was originally exposed by the opening P1, such as... Figure 24A and Figure 24B As shown; where, Figure 24A This is a cross-sectional view perpendicular to the substrate along the column direction. Figure 24B The cross section passes through the first insulating layer 41.

[0368] S720: Laterally etch the exposed second insulating layer 42 in the first through hole K1 and the second through hole K2, and expand the first through hole K1 and the second through hole K2 in the direction toward the transistor hole K3. After expansion, the first through hole K1 and the second through hole K2 expose at least a portion of the first sacrificial layer 51.

[0369] S730: A second sacrificial layer 52 is filled in the first through-hole K1 and the second through-hole K2, which expand in the direction toward the transistor hole K3, as shown. Figure 25A and Figure 25B As shown; where, Figure 25A This is a cross-sectional view perpendicular to the substrate along the column direction. Figure 25B The cross section passes through the second insulating layer 42.

[0370] Step S740 is the same as step S70 above, resulting in the following: Figure 26A and Figure 26B The device structure described above. Wherein, Figure 26B The cross section passes through the second insulating layer 42.

[0371] S750: Remove the second sacrificial layer 52 within the first through hole K1 and the second through hole K2, such as Figure 27A and Figure 27B As shown.

[0372] Up to step S750, this embodiment has formed a total of three etching windows (e.g. Figure 27B As indicated by the arrow in the diagram, it includes: a trench T4 extending toward the transistor hole K3, a first through hole K1, and a second through hole K2; the trench T4, the first through hole K1, and the second through hole K2 extending toward the transistor hole K3 respectively expose different regions of the first sacrificial layer on the sidewall of the same transistor hole.

[0373] S800: Remove the first sacrificial layer 51 to expose the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers; remove at least a portion of the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers.

[0374] For example, step S800 may include:

[0375] S810: Simultaneously using the trench T4, the first via K1, and the second via K2 expanding in the direction of the transistor hole as the etching window, the exposed area of ​​the first sacrificial layer 51 is etched within the etching window until the first sacrificial layer 51 is removed, exposing at least a portion of the semiconductor layer 23 located between two adjacent conductive layers 43 in different layers, such as... Figure 23A and Figure 23B As shown; where, Figure 23B The cross section passes through the second insulating layer 42.

[0376] S820: Etch the exposed area of ​​the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers to remove at least a portion of the semiconductor layer 23 between two adjacent conductive layers 43 located in different layers, i.e. remove the parasitic MOS, and disconnect the semiconductor layer 23 in the direction toward the substrate 10.

[0377] S830: Fill the space between trench T4 and conductive layer 43 located in different layers with insulating material to obtain, as shown below. Figures 1A to 1C The semiconductor device shown.

[0378] In other embodiments, only two etched windows may be formed, for example, a first through-hole K1 and a second through-hole K2.

[0379] In other embodiments, the timing of capacitor formation can be changed. For example, the capacitor via can be formed after the parasitic MOS is removed, and the capacitor can be formed within the capacitor via.

[0380] The semiconductor device manufacturing method of this application first forms an annular first sacrificial layer in contact with the semiconductor layer on the sidewall of the transistor hole, then removes the annular first sacrificial layer to expose the semiconductor layer of the parasitic MOS region, and then removes the parasitic MOS. This method can remove the parasitic MOS in a simple step without damaging the semiconductor layer in the channel region, and can improve the morphology of the semiconductor layer in the channel region.

[0381] In addition, the semiconductor device manufacturing method of this application avoids the formation of insulating / metal layer stacks by first forming an annular conductive layer on the sidewall of the transistor hole and then breaking the annular conductive layer to form the first electrode and the second electrode, thus reducing the process difficulty.

[0382] The semiconductor device manufacturing method of this application embodiment can reduce the number of wet etching operations, avoid the problems of insufficient etching stop layer capability and damage to undesirable etched film layers in wet etching under large aspect ratio conditions; and reduce the process of forming SiN under low temperature conditions, thereby solving the problem of unstable quality of SiN formed under low temperature conditions.

[0383] Furthermore, the semiconductor device manufacturing method of this application does not involve high-temperature processes after the semiconductor layer is formed, thus avoiding the semiconductor layer from being affected by high temperatures. Moreover, the second capacitor plate of the capacitor can be led out using tungsten-formed electrode signal lines.

[0384] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0385] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0386] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked and spaced apart on different layers along a direction perpendicular to the substrate; each memory cell includes a transistor, the transistor including a first electrode, a second electrode, a semiconductor layer and a gate electrode located between the first electrode and the second electrode, and a gate insulating layer is provided between the semiconductor layer and the gate electrode; Both the first electrode and the second electrode partially surround the semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, Both the first electrode and the second electrode are arc-shaped and recessed in a direction away from the semiconductor layer between them.

3. The semiconductor device according to claim 2, characterized in that, Both the first electrode and the second electrode are circular arcs, and the radius of curvature of the first electrode is the same as that of the second electrode.

4. The semiconductor device according to claim 3, characterized in that, The arc length of the first electrode is the same as the arc length of the second electrode.

5. The semiconductor device according to claim 2, characterized in that, The first electrode and the second electrode of the same transistor are spaced apart along a row direction parallel to the substrate; The width of the first electrode in the row direction is the same as the width of the second electrode in the row direction.

6. The semiconductor device according to claim 3, characterized in that, The arc center of the first electrode of the same transistor is the same as the arc center of the second electrode.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor layer at least partially surrounds the gate electrode, and the semiconductor layer extends in a direction perpendicular to the substrate; and / or, The semiconductor layers of a plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected; And / or, The gate insulating layers of the plurality of memory cells stacked along a direction perpendicular to the substrate are interconnected as a single, integral structure; and / or, The gate electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are interconnected as a single structure.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The storage cell further includes a capacitor; the capacitor includes a first capacitor electrode, a second capacitor electrode, and a dielectric layer located between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the second electrode of the transistor located in the same storage cell; the first capacitor electrode has a second upper surface and a second lower surface distributed in a direction perpendicular to the substrate, and a second sidewall connected between the second upper surface and the second lower surface.

9. The semiconductor device according to claim 8, characterized in that, The second electrode has a first upper surface and a first lower surface distributed along a direction perpendicular to the substrate, and a first sidewall connecting the first upper surface and the first lower surface; The first sidewall is in contact with the second sidewall; And / or, The second upper surface and the first upper surface are located on the same plane; and / or, The second lower surface and the first lower surface are located on the same plane.

10. The semiconductor device according to claim 8, characterized in that, The first capacitor electrode at least partially surrounds the second capacitor electrode.

11. The semiconductor device according to claim 10, characterized in that, The first capacitor electrode is ring-shaped.

12. The semiconductor device according to claim 8, characterized in that, The second capacitor electrode is connected to an electrode signal line, which is configured to lead out the second capacitor electrode; The electrode signal lines are made of tungsten.

13. The semiconductor device according to claim 8, characterized in that, The first capacitor electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are spaced apart and disconnected; and / or, The dielectric layers of the plurality of memory cells stacked along a direction perpendicular to the substrate are interconnected as a single, integral structure; and / or, The second capacitor electrodes of the plurality of memory cells stacked along a direction perpendicular to the substrate are interconnected as a single structure.

14. The semiconductor device according to any one of claims 1 to 7, characterized in that, It also includes bit lines and word lines; The bit line extends along a column direction parallel to the substrate and is connected to the first electrode of a column of memory cells spaced apart along the column direction; The word line extends in a direction perpendicular to the substrate; the gate electrode is part of the word line, and the gate electrodes of the plurality of memory cells stacked in a direction perpendicular to the substrate are located in different regions of the word line.

15. A method for manufacturing a semiconductor device, characterized in that, include: Multiple first insulating layers and multiple second insulating layers are sequentially and alternately deposited on a substrate to obtain a stacked structure; A transistor hole is formed through the stacked structure, and an annular conductive layer and a first sacrificial layer are formed on the sidewalls of the transistor hole located in the first insulating layer and the second insulating layer, respectively. A semiconductor layer, a gate insulating layer, and a gate electrode are sequentially formed on the inner wall of the transistor hole; Openings are formed on both sides of the transistor hole to expose the annular conductive layer. The annular conductive layer is broken within the opening to form a first electrode and a second electrode spaced apart. Remove the first sacrificial layer to expose the semiconductor layer located between two adjacent conductive layers in different layers; Remove at least a portion of the semiconductor layer located between two adjacent conductive layers in different layers.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method of forming a transistor hole through the stacked structure, and forming an annular conductive layer and a first sacrificial layer on the sidewalls of the transistor hole located in the first insulating layer and the second insulating layer, respectively, includes: The stacked structure is etched along the direction toward the substrate to form transistor holes that penetrate the stacked structure; The first insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the first insulating layer, forming a first groove of the transistor hole extending into the first insulating layer. An annular conductive layer is formed within the first groove; The second insulating layer is laterally etched within the transistor hole to expand the transistor hole along the direction toward the second insulating layer, forming a second groove of the transistor hole extending into the second insulating layer. An annular first sacrificial layer is formed within the second groove.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method of forming openings on both sides of the transistor hole to expose the annular conductive layer includes: A first through-hole and a second through-hole are formed in the stacked structure. The first through-hole and the second through-hole are located on both sides of the transistor hole along a column direction parallel to the substrate. The first through-hole and the second through-hole alternately expose the first insulating layer and the second insulating layer in a direction perpendicular to the substrate. The exposed first insulating layer is etched in the first and second through holes to form an opening on each side of the transistor hole along the column direction, and the opening exposes a portion of the annular conductive layer.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The step of breaking the annular conductive layer within the opening to form a spaced-apart first electrode and second electrode includes: The exposed area of ​​the annular conductive layer is etched within the opening, and a notch is formed on each side of the annular conductive layer along a column direction parallel to the substrate, the notch exposing the semiconductor layer; the two notches separate the conductive layer into a first electrode and a second electrode spaced apart along a row direction parallel to the substrate.

19. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The first sacrificial layer is removed to expose the semiconductor layer located between two adjacent conductive layers in different layers; Removing at least a portion of the semiconductor layer between two adjacent conductive layers located in different layers includes: The stacked structure is etched along a direction toward the substrate to form at least one etch window penetrating the stacked structure on at least one side of the transistor aperture; the etch window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture; The exposed area of ​​the first sacrificial layer is etched within the etching window until the first sacrificial layer is removed, exposing at least a portion of the semiconductor layer located between two adjacent conductive layers of different layers. The exposed area of ​​the semiconductor layer between two adjacent conductive layers in different layers is etched to remove at least a portion of the semiconductor layer between the two adjacent conductive layers in different layers, thereby breaking the semiconductor layer in the direction toward the substrate.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, The etched window includes at least one of a via extending in a direction toward the substrate and a trench extending in a direction parallel to the substrate.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that, The stacked structure is etched along the direction toward the substrate, forming at least one etched window through the stacked structure on at least one side of the transistor hole; The etched window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, including: The stacked structure is etched along the direction toward the substrate, forming trenches extending along the column direction parallel to the substrate on a first side of the transistor holes distributed along the row direction parallel to the substrate; the trenches alternately expose the first insulating layer and the second insulating layer in the direction toward the substrate. Laterally etch the first insulating layer exposed on both sides in the trench to form bit line grooves extending along the column direction on both sides of the trench; the bit line grooves expose the first electrode; A bit line connected to the first electrode is formed in the bit line groove; Laterally etch the second insulating layer exposed on both sides in the trench, expand the trench along the direction toward the transistor hole, and expose at least a portion of the first sacrificial layer on one side of the expanded trench. The trench, which expands in the direction of the transistor hole, serves as the etching window.

22. The method for manufacturing a semiconductor device according to claim 21, characterized in that, The stacked structure is etched along the direction toward the substrate, forming at least one etched window through the stacked structure on at least one side of the transistor hole; The etched window exposes at least a portion of the first sacrificial layer located on the outer wall of the transistor aperture, and further includes: After the first electrode and the second electrode are formed, a first etch barrier layer is formed in the opening of the first via and the second via, the first etch barrier layer covering the semiconductor layer that was originally exposed by the opening; Laterally etch the exposed second insulating layer in the first and second vias, and expand both the first and second vias in the direction toward the transistor hole. The expanded first and second vias expose at least a portion of the first sacrificial layer. Meanwhile, the trench, the first via, and the second via, which expand toward the transistor hole, serve as the etching window, and the trench, the first via, and the second via, which expand toward the transistor hole, respectively expose different regions of the first sacrificial layer on the sidewall of the same transistor hole.

23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, First, the first through hole and the second through hole are formed in the direction of expanding toward the transistor hole, and then the trench is formed in the direction of expanding toward the transistor hole; or, First, the trench is formed that expands in the direction of the transistor hole, and then the first through hole and the second through hole are formed that expand in the direction of the transistor hole. Wherein, when the first via and the second via expanding in the direction of the transistor aperture are formed first, and the trench expanding in the direction of the transistor aperture is formed subsequently, the manufacturing method further includes: after forming the first via and the second via expanding in the direction of the transistor aperture, and before etching the stacked structure to form the unexpanded trench, A second sacrificial layer is filled in the first and second vias that expand in the direction toward the transistor hole; And, after forming the trench that expands toward the transistor aperture, before etching the exposed area of ​​the first sacrificial layer within the etching window, After removing the second sacrificial layer, the first and second vias, which expand toward the transistor hole, expose different areas of the first sacrificial layer on the sidewall of the same transistor hole.

24. The method for manufacturing a semiconductor device according to any one of claims 15 to 23, characterized in that, Also includes: After the conductive layer is formed The stacked structure is etched along the direction toward the substrate to form capacitor holes on the second side of the transistor holes distributed in a row direction parallel to the substrate; The capacitor aperture alternately exposes the first insulating layer and the second insulating layer in the direction toward the substrate; Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole in the direction toward the transistor hole, and the expanded capacitor hole exposes the conductive layer. A capacitor connected to the conductive layer is formed within the expanded capacitor hole.

25. The method for manufacturing a semiconductor device according to claim 24, characterized in that, The first insulating layer exposed within the capacitor hole is laterally etched to expand the capacitor hole along the direction toward the transistor hole, and the expanded capacitor hole exposes the conductive layer. A capacitor connected to the conductive layer is formed within the expanded capacitor hole, comprising: Laterally etch the exposed first insulating layer inside the capacitor hole to expand the capacitor hole along the direction toward the transistor hole, forming a third groove of the capacitor hole; the third groove exposes the conductive layer located on the second side of the transistor hole; A first capacitor electrode connected to the conductive layer is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate; A dielectric layer and a second capacitor electrode are sequentially formed on the inner wall of the capacitor hole.

26. The method for manufacturing a semiconductor device according to claim 25, characterized in that, A first capacitor electrode, connected to the conductive layer, is formed on the inner wall of the third groove; the first capacitor electrodes located in different layers are spaced apart in a direction perpendicular to the substrate, including: A first electrode layer and a second etching barrier layer are sequentially formed on the inner wall of the expanded capacitor hole; Remove the second etch barrier layer and the first electrode layer located on the sidewall of the second insulating layer of the capacitor hole, break the first electrode layer in a direction perpendicular to the substrate, and retain the first electrode layer located on the inner wall of the third groove to obtain the first capacitor electrode located on the inner wall of the third groove. Remove the second etching barrier layer within the third groove.

27. The method for manufacturing a semiconductor device according to claim 26, characterized in that, The first capacitor electrode has a second upper surface and a second lower surface distributed along a direction perpendicular to the substrate, and a second sidewall connecting the second upper surface and the second lower surface; The manufacturing process further includes: after forming the first capacitor electrode, but before forming a dielectric layer on the inner wall of the capacitor hole. Laterally etch the exposed second insulating layer within the capacitor hole to expose at least a portion of at least one of the second upper surface and the second lower surface; The step of sequentially forming a dielectric layer and a second capacitor electrode on the inner wall of the capacitor hole includes: A dielectric layer and a second electrode layer are sequentially formed on the inner wall of the capacitor hole, both the dielectric layer and the second electrode layer surrounding the exposed areas of the second upper surface and the second lower surface; the second electrode layer includes second capacitor electrodes of a plurality of capacitors stacked and distributed along a direction perpendicular to the substrate; An insulating material is filled into the capacitor hole, and the insulating material inside the capacitor hole is etched back; an electrode signal line is formed in the space formed after the insulating material is etched back; the electrode signal line is connected to the second capacitor electrode.

28. The method for manufacturing a semiconductor device according to claim 24, characterized in that, After the gate electrode is formed, the capacitor hole is formed before openings exposing the annular conductive layer are formed on both sides of the transistor hole.

29. An electronic device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 14, or it includes the semiconductor device obtained by the manufacturing method according to any one of claims 15 to 28.

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