Semiconductor device including a transistor

Abstract

A semiconductor device includes: a first transistor; and a second transistor sharing an active region with the first transistor. The active region includes a common active region located between a channel region of the first transistor and a channel region of the second transistor. The common active region includes: a first segment extending from the channel region of the first transistor along a second horizontal direction perpendicular to a first horizontal direction; a second segment extending from the channel region of the second transistor along the second horizontal direction; and a third segment connecting the first segment and the second segment, and extending along an inclined direction intersecting the first and second horizontal directions. At least a portion of the third segment has a dimension in the first horizontal direction that differs from the dimension in the first horizontal direction of each of the first and second segments.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0189368, filed with the Korean Intellectual Property Office on December 18, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor device including a transistor. Background Technology

[0004] Semiconductor devices include memory devices for writing data. A memory device includes an array of memory cells and peripheral circuitry for controlling the array of memory cells. Summary of the Invention

[0005] In an embodiment, a semiconductor device may include: a first transistor; and a second transistor sharing an active region with the first transistor, wherein the active region includes a common active region located between the channel region of the first transistor and the channel region of the second transistor, wherein, in plan view, the common active region includes: a first segment extending from the channel region of the first transistor along a second horizontal direction perpendicular to a first horizontal direction; a second segment extending from the channel region of the second transistor along the second horizontal direction; and a third segment connecting the first segment and the second segment and extending along an inclined direction intersecting the first and second horizontal directions, wherein at least a portion of the third segment has a dimension in the first horizontal direction that is different from the dimension in the first horizontal direction of each of the first and second segments.

[0006] In an embodiment, a semiconductor device may include: a substrate defining an active region; and a first gate electrode and a second gate electrode extending on the substrate along a first horizontal direction and disposed parallel to each other; wherein the active region includes: a common active region, which, in plan view, is disposed between the first gate electrode and the second gate electrode; a first independent active region extending from the common active region along a second horizontal direction perpendicular to the first horizontal direction and intersecting the first gate electrode; and a second independent active region extending from the common active region along the second horizontal direction and intersecting the second gate electrode, wherein the common active region includes: a first segment extending from the first independent active region along the second horizontal direction; a second segment extending from the second independent active region along the second horizontal direction; and a third segment connecting the first segment and the second segment and extending along an inclined direction intersecting the first horizontal direction and the second horizontal direction, wherein at least a portion of the third segment has a dimension in the first horizontal direction that is different from the dimension in the first horizontal direction of each of the first segment and the second segment.

[0007] In an embodiment, a semiconductor device may include: a memory cell array; and a page buffer circuit connected to the memory cell array via bit lines; wherein the page buffer circuit includes a first transistor and a second transistor sharing an active region, wherein the active region includes a common active region located between the channel regions of the first transistor and the channel regions of the second transistor, wherein, in plan view, the common active region includes: a first segment extending from the channel region of the first transistor along a second horizontal direction perpendicular to a first horizontal direction; a second segment extending from the channel region of the second transistor along the second horizontal direction; and a third segment connecting the first segment and the second segment and extending along an inclined direction intersecting the first and second horizontal directions, wherein at least a portion of the third segment has a dimension in the first horizontal direction smaller than the dimension in the first horizontal direction of each of the first segment and the second segment. Attached Figure Description

[0008] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 yes Figure 1 The equivalent circuit diagram of the memory block shown is shown.

[0010] Figure 3 This is a plan view showing the transistors of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 It is shown Figure 3 A plan view of the active region.

[0012] Figure 5 It is along Figure 3 A cross-sectional view taken from the A-A' line.

[0013] Figure 6 and Figure 7 This is a plan view showing the transistors of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 8 and Figure 9 This is a plan view showing a transistor used for comparison with this disclosure.

[0015] Figure 10 It is along Figure 9 A cross-sectional view taken from the B-B' line. Detailed Implementation

[0016] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. The specific structural or functional descriptions in the embodiments are merely examples to illustrate the concepts disclosed in this application. Examples or embodiments of the concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0017] Crosshairs throughout the figures indicate corresponding or similar areas between figures, rather than representing material associated with those areas.

[0018] When one element is marked "connected" or "attached" to another element, the elements can be directly connected or attached, or connected or attached through an intermediate element between the elements. When two elements are marked "directly connected" or "directly attached," one element is directly connected or directly attached to the other element, and there is no intermediate element between the two elements.

[0019] When one element is identified as being "above", "over", "below", or "under" another element, the elements can be in direct contact, or an intermediate element can be placed between the elements.

[0020] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “over,” “side,” “upper,” “topmost,” “lower,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms indicating relative spatial relationships or directions are used for the purpose of description or reference to the accompanying drawings only and are not intended to be limiting. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of this disclosure.

[0021] Terms such as "first" and "second" are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, while in another example, the second element may be named the first element.

[0022] In the specification, when the elements included in the embodiments are described in the singular, the elements can be interpreted as including multiple elements that perform the same or similar functions.

[0023] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0024] Reference Figure 1The semiconductor device according to embodiments of the present disclosure may include a memory cell array 100 and peripheral circuitry 200. Peripheral circuitry 200 may include a row decoder (X-DEC) 210, a page buffer circuit 220, control logic 230, a column decoder 240, and input / output circuitry (IO circuitry) 250.

[0025] The memory cell array 100 may include a plurality of memory cells. The memory cell array 100 may be configured as a three-dimensional memory array, wherein the memory cells are stacked along a direction perpendicular to the substrate, but the configuration is not limited thereto.

[0026] The memory cell array 100 can be connected to the line decoder 210 via word line WL and select lines DSL and SSL. Select lines DSL and SSL may include a drain select line DSL and a source select line SSL. The memory cell array 100 can be connected to the page buffer circuit 220 via bit line BL. The memory cell array 100 can store data received through the page buffer circuit 220 during programming operations and can transfer the stored data to the page buffer circuit 220 during read operations.

[0027] Memory cell array 100 may include multiple memory blocks BLK. Each memory block BLK may be an erase unit. Word lines WL, select lines DSL and SSL, and bit lines BL may be connected to each memory block BLK. The word lines WL, DSL, and SSL may be connected to their respective memory block BLKs. The bit line BL may be connected to multiple memory block BLKs together. (See below for further details.) Figure 2 An example describing a storage block (BLK).

[0028] The row decoder 210 can be connected to the memory cell array 100 via word line WL and select lines DSL and SSL. The row decoder 210 can select one of the memory blocks BLK in the memory cell array 100 in response to a row address X-ADDR received from control logic 230. The row decoder 210 can transmit operating voltages to the word line WL and select lines DSL and SSL connected to the selected memory block BLK.

[0029] Page buffer circuit 220 can be connected to memory cell array 100 via bit line BL. Page buffer circuit 220 may include multiple page buffers PB respectively connected to bit line BL. Page buffers PB can exchange data with memory cell array 100 via bit line BL.

[0030] Page buffer circuit 220 can operate in response to page buffer control signal PBCON received from control logic 230. During a write operation, page buffer PB can store data to be programmed into a memory cell. Page buffer PB can apply voltages to multiple bit lines BL based on the stored data. During a read operation or a verified read operation, page buffer PB can sense the voltage on bit lines BL and store the sensing result.

[0031] Control logic 230 can generate the page buffer control signal PBCON in response to the command CMD input via input / output circuit 250. Control logic 230 can also generate the row address X-ADDR and column address Y-ADDR in response to the address signal ADDR input via input / output circuit 250.

[0032] The column decoder 240 can be connected to the page buffer PB via the page line PL. In response to the column address Y-ADDR received from the control logic 230, the column decoder 240 exchanges data with the page buffer PB via the page line PL.

[0033] Input / output circuit 250 can exchange data with column decoder 240 connected via column line CL. Input / output circuit 250 can exchange data DATA with external devices such as memory controllers via input / output paths, and can transmit commands CMD and address signals ADD received from external devices via input / output paths to control logic 230. Input / output paths can contain 2... N There are 1000 input / output pins (where N is a natural number equal to or greater than 2). In the example, N=3, meaning it can include eight input / output pins (IO). <0> To IO <7> .

[0034] All or part of the peripheral circuitry 200 may be disposed on a different plane from the memory cell array 100. For example, the memory cell array 100 may be disposed in a first semiconductor layer, and the peripheral circuitry 200 may be disposed in a second semiconductor layer that is perpendicularly overlapping the first semiconductor layer. Part or all of the peripheral circuitry 200 disposed in the second semiconductor layer may be perpendicularly overlapping the memory cell array 100.

[0035] Figure 2 yes Figure 1 The equivalent circuit diagram of the memory block shown is shown.

[0036] Reference Figure 2 Each storage block BLK may include multiple cell strings CSTRs connected between multiple bit lines BL and a common source line CSL.

[0037] Each cell string (CSTR) can be connected between the corresponding bit line (BL) and the common source line (CSL). Each cell string (CSTR) may include a source select transistor (SST) connected to the common source line (CSL), a drain select transistor (DST) connected to the bit line (BL), and multiple memory cells (MCs) connected between the source select transistor (SST) and the drain select transistor (DST). The gate of the source select transistor (SST) can be connected to the source select line (SSL). The gate of each memory cell (MC) can be connected to its corresponding word line (WL). The gate of the drain select transistor (DST) can be connected to the drain select line (DSL).

[0038] The source select line (SSL), word line (WL), and drain select line (DSL) can extend in a direction perpendicular to the bit line (BL). The source select line (SSL), word line (WL), and drain select line (DSL) can be stacked in a direction perpendicular to the substrate surface to form a three-dimensional structure.

[0039] The memory cells (MCs) included in a memory block (BLK) can be divided into physical page units or logical page units. For example, memory cells that share a single word line (WL) and are connected to different cell strings (CSTRs) can form a physical page (PG). A page can be the basic unit for read operations.

[0040] For example, Figure 2 The diagram shows one drain-select transistor (DST) and one source-select transistor (SST) in each cell string (CSTR). However, each cell string (CSTR) may also contain two or more drain-select transistors, or two or more source-select transistors.

[0041] In the following text and in the accompanying drawings, two directions parallel to the top surface of the substrate are defined as a first horizontal direction HD1 and a second horizontal direction HD2, respectively, and a direction protruding vertically from the top surface of the substrate is defined as a vertical direction. The first horizontal direction HD1 and the second horizontal direction HD2 may intersect each other perpendicularly.

[0042] Figure 3 This is a plan view showing the transistors of a semiconductor device according to an embodiment of the present disclosure. Figure 4 It is shown Figure 3 Plan view of the active region Figure 5 It is along Figure 3 A cross-sectional view taken from the A-A' line.

[0043] Reference Figures 3 to 5 An isolation layer ISO can be formed on the substrate SUB to define the active region ACTa. The substrate SUB can be formed of a semiconductor material. For example, the substrate SUB can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0044] The first transistor TR1 and the second transistor TR2 can be disposed in the active region ACTa. The first transistor TR1 and the second transistor TR2 can be included in the above reference. Figure 1 The peripheral circuitry 200 in the semiconductor device according to an embodiment of this disclosure is described. For example, a first transistor TR1 and a second transistor TR2 may be included above. Figure 1 The page buffer circuit 220 is described.

[0045] The first transistor TR1 and the second transistor TR2 share an active region ACTa. The active region ACTa includes a first independent active region SA1, a second independent active region SA2, and a common active region CA1a. The first independent active region SA1 and the second independent active region SA2 are offset from each other in the first horizontal direction HD1. In other words, the first independent active region SA1 and the second independent active region SA2 are not aligned with each other in the second horizontal direction HD2.

[0046] The gate electrode GE1 (hereinafter referred to as the "first gate electrode") of the first transistor TR1 and the gate electrode GE2 (hereinafter referred to as the "second gate electrode") of the second transistor TR2 are disposed on the substrate SUB. The first gate electrode GE1 intersects with the first independent active region SA1 in the first horizontal direction HD1, and the second gate electrode GE2 intersects with the second independent active region SA2 in the first horizontal direction HD1.

[0047] The first independent active region SA1 includes the channel region CH1 of the first transistor TR1 (hereinafter referred to as the "first channel region"), which overlaps with the first gate electrode GE1 in the vertical direction, and the second independent active region SA2 includes the channel region CH2 of the second transistor TR2 (hereinafter referred to as the "second channel region"), which overlaps with the second gate electrode GE2 in the vertical direction. The first channel region CH1 and the second channel region CH2 are offset from each other in the first horizontal direction HD1.

[0048] From the plan view, the common active region CA1a is located between the first gate electrode GE1 and the second gate electrode GE2. The common active region CA1a connects the first channel region CH1 and the second channel region CH2. The common active region CA1a includes a first segment FS1 connected to the first channel region CH1, a second segment SS1 connected to the second channel region CH2, and a third segment TS1a located between the first segment FS1 and the second segment SS1.

[0049] The first segment FS1 of the common active region CA1a extends from the first channel region CH1 along the second horizontal direction HD2. The dimension of the first segment FS1 of the common active region CA1a in the first horizontal direction HD1 can be the same as the dimension of the first channel region CH1 in the first horizontal direction HD1. The dimension of the first segment FS1 of the common active region CA1a and the dimension of the first channel region CH1 in the first horizontal direction HD1 can both be the same dimension W1.

[0050] The second segment SS1 of the common active region CA1a extends from the second channel region CH2 along the second horizontal direction HD2. The dimensions of the second segment SS1 of the common active region CA1a in the first horizontal direction HD1 can be the same as the dimensions of the second channel region CH2 in the first horizontal direction HD1. Furthermore, the dimensions of the second segment SS1 of the common active region CA1a in the first horizontal direction HD1 and the dimensions of the second channel region CH2 in the first horizontal direction HD1 can both be the same size W2.

[0051] The third segment TS1a of the common active region CA1a extends along an inclined direction intersecting the first horizontal direction HD1 and the second horizontal direction HD2. The third segment TS1a of the common active region CA1a may have stepped boundaries BD1a and BD2a. The third segment TS1a of the common active region CA1a may include multiple rectangular segments SG1, SG2, and SG3, and may be configured to be arranged in a stepped manner, offset from each other along the first horizontal direction HD1. The dimension of each of the rectangular segments SG1, SG2, and SG3 in the first horizontal direction HD1 is smaller than the dimension W1 of the first segment FS1 of the common active region CA1a in the first horizontal direction HD1, and smaller than the dimension W2 of the second segment SS1 of the common active region CA1a in the first horizontal direction HD1. The dimension of each of the rectangular segments SG1, SG2, and SG3 in the first horizontal direction HD1 is W3, and W3 is smaller than W1 and W2.

[0052] Since the dimension W3 of the third segment TS1a of the common active region CA1a in the first horizontal direction HD1 is smaller than the dimension W1 of the first segment FS1 of the common active region CA1a in the first horizontal direction HD1, and smaller than the dimension W2 of the second segment SS1 of the common active region CA1a in the first horizontal direction HD1, a larger spacing relative to adjacent active regions can be ensured for the rectangular segments in TS1a. For example, in the first horizontal direction, the spacing between adjacent rectangular segments SG3 in TS1a is greater than the spacing between adjacent second segments SS1.

[0053] The first independent active region SA1 extends from one end of the common active region CA1a along the second horizontal direction HD2. The second independent active region SA2 extends from the other end of the common active region CA1a along the second horizontal direction HD2.

[0054] The first transistor TR1 is disposed within a common active region CA1a and a first independent active region SA1, and the second transistor TR2 is disposed within a common active region CA1a and a second independent active region SA2. The first transistor TR1 and the second transistor TR2 share the common active region CA1a.

[0055] Reference Figure 5 The first independent active region SA1 includes a first segment disposed on the side of the first gate electrode GE1 opposite to the common active region CA1a. The second independent active region SA2 includes a second segment disposed on the side of the second gate electrode GE2 opposite to the common active region CA1a.

[0056] A first impurity can be doped into a first segment of a first independent active region SA1 to form a first junction region Jn1. The first impurity can be an n-type impurity. n-type impurities can include phosphorus (P), arsenic (As), and antimony (Sb). The first impurity can be doped into a second segment of a second independent active region SA2 to form a second junction region Jn2. The first impurity can be doped into a common active region CA1a to form a third junction region Jn3.

[0057] The first gate insulating layer GI1 is disposed between the first gate electrode GE1 and the substrate SUB, and the second gate insulating layer GI2 is disposed between the second gate electrode GE2 and the substrate SUB.

[0058] The first gate electrode GE1, the first gate insulating layer GI1, the first junction region Jn1 and the third junction region Jn3, and the first channel region CH1 constitute the first transistor TR1. The second gate electrode GE2, the second gate insulating layer GI2, the second junction region Jn2 and the third junction region Jn3, and the second channel region CH2 constitute the second transistor TR2. The first transistor TR1 and the second transistor TR2 share the third junction region Jn3.

[0059] The first contact CNT1 can be connected to the first junction region Jn1, the second contact CNT2 can be connected to the second junction region Jn2, and the third contact CNT3 can be connected to the third junction region Jn3.

[0060] Reference Figure 3The third contact CNT3 is disposed on either the first segment FS1 or the second segment SS1 of the common active region CA1a. The third contact CNT3 is not disposed on the third segment TS1a of the common active region CA1a. Since the third contact CNT3 is disposed on either the first segment FS1 or the second segment SS1 of the common active region CA1a, and the dimension of the first segment FS1 or the second segment SS1 in the first horizontal direction HD1 is larger than the dimension of any rectangular segment in the third segment TS1a of the common active region CA1a, the process margin for forming the contact can be improved compared to the case where the third contact CNT3 is formed on a rectangular segment of the third segment TS1a of the common active region CA1a.

[0061] Figure 6 This is a plan view showing the transistors of a semiconductor device according to an embodiment of the present disclosure.

[0062] Reference Figure 6 The third segment TS1b of the public active area CA1b includes the first boundary BD1b and the second boundary BD2b that are opposite each other in the first horizontal direction HD1.

[0063] The first boundary BD1b includes a first straight portion T1 extending from a first segment FS1 of the common active region CA1b along a second horizontal direction HD2, and a first inclined portion L1 connecting the first straight portion T1 and a second segment SS1 of the common active region CA1b. The first inclined portion L1 extends along an inclined direction intersecting the first horizontal direction HD1 and the second horizontal direction HD2.

[0064] The second boundary BD2b includes a second inclined portion L2 extending from the first segment FS1 of the common active region CA1b along an inclined direction, and a second straight portion T2 extending along the second horizontal direction HD2 to connect the second inclined portion L2 and the second segment SS1 of the common active region CA1b.

[0065] The first inclined portion L1 and the second inclined portion L2 may be parallel to each other. The first inclined portion L1 may have a slope of a first angle θ1 relative to the first straight portion T1. The second inclined portion L2 may have a slope of a first angle θ1 relative to the second straight portion T2.

[0066] The dimension of the end of the third segment TS1b of the common active region CA1b that contacts the first segment FS1 of the common active region CA1b in the first horizontal direction HD1 can be the same as the dimension of the first segment FS1 of the common active region CA1b in the first horizontal direction HD1. Since the dimension of the first segment FS1 of the common active region CA1b in the first horizontal direction HD1 can be dimension W1, the dimension of that end of the third segment TS1b of the common active region CA1b in the first horizontal direction HD1 can also be dimension W1.

[0067] The dimension of the other end of the third segment TS1b of the common active region CA1b, which contacts the second segment SS1 of the common active region CA1b, in the first horizontal direction HD1 can be the same as the dimension of the second segment SS1 of the common active region CA1b in the first horizontal direction HD1. The dimension of the second segment SS1 of the common active region CA1b in the first horizontal direction HD1 can be dimension W2, therefore, the dimension of the other end of the third segment TS1b of the common active region CA1b in the first horizontal direction HD1 can also be dimension W2. The dimension of the third segment TS1b of the common active region CA1b, located between the first segment FS1 and the second segment SS1, in the first horizontal direction HD1 is less than W1 or W2.

[0068] Figure 7 This is a plan view showing the transistors of a semiconductor device according to an embodiment of the present disclosure.

[0069] Reference Figure 7 The third segment TS1c of the common active region CA1c includes the first boundary BD1c and the second boundary BD2c that are opposite to each other in the first horizontal direction HD1.

[0070] Each of the first boundary BD1c and the second boundary BD2c may have a straight line shape extending along an inclined direction intersecting the first horizontal direction HD1 and the second horizontal direction HD2. The first boundary BD1c and the second boundary BD2c may each have a slope of a second angle θ2 relative to the second horizontal direction HD2 that is greater than 0 degrees and less than 90 degrees.

[0071] When the size of the first segment FS1 of the common active region CA1c in the first horizontal direction HD1 is W1 and the size of the second segment SS1 of the common active region CA1c in the first horizontal direction HD1 is W2, the size of the third segment TS1c of the common active region CA1c in the first horizontal direction HD1 is W4, where W4 is smaller than W1 and W2.

[0072] Figure 8 and Figure 9 This is a plan view showing a transistor used for comparison with this disclosure, and Figure 10It is along Figure 9 A cross-sectional view taken from the B-B' line.

[0073] Reference Figure 8 Unlike this disclosure, the size of the common active region CA in the first horizontal direction HD1 can be configured to have the same size as the size of each of the first independent active regions SA1' and the second independent active regions SA2' in the first horizontal direction HD1.

[0074] In this case, the interval between the first independent active regions SA1' in adjacent active regions ACT is d1, and the interval between the common active regions CA in adjacent active regions ACT is d2, where d2 is less than d1. For example, when the boundary of the common active region CA has a slope θ relative to the second horizontal direction HD2, the value of d2 is... .

[0075] An isolation layer defining the active region ACT can be formed by creating trenches in the substrate and filling the trenches with an insulating material. When the spacing between adjacent common active regions CA is narrow, the probability of defects increases due to insufficient process margin during the insulating material filling process. Furthermore, due to insufficient isolation layer thickness between adjacent common active regions CA, interference may occur between adjacent transistors, leading to transistor malfunctions.

[0076] Reference Figure 9 and Figure 10 When the size of the common active region CA in the first horizontal direction HD1 is determined to be smaller than the size of the first independent active region SA1' and the second independent active region SA2' in the first horizontal direction HD1, filling defects and interference between adjacent transistors during the formation of the isolation layer ISO can be reduced.

[0077] However, due to the reduced size of the common active region CA, insufficient process margin becomes available during the formation of the contact CNT connected to the common active region CA. This insufficient process margin can lead to defects where the contact CNT contacts the isolation layer ISO surrounding the common active region CA. Furthermore, when misalignment occurs between the common active region CA and the gate electrode GE, as shown in region E, the isolation layer ISO may be located below the gate electrode GE, potentially causing gate-induced drain leakage (GIDL).

[0078] According to embodiments of this disclosure, the common active region is divided into a third segment extending in an inclined direction, and a first segment and a second segment located on either side of the third segment. The dimension of the third segment in the first horizontal direction is determined to be smaller than the dimensions of the first segment and the second segment in the first horizontal direction. Therefore, the margin of the filling process for forming the isolation layer can be increased to suppress process defects, and the isolation layer can be ensured to have sufficient thickness to suppress interference between adjacent transistors. Furthermore, GIDL can be suppressed by avoiding the isolation layer being located below the gate electrode. Additionally, the margin of the contact process can be improved by connecting the contacts to be connected to the common active region to either the first or second segment of the common active region.

[0079] While detailed embodiments of the present disclosure have been presented herein, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All variations within the equivalent meaning and scope of the claims are included within the scope of the claims.

Claims

1. A semiconductor device, comprising: First transistor; as well as The second transistor shares the active region with the first transistor. The active region includes a common active region, which is located between the channel region of the first transistor and the channel region of the second transistor. From the plan view, the common active area includes: The first segment extends from the channel region of the first transistor along a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; The second segment extends from the channel region of the second transistor along the second horizontal direction; and The third segment connects the first segment and the second segment, and extends along an inclined direction intersecting the first horizontal direction and the second horizontal direction. Wherein, at least a portion of the third segment has a different dimension in the first horizontal direction than each of the first segment and the second segment in the first horizontal direction.

2. The semiconductor device according to claim 1, wherein, At least a portion of the third segment has a dimension in the first horizontal direction that is smaller than the dimension in the first horizontal direction of each of the first segment and the second segment.

3. The semiconductor device according to claim 1, further comprising: A contact point connected to one of the first segment and the second segment of the common active area.

4. The semiconductor device according to claim 1, wherein, The third section is stepped.

5. The semiconductor device according to claim 1, wherein, The third section consists of multiple rectangular segments arranged in a stepped manner.

6. The semiconductor device according to claim 5, wherein, The dimension of each of the plurality of rectangular segments in the first horizontal direction is smaller than the dimension of each of the first segment and the second segment in the first horizontal direction.

7. The semiconductor device according to claim 1, wherein, The third segment includes a first boundary and a second boundary that are opposite to each other in the first horizontal direction. The first boundary includes a first straight portion and a first inclined portion. The first straight portion extends from the first segment along the second horizontal direction, and the first inclined portion connects the first straight portion and the second segment and extends along the inclined direction. The second boundary includes a second inclined portion and a second straight portion, the second inclined portion extending from the first portion along the inclined direction, and the second straight portion connecting the second inclined portion and the second segment and extending along the second horizontal direction.

8. The semiconductor device according to claim 7, wherein, The first inclined portion and the second inclined portion are parallel to each other.

9. The semiconductor device according to claim 1, wherein, Each of the boundaries of the third segment has a straight line shape extending along the inclined direction.

10. The semiconductor device according to claim 1, wherein, The first segment of the common active region has the same dimension in the first horizontal direction as the channel region of the first transistor.

11. The semiconductor device according to claim 1, wherein, The second segment of the common active region has the same dimension in the first horizontal direction as the channel region of the second transistor.

12. A semiconductor device, comprising: The substrate defines the active region; as well as The first gate electrode and the second gate electrode extend along a first horizontal direction on the substrate and are arranged parallel to each other; The active region includes: The common active region, as seen in the plan view, is located between the first gate electrode and the second gate electrode; A first independent active region extends from the common active region along a second horizontal direction and intersects the first gate electrode, wherein the second horizontal direction is perpendicular to the first horizontal direction; and The second independent active region extends from the common active region along the second horizontal direction and intersects with the second gate electrode. The public active area includes: The first segment extends from the first independent active region along the second horizontal direction; The second segment extends from the second independent active region along the second horizontal direction; and The third segment connects the first segment and the second segment, and extends along an inclined direction intersecting the first horizontal direction and the second horizontal direction. Wherein, at least a portion of the third segment has a different dimension in the first horizontal direction than each of the first segment and the second segment in the first horizontal direction.

13. The semiconductor device according to claim 12, wherein, At least a portion of the third segment has a dimension in the first horizontal direction that is smaller than the dimension in the first horizontal direction of each of the first segment and the second segment.

14. The semiconductor device of claim 12, further comprising: A contact point connected to one of the first segment and the second segment.

15. The semiconductor device according to claim 12, wherein, Each of the boundaries of the third segment is stepped.

16. The semiconductor device of claim 12, wherein The third segment includes a first boundary and a second boundary that are opposite to each other in the first horizontal direction. The first boundary includes a first straight portion and a first inclined portion. The first straight portion extends from the first segment along the second horizontal direction, and the first inclined portion connects the first straight portion and the second segment and extends along the inclined direction. The second boundary includes a second inclined portion and a second straight portion, the second inclined portion extending from the first segment along the inclined direction, and the second straight portion connecting the second inclined portion and the second segment and extending along the second horizontal direction.

17. The semiconductor device according to claim 12, wherein, Each of the boundaries of the third segment is a straight line extending along the inclined direction.

18. The semiconductor device according to claim 12, wherein, The first segment of the public active area has the same dimension in the first horizontal direction as the first independent active area.

19. The semiconductor device according to claim 12, wherein, The second segment of the public active area has the same dimension in the first horizontal direction as the second independent active area.

20. A semiconductor device, comprising: Memory cell array; as well as The page buffer circuit is connected to the memory cell array via bit lines; The page buffer circuit includes a first transistor and a second transistor that share a common active region. The active region includes a common active region, which is located between the channel region of the first transistor and the channel region of the second transistor. From the plan view, the common active area includes: The first segment extends from the channel region of the first transistor along a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; The second segment extends from the channel region of the second transistor along the second horizontal direction; and The third segment connects the first segment and the second segment, and extends along an inclined direction intersecting the first horizontal direction and the second horizontal direction. Wherein, at least a portion of the third segment has a dimension in the first horizontal direction smaller than that of each of the first segment and the second segment in the first horizontal direction.

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