Charge-trapping memory, method of manufacturing the same, and reliability test method

Abstract

This invention provides a charge-trapping memory, its fabrication method, and a reliability testing method. The invention employs a sol-gel method to prepare a TiO2 charge-trapping layer and an Al2O3 barrier layer. By precisely controlling the precursor formulation, spin-coating parameters, and annealing process, the thickness and crystal phase of the core functional layer film can be accurately controlled, thereby improving device performance. The fabrication process is simple and has a short cycle time. The reliability testing method of this invention accelerates the aging of the memory by applying a constant voltage stress, making it suitable for rapidly evaluating the performance degradation and reliability of devices under complex stress environments. This invention is the first to use the sol-gel method to prepare all core functional layers of a charge-trapping memory, resulting in a simple and low-cost fabrication process. The testing method can improve testing efficiency by more than 85%, providing a new device fabrication method and reliability testing approach to a certain extent.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and in particular to a charge-trapping memory and its fabrication and reliability testing methods. Background Technology

[0002] Charge-trapped memory (CTM), as a new generation of non-volatile memory, has become a core technology in fields such as 3D NAND Flash and eFlash due to its advantages such as high storage density, strong anti-crosstalk capability, and large scaling potential. TiO2, as a high-dielectric (high-k) charge-trapping layer material, has characteristics such as high charge-trapping density and excellent dielectric properties; however, the complexity of its fabrication process and cost control have always been bottlenecks for its industrial application. Existing TiO2 thin film fabrication methods (such as atomic layer deposition and magnetron sputtering) suffer from problems such as expensive equipment and complex process flows.

[0003] Meanwhile, during long-term program / erase (P / E) cycles, charge trap memories are susceptible to bulk and interface traps due to electric field stress, leading to threshold voltage drift, memory window distortion, increased leakage current, and even time-to-delay breakdown (TDDB), severely impacting long-term device reliability. Existing reliability testing methods often employ single P / E cycles or high-temperature program / erase tests, which have the following drawbacks: 1. They cannot realistically simulate the complex operating conditions of "accumulated electric field stress + repeated write / erase" in actual device applications; 2. The testing cycle is long, making it difficult to quickly assess device lifetime. Therefore, there is an urgent need to develop a simple and low-cost TiO2-based charge trap memory fabrication method, as well as an efficient and accurate reliability testing method to address the shortcomings of existing technologies.

[0004] For the reasons stated above, this application is hereby submitted. Summary of the Invention

[0005] To address the aforementioned technical deficiencies, this invention provides a charge-trapping memory and its fabrication method, as well as a reliability testing method, to simplify the device fabrication process and reduce costs. The reliability testing method significantly improves testing efficiency and provides research ideas for device optimization.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a charge-trapping memory, comprising:

[0008] Substrate;

[0009] A TiO2 charge trapping layer is located on the surface of the substrate, and the TiO2 charge trapping layer does not completely cover the substrate;

[0010] An Al2O3 barrier layer is located on the surface of the TiO2 charge trapping layer away from the substrate;

[0011] The top electrode is located on the surface of the Al2O3 barrier layer away from the substrate;

[0012] The bottom electrode is located on the side surface of the substrate that is not covered by the TiO2 charge trapping layer.

[0013] Preferably, the substrate is a p-Si substrate;

[0014] The top electrode is Au;

[0015] The bottom electrode is a conductive silver paste.

[0016] Preferably, the thickness of the TiO2 charge trapping layer is 50~500 nm;

[0017] The thickness of the Al2O3 barrier layer is 20~100nm;

[0018] The thickness of the top electrode is 30~200nm;

[0019] The thickness of the bottom electrode is 30~200nm.

[0020] Secondly, the present invention also provides a method for fabricating the charge-trapping memory described above, comprising the following steps:

[0021] A TiO2 precursor solution was prepared, coated onto a substrate, pre-annealed, and then annealed to prepare a TiO2 charge trapping layer on the substrate surface.

[0022] An Al2O3 precursor solution was prepared and coated onto a TiO2 charge trapping layer. The solution was then pre-annealed and annealed again to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer.

[0023] A mask is covered on the surface of the Al2O3 barrier layer, and the top electrode is obtained by vapor deposition on the surface of the Al2O3 barrier layer;

[0024] A conductive silver paste is coated on the side of the substrate that is not covered by the TiO2 charge trapping layer to obtain the bottom electrode.

[0025] Preferably, the method for preparing the TiO2 precursor solution is as follows:

[0026] Tetrabutyl titanate was dissolved in 2-methoxyethanol, and then acetylacetone and glycerol were added and stirred to obtain a TiO2 precursor solution.

[0027] The volume ratio of tetrabutyl titanate, 2-methoxyethanol, acetylacetone and glycerol is (1.5~1.8):(8~12):(0.4~0.6):(0.3~0.5);

[0028] The method for preparing the Al2O3 precursor solution is as follows:

[0029] Aluminum isopropoxide was mixed with ethanol, concentrated nitric acid and acetylacetone were added, and the mixture was stirred at 70-80°C to obtain an Al2O3 precursor solution.

[0030] The mass-to-volume ratio of aluminum isopropoxide, ethanol, concentrated nitric acid, and acetylacetone is (3.8~4.2) g:(90~110) mL:(3~5) mL:(2~3) mL; the mass fraction of the concentrated nitric acid is 65~68%.

[0031] Preferably, the TiO2 precursor is spin-coated onto the substrate, then pre-annealed, and then annealed to prepare a TiO2 charge trapping layer on the substrate surface.

[0032] The spin coating parameters are as follows: spin rotation speed of 3000~3500 rpm and acceleration of 1000~1100 rad / s. 2 The spin coating time is 30~40 s;

[0033] The pre-annealing temperature is 100~110℃ and the time is 10~15min;

[0034] The annealing temperature is 500~800℃ and the time is 120~130min.

[0035] Preferably, the TiO2 precursor is spin-coated onto the substrate, then pre-annealed, and the spin-coating and pre-annealing steps are repeated before annealing, wherein the spin-coating and pre-annealing are repeated 1 to 4 times.

[0036] Preferably, the Al2O3 precursor solution is spin-coated onto the TiO2 charge trapping layer, then pre-annealed, and then annealed to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer.

[0037] The spin coating parameters are as follows: spin rotation speed of 3000~3500 rpm and acceleration of 1000~1100 rad / s. 2 The spin coating time is 30~40 s;

[0038] The pre-annealing temperature is 150~160℃ and the time is 15~20min;

[0039] The annealing temperature is 500~600℃ and the time is 5~120min.

[0040] Preferably, the Al2O3 precursor solution is spin-coated onto the TiO2 charge trapping layer, and then pre-annealed. The spin-coating and pre-annealing steps are repeated 1 to 4 times.

[0041] Thirdly, the present invention also provides a reliability testing method for the charge-trapping memory described above or the charge-trapping memory prepared by the described method, comprising the following steps:

[0042] A voltage is applied to the top electrode of the charge-trapping memory. After the voltage is applied, the charge-trapping memory is programmed and erased.

[0043] The charge-trapping memory, its fabrication method, and its reliability testing method of the present invention have the following advantages compared with the prior art:

[0044] 1. This invention uses the sol-gel method to prepare TiO2 charge trapping layer and Al2O3 barrier layer. By precisely controlling the precursor formula, spin coating parameters and annealing process, the thickness and crystal phase of the core functional layer film of the device can be precisely controlled, thereby improving the device performance. Moreover, the preparation process is simple and the process cycle is short.

[0045] 2. The reliability testing method for charge-trapping memory of the present invention adopts a "CVS+P / E cycle" coupled stress mode, which realistically simulates the complex working conditions of electric field stress accumulation and repeated erasing and writing in actual device applications, making the test results more valuable for reference; the accelerated aging effect is significant, reducing the number of cycles required to reach the same degree of degradation by more than 85% compared with the traditional single P / E cycle test, greatly shortening the test cycle; combined with multi-frequency CV / GV testing, the evolution law of volume traps and interface traps can be accurately distinguished, providing a direct theoretical basis for device structure optimization. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the charge-trapping memory of the present invention;

[0048] Figure 2 The image shown is a scanning electron microscope image of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Embodiment 1 of the present invention.

[0049] Figure 3The CV test curves are for devices prepared by the TiO2 charge trapping layer in Examples 2-5 at different annealing temperatures.

[0050] Figure 4 These are scanning electron microscope images of the TiO2 charge trapping layer films in Examples 2-5 at different annealing temperatures.

[0051] Figure 5 The CV test curves are for devices prepared with different spin-coating numbers of TiO2 charge trapping layers in Examples 1 and 6-8.

[0052] Figure 6 The CV test curves are for devices prepared with Al2O3 barrier layers at different annealing times in Examples 1 and 9-11.

[0053] Figure 7 The CV curve of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 12 under P / E cycling;

[0054] Figure 8 This refers to the storage window data of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 12 under P / E cycles.

[0055] Figure 9 The CV curve of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 under constant voltage stress and P / E cyclic coupling is shown.

[0056] Figure 10 This refers to the storage window data of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 under constant voltage stress and P / E cyclic coupling.

[0057] Figure 11 The CV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 are shown before and after constant voltage stress and P / E cyclic coupling.

[0058] Figure 12 The IV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 are shown before and after constant voltage stress and P / E cyclic coupling.

[0059] Figure 13 The CV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 14 are shown when constant voltage stress and P / E cyclic coupling are applied for different durations. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0061] It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". Various embodiments of the present invention may exist in the form of a range; it should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a rigid limitation on the scope of the invention; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single digits within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. Additionally, whenever a numerical range is indicated herein, it means including any referenced number (fraction or integer) within the indicated range.

[0062] This application provides a charge-trapping memory, including:

[0063] Substrate 1;

[0064] TiO2 charge trapping layer 2 is located on the surface of substrate 1, and TiO2 charge trapping layer 2 does not completely cover substrate 1;

[0065] Al2O3 barrier layer 3 is located on the surface of TiO2 charge trapping layer 2 away from substrate 1;

[0066] Top electrode 4 is located on the surface of Al2O3 barrier layer 3 away from substrate 1;

[0067] Bottom electrode 5 is located on the side surface of substrate 1 that is not covered by TiO2 charge trapping layer 2.

[0068] like Figure 1As shown, the charge-trapping memory of the present invention includes: a substrate 1, a TiO2 charge-trapping layer 2, an Al2O3 barrier layer 3, a top electrode 4, and a bottom electrode 5; wherein, the TiO2 charge-trapping layer 2 is located on the surface of the substrate 1, and the TiO2 charge-trapping layer 2 does not completely cover the substrate 1, that is, one side of the surface of the substrate 1 is covered by the TiO2 charge-trapping layer 2, and the other side is not covered by the TiO2 charge-trapping layer 2; the Al2O3 barrier layer 3 is located on the surface of the TiO2 charge-trapping layer 2, the top electrode 4 is located on the surface of the Al2O3 barrier layer 3, and the bottom electrode 5 is located on the side of the substrate 1 that is not covered by the TiO2 charge-trapping layer 2.

[0069] In some embodiments, substrate 1 is a p-Si substrate, i.e., a p-type single-crystal silicon substrate, and the crystal orientation of the p-Si substrate is as follows: <100> Its resistivity is 1~10 Ω·cm.

[0070] The top electrode 4 is made of Au, and the top electrodes are arranged in an array on the surface of the Al2O3 barrier layer 3.

[0071] The bottom electrode 5 is made of conductive silver paste.

[0072] In some embodiments, the thickness of the TiO2 charge trapping layer 2 is 50~500 nm;

[0073] The thickness of the Al2O3 barrier layer is 20~100nm;

[0074] The thickness of the top electrode is 30~200nm;

[0075] The thickness of the bottom electrode is 30~200nm.

[0076] The charge-trapping memory of the present invention is an Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory.

[0077] Based on the same inventive concept, the present invention also provides a method for fabricating the above-mentioned charge-trapping memory, comprising the following steps:

[0078] S1. Prepare a TiO2 precursor solution, coat the TiO2 precursor solution onto the substrate, pre-anneal and then anneal to prepare a TiO2 charge trapping layer on the substrate surface.

[0079] S2. Prepare an Al2O3 precursor solution, coat the Al2O3 precursor solution onto the TiO2 charge trapping layer, pre-anneal and then anneal to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer.

[0080] S3. Cover the surface of the Al2O3 barrier layer with a mask, and deposit the top electrode on the surface of the Al2O3 barrier layer by vapor deposition;

[0081] S4. Coat the substrate with conductive silver paste on the side of the substrate that is not covered by the TiO2 charge trapping layer to obtain the bottom electrode.

[0082] In some embodiments, the TiO2 precursor solution is prepared as follows:

[0083] Tetrabutyl titanate was dissolved in 2-methoxyethanol, and then acetylacetone and glycerol (i.e., glycerol) were added and stirred to obtain a TiO2 precursor solution.

[0084] The volume ratio of tetrabutyl titanate, 2-methoxyethanol, acetylacetone and glycerol is (1.5~1.8):(8~12):(0.4~0.6):(0.3~0.5).

[0085] In some embodiments, the Al2O3 precursor solution is prepared as follows:

[0086] Aluminum isopropoxide was mixed with ethanol, concentrated nitric acid and acetylacetone were added, and the mixture was stirred at 70-80°C to obtain an Al2O3 precursor solution.

[0087] The mass-to-volume ratio of aluminum isopropoxide, ethanol, concentrated nitric acid, and acetylacetone is (3.8~4.2) g:(90~110) mL:(3~5) mL:(2~3) mL; the mass fraction of concentrated nitric acid is 65~68%.

[0088] In some embodiments, a TiO2 precursor solution is spin-coated onto a substrate, then pre-annealed, and then annealed to prepare a TiO2 charge trapping layer on the substrate surface.

[0089] The spin coating parameters are as follows: spin rotation speed of 3000~3500 rpm and acceleration of 1000~1100 rad / s. 2 (Angular acceleration, in radians squared per second (rad / s²)), spin coating time is 30~40 s;

[0090] The pre-annealing temperature is 100~110℃ and the time is 10~15min;

[0091] The annealing temperature is 500~800℃ and the time is 120~130min.

[0092] In some embodiments, a TiO2 precursor is spin-coated onto a substrate, then pre-annealed, and the spin-coating and pre-annealing steps are repeated before annealing, wherein the spin-coating and pre-annealing are repeated 1 to 4 times.

[0093] In some embodiments, an Al2O3 precursor solution is spin-coated onto a TiO2 charge trapping layer, then pre-annealed, and then annealed to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer.

[0094] The spin coating parameters are as follows: spin rotation speed of 3000~3500 rpm and acceleration of 1000~1100 rad / s. 2 The spin coating time is 30~40 s;

[0095] The pre-annealing temperature is 150~160℃ and the time is 15~20min;

[0096] The annealing temperature is 500~600℃ and the time is 5~120min.

[0097] In some embodiments, an Al2O3 precursor solution is spin-coated onto a TiO2 charge trapping layer, followed by pre-annealing. The spin-coating and pre-annealing steps are repeated 1 to 4 times.

[0098] In some embodiments, Au is deposited as the top electrode using a vacuum deposition apparatus, and the specific controlled parameters are: deposition power of 180~200 W and deposition rate of Au of 0.1~0.3 nm / s.

[0099] In some embodiments, a conductive silver paste is coated on the side of the substrate that is not covered by the TiO2 charge trapping layer to obtain a bottom electrode, wherein the resistance of the conductive silver paste is ≤0.01 Ω.

[0100] In some embodiments, before coating the TiO2 precursor solution onto the substrate, the substrate is further cleaned, specifically by ultrasonically cleaning the substrate with acetone, anhydrous ethanol, and deionized water for 15-20 minutes each.

[0101] This invention uses the sol-gel method to prepare a TiO2 charge trapping layer and an Al2O3 barrier layer. By precisely controlling the precursor formulation, spin coating parameters and annealing process, the thickness and crystal phase of the core functional layer film of the device can be precisely controlled, thereby improving the device performance. Moreover, the preparation process is simple and has a short cycle time.

[0102] Based on the same inventive concept, the present invention also provides a reliability testing method for the above-described charge-trapping memory or the charge-trapping memory prepared by the above-described preparation method, comprising:

[0103] A voltage is applied to the top electrode of the charge trapping memory and held for a certain period of time to accumulate electrical stress. The magnitude of the electrical stress is controlled by the application time, such as 1~10s. After the voltage is applied, the charge trapping memory is programmed and erased.

[0104] In some embodiments, the applied voltage stress is a constant voltage stress, or the stress parameters can be adjusted by adjusting the scanning voltage (e.g., -5 to -10V) and the application time.

[0105] Specifically, the reliability testing method of this invention simulates a complex stress environment through the coupling effect of "constant voltage stress (CVS) and P / E cycle," and analyzes the degradation mechanism through test analysis. Specifically, it is described as follows: Before performing programming and erasing operations, a constant voltage is applied to the device to accumulate electrical stress. The magnitude of the electrical stress is controlled by the application time. After the electrical stress is applied, a programming and erasing operation is performed. The steps are as follows:

[0106] Step 1: Setting up the test equipment:

[0107] A semiconductor parameter analyzer (Keithley B1500A) was used with a probe station to connect the probes to the top and bottom electrodes of the memory to ensure a stable electrical connection.

[0108] Step 2: Coupled stress aging treatment:

[0109] (1) Constant voltage stress (CVS) application: A set constant high voltage is applied to the memory gate (Au top electrode) for 1~10s to achieve rapid accumulation of electrical stress;

[0110] (2) P / E cycle execution: After removing the constant voltage, a complete P / E test is immediately performed (i.e., P / E test is programming / erase test); the specific programming and erasure principles are as follows: Programming: Apply a forward / reverse bias voltage between the Au top electrode and the bottom electrode, so that the charge carriers pass through the Al2O3 barrier layer through the tunneling effect, are injected and trapped in the trap sites of the TiO2 charge trapping layer, the device forms a programmed state, and the corresponding capacitance-voltage (CV) curve shifts; Erasure: Apply a bias voltage opposite to the programming direction, so that the charge carriers in the TiO2 trapping layer are detrapped and tunnel back to the substrate / electrode, the device returns to the erased state, and the CV curve shifts back;

[0111] (3) Cyclic aging: Repeat steps (1) and (2) to perform a total of 1 to 200 combined P / E cycle tests to complete the accelerated aging of the device. Repeat the P / E cycle operation to simulate the repeated read and write process in actual memory applications. During the cycle, monitor the CV curve shape, memory window size, and leakage current changes to evaluate the degree of device aging and degradation.

[0112] The reliability testing method for charge-trapping memory of the present invention adopts the "CVS+P / E cycle" coupled stress mode, which truly simulates the complex working conditions of electric field stress accumulation and repeated erasing and writing in actual device applications, making the test results more valuable for reference; the accelerated aging effect is significant, and compared with the traditional single P / E cycle test, the number of cycles required to reach the same degree of degradation is reduced by more than 85%, greatly shortening the test cycle.

[0113] The following further illustrates the charge-trapping memory and its fabrication and reliability testing methods using specific embodiments. This section further describes the content of the invention in conjunction with specific embodiments, but should not be construed as limiting the invention. Unless otherwise specified, the technical means used in the embodiments are conventional means well known to those skilled in the art. Unless otherwise specified, the reagents, methods, and equipment used in the present invention are conventional reagents, methods, and equipment in the art.

[0114] In the following examples, the p-Si substrate was purchased from Hefei Kejing Materials Technology Co., Ltd.;

[0115] The conductive silver paste is specifically Kingstar K-818 conductive silver paste.

[0116] Example 1

[0117] This embodiment provides a charge-trapping memory, including:

[0118] Substrate;

[0119] A TiO2 charge trapping layer is located on the substrate surface, and the TiO2 charge trapping layer does not completely cover the substrate;

[0120] An Al2O3 barrier layer is located on the surface of the TiO2 charge trapping layer away from the substrate.

[0121] The top electrode is located on the surface of the Al2O3 barrier layer away from the substrate.

[0122] The bottom electrode is located on the side of the substrate that is not covered by the TiO2 charge trapping layer.

[0123] The top electrode is Au, and the top electrodes are arranged in an array on the surface of the Al2O3 barrier layer with a thickness of 40 nm.

[0124] The bottom electrode is a conductive silver paste with a thickness of 100 nm;

[0125] The TiO2 charge trapping layer has a thickness of 110 nm.

[0126] An Al2O3 barrier layer with a thickness of 55 nm;

[0127] The method for fabricating the above-mentioned charge-trapping memory includes the following steps:

[0128] S1. The p-Si substrate is ultrasonically cleaned for 15 min each with acetone, anhydrous ethanol and deionized water. After ultrasonic cleaning, it is placed in a drying oven for drying and ready for use.

[0129] S2. Preparation of TiO2 precursor solution: Dissolve 1.702 mL of tetrabutyl titanate in 10 mL of 2-methoxyethanol, then add 0.514 mL of acetylacetone and 0.4 mL of glycerol, stir on a magnetic stirrer for 3 h, and after mixing, obtain TiO2 precursor solution.

[0130] The TiO2 precursor solution was spin-coated onto a p-Si substrate, and the spin-coated sample was pre-annealed on a 100°C hot plate for 10 min. To achieve a TiO2 charge trapping layer thickness of 110 nm, the spin-coating and pre-annealing operations were repeated three times. The spin-coating parameters were: spin speed of 3000 rpm and acceleration of 1000 rad / s. 2 The spin coating time is 30 seconds.

[0131] Finally, the pre-annealed sample was placed in a muffle furnace for annealing at a temperature of 600℃ for 2 hours to prepare a TiO2 charge trapping layer on the p-Si substrate surface.

[0132] S3. Preparation of Al2O3 precursor solution: Mix 4.08 g aluminum isopropoxide with 100 mL anhydrous ethanol, add 4 mL concentrated nitric acid (68% by mass) and 2.5 mL acetylacetone, and stir in an 80℃ constant temperature oil bath stirrer for 1 h. After mixing, the Al2O3 precursor solution is obtained.

[0133] The Al2O3 precursor solution was spin-coated onto the TiO2 charge trapping layer, and the spin-coated sample was placed on a 150℃ hot plate for 15 min of pre-annealing. To achieve an Al2O3 barrier layer thickness of 55 nm, the spin-coating and pre-annealing operations were repeated twice. The spin-coating parameters were: spin speed of 3000 rpm and acceleration of 1000 rad / s. 2 The spin coating time is 30 seconds.

[0134] Finally, the pre-annealed sample was placed in a muffle furnace for annealing at a temperature of 500 °C for 5 min, so as to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer.

[0135] S4. Cover the surface of the Al2O3 barrier layer with a mask, load Au particles into the tungsten boat of the coating instrument, and vapor deposit a 40 nm thick Au top electrode on the surface of the Al2O3 barrier layer. The vapor deposition power is 200 W and the Au vapor deposition rate is 0.3 nm / s.

[0136] S5. Coat the surface of the p-Si substrate with conductive silver paste on the side not covered by the TiO2 charge trapping layer to obtain a bottom electrode with a thickness of 100 nm.

[0137] Example 2 (Charge trapping layer annealed at 500°C)

[0138] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters are different in that the annealing temperature of the TiO2 charge-trapping layer is 500℃, the thickness of the TiO2 charge-trapping layer is 110 nm, the thickness of the Al2O3 barrier layer is 55 nm, and the annealing time is 120 min.

[0139] Example 3 (Charge trapping layer annealed at 600°C)

[0140] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters are different in that the annealing temperature of the TiO2 charge-trapping layer is 600℃, the thickness of the TiO2 charge-trapping layer is 110 nm, the thickness of the Al2O3 barrier layer is 55 nm, and the annealing time is 120 min.

[0141] Example 4 (Charge trapping layer annealed at 700°C)

[0142] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters are different in that the annealing temperature of the TiO2 charge-trapping layer is 700℃, the thickness of the TiO2 charge-trapping layer is 110 nm, the thickness of the Al2O3 barrier layer is 55 nm, and the annealing time is 120 min.

[0143] Example 5 (Charge trapping layer annealed at 800°C)

[0144] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters are different in that the annealing temperature of the TiO2 charge-trapping layer is 800℃, the thickness of the TiO2 charge-trapping layer is 110 nm, the thickness of the Al2O3 barrier layer is 55 nm, and the annealing time is 120 min.

[0145] Example 6 (1 L charge trapping layer)

[0146] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that, in order to achieve a TiO2 charge-trapping layer thickness of 50 nm, the above spin-coating and pre-annealing operations are performed once, the Al2O3 barrier layer thickness is 55 nm, and the annealing time is 5 min.

[0147] Example 7 (2 L charge trapping layer)

[0148] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that, in order to achieve a TiO2 charge-trapping layer thickness of 80 nm, the above spin-coating and pre-annealing operations are performed twice, the Al2O3 barrier layer thickness is 55 nm, and the annealing time is 5 min.

[0149] Example 8 (4 L charge trapping layer)

[0150] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that, in order to achieve a TiO2 charge-trapping layer thickness of 140 nm, the above spin-coating and pre-annealing operations are performed four times, the Al2O3 barrier layer thickness is 55 nm, and the annealing time is 5 min.

[0151] Example 9 (Block layer annealing time 30 min)

[0152] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that the annealing time of the Al2O3 barrier layer in this embodiment is 30 min, and the thickness of the Al2O3 barrier layer is 55 nm.

[0153] Example 10 (Block layer annealing time 60 min)

[0154] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that the annealing time of the Al2O3 barrier layer in this embodiment is 60 min, and the thickness of the Al2O3 barrier layer is 55 nm.

[0155] Example 11 (Block layer annealing time 120 min)

[0156] This embodiment provides a method for fabricating a charge-trapping memory. Similar to Embodiment 1, the process parameters differ in that the annealing time of the Al2O3 barrier layer in this embodiment is 120 min, and the thickness of the Al2O3 barrier layer is 55 nm.

[0157] Example 12

[0158] Device P / E Cyclic Testing under Stress-Free Coupling

[0159] The fabrication method of the test device used in this embodiment is completely consistent with that in Embodiment 1. In this embodiment, conventional stress-free P / E cycle testing is performed on the device. Conventional stress-free P / E cycle testing is a traditional benchmark test method for reliability assessment of charge-trap memory. Its core feature is that during the test, the device is aged only by repeatedly performing programming and erasing operations, without applying additional constant voltage stress (CVS) or other accelerated aging methods. The specific operation is as follows:

[0160] (1) Test platform setup: A semiconductor parameter analyzer (Keithley B1500A) was used with a probe station. The probes were reliably connected to the top and bottom electrodes to ensure stable electrical contact. The test environment was kept at room temperature to avoid temperature stress from interfering with the test results.

[0161] (2) Test parameter settings: The programming / erasing scan voltage range is set to ±1~±8 V, the scan rate adopts the conventional test standard, there is no additional voltage stress superposition, and the number of cycles is set to 2600 times; the capacitance-voltage (CV) test curve is the core, and the current-voltage (IV) characteristic data are recorded synchronously.

[0162] (3) Cycle interval setting: After a single P / E cycle is completed, no additional resting or stress application is required. The next cycle can be started directly to ensure that the test process is only affected by the electric field of the P / E operation itself.

[0163] Example 13

[0164] Cyclic P / E test of the device under constant voltage stress coupling (200 cycles)

[0165] The fabrication method of the test device used in this embodiment is completely consistent with that in Embodiment 1. This embodiment performs P / E cycle testing on the device under constant voltage stress (CVS) coupling. The testing method in this embodiment is basically the same as that in Embodiment 2; the differences lie only in the setting of test parameters and the setting of the cycle interval. The specific differences are as follows:

[0166] (1) Test parameter settings: The programming / erasing scan voltage range is set to ±1~±8 V, the scan rate adopts the conventional test standard, and an additional -8 V constant voltage stress is superimposed before each P / E cycle is executed. The number of cycles is set to 200. The current-voltage (IV) characteristic data is recorded synchronously with the CV test curve as the core.

[0167] (2) Cycle interval setting: After a single P / E cycle is completed, a constant voltage stress application step with a preset duration is added. After the constant voltage stress reaches the set duration of 10s, the next P / E cycle is started, forming a continuous test sequence of "CVS+P / E cycle".

[0168] Example 14

[0169] Single P / E test of devices under constant voltage stress coupling

[0170] The fabrication method of the test device used in this embodiment is exactly the same as that in Embodiment 1. This embodiment focuses on performing a single P / E test under constant voltage stress coupling on the device. The test method in this embodiment is basically the same as that in Embodiment 3. The core difference is that this embodiment only performs a single P / E cycle test. The specific test timing design is as follows: First, a constant voltage (-8V) stress application step with a preset duration is set. After the constant voltage stress reaches the preset duration, the single P / E cycle operation is started, forming a test timing sequence of "CVS + single P / E cycle". This embodiment tests the CV test curves of the device under different stress durations by changing the preset application duration of the above constant voltage stress (duration is 0~10s).

[0171] Performance testing

[0172] Figure 2 These are scanning electron microscope images of the charge-trapping memory prepared in Example 1, from... Figure 2 As can be seen, the thickness of the TiO2 charge trapping layer in the device is 110 nm, the thickness of the Al2O3 barrier layer is 55 nm, and the thickness of the Au top electrode is 40 nm. Furthermore, it can be observed that the functional layers are deposited uniformly, with clear and distinct interlayer boundaries.

[0173] Figure 3 The CV test curves are for charge-trapping memory prepared by TiO2 charge-trapping layers in Examples 2-5 at different annealing temperatures. Figure 3 Example 5 corresponds to 800℃, Example 4 corresponds to 700℃, Example 2 corresponds to 500℃, and Example 3 corresponds to 600℃.

[0174] Depend on Figure 3 It can be seen that the storage window of the device is larger after annealing at 500℃ and 600℃. At 500℃, the curve is severely distorted due to the presence of more interface states. Therefore, 600℃ is the optimal annealing temperature for the TiO2 charge trapping layer.

[0175] Figure 4 These are scanning electron microscope images of the TiO2 charge trapping layer films in Examples 2-5 at different annealing temperatures. Figure 3 Example 5 corresponds to 800℃, Example 4 corresponds to 700℃, Example 2 corresponds to 500℃, and Example 3 corresponds to 600℃.

[0176] Depend on Figure 4 As can be seen, the degree of crystallization gradually increases with the continuous increase of annealing temperature, and no obvious grains are present when annealing at 500℃ and 600℃.

[0177] Figure 5 The CV test curves are for charge-trapping memory prepared by TiO2 charge-trapping layers with different spin-coating numbers in Examples 1, 6-8. Figure 5 In the middle, 4L corresponds to Example 8, 2L corresponds to Example 7, 3L corresponds to Example 1, and 1L corresponds to Example 6.

[0178] Depend on Figure 5 As can be seen, the storage window of the device increases with the increase of the charge trapping layer thickness. However, at 4 L, the film thickness is too large, leading to film cracking, so 3 L is the optimal thickness.

[0179] Figure 6 The CV test curves are for the charge-trapping memory prepared by Al2O3 barrier layers in Examples 1 and 9-11 at different annealing times. Figure 6 5 min corresponds to Example 1, 30 min corresponds to Example 9, 60 min corresponds to Example 10, and 120 min corresponds to Example 11. Figure 6 5min in Figure 5 In both cases, 3L corresponds to Example 1. The storage windows of the two are similar, both being approximately 5V, while the capacitance on the vertical axis differs slightly, which is within the experimental error range.

[0180] Depend on Figure 6 It can be seen that the device's storage window is largest when the annealing time is 5 minutes.

[0181] Figure 7 The CV curve of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 12 is shown below under P / E cycles. Figure 7 As can be seen, after long-term P / E cycles, the consistency of the device's CV curve significantly decreases, and the overall shape of the memory window undergoes significant distortion. Specifically, the curve shifts slightly to the right, and the slope of the curve decreases significantly before and after the cycle, exhibiting obvious degradation. Furthermore, Figure 8 This refers to the storage window data of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 12 under P / E cycles. Figure 8 As can be seen, the device storage window exhibits a trend of "first increasing and then decreasing". The main reason is likely the oxide layer degradation induced by repeated P / E cycles. The degraded oxide layer generates a large number of defects, which in turn form leakage paths, leading to undesirable tunneling and leakage transport of charge carriers.

[0182] Figure 9 The CV curve of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 is shown below under constant voltage stress and P / E cyclic coupling. Figure 9 As can be seen, the trend of the CV curve under the coupled stress test is consistent with that of the stress-free P / E cycle test, both showing a significant decrease in the consistency of the CV curve and a significant distortion in the overall shape of the memory window. Specifically, the programmed state curve shifts slightly to the right, and the slope of the curves before and after the cycle decreases significantly. This phenomenon indicates that the device degradation effect under 200 "CVS+P / E" coupled cycles in this embodiment is comparable to the degradation effect under stress-free conditions of more than 2000 P / E cycles, thus confirming that the coupled stress test method significantly improves the efficiency of device reliability testing. Furthermore, Figure 10 This refers to the storage window data of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 under constant voltage stress and P / E cyclic coupling. Figure 10 As can be seen, the trend of the device's storage window change is the same as that when no constant voltage stress is applied, and the degradation effect that can be achieved in 200 cycles is comparable to that in about 1600 cycles when no stress is applied. This indicates that the reliability test efficiency can be improved by about 85% when a constant voltage stress is applied.

[0183] Figure 11 The figure shows the CV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 before and after constant voltage stress and P / E cyclic coupling. As can be seen from the figure, the storage window is small and the curve shape is relatively regular when no stress is applied (Th=0 s). After applying constant voltage stress (Th=10 s), the storage window increases and the curve distortion is severe, especially the slope of the curve, which differs significantly from the stress-free state. After removing the constant voltage stress, the storage window size does not change much, but the curve distortion is significantly alleviated, indicating that the degradation induced by constant voltage stress is irreversible.

[0184] Figure 12 The figure shows the IV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 13 before and after constant voltage stress and P / E cycle coupling. As can be seen from the figure, the leakage current increases significantly after P / E cycling. This phenomenon is basically consistent with the characteristics of stress-induced leakage current (SILC) or soft breakdown (SB) during oxide layer breakdown. If the stress continues, the device may further undergo hard breakdown (HB) after experiencing soft breakdown.

[0185] Figure 13The table shows the CV curves of the Au / Al2O3 / TiO2 / p-Si structure charge-trapping memory in Example 14 under constant voltage stress and P / E cyclic coupling at different times. It can be observed that the slope of the CV curve in the inversion region changes with stress applied for different times; the slope of the upper half of the curve in the inversion region gradually decreases with increasing time. This indicates that applying stress for different times does indeed cause varying degrees of degradation.

[0186] It is understood that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The above are merely preferred embodiments of this application, and only specifically describe the technical principles of this application. These descriptions are only for explaining the principles of this application and should not be construed as limiting the scope of protection of this application in any way. Based on this explanation, any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application, as well as other specific embodiments of this application that can be conceived by those skilled in the art without creative effort, should be included within the scope of protection of this application.

Claims

1. A charge-trap memory, comprising: include: Substrate; A TiO2 charge trapping layer is located on the surface of the substrate, and the TiO2 charge trapping layer does not completely cover the substrate; An Al2O3 barrier layer is located on the surface of the TiO2 charge trapping layer away from the substrate; The top electrode is located on the surface of the Al2O3 barrier layer away from the substrate; The bottom electrode is located on the side surface of the substrate that is not covered by the TiO2 charge trapping layer.

2. The charge-trap memory of claim 1, wherein, The substrate is a p-Si substrate; The top electrode is Au; The bottom electrode is a conductive silver paste.

3. The charge-trap memory of claim 1, wherein, The thickness of the TiO2 charge trapping layer is 50~500nm; The thickness of the Al2O3 barrier layer is 20~100nm; The thickness of the top electrode is 30~200nm; The thickness of the bottom electrode is 30~200nm.

4. A method of manufacturing a charge-trap memory device as claimed in any one of claims 1 to 3, characterized in that Includes the following steps: A TiO2 precursor solution was prepared, coated onto a substrate, pre-annealed, and then annealed to prepare a TiO2 charge trapping layer on the substrate surface. An Al2O3 precursor solution was prepared and coated onto a TiO2 charge trapping layer. The solution was then pre-annealed and annealed again to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer. A mask is covered on the surface of the Al2O3 barrier layer, and the top electrode is obtained by vapor deposition on the surface of the Al2O3 barrier layer; A conductive silver paste is coated on the side of the substrate that is not covered by the TiO2 charge trapping layer to obtain the bottom electrode.

5. The method of producing a charge trapping memory as claimed in claim 4, wherein, The method for preparing the TiO2 precursor solution is as follows: Tetrabutyl titanate was dissolved in 2-methoxyethanol, and then acetylacetone and glycerol were added and stirred to obtain a TiO2 precursor solution. The volume ratio of tetrabutyl titanate, 2-methoxyethanol, acetylacetone and glycerol is (1.5~1.8):(8~12):(0.4~0.6):(0.3~0.5); The method for preparing the Al2O3 precursor solution is as follows: Aluminum isopropoxide was mixed with ethanol, concentrated nitric acid and acetylacetone were added, and the mixture was stirred at 70-80°C to obtain an Al2O3 precursor solution. The mass-to-volume ratio of aluminum isopropoxide, ethanol, concentrated nitric acid, and acetylacetone is (3.8~4.2) g:(90~110) mL:(3~5) mL:(2~3) mL; the mass fraction of the concentrated nitric acid is 65~68%.

6. The method of producing a charge-trapped memory according to claim 4, wherein TiO2 precursor was spin-coated onto a substrate, then pre-annealed, and then annealed to prepare a TiO2 charge trapping layer on the substrate surface. The spin coating parameters are as follows: the spin coating speed is 3000-3500 rpm, the acceleration is 1000-1100 rad / s, and the spin coating time is 30-40 s. 2 , The pre-annealing temperature is 100~110℃ and the time is 10~15min; The annealing temperature is 500~800℃ and the time is 120~130min.

7. The method for fabricating a charge-trapping memory as described in claim 6, characterized in that, The TiO2 precursor is spin-coated onto the substrate and then pre-annealed. The spin-coating and pre-annealing steps are repeated 1 to 4 times.

8. The method for fabricating a charge-trapping memory as described in claim 4, characterized in that, An Al2O3 precursor solution was spin-coated onto a TiO2 charge trapping layer, followed by pre-annealing and then annealing to prepare an Al2O3 barrier layer on the surface of the TiO2 charge trapping layer. The spin coating parameters are as follows: the spin coating speed is 3000-3500 rpm, the acceleration is 1000-1100 rad / s, and the spin coating time is 30-40 s. 2 , The pre-annealing temperature is 150~160℃ and the time is 15~20min; The annealing temperature is 500~600℃ and the time is 5~120min.

9. The method for fabricating a charge-trapping memory as described in claim 8, characterized in that, The Al2O3 precursor solution was spin-coated onto the TiO2 charge trapping layer, and then pre-annealed. The spin-coating and pre-annealing steps were repeated 1 to 4 times.

10. A reliability testing method for a charge-trapping memory as described in any one of claims 1 to 3 or a charge-trapping memory prepared by the preparation method as described in any one of claims 4 to 9, characterized in that, Includes the following steps: A voltage is applied to the top electrode of the charge-trapping memory. After the voltage is applied, the charge-trapping memory is programmed and erased.

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