storage device

Abstract

Embodiments of the present invention relate to a storage device. The storage device of the embodiment includes a storage cell comprising a switching layer between a first conductive layer and a third conductive layer, and a resistance-changing layer between the third conductive layer and a second conductive layer. The switching layer comprises: a first oxide selected from Mg, Y, La, Ce, Zr, Hf, Al, Ti, and Si; a second element selected from Zn, Ga, In, Sn, and Bi; a third element selected from P, As, Sb, Bi, S, Se, and Te; and a fourth element selected from the group consisting of V, Nb, Ta, Cr, B, Ga, and Si. The switching layer includes a first region, a second region, and a third region, with the first region disposed between the second and third regions. The first region contains the first oxide, and the second and third regions contain a fourth oxide of the fourth element.

Description

Technical Field

[0001] Embodiments of the present invention relate to a storage device. Background Technology

[0002] As a high-capacity non-volatile storage device, there is a cross-point type 2-terminal storage device. The storage cells of the cross-point type 2-terminal storage device are easy to miniaturize and highly integrate.

[0003] The storage cells of a cross-point type two-terminal storage device have, for example, a resistance changing element and a switching element. By having a switching element in the storage cell, current flowing to storage cells other than the selected storage cell can be suppressed.

[0004] Switching elements are required to have excellent characteristics such as low leakage current, high on-state current, and high reliability. Summary of the Invention

[0005] The storage device of the embodiment includes a storage unit, the storage unit comprising: a first conductive layer; a second conductive layer; a third conductive layer disposed between the first conductive layer and the second conductive layer; a switching layer disposed between the first conductive layer and the third conductive layer; and a resistance changing layer disposed between the third conductive layer and the second conductive layer; the switching layer comprising: a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si); at least one second element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), different from the first element; and at least one second element selected from the group consisting of phosphorus (…) different from the first element and the second element… At least one third element selected from the group consisting of P, arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te); and at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), different from the first, second, and third elements; the switching layer includes a first region, a second region, and a third region in a cross section parallel to a first direction connecting the first conductive layer and the second conductive layer, wherein in a second direction perpendicular to the first direction of the cross section, the first region is disposed between the second region and the third region, the first region contains the first oxide, and the second and third regions contain a fourth oxide of the fourth element.

[0006] According to this embodiment, a storage device having a switching element with excellent characteristics can be provided. Attached Figure Description

[0007] Figure 1 This is a block diagram of the storage device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view of the storage unit of the storage device according to the first embodiment.

[0009] Figure 3 It is a graph representing the standard formation energy of oxides of elements.

[0010] Figure 4 This is a schematic cross-sectional view showing a method for manufacturing a storage cell of the storage device according to the first embodiment.

[0011] Figure 5 This is a schematic cross-sectional view showing a method for manufacturing a storage cell of the storage device according to the first embodiment.

[0012] Figure 6 This is a schematic cross-sectional view showing a method for manufacturing a storage cell of the storage device according to the first embodiment.

[0013] Figure 7 This is a schematic cross-sectional view showing a method for manufacturing a storage cell of the storage device according to the first embodiment.

[0014] Figure 8 This is an explanatory diagram illustrating the problem of the storage device according to the first embodiment.

[0015] Figure 9 This is an explanatory diagram of the current-voltage characteristics of the switching element in the first embodiment.

[0016] Figure 10 This is a schematic cross-sectional view of the storage unit of the storage device in the first variation of the first embodiment.

[0017] Figure 11 This is a schematic cross-sectional view of the storage unit of the storage device in the second variation of the first embodiment.

[0018] Figure 12 This is a schematic cross-sectional view of the storage unit of the storage device in the third variation of the first embodiment.

[0019] Figure 13 This is a schematic cross-sectional view of the storage unit of the storage device according to the second embodiment.

[0020] Figure 14 This is a schematic cross-sectional view of the storage unit of the storage device according to the third embodiment.

[0021] Figure 15 This is an explanatory diagram of the current-voltage characteristics of the memory element in the third embodiment.

[0022] Figure 16 This is an explanatory diagram of the first operation example of the memory operation of the storage device in the third embodiment.

[0023] Figure 17 This is an explanatory diagram of a second example of the operation of the memory in the storage device of the third embodiment.

[0024] Figure 18 This is an explanatory diagram of the current-voltage characteristics of the memory element in the first variation of the third embodiment.

[0025] Figure 19 This is an explanatory diagram of a third example of the operation of the memory of the storage device in the first variation of the third embodiment.

[0026] Figure 20 This is an explanatory diagram of the fourth operation example of the memory operation of the storage device in the first variation of the third embodiment.

[0027] Figure 21 This is an explanatory diagram of the current-voltage characteristics of the memory element in the second variation of the third embodiment.

[0028] Figure 22 This is an explanatory diagram of the fifth operation example of the memory operation of the storage device in the second variation of the third embodiment.

[0029] Figure 23 This is an explanatory diagram of the sixth operation example of the memory operation of the storage device in the second variation of the third embodiment.

[0030] Figure 24 This is an explanatory diagram of the current-voltage characteristics of the memory element in the third variation of the third embodiment.

[0031] Figure 25 This is an explanatory diagram of the seventh operation example of the memory operation of the storage device in the third variation of the third embodiment.

[0032] Figure 26 This is an explanatory diagram of the eighth operation example of the memory operation of the storage device in the third variation of the third embodiment. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will be appropriately omitted.

[0034] Qualitative and quantitative analyses of the chemical composition of the storage device constituting this specification can be performed using, for example, Rutherford Backscattering Spectroscopy (RBS), Secondary Ion Mass Spectroscopy (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), and Electron Energy Loss Spectroscopy (EELS). Furthermore, measurements of the thickness of components constituting the storage device, the distances between components, etc., can be performed using, for example, a Transmission Electron Microscope (TEM). In addition, the identification of the constituent materials of the components constituting the storage device, the measurement of the proportion of the constituent materials, the identification of the bonding state of the constituent materials, the identification of the local structure (interatomic distance, coordination number) of the constituent materials, the measurement of the chemical state of the constituent materials, and the comparison of the concentration of the constituent materials can be performed using, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure (XAFS), Raman spectroscopy (Raman), scanning transmission electron microscopy (STEM), or EELS.

[0035] (First Embodiment)

[0036] The storage device according to the first embodiment includes a storage unit, the storage unit comprising: a first conductive layer; a second conductive layer; a third conductive layer disposed between the first conductive layer and the second conductive layer; a switching layer disposed between the first conductive layer and the third conductive layer; and a resistance variation layer disposed between the third conductive layer and the second conductive layer. The switching layer comprises: a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si); at least one second element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), other than the first element; at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), other than the first and second elements; and at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), other than the first, second, and third elements. The switching layer includes a first region, a second region, and a third region in a cross section parallel to a first direction connecting the first conductive layer and the second conductive layer. In a second direction perpendicular to the first direction of the cross section, the first region is disposed between the second region and the third region. The first region contains a first oxide, and the second and third regions contain a fourth oxide of a fourth element.

[0037] Furthermore, the storage device of the first embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The storage cell is disposed in the region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

[0038] Figure 1 This is a block diagram of the storage device according to the first embodiment.

[0039] The memory cell array 100 of the memory device in the first embodiment has, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102 on a semiconductor substrate 101 separated by an insulating layer. The bit lines 103 are disposed, for example, on the upper layer of the word lines 102. In addition, a first control circuit 104, a second control circuit 105, and a sensing circuit 106 are disposed around the memory cell array 100 as peripheral circuits.

[0040] Word line 102 is an example of the first wiring. Bit line 103 is an example of the second wiring.

[0041] Multiple memory cells MC are provided in the area where word line 102 and bit line 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory with an intersection structure.

[0042] Multiple word lines 102 are connected to the first control circuit 104. Additionally, multiple bit lines 103 are connected to the second control circuit 105. A sensing circuit 106 is connected to both the first control circuit 104 and the second control circuit 105.

[0043] The first control circuit 104 and the second control circuit 105 have functions such as: selecting the desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, and erasing data from the memory cell MC. When reading data, the data in the memory cell MC is read as the amount of current flowing between the word line 102 and the bit line 103, or as a potential change in the bit line 103. The sensing circuit 106 has the function of determining the amount of current and determining the polarity of the data. For example, determining whether the data is "0" or "1".

[0044] The first control circuit 104, the second control circuit 105, and the sensing circuit 106 include, for example, electronic circuitry using a semiconductor device formed on a semiconductor substrate 101.

[0045] Figure 2 This is a schematic cross-sectional view of the storage unit of the storage device according to the first embodiment. Figure 2 express Figure 1 The cross-section of a memory cell MC, for example, represented by a dashed circle in the memory cell array 100. Figure 2 It is a cross section parallel to the first direction that connects the lower electrode 10 to the upper electrode 20.

[0046] Storage unit MC such as Figure 2 As shown, the device includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistance variation layer 50, and a sidewall insulating layer 55. The switching layer 40 includes an internal region 41, a first sidewall region 42a, and a second sidewall region 42b. Hereinafter, the first sidewall region 42a and the second sidewall region 42b may be referred to individually or collectively as sidewall region 42. The resistance variation layer 50 includes a fixed layer 51, a tunneling layer 52, and a free layer 53. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b.

[0047] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer. The inner region 41 is an example of a first region. The first sidewall region 42a is an example of a second region. The second sidewall region 42b is an example of a third region.

[0048] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance changing layer 50, and the upper electrode 20 constitute the resistance changing element of the memory cell MC.

[0049] The lower electrode 10 is connected to the word line 102. The lower electrode 10 is, for example, a metal. The lower electrode 10 may contain at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The lower electrode 10 may be part of the word line 102.

[0050] The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 may contain at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The upper electrode 20 may be a part of the bit line 103.

[0051] An intermediate electrode 30 is disposed between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 may contain at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0052] A switching layer 40 is disposed between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, 5 nm or more and 50 nm or less. The thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, more preferably 5 nm or more and 20 nm or less. The length of the switching layer 40 in the second direction perpendicular to the first direction is, for example, 10 nm or more and 50 nm or less.

[0053] Switching layer 40 has the function of suppressing the increase of half-select leakage current flowing in the half-select unit. Switching layer 40 has nonlinear current-voltage characteristics where the current rises sharply at a specific threshold voltage.

[0054] The switching layer 40 contains the first oxide of the first element, the second element, the third element, and the fourth element.

[0055] The first element is at least one element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si). The first oxide is, for example, magnesium oxide, yttrium oxide, lanthanum oxide, cerium oxide, zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, or silicon oxide.

[0056] The second element is an element different from the first element. The second element is selected from at least one element in the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi).

[0057] The third element is an element that is different from the first and second elements. The third element is selected from at least one element in the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te).

[0058] The switching layer 40 may contain, for example, a first compound containing a second element and a third element. The first compound containing the second element and the third element may be zinc telluride, for example, zinc telluride if the second element is zinc (Zn) and the third element is tellurium (Te).

[0059] The fourth element is an element that is different from the first, second, and third elements. The fourth element is selected from at least one element in the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si).

[0060] Element 4 is an element that is more difficult to oxidize than element 1, but easier to oxidize than elements 2 and 3. In other words, the standard formation energy of the oxide of element 4 is greater than that of element 1, but less than that of element 2 and element 3.

[0061] The standard energy of formation of oxides can be translated as the standard Gibbs energy of formation of oxides. The standard Gibbs energy of formation of oxides is the Gibbs energy required for the formation of oxides from elemental substances. The unit of the standard Gibbs energy of formation of oxides is kJ / mol.

[0062] Figure 3 It is a graph representing the standard formation energy of oxides of elements. Figure 3 The standard formation energies of the oxides of each element are shown. Figure 3 This represents the standardized value with one oxygen atom in the oxide. Since it is a standardized value with one oxygen atom in the oxide, the unit is indicated as kJ / mol·O.

[0063] like Figure 3 As shown, the standard formation energy of the oxide of element 4 is greater than that of the oxide of element 1, but less than that of the oxides of element 2 and element 3.

[0064] For example, if the first element is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B), then... Figure 3 As shown, the standard formation energy of boron (B) oxide is greater than that of zirconium (Zr) oxide, but less than that of zinc (Zn) oxide and tellurium (Te) oxide.

[0065] The switching layer 40 may contain, for example, a second compound of a second element and a fourth element, or a third compound of a third element and a fourth element. For example, if the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B), the switching layer 40 may contain boron telluride as the third compound.

[0066] The binding energy of the second compound of element 2 and element 4, and the binding energy of the third compound of element 3 and element 4, are, for example, less than the binding energy of the first compound of element 2 and element 3. When the binding energies of the second and third compounds are less than the binding energy of the first compound, the first compound is difficult to decompose in the presence of the first and fourth compounds.

[0067] The binding energy of a compound refers to the energy required for the compound to separate into its elemental components. The unit of binding energy is kJ / mol. If the constituent elements are specified, the binding energy of the compound can be determined.

[0068] For example, when the second element is zinc (Zn), the third element is tellurium (Te), and the first compound is zinc telluride (ZnTe), the binding energy of the first compound is the energy required for zinc telluride (ZnTe) to separate into zinc (Zn) and tellurium (Te). For example, when the second element is zinc (Zn), the third element is tellurium (Te), and the first compound is zinc telluride, as long as the fourth element is not gallium (Ga), the condition that the binding energies of the second and third compounds are less than the binding energy of the first compound is satisfied.

[0069] Furthermore, if the constituent elements are specified, the binding energy of the compound can be specified.

[0070] The sum of the atomic concentrations of the first element, the second element, the third element, the fourth element, and oxygen (O) in the switch layer 40 is, for example, more than 80% and less than 100%.

[0071] The ratio of the sum of the atomic concentrations of the first element and oxygen (O) in the switch layer 40 to the sum of the atomic concentrations of the first element, the second element, the third element, the fourth element, and oxygen (O) is, for example, more than 5% and less than 90%.

[0072] The ratio of the sum of the atomic concentrations of the fourth element in the switch layer 40 to the sum of the atomic concentrations of the first, second, third, and fourth elements is, for example, more than 1% and less than 20%, ideally more than 1% and less than 10%.

[0073] The atomic concentration of the fourth element in the switch layer 40 is, for example, lower than the atomic concentration of the second element and the atomic concentration of the third element.

[0074] The atomic concentration of the fourth element in the switch layer 40 is, for example, lower than that of the first element.

[0075] The switching layer 40 includes, for example, at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N). The fifth element is different from the first, second, third, and fourth elements.

[0076] The atomic concentration of the fifth element in the switching layer 40 is, for example, lower than the atomic concentrations of the first, second, and third elements. The atomic concentration of the fifth element contained in the switching layer 40 is, for example, more than 1% and less than 10%.

[0077] Furthermore, the atomic concentration of each element in the switching layer 40 can be obtained, for example, by performing a line analysis of the atomic concentration between the ends of the switching layer 40 along the second direction in a cross section parallel to the first direction from the lower electrode 10 to the upper electrode 20, and calculating the average value of the atomic concentration.

[0078] The switching layer 40 includes an internal region 41 and a sidewall region 42. The sidewall region 42 includes a first sidewall region 42a and a second sidewall region 42b.

[0079] In a second direction perpendicular to the first direction of the cross-section that connects the lower electrode 10 to the upper electrode 20, an inner region 41 is disposed between the first sidewall region 42a and the second sidewall region 42b. The first sidewall region 42a and the second sidewall region 42b are, for example, disposed between the lower electrode 10 and the intermediate electrode 30 in the first direction. The first sidewall region 42a and the second sidewall region 42b are, for example, connected to the lower electrode 10 and the intermediate electrode 30 respectively in the first direction.

[0080] The internal region 41 contains the first oxide, the second element, the third element, and the fourth element.

[0081] Internal region 41 may or may not contain a fourth oxide of element 4. Internal region 41 may or may not contain a second oxide of element 2. Internal region 41 may or may not contain a third oxide of element 3.

[0082] Internal region 41 may contain, for example, a first compound containing elements 2 and 3. Internal region 41 may contain, for example, a second compound containing elements 2 and 4, or a third compound containing elements 3 and 4.

[0083] Sidewall region 42 contains a fourth oxide of element 4. Sidewall region 42 may or may not contain elements 1, 2, and 3. Sidewall region 42 may or may not contain a second oxide of element 2 or a third oxide of element 3.

[0084] Sidewall region 42 may or may not contain a second compound of elements 2 and 4. Sidewall region 42 may or may not contain a third compound of elements 3 and 4.

[0085] The atomic concentration of the fourth element in sidewall region 42 is, for example, higher than that in inner region 41. The concentration of the fourth oxide in sidewall region 42 is, for example, higher than that in inner region 41.

[0086] The concentration of the fourth oxide in sidewall region 42 is, for example, higher than the concentration of the second oxide in sidewall region 42. The concentration of the fourth oxide in sidewall region 42 is, for example, higher than the concentration of the third oxide in sidewall region 42.

[0087] When the inner region 41 contains the second compound, the concentration of the second compound in the sidewall region 42 is, for example, lower than the concentration of the second compound in the inner region 41. When the inner region 41 contains the third compound, the concentration of the third compound in the sidewall region 42 is, for example, lower than the concentration of the third compound in the inner region 41.

[0088] The oxygen concentration in the sidewall region 42 is, for example, higher than that in the inner region 41.

[0089] In addition, the concentration of oxides and compounds is, for example, molar concentration.

[0090] The thickness of the first sidewall region 42a and the second sidewall region 42b in the second direction is, for example, 0.5 nm or more and 5 nm or less.

[0091] A resistance variation layer 50 is disposed between the intermediate electrode 30 and the upper electrode 20. The resistance variation layer 50 has a fixed layer 51, a tunneling layer 52, and a free layer 53. The resistance variation layer 50 includes a magnetic tunnel junction, which includes the fixed layer 51, the tunneling layer 52, and the free layer 53.

[0092] The resistance variation layer 50 has the function of storing data based on resistance changes. For example, the resistance variation layer 50 has the characteristic that the resistance changes when a specified voltage is applied.

[0093] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction remains unchanged relative to a specified write voltage, and the magnetization direction is fixed to a specific direction.

[0094] The tunneling layer 52 is an insulator. In the tunneling layer 52, electrons pass through using the tunneling effect.

[0095] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes relative to a specified write voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, by applying a voltage between the intermediate electrode 30 and the upper electrode 20 and allowing current to flow, the magnetization direction of the free layer 53 can be changed.

[0096] By changing the magnetization direction of the free layer 53, the resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state where current flow is difficult. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state where current flow is easy. Furthermore, the arrangement of the fixed layer 51 and the free layer 53 can also be reversed. That is, they can also be stacked in the order of intermediate electrode 30, free layer 53, tunneling layer 52, fixed layer 51, and upper electrode 20.

[0097] The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b. In a second direction, a lower electrode 10, a switching layer 40, and an intermediate electrode 30 are disposed between the first portion 55a and the second portion 55b. For example, the first sidewall region 42a is connected to the first portion 55a. Additionally, the second sidewall region 42b is connected to the second portion 55b.

[0098] The chemical composition of the sidewall insulating layer 55 may differ from that of the sidewall region 42. The sidewall insulating layer 55 may be, for example, silicon oxide.

[0099] Next, the manufacturing method of the storage cell of the storage device of the first embodiment will be described.

[0100] Figure 4 , Figure 5 , Figure 6 ,and Figure 7 This is a schematic cross-sectional view showing a method for manufacturing a storage cell of the storage device according to the first embodiment. Figure 4 , Figure 5 , Figure 6 ,and Figure 7 To and Figure 2 The corresponding cross-section.

[0101] The following explanation will be based on the case where the first element is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), the fourth element is boron (B), and the first oxide is zirconium oxide.

[0102] First, a first carbon film 2, a zirconium oxide film 3 containing zinc (Zn), tellurium (Te), and boron (B), and a second carbon film 4 are formed on a substrate 1. Figure 4 ).

[0103] Zinc telluride, a compound of zinc (Zn) and tellurium (Te), is present in the zirconia film 3. Zinc telluride is an example of the first compound. Boron (B) exists, for example, as an element in the zirconia film 3.

[0104] The substrate 1 is, for example, a conductive layer. The first carbon film 2, the zirconium oxide film 3, and the second carbon film 4 are formed, for example, by sputtering. The first carbon film 2, the zirconium oxide film 3, and the second carbon film 4 ultimately become the lower electrode 10, the switching layer 40, and the intermediate electrode 30, respectively.

[0105] Next, a resist pattern is formed on the second carbon film 4 using photolithography. Then, using the resist as a mask, reactive ion etching (RIE) is performed to process the second carbon film 4, the zirconium oxide film 3, and the first carbon film 2. Figure 5 ).

[0106] Next, an oxidation treatment is performed to oxidize the side surfaces of the zirconium oxide film 3. Figure 6 Oxidation treatment can be, for example, heat treatment in an environment containing oxidizing gases. Oxidation treatment can be performed, for example, in the same chamber as RIE. For example, RIE and oxidation treatment can be performed consecutively in the same chamber. For example, RIE and oxidation treatment can be performed without exposing substrate 1 to the atmosphere outside the chamber.

[0107] An oxidation region 5 is formed on the side surface of a zirconium oxide film 3 containing zinc (Zn), tellurium (Te), and boron (B) through an oxidation treatment. An oxide of boron (B), which is more easily oxidized than zinc (Zn) or tellurium (Te), is formed in the oxidation region 5. That is, boron oxide is formed in the oxidation region 5. Boron oxide is an example of a fourth oxide. The oxidation region 5 ultimately becomes the sidewall region 42.

[0108] Furthermore, through oxidation treatment, for example, a portion of zinc (Zn), which is more easily oxidized than tellurium (Te), is oxidized, and zinc telluride decomposes to form zinc oxide. For example, elemental tellurium (Te) formed by the decomposition of zinc telluride combines with boron (B) to form boron telluride in the zirconium oxide film 3. Boron telluride is an example of the third compound.

[0109] Furthermore, through oxidation treatment, for example, boron (B) inside the zirconia film 3 diffuses toward the side of the zirconia film 3, the atomic concentration of boron (B) in the oxidation region 5 becomes higher than the atomic concentration of boron (B) inside the zirconia film 3.

[0110] Next, a silicon oxide film 6 is formed on the sides of the first carbon film 2, the zirconium oxide film 3, and the second carbon film 4. Figure 7The silicon oxide film 6 is formed, for example, by chemical vapor deposition. The silicon oxide film 6 ultimately becomes the sidewall insulating layer 55.

[0111] Subsequently, a resistance variation layer 50 and an upper electrode 20 are formed using a known manufacturing method. The storage unit of the storage device according to the first embodiment is thus formed using the above manufacturing method.

[0112] Next, the function and effects of the storage device in the first embodiment will be explained.

[0113] The storage device of the first embodiment, as described above, changes the resistance of the resistance-changing layer 50 by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state where current flow is difficult. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state where current flow is easy.

[0114] For example, the high resistance state of the resistance variation layer 50 is defined as data "1", and the low resistance state is defined as data "0". The memory cell MC can store 1 bit of data "0" and "1" by maintaining different resistance states. Writing to a memory cell MC is performed by applying a voltage and flowing current between the bit line 103 and the word line 102 connected to the memory cell MC.

[0115] Figure 8 This is an explanatory diagram illustrating the problem of the storage device according to the first embodiment. Figure 8 This shows the voltage applied to a memory cell MC when selecting one memory cell MC within the memory cell array for a write operation. The intersection of the word line and the bit line represents each memory cell MC.

[0116] The selected memory cell MC is memory cell A (selection cell). A write voltage Vwrite is applied to the word line connected to memory cell A. Additionally, 0V is applied to the bit line connected to memory cell A.

[0117] The following explanation will be based on the case where half the write voltage (Vwrite / 2) is applied to the word line and bit line that are not connected to memory cell A.

[0118] The voltage applied to memory cell C (non-selection cell), which is connected to word lines and bit lines not connected to memory cell A, is 0V. That is, no voltage is applied.

[0119] On the other hand, half of the write voltage Vwrite (Vwrite / 2) is applied to memory cell B (half-select cell), which is connected to the word line or bit line connected to memory cell A. Therefore, half-select leakage current flows in memory cell B (half-select cell).

[0120] In addition to the above-mentioned application methods, the following methods may also be used: apply half the write voltage (Vwrite / 2) to the word line connected to memory cell A, apply half the write voltage negative voltage (-Vwrite / 2) to the bit line, and apply 0V to the word line and bit line not connected to memory cell A.

[0121] Figure 9 This is an explanatory diagram of the current-voltage characteristics of the switching element according to the first embodiment. The horizontal axis represents the voltage applied to the switching element, and the vertical axis represents the current flowing through the switching element.

[0122] The switching element exhibits a nonlinear current-voltage characteristic where the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, above 0.5V and below 3V.

[0123] The write voltage Vwrite is set such that the write voltage Vwrite is higher than the threshold voltage Vth, and half of the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current flowing through the switching element when the write voltage Vwrite is applied is the on-state current. Figure 9 The current flowing through the switching element when half of the write voltage Vwrite (Vwrite / 2) is applied is the half-selection leakage current (Ion). Figure 9 (Ihalf in the middle).

[0124] In addition, the read voltage Vread of the memory cell MC is, for example, Figure 9 As shown, the voltage is set to be higher than the threshold voltage Vth and lower than the write voltage Vwrite. Therefore, during the read operation of the memory cell MC, the half-select leakage current flowing in the half-select cell can also be suppressed.

[0125] If the half-select leakage current is large, it can lead to increased power consumption of the chip. Additionally, it can increase voltage drop in the wiring, preventing the application of a sufficiently high voltage to the select cell and causing instability in the write operation to the memory cell MC. Conversely, if the on-state current is small, insufficient current can flow through the select cell, resulting in insufficient writes to the memory cell MC. Therefore, the current-voltage characteristics of the switching element must balance low half-select leakage current with high on-state current.

[0126] Furthermore, high reliability is required for the current and voltage characteristics of the switching elements. That is, it is required to suppress characteristic variations such as changes in half-select leakage current or on-state current when repeatedly writing data to the memory cell MC, in order to achieve high reliability.

[0127] For example, as a comparative example of a switching element, consider a switching element whose switching layer does not contain the fourth element. A switching layer that does not contain the fourth element can be formed, for example, by using a film of an oxide containing the first element, which contains the second and third elements. In other words, it can be formed by using an oxide film that differs from the first embodiment in that it does not contain the fourth element. In the comparative example of the switching element, there are problems such as high half-selection leakage current or significant characteristic variations when repeatedly writing data to the memory cell MC.

[0128] One reason for the problems observed in the comparative example's switching element is that the second or third element exists locally in the sidewall region of the switching layer, not as a compound, but as an elemental substance. Because the second or third element exists in the sidewall region of the switching layer as an elemental substance, a current leakage path is formed, resulting in a higher semi-selective leakage current. Furthermore, it is believed that because the second or third element exists in the sidewall region of the switching layer as an elemental substance, the aggregation of the second or third element is accelerated when data is repeatedly written to the memory cell MC, leading to greater characteristic variations.

[0129] The oxidation process performed after processing the oxide film, which serves as the switching layer, using RIE (Residual Etching) can restore residual etching damage on the sides of the switching layer. If residual etching damage remains, for example, the half-select leakage current becomes high.

[0130] On the other hand, through oxidation treatment, the second or third element is oxidized near the side of the switching layer, forming a second or third oxide. In this case, the first compound decomposes. In the case of forming a second oxide, the third element remains as an elemental substance. In the case of forming a third oxide, the second element remains as an elemental substance. Elements that are difficult to oxidize, such as the second and third elements, remain as elemental substances.

[0131] For example, consider the case where the first element in the switching layer of the comparative example switching element is zirconium (Zr), the second element is zinc (Zn), and the third element is tellurium (Te). In the switching layer, zirconium oxide contains zinc telluride as the first compound. If an oxidation treatment is performed on the side of the switching layer, zinc (Zn), which is more easily oxidized than tellurium (Te), is oxidized near the side of the switching layer to form zinc oxide. Zinc telluride decomposes, leaving tellurium (Te) in elemental form. The tellurium (Te) remaining in elemental form forms a current leakage path, increasing the semi-selective leakage current. Furthermore, when data is repeatedly written to the memory cell MC, the agglomeration of tellurium (Te) accelerates, leading to greater characteristic variations.

[0132] The switching layer 40 of the first embodiment contains a fourth element. Furthermore, the sidewall region 42 of the switching layer 40 contains a fourth oxide formed by oxidizing the fourth element. By containing the fourth oxide, the first compound of the second and third elements decomposes, thereby suppressing the presence of the second or third element in the sidewall region 42 of the switching layer 40 as an elemental substance.

[0133] For example, consider the case where the first element in the switching layer 40 of the switching element in the first embodiment is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B). Similar to the comparative example, in the switching layer 40, zinc telluride is included as the first compound in the zirconium oxide. Boron (B) is more easily oxidized than either zinc (Zn) or tellurium (Te). Therefore, if an oxidation treatment is performed on the sides of the switching layer 40, boron (B), which is more easily oxidized than zinc (Zn) and tellurium (Te), is oxidized near the sides of the switching layer 40, forming boron oxide as the fourth oxide. Therefore, the decomposition of zinc telluride is suppressed, thereby preventing tellurium (Te) from existing in elemental form as in the comparative example.

[0134] Furthermore, the standard formation energy of the oxide of element 4 is higher than that of the oxide of element 1. In other words, element 1 is more easily oxidized than element 4. Therefore, even if element 4 is present in the switch layer 40, the first oxide of element 1 can exist stably without being reduced.

[0135] The switching element according to the first embodiment can achieve lower half-selection leakage current and suppression of characteristic variations. According to the first embodiment, a storage device having a switching element with excellent characteristics can be provided.

[0136] The ratio of the sum of the atomic concentrations of the fourth element in the switching layer 40 to the sum of the atomic concentrations of the first, second, third, and fourth elements is preferably 1% to 10%. By satisfying this lower limit, lower half-selection leakage current and suppression of characteristic variations in the switching element can be achieved. By satisfying this upper limit, the deterioration of the switching element's characteristics due to the fourth element remaining in its elemental form can be suppressed.

[0137] The atomic concentration of the fourth element in the switching layer 40 is preferably lower than that of the second and third elements. Furthermore, the atomic concentration of the fourth element in the switching layer 40 is preferably lower than that of the first element. This helps to suppress the situation where an excessive amount of the fourth element deteriorates the characteristics of the switching element.

[0138] From the viewpoint of restoring the etching damage remaining on the sidewalls of the switching layer 40 and achieving a lower half-select leakage current of the switching element, it is preferable that the sidewall region 42 is sufficiently oxidized. Therefore, the oxygen concentration in the sidewall region 42 is preferably higher than the oxygen concentration in the inner region 41. In addition, the concentration of the fourth oxide in the sidewall region 42 is preferably higher than the concentration of the fourth oxide in the inner region 41.

[0139] The atomic concentration of the fourth element in the sidewall region 42 is preferably higher than that in the inner region 41. This configuration allows for sufficient oxidation of the sidewall region 42. This configuration is achieved by utilizing the diffusion of the fourth element obtained through oxidation.

[0140] From the viewpoint of avoiding the presence of the second or third element in the form of an elemental substance in the sidewall region 42 and achieving a switching element with excellent characteristics, it is preferable to oxidize the fourth element rather than oxidize the second or third element. Therefore, the concentration of the fourth oxide in the sidewall region 42 is preferably higher than the concentration of the second oxide in the sidewall region 42. Furthermore, the concentration of the fourth oxide in the sidewall region 42 is preferably higher than the concentration of the third oxide in the sidewall region 42.

[0141] From the viewpoint of preventing the second or third element from existing in its elemental form and achieving a switching element with excellent characteristics when the first compound decomposes due to oxidation of the second or third element, the switching layer 40 is preferably a second compound containing the second and fourth elements, or a third compound containing the third and fourth elements. By forming the second or third compound, it is possible to suppress the existence of the second or third element in its elemental form.

[0142] The binding energy of the second compound of the second element and the fourth element, and the binding energy of the third compound of the third element and the fourth element, are preferably less than the binding energy of the first compound of the second element and the third element. By satisfying the above conditions, the decomposition of the first compound can be suppressed by the binding of the fourth element with the second element or the binding of the fourth element with the third element.

[0143] From the viewpoint of suppressing leakage current in the sidewall of the switching layer 40 and improving the characteristics of the switching element, the sidewall region 42 is preferably connected to the lower electrode 10 and the intermediate electrode 30 in the first direction.

[0144] The switching layer 40 preferably contains at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N). By including a fifth element in the switching layer 40, crystallization of the switching layer 40 can be suppressed, for example, reducing the semi-selective leakage current.

[0145] (Example of the first variation)

[0146] The storage device of the first variation of the first embodiment differs from the storage device of the first embodiment in that the first conductive layer includes a first portion and a second portion, and the first portion contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr) and titanium (Ti).

[0147] Figure 10 This is a schematic cross-sectional view of the storage unit of the storage device in the first variation of the first embodiment. Figure 10 For the purposes of the first embodiment Figure 2 The corresponding diagram.

[0148] The lower electrode 10 includes a first part 11 and a second part 12. The second part 12 is disposed between the first part 11 and the switching layer 40.

[0149] Part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). Part 11 may include, for example, borides of said elements. Part 11 may also include, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0150] Part 2, 12, includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0151] The storage device of the first variation of the first embodiment suppresses the degradation of the characteristics of the resistance changing element by including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti) in the first portion 11 of the lower electrode 10. In addition, by not being in contact with the switching layer 40, oxygen (O) is suppressed from detaching from the switching layer 40, thus suppressing the degradation of the characteristics of the switching element.

[0152] According to the first variation of the first embodiment, a switching element with excellent characteristics of low half-selection leakage current and high reliability can be realized in the same way as the first embodiment.

[0153] (Second variation example)

[0154] The storage device of the second variation of the first embodiment differs from the storage device of the first embodiment in the following aspects: the first conductive layer includes a first portion and a second portion, the first portion contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer contains one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, the fourth portion contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0155] Figure 11 This is a schematic cross-sectional view of the storage unit of the storage device in the second variation of the first embodiment. Figure 11 For the purposes of the first embodiment Figure 2 The corresponding diagram.

[0156] The lower electrode 10 includes a first part 11 and a second part 12. The second part 12 is disposed between the first part 11 and the switching layer 40.

[0157] Part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). Part 11 may include, for example, borides of said elements. Part 11 may also include, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0158] Part 2, 12, includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0159] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 may, for example, contain a boride of said element. The upper electrode 20 may, for example, contain at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0160] The intermediate electrode 30 includes a third part 31 and a fourth part 32. The third part 31 is disposed between the fourth part 32 and the switching layer 40.

[0161] Part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide and tantalum nitride.

[0162] Part 4, 32 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). Part 4, 32 includes, for example, borides of said elements. Part 4, 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0163] The storage device in the second variation of the first embodiment suppresses the degradation of the resistance-changing element's characteristics by including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti) in the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30. Furthermore, by preventing oxygen (O) from detaching from the switching layer 40, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not connected to the switching layer 40, thus suppressing the degradation of the switching element's characteristics.

[0164] According to the second variation of the first embodiment, a switching element with excellent characteristics of lower half-selection leakage current and higher reliability can be realized in the same way as the first embodiment.

[0165] (Example 3)

[0166] The storage device of the third variation of the first embodiment differs from the storage device of the first embodiment in the following aspects: the first conductive layer includes a first part, a second part and a fifth part, the first part contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr) and titanium (Ti), the second conductive layer contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr) and titanium (Ti), and the third conductive layer includes a third part and a fourth part, the fourth part contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr) and titanium (Ti).

[0167] Figure 12 This is a schematic cross-sectional view of the storage unit of the storage device in the third variation of the first embodiment. Figure 12 For the purposes of the first embodiment Figure 2 The corresponding diagram.

[0168] The lower electrode 10 includes a first part 11, a second part 12, and a fifth part 13. The second part 12 is disposed between the first part 11 and the switching layer 40. The first part 11 is disposed between the fifth part 13 and the second part 12.

[0169] Part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). Part 11 may include, for example, borides of said elements. Part 11 may also include, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0170] Part 2, section 12 and Part 5, section 13 include, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide and tantalum nitride.

[0171] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 may, for example, contain a boride of said element. The upper electrode 20 may, for example, contain at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0172] The intermediate electrode 30 includes a third part 31 and a fourth part 32. The third part 31 is disposed between the fourth part 32 and the switching layer 40.

[0173] Part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide and tantalum nitride.

[0174] Part 4, 32 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). Part 4, 32 includes, for example, borides of said elements. Part 4, 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0175] The storage device in the third variation of the first embodiment suppresses the degradation of the resistance changing element's characteristics by including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti) in the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30. Furthermore, by preventing oxygen (O) from detaching from the switching layer 40, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not connected to the switching layer 40, thus suppressing the degradation of the switching element's characteristics.

[0176] According to the third variation of the first embodiment, a switching element with excellent characteristics of low half-selection leakage current and high reliability can be realized in the same way as the first embodiment.

[0177] According to the first embodiment and its variations, a switching element with excellent characteristics, including low half-selection leakage current and high reliability, can be realized. Therefore, according to the first embodiment and its variations, a storage device with a switching element exhibiting excellent characteristics can be realized.

[0178] (Second Implementation)

[0179] The storage device in the second embodiment is a resistive random access memory (ReRAM), which differs from the storage device in the first embodiment. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0180] Figure 13 This is a schematic cross-sectional view of the storage unit of the storage device according to the second embodiment. Figure 13 express Figure 1 The cross-section of a memory cell MC, for example, represented by a dashed circle in the memory cell array 100.

[0181] Storage unit MC such as Figure 13 As shown, the device includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistance variation layer 50, and a sidewall insulating layer 55. The switching layer 40 includes an internal region 41, a first sidewall region 42a, and a second sidewall region 42b. The resistance variation layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b.

[0182] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer. The middle electrode 30 is an example of a third conductive layer. The inner region 41 is an example of a first region. The first sidewall region 42a is an example of a second region. The second sidewall region 42b is an example of a third region.

[0183] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistance changing layer 50, and the upper electrode 20 constitute the resistance changing element of the memory cell MC.

[0184] The configuration of the switch layer 40 is the same as that of the storage device in the first embodiment.

[0185] The resistance variation layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

[0186] The high-resistivity layer 50x is, for example, a metal oxide. The high-resistivity layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0187] The low-resistivity layer 50y is, for example, a metal oxide. The low-resistivity layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0188] The resistance variation layer 50 has the function of storing data based on resistance changes. For example, the resistance variation layer 50 has the characteristic that the resistance changes when a specified voltage is applied.

[0189] By applying a voltage to the resistance-varying layer 50, the layer changes from a high-resistance state to a low-resistance state, or vice versa. Applying a voltage to the resistance-varying layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen defects (oxygen vacancies) in the low-resistance layer 50y. Accompanying this change in the amount of oxygen defects in the low-resistance layer 50y, the conductivity of the resistance-varying layer 50 changes. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0190] For example, a high-resistance state can be defined as data "1", and a low-resistance state can be defined as data "0". The memory cell MC can store 1 bit of data, either "0" or "1".

[0191] As described above, the storage device according to the second embodiment can, in the same manner as the first embodiment, realize a switching element with excellent characteristics, including low half-selection leakage current and high reliability. Therefore, according to the second embodiment, a storage device with a switching element possessing excellent characteristics can be realized.

[0192] (Third Implementation)

[0193] The storage device of the third embodiment includes a storage unit, which includes a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer comprises: a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si); at least one second element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), other than the first element; at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), other than the first and second elements; and at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), other than the first, second, and third elements. The switching layer includes a first region, a second region, and a third region in a cross section parallel to a first direction connecting the first conductive layer and the second conductive layer. In a second direction perpendicular to the first direction of the cross section, the first region is disposed between the second region and the third region. The first region contains a first oxide, and the second region and the third region contain a fourth oxide of a fourth element.

[0194] Furthermore, the storage device of the third embodiment further includes a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The storage cell is disposed in the region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

[0195] The storage cell of the storage device in the third embodiment does not include a third conductive layer and a resistance variation layer, and includes the same configuration as the switching layer in the first and second embodiments as a memory layer. This aspect differs from the storage devices of the first and second embodiments. Hereinafter, some descriptions that are repeated in the first or second embodiments will be omitted.

[0196] Figure 14 This is a schematic cross-sectional view of the storage unit of the storage device according to the third embodiment. Figure 14 express Figure 1 The cross-section of a memory cell MC, for example, represented by a dashed circle in the memory cell array 100.

[0197] Storage unit MC such as Figure 14 As shown, the device includes a lower electrode 10, an upper electrode 20, a sidewall insulating layer 55, and a memory layer 60. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b. The memory layer 60 includes an internal region 61, a first sidewall region 62a, and a second sidewall region 62b.

[0198] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0199] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function of storing information.

[0200] The memory layer 60 has the same configuration as the switch layer 40 in the first and second embodiments. The internal region 61, the first sidewall region 62a, and the second sidewall region 62b of the memory layer 60 have the same configuration as the internal region 41, the first sidewall region 42a, and the second sidewall region 42b of the switch layer 40 in the first and second embodiments.

[0201] The memory layer 60 exhibits a nonlinear current-voltage characteristic where the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic where the threshold voltage varies with the applied specified voltage. The memory layer 60 also has a characteristic where the resistance varies with the applied specified voltage. In the third embodiment, a high-resistance state refers to a state where the resistance of the memory layer 60 is relatively high at the read voltage. Conversely, in the third embodiment, a low-resistance state refers to a state where the resistance of the memory layer 60 is relatively low at the read voltage.

[0202] The memory layer 60 has the function of suppressing the increase of half-select leakage current flowing in the half-select unit. In addition, the memory layer 60 has the function of storing data according to the resistance change. The memory layer 60 implements the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment and the second embodiment in a single layer.

[0203] Figure 15 This is an explanatory diagram of the current-voltage characteristics of the memory element according to the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. Figure 15 In the figure, the voltage applied to the upper electrode 20 based on the potential of the lower electrode 10 is shown on the horizontal axis. Figure 15 This refers to the current and voltage characteristics of the memory layer 60 in the third embodiment. Figure 15 This refers to the current and voltage characteristics of the memory cell MC in the third embodiment.

[0204] The memory element of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. Figure 15In the figure, the solid line represents the current-voltage characteristics when a specified positive voltage is applied to the upper electrode 20, and the dashed line represents the current-voltage characteristics when a specified negative voltage is applied to the upper electrode 20.

[0205] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Similarly, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0206] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Similarly, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0207] The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp. Additionally, the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

[0208] The memory element in the third embodiment can achieve both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a high-resistance state on both the positive and negative voltage sides. Conversely, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a low-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1", and the low-resistance state is defined as data "0". The memory cell MC can store 1 bit of data, either "0" or "1".

[0209] Figure 16 This is an explanatory diagram of the first operation example of the memory operation of the storage device in the third embodiment. Figure 16 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and negative read voltage Vrn during memory operation.

[0210] In the first example of operation, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the first example of operation, the negative side read voltage Vrn is used as the read voltage.

[0211] When writing data "1" to the selection unit, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and data "1" is written to the selection unit.

[0212] When writing data "0" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the first negative voltage side threshold voltage Vtpn. By applying the negative-side write voltage Vwn to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and data "0" is written to the selection unit.

[0213] In the first example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", current will flow even if the positive side write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive side write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the storage device.

[0214] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the second positive voltage-side threshold voltage Vtnp. Furthermore, voltage Vwn / 2 is higher than the second negative voltage-side threshold voltage Vtnn.

[0215] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0216] When reading the data from the selection unit, a negative readout voltage Vrn is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0217] Furthermore, in the case of the first operating example, regardless of whether the data in the selection unit is data "1" or data "0", there will be no data corruption caused by the application of the negative side readout voltage Vrn. In other words, in the case of the first operating example, non-destructive readout can be achieved regardless of whether the data in the selection unit is data "1" or data "0".

[0218] Figure 17 This is an explanatory diagram of a second example of the operation of the memory in the storage device of the third embodiment. Figure 17 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and positive read voltage Vrp during memory operation.

[0219] In the second example of operation, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the second example of operation, the positive side read voltage Vrp is used as the read voltage.

[0220] When writing data "1" to the selection unit, a positive side write voltage Vwp is applied to the upper electrode 20. The positive side write voltage Vwp is a voltage higher than the first positive voltage side threshold voltage Vtpp. By applying the positive side write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and data "1" is written to the selection unit.

[0221] When writing data "0" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the first negative voltage side threshold voltage Vtpn. By applying the negative-side write voltage Vwn to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and data "0" is written to the selection unit.

[0222] In the second example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", even if the positive side write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, current will still flow as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive side write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the storage device.

[0223] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the second positive voltage-side threshold voltage Vtnp. Furthermore, voltage Vwn / 2 is higher than the second negative voltage-side threshold voltage Vtnn.

[0224] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0225] When reading the data from the selection unit, a positive readout voltage Vrp is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0226] Furthermore, in the second operating example, when the data in the selection unit is data "1", no data corruption will occur due to the application of the positive readout voltage Vrp. In other words, in the second operating example, non-destructive readout can be achieved as long as the data in the selection unit is data "1".

[0227] On the other hand, if the data in the selection unit is "0", there is a risk that current might flow due to the application of a positive side readout voltage Vrp that is higher than the second positive voltage side threshold voltage Vtnp, causing the data in the selection unit to change to "1". In other words, in the second operating example, if the data in the selection unit is "0", there is a possibility of disrupting the readout. Therefore, if the data in the selection unit is "0", after reading the data in the selection unit, there is a possibility that the data "0" needs to be written back to maintain the data in the selection unit.

[0228] (Example of the first variation)

[0229] The storage device of the first variation of the third embodiment differs from the storage device of the third embodiment in that the current and voltage characteristics of the memory elements are different.

[0230] Figure 18 This is an explanatory diagram of the current-voltage characteristics of the memory element in the first variation of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. Figure 18 In the figure, the voltage applied to the upper electrode 20 based on the potential of the lower electrode 10 is shown on the horizontal axis. Figure 18 The current-voltage characteristics of the memory layer 60 in the first variation of the third embodiment. Figure 18 The current-voltage characteristics of the memory cell MC in the first variation of the third embodiment.

[0231] The memory element of the first variation of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. Figure 18 In the figure, the solid line represents the current-voltage characteristics when a specified positive voltage is applied to the upper electrode 20, and the dashed line represents the current-voltage characteristics when a specified negative voltage is applied to the upper electrode 20.

[0232] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Similarly, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0233] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Similarly, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0234] The threshold voltage Vtpp on the first positive voltage side is lower than the threshold voltage Vtnp on the second positive voltage side. Additionally, the threshold voltage Vtpn on the first negative voltage side is higher than the threshold voltage Vtnn on the second negative voltage side.

[0235] The memory element in the first variation of the third embodiment can obtain both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a low-resistance state on both the positive and negative voltage sides. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a high-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1", and the low-resistance state is defined as data "0". The memory cell MC can store 1 bit of data, both "0" and "1".

[0236] Figure 19 This is an explanatory diagram of a third example of the operation of the memory of the storage device in the first variation of the third embodiment. Figure 19 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and negative read voltage Vrn during memory operation.

[0237] In the third example of operation, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the third example of operation, the negative side read voltage Vrn is used as the read voltage.

[0238] When writing data "1" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative voltage side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high-resistance state is achieved on the negative voltage side, and data "1" is written to the selection unit.

[0239] When writing data "0" to the selection cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and data "0" is written to the selection cell.

[0240] In the third example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", even if the negative side write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn, current will still flow. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative side write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the storage device.

[0241] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the first positive voltage-side threshold voltage Vtpp. Furthermore, voltage Vwn / 2 is higher than the first negative voltage-side threshold voltage Vtpn.

[0242] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0243] When reading the data from the selection unit, a negative readout voltage Vrn is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0244] Furthermore, in the third operating example, when the data in the selection unit is data "1", no data corruption will occur due to the application of the negative side readout voltage Vrn. In other words, in the third operating example, as long as the data in the selection unit is data "1", non-destructive readout can be achieved.

[0245] On the other hand, if the data in the selection unit is "0", there is a risk that current might flow due to the application of a negative side readout voltage Vrn that is lower than the first negative voltage side threshold voltage Vtpn, causing the data in the selection unit to change to "1". In other words, in the case of the third operating example, if the data in the selection unit is "0", there is a possibility of disrupting the readout. Therefore, if the data in the selection unit is "0", after reading the data in the selection unit, there is a possibility that the data "0" needs to be written back to maintain the data in the selection unit.

[0246] Figure 20 This is an explanatory diagram of the fourth operation example of the memory operation of the storage device in the first variation of the third embodiment. Figure 20 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and positive read voltage Vrp during memory operation.

[0247] In the fourth example of operation, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the fourth example of operation, the positive side read voltage Vrp is used as the read voltage.

[0248] When writing data "1" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative voltage side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and data "1" is written to the selection unit.

[0249] When writing data "0" to the selection cell, a positive side write voltage Vwp is applied to the upper electrode 20. The positive side write voltage Vwp is a voltage higher than the second positive voltage side threshold voltage Vtnp. By applying the positive side write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and data "0" is written to the selection cell.

[0250] In the fourth example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", even if the negative side write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn, current will still flow. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative side write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the storage device.

[0251] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the first positive voltage-side threshold voltage Vtpp. Furthermore, voltage Vwn / 2 is higher than the first negative voltage-side threshold voltage Vtpn.

[0252] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0253] When reading the data from the selection unit, a positive readout voltage Vrp is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0254] Furthermore, in the fourth operating example, regardless of whether the data in the selection unit is data "1" or data "0", no data corruption will occur due to the application of the positive readout voltage Vrp. In other words, in the fourth operating example, non-destructive readout can be achieved regardless of whether the data in the selection unit is data "1" or data "0".

[0255] (Second variation example)

[0256] The storage device of the second variation of the third embodiment differs from the storage device of the third embodiment in that the current and voltage characteristics of the memory elements are different.

[0257] Figure 21 This is an explanatory diagram of the current-voltage characteristics of the memory element in the second variation of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. Figure 21 In the figure, the voltage applied to the upper electrode 20 based on the potential of the lower electrode 10 is shown on the horizontal axis. Figure 21 The current-voltage characteristics of the memory layer 60 in the second variation of the third embodiment. Figure 21 The current-voltage characteristics of the storage cell MC in the second variation of the third embodiment.

[0258] The memory element of the second variation of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. Figure 21 In the figure, the solid line represents the current-voltage characteristics when a specified positive voltage is applied to the upper electrode 20, and the dashed line represents the current-voltage characteristics when a specified negative voltage is applied to the upper electrode 20.

[0259] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Similarly, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0260] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Similarly, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0261] The first positive voltage side threshold voltage Vtpp is lower than the second positive voltage side threshold voltage Vtnp. Additionally, the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

[0262] The memory element in the second variation of the third embodiment can obtain a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1", and the low-resistance state is defined as data "0". The memory cell MC can store 1 bit of data, "0" and "1".

[0263] Figure 22 This is an explanatory diagram of the fifth operation example of the memory operation of the storage device in the second variation of the third embodiment. Figure 22 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and negative read voltage Vrn during memory operation.

[0264] In the fifth example of operation, the high resistance state and low resistance state on the negative voltage side are used for memory operation. In the fifth example of operation, the negative side read voltage Vrn is used as the read voltage.

[0265] When writing data "1" to the selection unit, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage side threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and data "1" is written to the selection unit.

[0266] When writing data "0" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the first negative voltage side threshold voltage Vtpn. By applying the negative-side write voltage Vwn to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and data "0" is written to the selection unit.

[0267] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the first positive voltage-side threshold voltage Vtpp. Furthermore, voltage Vwn / 2 is higher than the second negative voltage-side threshold voltage Vtnn.

[0268] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0269] When reading the data from the selection unit, a negative readout voltage Vrn is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0270] Furthermore, in the case of the fifth operating example, regardless of whether the data in the selection unit is data "1" or data "0", there will be no data corruption caused by the application of the negative side readout voltage Vrn. In other words, in the case of the fifth operating example, non-destructive readout can be achieved regardless of whether the data in the selection unit is data "1" or data "0".

[0271] Figure 23 This is an explanatory diagram of the sixth operation example of the memory operation of the storage device in the second variation of the third embodiment. Figure 23 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and positive read voltage Vrp during memory operation.

[0272] In the sixth example of operation, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the sixth example of operation, the positive side read voltage Vrp is used as the read voltage.

[0273] When writing data "1" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the first negative voltage side threshold voltage Vtpn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and data "1" is written to the selection unit.

[0274] When writing data "0" to the selection cell, a positive side write voltage Vwp is applied to the upper electrode 20. The positive side write voltage Vwp is a voltage higher than the second positive voltage side threshold voltage Vtnp. By applying the positive side write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and data "0" is written to the selection cell.

[0275] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the first positive voltage-side threshold voltage Vtpp. Furthermore, voltage Vwn / 2 is higher than the second negative voltage-side threshold voltage Vtnn.

[0276] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0277] When reading the data from the selection unit, a positive readout voltage Vrp is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0278] Furthermore, in the case of the sixth operating example, regardless of whether the data in the selection unit is data "1" or data "0", no data corruption will occur due to the application of the positive readout voltage Vrp. In other words, in the case of the sixth operating example, non-destructive readout can be achieved regardless of whether the data in the selection unit is data "1" or data "0".

[0279] (Example 3)

[0280] The storage device of the third variation of the third embodiment differs from the storage device of the third embodiment in that the current and voltage characteristics of the memory elements are different.

[0281] Figure 24 This is an explanatory diagram of the current-voltage characteristics of the memory element in the third variation of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. Figure 24In the figure, the voltage applied to the upper electrode 20 based on the potential of the lower electrode 10 is shown on the horizontal axis. Figure 24 The current-voltage characteristics of the memory layer 60 in the third variation of the third embodiment. Figure 24 The current-voltage characteristics of the memory cell MC in the third variation of the third embodiment.

[0282] The memory element of the third variation of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. Figure 24 In the figure, the solid line represents the current-voltage characteristics when a specified positive voltage is applied to the upper electrode 20, and the dashed line represents the current-voltage characteristics when a specified negative voltage is applied to the upper electrode 20.

[0283] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Similarly, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0284] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Similarly, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0285] The threshold voltage Vtpp on the first positive voltage side is higher than the threshold voltage Vtnp on the second positive voltage side. Additionally, the threshold voltage Vtpn on the first negative voltage side is higher than the threshold voltage Vtnn on the second negative voltage side.

[0286] The memory element in the third variation of the third embodiment can obtain both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1", and the low-resistance state is defined as data "0". The memory cell MC can store 1 bit of data, both "0" and "1".

[0287] Figure 25 This is an explanatory diagram of the seventh operation example of the memory operation of the storage device in the third variation of the third embodiment. Figure 25The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and negative read voltage Vrn during memory operation.

[0288] In the seventh example of operation, the high resistance state and low resistance state of the negative voltage side are used for memory operation. In the seventh example of operation, the negative side read voltage Vrn is used as the read voltage.

[0289] When writing data "1" to the selection unit, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative voltage side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high-resistance state is achieved on the negative voltage side, and data "1" is written to the selection unit.

[0290] When writing data "0" to the selection cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and data "0" is written to the selection cell.

[0291] In the seventh example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", even if the negative side write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn, current will still flow. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative side write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the storage device.

[0292] Furthermore, in the seventh operating example, when writing data "0" to the selection unit, if the data stored in the selection unit is data "1", then even if the positive side write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp, current will still flow. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the positive side write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the storage device.

[0293] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the second positive voltage-side threshold voltage Vtnp. Furthermore, voltage Vwn / 2 is higher than the first negative voltage-side threshold voltage Vtpn.

[0294] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0295] When reading the data from the selection unit, a negative readout voltage Vrn is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0296] Furthermore, in the case of the seventh operating example, when the data in the selection unit is data "1", no data corruption will occur due to the application of the negative side readout voltage Vrn. In other words, in the case of the seventh operating example, non-destructive readout can be achieved as long as the data in the selection unit is data "1".

[0297] On the other hand, if the data in the selection unit is "0", there is a risk that current might flow due to the application of a negative side readout voltage Vrn that is lower than the first negative voltage side threshold voltage Vtpn, causing the data in the selection unit to change to "1". In other words, in the case of the seventh operating example, if the data in the selection unit is "0", there is a possibility of disrupting the readout. Therefore, if the data in the selection unit is "0", after reading the data in the selection unit, there is a possibility that the data "0" needs to be written again to maintain the data in the selection unit.

[0298] Figure 26 This is an explanatory diagram of the eighth operation example of the memory operation of the storage device in the third variation of the third embodiment. Figure 26 The diagram shows the positive write voltage Vwp, half of the positive write voltage Vwp (Vwp / 2), negative write voltage Vwn, half of the negative write voltage Vwn (Vwn / 2), and positive read voltage Vrp during memory operation.

[0299] In the 8th operation example, the high resistance state and low resistance state on the positive voltage side are used for memory operation. In the 8th operation example, the positive side read voltage Vrp is used as the read voltage.

[0300] When writing data "1" to the selection unit, a positive side write voltage Vwp is applied to the upper electrode 20. The positive side write voltage Vwp is a voltage higher than the first positive voltage side threshold voltage Vtpp. By applying the positive side write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and data "1" is written to the selection unit.

[0301] When writing data "0" to the selection cell, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative voltage side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and data "0" is written to the selection cell.

[0302] In the eighth example, when writing data "1" to the selection unit, if the data stored in the selection unit is data "0", current will flow even if the positive side write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive side write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the storage device.

[0303] Furthermore, in the eighth example, when writing data "0" to the selection unit, if the data stored in the selection unit is data "1", even if the negative side write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, current will still flow as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the negative side write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the storage device.

[0304] Furthermore, when a positive-side write voltage Vwp is applied to the select unit, a voltage Vwp / 2 is applied to the half-select unit. Similarly, when a negative-side write voltage Vwn is applied to the select unit, a voltage Vwn / 2 is applied to the half-select unit. Voltage Vwp / 2 is lower than the second positive voltage-side threshold voltage Vtnp. Furthermore, voltage Vwn / 2 is higher than the first negative voltage-side threshold voltage Vtpn.

[0305] Therefore, even when the half-selection cell is in a low-resistance state, the half-selection leakage current flowing in the half-selection cell can be suppressed. Thus, the memory element also functions as a switching element.

[0306] When reading the data from the selection unit, a positive readout voltage Vrp is applied to the selection unit. The data from the selection unit can be determined by detecting the change in current or potential caused by the difference between the current flowing when the data is "1" and when the data is "0".

[0307] Furthermore, in the case of the 8th operating example, when the data in the selection unit is data "1", no data corruption will occur due to the application of the positive readout voltage Vrp. In other words, in the case of the 8th operating example, non-destructive readout can be achieved as long as the data in the selection unit is data "1".

[0308] On the other hand, if the data in the selection unit is "0", there is a risk that current might flow due to the application of a positive side readout voltage Vrp that is higher than the second positive voltage side threshold voltage Vtnp, causing the data in the selection unit to change to "1". In other words, in the case of the eighth operating example, if the data in the selection unit is "0", there is a possibility of disrupting the readout. Therefore, if the data in the selection unit is "0", after reading the data in the selection unit, there is a possibility that the data "0" needs to be written back to maintain the data in the selection unit.

[0309] In the storage device of the third embodiment and its variations, the memory element of the storage cell MC has a switching function and a function of storing information. The memory layer 60 implements the functions of the switching layer 40 and the resistance changing layer 50 of the first and second embodiments in a single layer. By having the switching function and the memory function in a single layer in the third embodiment, the structure of the storage cell MC can be made extremely simple.

[0310] Furthermore, the memory layer 60 of the storage device in the third embodiment and its variations has the same configuration as the switch layer 40 in the first and second embodiments. Therefore, according to the third embodiment and its variations, a storage device with excellent switching characteristics, having lower half-selection leakage current and higher reliability, can be realized, just like in the first and second embodiments.

[0311] Furthermore, the various current-voltage characteristics of the memory element shown in the third embodiment and its variations can be achieved, for example, by employing a memory layer 60 with a suitable chemical composition.

[0312] In the first embodiment, a magnetoresistive memory is described as an example of a two-terminal storage device, and in the second embodiment, a resistance-changing memory is described as an example of a storage device. However, the present invention can also be applied to other two-terminal storage devices. For example, the present invention can be applied to phase-change memory (PCM) or ferroelectric random access memory (FeRAM).

[0313] For the above, several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0314] [Explanation of Symbols]

[0315] 10. Lower electrode (first conductive layer)

[0316] 20 Upper electrode (second conductive layer)

[0317] 30 Intermediate electrode (3rd conductive layer)

[0318] 40 Switching Layer

[0319] 41. Internal Area (Area 1)

[0320] 42a First sidewall region (second region)

[0321] 42b Second sidewall region (third region)

[0322] 50 Resistance Variation Layer

[0323] 55 Sidewall insulation layer (insulation layer)

[0324] 55a Part 1

[0325] 55b Part 2

[0326] 60 Memory Layer

[0327] 61. Internal Area (Area 1)

[0328] 62a First sidewall region (second region)

[0329] 62b Second sidewall region (third region)

[0330] 102-digit line (first wiring)

[0331] 103 bit line (second wiring)

[0332] MC storage unit.

Claims

1. A storage device comprising a storage unit, the storage unit comprising: First conductive layer; Second conductive layer; A third conductive layer is disposed between the first conductive layer and the second conductive layer; A switching layer is disposed between the first conductive layer and the third conductive layer; and A resistance variation layer is disposed between the third conductive layer and the second conductive layer; The switching layer includes: The first oxide of at least one first element selected from the group consisting of magnesium, yttrium, lanthanum, cerium, zirconium, hafnium, aluminum, titanium, and silicon; The second element is selected from at least one element in the group consisting of zinc, gallium, indium, tin, and bismuth, instead of the first element. A third element selected from the group consisting of phosphorus, arsenic, antimony, bismuth, sulfur, selenium, and tellurium, other than the first element and the second element; and A fourth element selected from the group consisting of vanadium, niobium, tantalum, chromium, boron, gallium, and silicon, which is different from the first element, the second element, and the third element. The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer. In a second direction perpendicular to the first direction of the cross-section, the first region is disposed between the second region and the third region. The first region contains the first oxide, and the second and third regions contain the fourth oxide of the fourth element.

2. The storage device according to claim 1, wherein the first region may or may not contain the fourth oxide, and the concentration of the fourth oxide in the second region and the third region is higher than the concentration of the fourth oxide in the first region.

3. The storage device according to claim 1, wherein the second region may or may not contain a second oxide of the second element, and the concentration of the fourth oxide in the second region is higher than the concentration of the second oxide in the second region. The second region may or may not contain the third oxide of the third element, and the concentration of the fourth oxide in the second region is higher than the concentration of the third oxide in the second region. The third region may or may not contain the second oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the second oxide in the third region. The third region may or may not contain the third oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the third oxide in the third region.

4. The storage device according to claim 1, wherein the ratio of the atomic concentration of the fourth element in the switching layer to the sum of the atomic concentrations of the first element, the second element, the third element, and the fourth element is more than 1% and less than 20%.

5. The storage device according to claim 1, wherein the atomic concentration of the fourth element in the second region and the atomic concentration of the fourth element in the third region are higher than the atomic concentration of the fourth element in the first region.

6. The storage device of claim 1, wherein the switching layer comprises a first compound of the second element and the third element.

7. The storage device of claim 1, wherein the switching layer comprises a second compound of the second element and the fourth element, or a third compound of the third element and the fourth element.

8. The storage device according to claim 7, wherein, when the first region contains the second compound, The second region may or may not contain the second compound, and the concentration of the second compound in the second region is lower than the concentration of the second compound in the first region. The third region may or may not contain the second compound, and the concentration of the second compound in the third region is lower than the concentration of the second compound in the first region. In the case where the third compound is contained in the first region, The second region may or may not contain the third compound, and the concentration of the third compound in the second region is lower than the concentration of the third compound in the first region. The third region may or may not contain the third compound, and the concentration of the third compound in the third region is lower than the concentration of the third compound in the first region.

9. The storage device according to claim 1, wherein the atomic concentration of the fourth element in the switching layer is lower than the atomic concentration of the second element and the atomic concentration of the third element.

10. The storage device according to claim 1, wherein the atomic concentration of the fourth element in the switching layer is lower than the atomic concentration of the first element.

11. The storage device of claim 1, wherein the switching layer further comprises at least one fifth element, the at least one fifth element being different from the first element, the second element, the third element, and the fourth element, and selected from the group consisting of carbon, boron, and nitrogen.

12. The storage device according to claim 1, wherein the second region and the third region are disposed between the first conductive layer and the third conductive layer in the first direction.

13. The storage device according to claim 1, wherein the oxygen concentration in the second region and the oxygen concentration in the third region are higher than the oxygen concentration in the first region.

14. The storage device according to claim 1, wherein the length of the cross-section of the second region and the third region in the second direction is 0.5 nm or more and 5 nm or less.

15. The storage device of claim 1, further comprising an insulating layer, the insulating layer comprising a first portion and a second portion, In the second direction of the cross section, the first conductive layer, the third conductive layer, and the switching layer are disposed between the first portion and the second portion. The second region is connected to the first part, and the third region is connected to the second part.

16. The storage device of claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

17. The storage device of claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

18. The storage device of claim 1, wherein the resistance variation layer comprises a magnetic tunnel junction.

19. The storage device of claim 1, wherein the resistance of the resistance-changing layer changes upon application of a predetermined voltage. The switching layer has a nonlinear current-voltage characteristic where the current rises at a specific threshold voltage.

20. The storage device according to claim 1, further comprising: Multiple first wirings; and Multiple second wirings intersect with the multiple first wirings. The storage unit is disposed in the area where one of the plurality of first wirings intersects with one of the plurality of second wirings.

21. A storage device comprising a storage unit, the storage unit comprising: First conductive layer; The second conductive layer; and A memory layer is disposed between the first conductive layer and the second conductive layer; The memory layer includes: The first oxide of at least one first element selected from the group consisting of magnesium, yttrium, lanthanum, cerium, zirconium, hafnium, aluminum, titanium, and silicon; The second element is selected from at least one element in the group consisting of zinc, gallium, indium, tin, and bismuth, instead of the first element. A third element selected from the group consisting of phosphorus, arsenic, antimony, bismuth, sulfur, selenium, and tellurium, other than the first element and the second element; and A fourth element selected from the group consisting of vanadium, niobium, tantalum, chromium, boron, gallium, and silicon, which is different from the first element, the second element, and the third element. The memory layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer. In a second direction perpendicular to the first direction of the cross-section, the first region is disposed between the second region and the third region. The first region contains the first oxide, and the second and third regions contain the fourth oxide of the fourth element.

22. The storage device of claim 21, wherein the first region may or may not contain the fourth oxide, and the concentration of the fourth oxide in the second region and the third region is higher than the concentration of the fourth oxide in the first region.

23. The storage device of claim 21, wherein the second region may or may not contain a second oxide of the second element, and the concentration of the fourth oxide in the second region is higher than the concentration of the second oxide in the second region. The second region may or may not contain the third oxide of the third element, and the concentration of the fourth oxide in the second region is higher than the concentration of the third oxide in the second region. The third region may or may not contain the second oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the second oxide in the third region. The third region may or may not contain the third oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the third oxide in the third region.

24. The storage device according to claim 21, wherein the ratio of the atomic concentration of the fourth element in the memory layer to the sum of the atomic concentrations of the first element, the second element, the third element, and the fourth element is more than 1% and less than 20%.

25. The storage device of claim 21, wherein the atomic concentration of the fourth element in the second region and the atomic concentration of the fourth element in the third region are higher than the atomic concentration of the fourth element in the first region.

26. The storage device of claim 21, wherein the memory layer comprises a first compound of the second element and the third element.

27. The storage device of claim 21, wherein the memory layer comprises a second compound of the second element and the fourth element, or a third compound of the third element and the fourth element.

28. The storage device according to claim 27, wherein, when the first region contains the second compound, The second region may or may not contain the second compound, and the concentration of the second compound in the second region is lower than the concentration of the second compound in the first region. The third region may or may not contain the second compound, and the concentration of the second compound in the third region is lower than the concentration of the second compound in the first region. In the case where the third compound is contained in the first region, The second region may or may not contain the third compound, and the concentration of the third compound in the second region is lower than the concentration of the third compound in the first region. The third region may or may not contain the third compound, and the concentration of the third compound in the third region is lower than the concentration of the third compound in the first region.

29. The storage device of claim 21, wherein the atomic concentration of the fourth element in the memory layer is lower than the atomic concentration of the second element and the atomic concentration of the third element.

30. The storage device of claim 21, wherein the atomic concentration of the fourth element in the memory layer is lower than the atomic concentration of the first element.

31. The storage device of claim 21, wherein the memory layer further comprises at least one fifth element, the at least one fifth element being different from the first element, the second element, the third element, and the fourth element, and selected from the group consisting of carbon, boron, and nitrogen.

32. The storage device of claim 21, wherein the second region and the third region are disposed between the first conductive layer and the second conductive layer in the first direction.

33. The storage device according to claim 21, wherein the oxygen concentration in the second region and the oxygen concentration in the third region are higher than the oxygen concentration in the first region.

34. The storage device according to claim 21, wherein the length of the cross-section of the second region and the third region in the second direction is 0.5 nm or more and 5 nm or less.

35. The storage device of claim 21, wherein the memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, the threshold voltage changing as a predetermined voltage is applied.

36. The storage device according to claim 21, further comprising: Multiple first wirings; and Multiple second wirings intersect with the multiple first wirings; The storage unit is disposed in the area where one of the plurality of first wirings intersects with one of the plurality of second wirings.

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