Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a semiconductor memory comprising at least one stacked structure. Each stacked structure includes: an electrode pattern; a magnetic tunnel junction (MTJ) pattern formed on the electrode pattern; a hard mask pattern formed on the MTJ pattern; a first spacer formed on two sidewalls of the electrode pattern; and a sacrificial layer pattern formed on at least a portion of the first spacer and supporting the MTJ pattern and the hard mask pattern.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Application No. 10-2024-0189437, filed on December 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various embodiments of this disclosure relate to semiconductor technology, and more specifically, to a semiconductor device including a magnetic tunnel junction (MTJ) and a method for manufacturing the semiconductor device. Background Technology

[0003] Recent demands for miniaturization, low power consumption, high performance, and versatility in electronic devices require semiconductor devices to store data in various electronic devices, such as computers and portable communication devices. Researchers and industry are researching and developing semiconductor devices that meet these requirements. Semiconductor devices being developed and researched for these purposes include those capable of storing data by switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses. Summary of the Invention

[0004] Embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the same, which can ensure the reliability and performance of MTJ devices by effectively removing MTJ etching byproducts.

[0005] According to embodiments of the present disclosure, a semiconductor device includes: a semiconductor memory including at least one stacked structure, wherein each of the at least one stacked structure includes: an electrode pattern; a magnetic tunnel junction (MTJ) pattern formed on the electrode pattern; a hard mask pattern formed on the MTJ pattern; a first spacer formed on two sidewalls of the electrode pattern; and a sacrificial layer pattern formed on at least a portion of the first spacer and supporting the MTJ pattern and the hard mask pattern.

[0006] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device includes: forming a magnetic tunnel junction (MTJ) layer over a sacrificial layer having an electrode pattern buried therein; forming a hard mask layer over the MTJ layer; forming the MTJ pattern and the hard mask pattern by etching the MTJ layer and the hard mask layer, wherein etching byproducts of the MTJ layer are accumulated on the upper surface of the sacrificial layer; and removing the etching byproducts when removing the sacrificial layer. Attached Figure Description

[0007] Figures 1A to 1C This is a cross-sectional view showing a semiconductor device and its manufacturing method according to a comparative example.

[0008] Figures 2A to 2D This is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure.

[0009] Figures 3A to 3D This is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. Detailed Implementation

[0010] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] Various embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of this disclosure.

[0012] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to clearly show the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that the third layer exists between the first layer and the second layer or the substrate.

[0013] Before describing embodiments of this disclosure, comparative examples and their problems for comparison with embodiments of this disclosure are first described.

[0014] Figures 1A to 1C This is a cross-sectional view showing a semiconductor device and its manufacturing method according to a comparative example.

[0015] refer to Figure 1A A first interlayer dielectric layer 105 can be formed on the substrate 100.

[0016] Subsequently, the first interlayer dielectric layer 105 can be selectively etched to form a hole that exposes a portion of the substrate 100, and a lower contact plug 110 can then be formed to fill the lower portion of the hole.

[0017] Subsequently, a lower electrode layer can be formed over the lower contact plug 110. A hard mask layer can then be formed over the lower electrode layer, and a lower electrode pattern 121 can be formed by using the hard mask layer as an etch stop layer and patterning the lower electrode layer into a pillar shape. The hard mask layer may include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and may have a single-layer or multi-layer structure. The dielectric material may include oxides, nitrides, or a combination thereof. For example, the hard mask layer may include a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide. The lower electrode pattern 121 may be part of a variable resistor element and may be distinguished from the lower contact plug 110 coupled to the lower end of the variable resistor element to couple the variable resistor element to another element. After the lower electrode pattern 121 is formed, dielectric material used as a spacer can be deposited onto the lower electrode pattern 121 and the first interlayer dielectric layer 105 by methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The spacer 122 can be formed by performing an isotropic dry etching process to remove the dielectric material from the top of the first interlayer dielectric layer 105 and leaving only the dielectric material on the sidewalls of the lower electrode pattern 121. The dielectric material is retained only on the sidewalls of the lower electrode pattern 121 by performing a selective etching process in the vertical direction via reactive ion etching (RIE).

[0018] After forming the lower electrode pattern 121 and the spacer 122, a sacrificial layer 115 may be formed to fill the space between the lower electrode patterns 121. The sacrificial layer 115 may include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and the sacrificial layer 115 may be formed as a single-layer structure or a multilayer structure. Oxides, nitrides, or combinations thereof may be used as dielectric materials. For example, the sacrificial layer 115 may include SiO2, SiN4, SiOCN, SiON, polysilicon (Poly-Si), or a combination thereof. Subsequently, after planarizing the upper surface of the sacrificial layer 115 and the upper surface of the lower electrode pattern 121, a magnetic tunnel junction (MTJ) layer 120 may be formed on the upper surface of the sacrificial layer 115 and the upper surface of the lower electrode pattern 121. According to this comparative example, the MTJ layer 120 may include a free layer 123, a tunnel barrier layer 124, and a fixing layer 125 sequentially stacked therein. Subsequently, a hard mask layer 126 may be formed on the fixing layer 125 of the MTJ layer 120.

[0019] refer to Figure 1BThe MTJ layer 120, comprising the free layer 123, the tunnel barrier layer 124, and the fixed layer 125, can be patterned into a pillar shape using a hard mask layer 126 as an etch stop layer. The hard mask layer 126 may include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and may have a single-layer or multi-layer structure. The dielectric material may include oxides, nitrides, or a combination thereof. For example, the hard mask layer 126 may include a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0020] This patterning allows the MTJ pattern 120A, including the free layer pattern 123A, the tunnel barrier layer pattern 124A, and the fixed layer pattern 125A, and the hard mask pattern 126A, to be formed into a pillar shape. In this case, MTJ etching byproducts 130 can accumulate on the upper surface of the sacrificial layer 115 and the upper surface of the spacer 122. The accumulated MTJ etching byproducts 130 can form an electrical bridge between the lower electrode patterns 121. This electrical bridge can cause short circuits between the electrodes, which may interfere with the normal operation of the MTJ device and lead to failure. The MTJ etching byproducts 130 can be formed primarily of metals with low reactivity, and therefore may be difficult to remove by conventional reactive ion etching (RIE) processes or wet cleaning (CLN) processes. Therefore, there is a need to develop a technique for effectively removing MTJ etching byproducts 130.

[0021] refer to Figure 1C , can Figure 1B A second interlayer dielectric layer 135 is formed on top of the structure. The second interlayer dielectric layer 135 may include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and the second interlayer dielectric layer 135 may be formed as a single-layer structure or a multilayer structure. Oxides, nitrides, or combinations thereof may be used as dielectric materials.

[0022] MTJ etching byproducts 130 generated in a conventional MTJ patterning process, as illustrated in the comparative example, can accumulate on the upper surface of the sacrificial layer 115 and the upper surface of the spacer 122, and may be difficult to remove. Furthermore, MTJ etching byproducts 130 may affect the uniformity of the second interlayer dielectric layer 135 formed thereon (and on the upper surface of the sacrificial layer 115), thereby degrading the performance of subsequent processes. Due to incomplete removal of MTJ etching byproducts 130, interlayer insulation performance may deteriorate, and ultimately, MTJ etching byproducts 130 may also negatively impact the electrical characteristics of the MTJ device. Moreover, when MTJ etching byproducts 130 remain, this may adversely affect the magnetoresistive characteristics of the MTJ device, thereby reducing its reliability.

[0023] To address the problems of the semiconductor device according to the comparative example described above, a semiconductor device and its manufacturing method according to embodiments of this disclosure can provide a method for effectively removing MTJ etching byproducts 130 by forming a sacrificial layer made of a material having etch selectivity relative to the hard mask layer, and removing the sacrificial layer together with the MTJ etching byproducts. Reference will be made below. Figures 2A to 2D To provide a detailed description of the contents of this disclosure.

[0024] Figures 2A to 2D This is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure.

[0025] refer to Figure 2A A substrate 200 may be provided, comprising a desired predetermined structure formed therein, such as a switching element (not shown). In this case, the switching element may be coupled to a variable resistor element to control the supply of current or voltage to the variable resistor element, and the switching element may include, for example, a transistor, a diode, etc. One end of the switching element may be electrically connected to a lower contact plug 210, which will be described below, and the other end of the switching element may be electrically connected to an interconnect (not shown), such as a source line.

[0026] Subsequently, a first interlayer dielectric layer 205 may be formed on the substrate 200. The first interlayer dielectric layer 205 may include various dielectric materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0027] Subsequently, the first interlayer dielectric layer 205 can be selectively etched to form a hole exposing a portion of the substrate 200, and a lower contact plug 210 can then be formed to fill the lower portion of the hole. The lower contact plug 210 can be formed by selectively etching the first interlayer dielectric layer 205 to form a contact hole exposing a portion of the substrate 200, depositing a conductive material of sufficient thickness to fill the contact hole, and performing a planarization process such as chemical mechanical polishing (CMP) until the upper surface of the first interlayer dielectric layer 205 is exposed. The lower contact plug 210 can include a conductive material with excellent filling properties and high conductivity. The lower contact plug 210 can include, for example, metals such as tungsten (W), tantalum (Ta), or metal nitrides such as titanium nitride (TiN).

[0028] Subsequently, a lower electrode layer can be formed on the lower contact plug 210. Then, a lower electrode pattern 221 can be formed by forming a hard mask layer on the lower electrode layer and using the hard mask layer as an etch stop layer to pattern the lower electrode layer into a pillar shape. The lower electrode pattern 221 can be part of a variable resistor element. The lower electrode pattern 221 can be distinguished from the lower contact plug 210, which is coupled to the lower end of the variable resistor element to couple the variable resistor element to another element. The lower electrode pattern 221 can include tungsten (W), titanium nitride (TiN), tantalum (Ta), molybdenum (Mo), or copper (Cu).

[0029] After the lower electrode pattern 221 is formed, dielectric material for forming spacers can be deposited onto the lower electrode pattern 221 and the first interlayer dielectric layer 205 using methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Spacers 222 can be formed by performing an isotropic dry etching process to remove dielectric material from the top of the first interlayer dielectric layer 205 and leave dielectric material only on the sidewalls(s) of the lower electrode pattern 221. Selective etching can be performed in the vertical direction using reactive ion etching (RIE) until only the dielectric material located on the sidewalls of the electrode pattern 221 is retained. Spacers 222 may primarily comprise carbon, and spacers 222 may have dielectric properties. Additionally or alternatively, spacers 222 may also contain a small amount of metal or metal oxides compared to the amount of carbon in spacers 222. The metal may be the same metal included in the lower electrode pattern 221, but may be additionally included according to alternative embodiments of the process. Figure 2B The MTJ pattern 220A shown includes a metal. The oxide of the metal may have dielectric properties. For example, spacer 222 may include silicon oxide, silicon nitride, hafnium oxide, tantalum oxide, tantalum nitride, titanium nitride, aluminum oxide, or combinations thereof.

[0030] According to an embodiment of this disclosure, since the lower contact plug 210 is formed in a hole located in the first interlayer dielectric layer 205, and the lower electrode pattern 221 is formed in another hole located in the sacrificial layer 215, the sidewalls of the lower contact plug 210 and the lower electrode pattern 221 may be misaligned with each other. However, according to another embodiment of this disclosure, the lower contact plug 210 and the lower electrode pattern 221 may have sidewalls aligned with each other.

[0031] According to an embodiment of the present disclosure, the lower electrode pattern 221 may have a width greater than that of the lower contact plug 210, while overlapping with the lower contact plug 210. However, according to another embodiment of the present disclosure, the position and width of the lower electrode pattern 221 may vary only when the lower electrode pattern 221 is coupled to the lower contact plug 210.

[0032] After forming the lower electrode pattern 221 and the spacer 222, a sacrificial layer 215 may be formed to fill the space between the spacers 222 and the lower electrode pattern 221. The sacrificial layer 215 may be formed of a material with etch selectivity relative to the hard mask layer 226. The hard mask layer 226 may be formed of a dielectric material, and the dielectric material may include silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride, which can be used to form the dielectric layer of the hard mask layer 226. Considering the etch selectivity relative to the hard mask layer 226, the sacrificial layer 215 may be formed of a carbon-containing material, such as amorphous carbon, diamond-like carbon (DLC), graphite, carbon-containing polyimide, or parylene-C.

[0033] Subsequently, after planarizing the upper surface of the sacrificial layer 215 and the upper surface of the lower electrode pattern 221, a magnetic tunnel junction (MTJ) layer 220 can be formed on the upper surface of the sacrificial layer 215 and the upper surface of the lower electrode pattern 221. According to embodiments of this disclosure, the MTJ layer 220 may include a free layer 223, a tunnel barrier layer 224, and a fixed layer 225 stacked sequentially. In some embodiments, to form the MTJ structure, the free layer 223 has a variable magnetization direction, the fixed layer 225 has a fixed magnetization direction, and the tunnel barrier layer 224 is interposed between the free layer 223 and the fixed layer 225, which allows electron tunneling when necessary (e.g., during data write operations that change the resistance state of a variable resistive element). Each of the free layer 223 and the fixed layer 225 may have a single-layer structure or a multi-layer structure comprising a ferromagnetic material. Ferromagnetic materials can include alloys containing iron (Fe), nickel (Ni), or cobalt (Co) as the main component, such as iron-platinum (Fe-Pt) alloys, iron-palladium (Fe-Pd) alloys, cobalt-iron (Co-Fe) alloys, cobalt-palladium (Co-Pd) alloys, cobalt-platinum (Co-Pt) alloys, cobalt-iron-nickel (Co-Fe-Ni) alloys, iron-nickel-platinum (Fe-Ni-Pt) alloys, cobalt-iron-platinum (Co-Fe-Pt) alloys, cobalt-nickel-platinum (Co-Ni-Pt) alloys, cobalt-iron-boron (Co-Fe-B) alloys, etc., or stacked structures such as cobalt / platinum (Co / Pt), cobalt / palladium (Co / Pd), etc. The positions of the free layer 223 and the fixed layer 225 can be interchanged, and the tunnel barrier layer 224 is located between them. In other words, the free layer 223 can be disposed above the tunnel barrier layer 224, and the fixed layer 225 can be disposed below the tunnel barrier layer 224 and above the lower electrode pattern 221. The tunnel barrier layer 224 can have a single-layer or multi-layer structure, including, for example, metal oxides such as magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), titanium oxide (TiO), vanadium oxide (VO), niobium oxide (NbO), etc. Subsequently, a hard mask layer 226 can be formed on the fixed layer 225 of the MTJ layer 220. The hard mask layer 226 can include a dielectric material, polysilicon (Poly-Si), or a combination thereof, and the hard mask layer 226 can have a single-layer or multi-layer structure. The dielectric material can include oxides, nitrides, or a combination thereof. For example, the hard mask layer 226 can include a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

[0034] refer to Figure 2BThe MTJ layer 220, comprising the free layer 223, tunnel barrier layer 224, and fixed layer 225, can be patterned into a pillar shape using a hard mask layer 226 as an etching barrier layer. The etching process can be performed using a process with enhanced physical etching properties, such as ion beam etching (IBE). Therefore, the resulting stacked structure can have a shape where the width increases from the top to the (base or) bottom of the structure. The upper portion of the lower electrode pattern 221 may have sidewalls aligned with the MTJ pattern 220A, but the lower portion of the lower electrode pattern 221 may not be aligned with the MTJ pattern 220A. The hard mask pattern 226A can be removed during the etching process or by a separate removal process. Additionally, when the hard mask pattern 226A includes conductive material, a portion of the hard mask pattern 226A can be retained (i.e., the hard mask patterning feature with residual hard mask pattern 226A is incorporated into the device).

[0035] A stacked structure can be formed through a patterning process, in which a columnar MTJ pattern 220A, including a free layer pattern 223A, a tunnel barrier layer pattern 224A, and a fixed layer pattern 225A, and a hard mask pattern 226A are stacked. In these cases, MTJ etching byproducts 230 can accumulate on the upper surface of the sacrificial layer 215 and the upper surface of the spacer 222. The MTJ etching byproducts 230 can form electrical bridges between the lower electrode patterns 221. The lower electrode pattern 221 can include an upper portion and a lower portion, the sidewalls of the upper portion being aligned with the MTJ pattern 220A, and the sidewalls of the lower portion being misaligned with the upper portion and having a width greater than the width of the upper portion.

[0036] refer to Figure 2C The MTJ etching byproducts 230 can be removed together with the sacrificial layer 215. The sacrificial layer 215 can be a layer designed to be removed together with the MTJ etching byproducts 230, and a dry etching process or a plasma etching process can be performed to remove the sacrificial layer 215. Since the sacrificial layer 215 is formed of a material with etch selectivity relative to the hard mask pattern 226A, when the sacrificial layer 215 is etched, only the sacrificial layer 215 and the MTJ etching byproducts 230 accumulated thereon can be selectively removed without damaging the MTJ pattern 226A.

[0037] In dry etching processes, oxygen plasma or fluorine-based plasma can be used, which is effective in selectively removing the carbon-based sacrificial layer 215. Fine byproducts that may remain after dry etching can be removed by wet cleaning processes. Wet cleaning processes can be processes that remove residues or byproducts retained on the surface using chemical solutions, and can use acidic or alkaline solutions. This process effectively removes MTJ etching byproducts 230 and cleans the surface of the stacked structure. Since the surface can be prepared for subsequent processes by removing the sacrificial layer 215 and MTJ etching byproducts 230, embodiments of this disclosure provide the ability to prevent degradation of the interlayer dielectric layer performance or other process performance, and to ensure electrical reliability.

[0038] Most of the sacrificial layer 215 can be removed, but a portion can be retained, thus allowing a sacrificial layer pattern (not shown) to be formed over at least a portion of the spacer 222. The sacrificial layer pattern can structurally support the MTJ pattern 220A and the hard mask pattern 226A. This support helps maintain the physical stability of the MTJ pattern 220A, especially after its formation. The MTJ pattern 220A can have a delicate (e.g., fragile) structure and can be easily damaged during etching or subsequent processes. However, because the sacrificial layer pattern physically supports the MTJ pattern 220A, it prevents deformation, breakage, or other damage. Additionally, the sacrificial layer pattern can mitigate thermal and mechanical stresses that may occur during subsequent processes. When the sacrificial layer pattern remains on the spacer 222, it further enhances the physical bond between the spacer and the MTJ pattern. In this way, the sacrificial layer pattern can serve as a critical element, not only providing removable functionality (during device formation) but also enhancing the stability of the patterned structure and ensuring device performance and reliability. Similar to the composition of sacrificial layer 215, the sacrificial layer pattern can be formed from carbon-containing materials such as amorphous carbon, diamond-like carbon (DLC), graphite, carbon-containing polyimide, or parylene-C. Alternatively, the sacrificial layer pattern may also include polycrystalline silicon, silicon oxide, silicon nitride, aluminum oxide, or titanium oxide.

[0039] refer to Figure 2D , can Figure 2C A second interlayer dielectric layer 235 is formed on top of the existing structure. The second interlayer dielectric layer 235 can be formed of a dielectric material, polysilicon (Poly-Si), or a combination thereof. The second interlayer dielectric layer 235 can be formed as a single-layer structure or a multilayer structure. Oxides, nitrides, or combinations thereof can be used as the dielectric material, and the dielectric material can include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or a combination thereof. Figure 2CThe surface of the structure is cleaned using dry etching and wet cleaning processes, thus the second interlayer dielectric layer 235 and... Figure 2C The bonding quality between the surfaces of the structure can be improved.

[0040] The above process can be used to form such as Figure 2D The semiconductor device shown.

[0041] Return to reference Figure 2D The semiconductor device according to embodiments of the present disclosure may include: a lower contact plug 210 disposed on and coupled to a portion of a substrate 200; a first interlayer dielectric layer 205 filling the space between the lower contact plugs 210; a lower electrode pattern 221 coupled to the lower contact plugs 210; a spacer 222 formed on a sidewall of the lower electrode pattern 221; an MTJ pattern 220A coupled to the lower electrode pattern 221; a hard mask pattern 226A formed on the MTJ pattern 220A; and a second interlayer dielectric layer 235 covering the upper surfaces of the spacer 222, the MTJ pattern 220A, and the hard mask pattern 226A.

[0042] Spacer 222 may primarily comprise carbon and may have dielectric properties. Additionally, compared to the amount of carbon in spacer 222, spacer 222 may also contain small amounts of metal (or metalloid, such as silicon) or metal oxides. Spacer 222 may alternatively comprise nitrides. The metal may be the metal included in the lower electrode pattern 221, and may also include the metal included in the MTJ pattern 220A depending on the specific process. The oxide (or nitride) of the metal (or metalloid) may have dielectric properties. For example, spacer 222 may comprise silicon oxide, silicon nitride, hafnium oxide, tantalum oxide, tantalum nitride, titanium nitride, aluminum oxide, or combinations thereof.

[0043] The MTJ pattern 220A can store data by switching between different resistance states according to the voltage or current applied to its lower and upper parts. More specifically, the MTJ pattern 220A can store data in a manner opposite to the magnetization direction of the fixed layer pattern 225A by changing the magnetization direction of the free layer pattern 223A according to the voltage or current applied to it. When the magnetization directions of the free layer pattern 223A and the fixed layer pattern 225A are parallel to each other, the MTJ pattern 220A can be in a low resistance state, and the MTJ pattern 220A can store, for example, data "1". Conversely, when the magnetization directions of the free layer pattern 223A and the fixed layer pattern 225A are antiparallel to each other, the MTJ pattern 220A can be in a high resistance state, and the MTJ pattern 220A can store, for example, data "0". The magnetization direction of the free layer pattern 223A can be changed due to spin torque. The magnetization direction of the free layer pattern 223A and the magnetization direction of the fixed layer pattern 225A can be perpendicular to the interface of the layers, for example, the interface between the free layer pattern 223A and the tunnel barrier layer pattern 224A.

[0044] According to the semiconductor devices and manufacturing methods described above, these embodiments effectively remove MTJ etching byproducts 230 to prevent degradation of the magnetoresistive characteristics and reliability of the MTJ device, as well as degradation of the interlayer insulation performance and electrical characteristics of the MTJ device. Furthermore, the sacrificial layer pattern can structurally support the MTJ pattern 220A and help maintain the physical stability of the MTJ pattern 220A.

[0045] Furthermore, according to embodiments of this disclosure, the stacked structure may include an MTJ pattern 220A and a hard mask pattern 226A, but other embodiments of this disclosure are also possible. For example, the stacked structure may also include any one (or a combination thereof) of an exchange bonding layer pattern, a magnetic compensation layer pattern, and a cover layer pattern located on the MTJ pattern 220A, and may also include a second spacer located on the sidewall of the stacked structure. Reference will be made below. Figures 3A to 3D This embodiment will now be described in detail.

[0046] Figures 3A to 3D This is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. Detailed descriptions of aspects substantially the same as those described above with respect to the embodiments of the present disclosure will be omitted.

[0047] refer to Figure 3AA substrate 300 may be provided, which includes desired predetermined structures formed therein, such as switching elements (not shown). One end of the switching element may be electrically connected to a lower contact plug 310, which will be described below, and the other end of the switching element may be electrically connected to an interconnect (not shown), such as a source line.

[0048] Subsequently, a first interlayer dielectric layer 305 may be formed on the substrate 300. Subsequently, a lower contact plug 310 may be formed that penetrates the first interlayer dielectric layer 305 to couple to a portion of the substrate 300 (e.g., one end of a switching element).

[0049] Subsequently, a lower electrode layer can be formed on the lower contact plug 310. Then, a lower electrode pattern 321 can be formed by forming a hard mask layer on the lower electrode layer and using the hard mask layer as an etch stop layer to pattern the lower electrode layer into a pillar shape. After forming the lower electrode pattern 321, dielectric material for forming spacers can be deposited on the lower electrode pattern 321 and the first interlayer dielectric layer 305 using methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). An isotropic dry etching process can be performed to remove the dielectric material from the top of the first interlayer dielectric layer 305, and spacers 322 can be formed by leaving dielectric material only on the sidewalls of the lower electrode pattern 321. After forming the lower electrode pattern 321 and the spacers 322, a sacrificial layer 315 can be formed to fill the space between the lower electrode patterns 321. Considering the etching selectivity relative to the hard mask layer 329, the sacrificial layer 315 can be formed of a carbon-containing material, such as amorphous carbon, diamond-like carbon (DLC), graphite, carbon-containing polyimide, or parylene-C.

[0050] Subsequently, the upper surface of the sacrificial layer 315 and the upper surface of the lower electrode pattern 321 can be planarized, and then an MTJ layer 320 can be formed on the upper surface of the sacrificial layer 315 and the upper surface of the lower electrode pattern 321. According to embodiments of the present disclosure, the MTJ layer 320 may include a free layer 323, a tunnel barrier layer 324, and a fixed layer 325 stacked in sequence.

[0051] Additionally, a variable resistive element comprising an exchange bonding layer 326, a magnetic compensation layer 327, and a capping layer 328 can be formed by further stacking an exchange bonding layer 326, a magnetic compensation layer 327, and a capping layer 328 on top of the MTJ layer 320. The magnetic compensation layer 327 can counteract or reduce (e.g., eliminate or partially reduce) the effects of stray magnetic fields generated above the fixed layer 325 by the fixed layer 325. For this purpose, the magnetic compensation layer 327 can have a magnetization direction opposite to that of the fixed layer 325. The exchange bonding layer 326 can be interposed between the fixed layer 325 and the magnetic compensation layer 327 to provide an exchange bond between the fixed layer 325 and the magnetic compensation layer 327. The capping layer 328 can be disposed on top of the variable resistive element and can be used as a hard mask (described below) during patterning of the variable resistive element, while also serving as the upper electrode of the variable resistive element.

[0052] Subsequently, a hard mask layer 329 for patterning the stacked structure can be formed on top of the cover layer 328.

[0053] refer to Figure 3B The stacked structure of MTJ pattern 320A, including cover layer pattern 328A, magnetic compensation layer pattern 327A, exchange bonding layer pattern 326A, fixed layer pattern 325A, tunnel barrier layer pattern 324A and free layer pattern 323A, can be formed by etching the cover layer 328, magnetic compensation layer 327, exchange bonding layer 326, fixed layer 325, tunnel barrier layer 324 and free layer 323 using a hard mask layer 329 as an etching barrier layer.

[0054] As a result, a variable resistor element can be formed, including a lower electrode pattern 321, a cover layer pattern 328A, a magnetic compensation layer pattern 327A, an exchange bonding layer pattern 326A, a fixed layer pattern 325A, a tunnel barrier layer pattern 324A, and a free layer pattern 323A stacked therein.

[0055] Simultaneously, in the etching process used to form the variable resistance element, etching byproducts originating from the etching target can be redeposited on the surface being etched. As a result, after the variable resistance element is patterned, a second spacer 340 originating from the etching byproducts can be formed on the sidewall of the variable resistance element. However, etching byproducts originating from later etched layers (i.e., layers in the lower portion) of the multiple layers of the variable resistance element can form a larger proportion of the spacer 340, while etching byproducts originating from earlier etched layers (i.e., layers in the upper portion) of the multiple layers of the variable resistance element may be almost entirely absent from the spacer 340 (e.g., forming a smaller or minimum proportion of the spacer 340). This is because most of the etching byproducts redeposited during the etching process are removed again as the etching continues. The second spacer 340 can be disposed on at least a portion of the sidewall of the MTJ pattern 320A and can comprise carbon, aluminum oxide, titanium oxide, or tantalum oxide.

[0056] refer to Figure 3C The MTJ etching byproducts 330 can be removed together with the sacrificial layer 315. The sacrificial layer 315 can be a layer designed to be removed together with the MTJ etching byproducts 330, and a dry etching process or a plasma etching process can be performed to remove the sacrificial layer 315. Since the sacrificial layer 315 is formed of a material that has etch selectivity relative to the hard mask pattern 329A, the sacrificial layer 315 and the MTJ etching byproducts 330 accumulated on the sacrificial layer 315 can be selectively removed only during the etching process of the sacrificial layer 315 without damaging the MTJ pattern 320A, which includes the capping layer pattern 328A, the magnetic compensation layer pattern 327A, the exchange bonding layer pattern 326A, the fixed layer pattern 325A, the tunnel barrier layer pattern 324A, and the free layer pattern 323A.

[0057] Most of the sacrificial layer 315 can be removed using dry etching and wet cleaning processes, but a portion of the sacrificial layer 315 can be retained to form a sacrificial layer pattern (not shown) on at least a portion of the spacer 322. This sacrificial layer pattern can structurally support a variable resistor element including an MTJ pattern 320A, which comprises a capping layer pattern 328A, a magnetic compensation layer pattern 327A, an exchange bonding layer pattern 326A, a fixing layer pattern 325A, a tunnel barrier layer pattern 324A, and a free layer pattern 323A. This support can help maintain the physical stability of the variable resistor element, especially after the pattern has been formed.

[0058] refer to Figure 3D , can Figure 3C A second interlayer dielectric layer 335 is formed on the structure. Figure 3CIn cases where the surface of the structure is cleaned using both dry etching and wet cleaning processes, the second interlayer dielectric layer 335 and... Figure 3C The joints between the surfaces of a structure can be (more easily) facilitated or improved.

[0059] The above process can be used to form such as Figure 3D The semiconductor device shown.

[0060] Return to reference Figure 3D The semiconductor device according to embodiments of the present disclosure may include: a lower contact plug 310 disposed on and coupled to a portion of a substrate 300; a first interlayer dielectric layer 305 filling the space between the lower contact plugs 310; a lower electrode pattern 321 coupled to the lower contact plugs 310; a spacer 322 formed on the sidewall of the lower electrode pattern 321; an MTJ pattern 320A coupled to the lower electrode pattern 321; and a second interlayer dielectric layer 335 covering an exchange bonding layer pattern 326A, a magnetic compensation layer pattern 327A, a cover layer pattern 328A, a hard mask pattern 329A, the first spacer 322, the second spacer 340, and their upper surfaces.

[0061] According to embodiments of the present disclosure, a structure can be formed that includes an exchange bonding layer pattern 326A, a magnetic compensation layer pattern 327A, and a capping layer pattern 328A further stacked on the MTJ pattern 320A, and includes a second spacer 340 further formed on the sidewall of the variable resistor element. According to embodiments of the present disclosure, all the advantages described in the above embodiments of the present disclosure can also be obtained. For example, MTJ etching byproducts 330 can be effectively removed to prevent degradation of the magnetoresistive characteristics and reliability of the MTJ element, and to prevent degradation of the interlayer insulation performance and electrical characteristics of the MTJ element. Additionally, the sacrificial layer pattern can structurally support the MTJ pattern 320A and help maintain the physical stability of the MTJ pattern 320A.

[0062] According to embodiments of the present disclosure, semiconductor devices and manufacturing methods thereof can prevent MTJ device failure and significantly improve the performance and reliability of MTJ devices by effectively addressing the problem that byproducts generated after the MTJ etching process accumulate between electrodes and act as bridge sources.

[0063] While this disclosure has been described with reference to specific embodiments, various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Semiconductor memory; The semiconductor memory includes at least one stacked structure, wherein each of the at least one stacked structure includes: Electrode pattern; A magnetic tunnel junction (MTJ) pattern is formed on the electrode pattern. Hard mask pattern, the hard mask pattern being formed on the MTJ pattern; A first spacer is formed on two sidewalls of the electrode pattern; and A sacrificial layer pattern is formed on at least a portion of the first spacer and supports the MTJ pattern and the hard mask pattern.

2. The semiconductor device as claimed in claim 1, wherein, The sacrificial layer pattern includes carbon.

3. The semiconductor device as claimed in claim 2, wherein, The sacrificial layer pattern also includes: Polycrystalline silicon, silicon oxide, silicon nitride, aluminum oxide, or titanium oxide.

4. The semiconductor device as claimed in claim 1, wherein, The first spacer includes: Silicon oxide, silicon nitride, hafnium oxide, tantalum oxide, tantalum nitride, titanium nitride, aluminum oxide, or combinations thereof.

5. The semiconductor device as claimed in claim 1, wherein, The semiconductor memory further includes: An interlayer dielectric layer adapted to cover at least a portion of the MTJ pattern, the hard mask pattern, and the first spacer.

6. The semiconductor device of claim 5, wherein, The interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or a combination thereof.

7. The semiconductor device of claim 1, wherein, The MTJ pattern includes: A free-layer pattern having a variable magnetization direction. A fixed layer pattern having a fixed magnetization direction; and A tunnel barrier layer pattern, wherein the tunnel barrier layer pattern is located between the free layer pattern and the fixed layer pattern.

8. The semiconductor device of claim 7, further comprising: A magnetic compensation layer pattern that at least partially counteracts the effects of stray magnetic fields located above the fixed layer pattern generated by the fixed layer pattern.

9. The semiconductor device of claim 1, further comprising: A second spacer is disposed on at least a portion of the sidewall of the MTJ pattern and comprises carbon, aluminum oxide, titanium oxide, or tantalum oxide.

10. The semiconductor device of claim 1, wherein, The electrode pattern includes: The upper part, having an upper sidewall aligned with the MTJ pattern, and The lower part has a lower sidewall, wherein the lower sidewall is not aligned with the upper part and its width is greater than that of the upper part.

11. The semiconductor device of claim 1, wherein, The hard mask pattern includes a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

12. A method for manufacturing a semiconductor device, comprising: A magnetic tunnel junction (MTJ) layer is formed on top of the sacrificial layer, the sacrificial layer having an electrode pattern embedded therein; A hard mask layer is formed on top of the MTJ layer; The MTJ pattern and the hard mask pattern are formed by etching the MTJ layer and the hard mask layer, wherein the etching byproducts of the MTJ layer are accumulated on the upper surface of the sacrificial layer. The etching byproducts are removed during the removal of the sacrificial layer.

13. The method of claim 12, wherein, The sacrificial layer comprises carbon.

14. The method of claim 13, wherein, The sacrificial layer may also include polysilicon, silicon oxide, silicon nitride, aluminum oxide, or titanium oxide.

15. The method of claim 12, wherein, The etching of the MTJ layer is performed using an ion beam etching (IBE) process.

16. The method of claim 12, wherein, The steps for forming the MTJ layer include sequentially forming a free layer, a tunnel barrier layer, and a fixed layer, and The steps for forming the MTJ pattern include forming a free layer pattern, a tunnel barrier layer pattern, and a fixed layer pattern.

17. The method of claim 16, further comprising: A magnetic compensation layer is formed between the MTJ layer and the hard mask layer, and A magnetic compensation layer pattern is formed between the MTJ pattern and the hard mask pattern by etching the magnetic compensation layer, and the magnetic compensation layer pattern at least partially counteracts the effects of stray magnetic fields generated by the fixed layer pattern.

18. The method of claim 12, wherein, The step of forming the MTJ pattern by etching the MTJ layer includes: A second spacer comprising carbon, aluminum oxide, titanium oxide, or tantalum oxide is formed on at least a portion of the sidewall of the MTJ pattern.

19. The method of claim 12, wherein, The hard mask layer comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, aluminum oxide, hafnium oxide, titanium oxide, and zirconium oxide.

20. The method of claim 12, further comprising: After removing the sacrificial layer and the etching byproducts, an interlayer dielectric layer is formed covering at least a portion of the MTJ pattern and the hard mask pattern.

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