Silicon-based inductive structure and method of manufacturing the same

Abstract

The method for fabricating a silicon-based inductor structure according to the present invention includes a silicon substrate, a first metal layer, a first insulating layer, a second metal layer, and a plurality of conductive pillars. The first metal layer is disposed on the silicon substrate and includes a plurality of first metal segments spaced apart along a first direction. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed above the first insulating layer and includes a plurality of second metal segments spaced apart along the first direction. A plurality of conductive pillars vertically penetrate the first insulating layer, and the first metal segments, second metal segments, and conductive pillars are sequentially and alternately connected to form a continuous three-dimensional spiral structure. This method overcomes the limitation of traditional planar spiral inductors on chip area, achieving higher inductance within the same area and significantly improving the integration density per unit area.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a silicon-based inductor structure and its fabrication method. Background Technology

[0002] Inductors are core passive components in fields such as radio frequency integrated circuits and power management integrated circuits, and their performance directly affects the stability and reliability of the entire circuit system. In radio frequency front-end modules, inductors are often used for impedance matching, resonant circuits, and filtering circuits. Their quality factor (Q value) and self-resonant frequency (SRF) directly determine signal transmission efficiency and bandwidth selectivity. In power management chips, inductors are key components for energy storage and voltage conversion, and their DC resistance (DCR) and saturation current characteristics affect power conversion efficiency and load capacity.

[0003] With the evolution of wireless communication technology towards 5G / 6G and the widespread adoption of IoT devices, integrated circuits are rapidly developing towards higher frequencies, miniaturization, and high-density integration. The continuous increase in operating frequency requires inductors to maintain excellent performance at higher frequencies, while the continuous shrinking of chip area imposes stringent space constraints on the inductor's footprint. Furthermore, modern System-on-Chip (SoC) needs to integrate digital, analog, and radio frequency circuits on the same chip, which requires inductors to be fully compatible with standard CMOS processes to achieve low-cost, large-scale manufacturing.

[0004] However, existing silicon-based inductors mostly employ planar circular or octagonal spiral coil structures. While this design is simple, it has significant limitations in terms of integration with semiconductor processes. On one hand, the planar spiral structure occupies a large chip area, making it difficult to meet the demands of high-density integration. On the other hand, its magnetic field distribution is mainly confined to the coil plane, resulting in low utilization of vertical magnetic coupling and limiting the increase in inductance per unit area. More importantly, traditional inductor structures often require additional process steps or special materials, exhibiting poor compatibility with standard CMOS processes, increasing manufacturing costs and process complexity. Summary of the Invention

[0005] In view of the problems existing in the prior art described above, this application provides a silicon-based inductor structure and its fabrication method, which can solve the problem of poor integration density of traditional inductors.

[0006] To achieve the above and other related objectives, the present invention provides a silicon-based inductor structure, comprising:

[0007] silicon substrate;

[0008] A first metal layer is disposed on a silicon substrate and includes a plurality of first metal segments spaced apart along a first direction;

[0009] A first insulating layer is disposed on a first metal layer;

[0010] The second metal layer is disposed above the first insulating layer and includes a plurality of second metal segments spaced apart along the first direction;

[0011] Multiple conductive pillars are vertically inserted into the first insulating layer. The first metal segment, the second metal segment, and the conductive pillars are alternately connected in sequence to form a continuous three-dimensional spiral structure. The multiple conductive pillars include two edge conductive pillars and multiple intermediate conductive pillars. The two edge conductive pillars are respectively connected to the first metal segment or the second metal segment at the starting point and the ending point of the three-dimensional spiral structure. The multiple intermediate conductive pillars are alternately connected to the first metal segment and the second metal segment.

[0012] Optionally, the materials of the first metal segment, the second metal segment, and the conductive pillar are all selected from any one or more combinations of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti).

[0013] Optionally, the material of the first insulating layer is tetraethyl orthosilicate (TEOS) oxide.

[0014] Optionally, the silicon substrate includes: a plurality of receiving trenches, the number and shape of which are consistent with the number and shape of the first metal segments, for receiving the first metal segments, the upper end surface of which is flush with the upper end surface of the silicon substrate.

[0015] Optionally, the number of second metal segments is n, the number of first metal segments is n+1, two edge conductive pillars are respectively connected to the first metal segments at the start and end positions of the three-dimensional spiral structure, and multiple intermediate conductive pillars alternately connect the first metal segments and the second metal segments.

[0016] Optionally, the number of first metal segments is n, the number of second metal segments is n+1, two edge conductive pillars are respectively connected to the second metal segments at the start and end positions of the three-dimensional spiral structure, and multiple intermediate conductive pillars alternately connect the first metal segments and the second metal segments.

[0017] Optionally, the height of the conductive pillar is between 20 μm and 40 μm.

[0018] Optionally, the widths of the first metal segment, the second metal segment, and the conductive post are all between 0.8 μm and 2 μm.

[0019] Optionally, the thickness of the silicon-based inductor structure is between 120 μm and 200 μm.

[0020] Alternatively, the silicon-based inductor structure also includes:

[0021] A second insulating layer covers the first insulating layer;

[0022] Multiple through holes are vertically inserted into the second insulating layer. The number and shape of the through holes are consistent with the number and shape of the second metal segments to accommodate the second metal segments. The upper surface of the second metal segments is flush with the upper surface of the second insulating layer.

[0023] Optionally, the material of the second insulating layer is tetraethyl orthosilicate (TEOS) oxide.

[0024] Optionally, the first metal segment and the second metal segment at least partially overlap in a direction perpendicular to the silicon substrate.

[0025] Optionally, the silicon-based inductor structure also includes a passivation protective layer covering the second metal layer.

[0026] Another aspect of the present invention provides a method for fabricating a silicon-based inductor structure, comprising the following steps:

[0027] Provide a silicon substrate;

[0028] A first metal layer is disposed on a silicon substrate, the first metal layer comprising a plurality of first metal segments spaced apart along a first direction;

[0029] A first insulating layer is disposed on the first metal layer;

[0030] Multiple conductive pillars are vertically arranged in the first insulating layer;

[0031] A second metal layer is disposed above the first insulating layer. The second metal layer includes multiple second metal segments arranged at intervals along the first direction. The first metal segments, the second metal segments and the conductive pillars are alternately connected in sequence to form a continuous three-dimensional spiral structure. The multiple conductive pillars include two edge conductive pillars and multiple intermediate conductive pillars. The two edge conductive pillars are respectively connected to the first metal segment or the second metal segment at the start and end positions of the three-dimensional spiral structure. The multiple intermediate conductive pillars alternately connect the first metal segment and the second metal segment.

[0032] Optionally, forming a first metal layer on a silicon substrate includes the following steps:

[0033] Multiple receiving trenches are formed on a silicon substrate, the number and shape of which are consistent with the number and shape of the first metal segment;

[0034] A first metal layer is formed by depositing metallic material in a receiving tank.

[0035] The upper surface of the first metal layer is made flush with the upper surface of the silicon substrate by chemical mechanical polishing.

[0036] As described above, the silicon-based inductor structure and its fabrication method provided by the present invention have at least the following beneficial technical effects:

[0037] The silicon-based inductor structure of this invention includes a silicon substrate, a first metal layer, a first insulating layer, a second metal layer, and a plurality of conductive pillars. The first metal layer is disposed on the silicon substrate and includes a plurality of first metal segments spaced apart along a first direction. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed above the first insulating layer and includes a plurality of second metal segments spaced apart along the first direction. A plurality of conductive pillars vertically penetrate the first insulating layer, and the first metal segments, second metal segments, and conductive pillars are sequentially and alternately connected to form a continuous three-dimensional spiral structure. This structure overcomes the limitations of traditional planar spiral inductors on chip area, achieving higher inductance within the same area, significantly improving integration density per unit area, and is suitable for large-scale production of high-frequency integrated circuits.

[0038] Furthermore, the thickness of the silicon-based inductor structure in this embodiment is between 120 μm and 200 μm, which achieves device thinning while ensuring performance, thus meeting the demand for lightweight and thin devices in modern electronic devices. Attached Figure Description

[0039] Figure 1 The diagram shown is a schematic diagram of a silicon-based inductor structure provided in an embodiment of the present invention.

[0040] Figure 2 The diagram shown is a schematic diagram of the structure of a silicon substrate provided in an embodiment of the present invention.

[0041] Figure 3 The diagram shown is a schematic diagram of the structure after forming a receiving trench on a silicon substrate according to an embodiment of the present invention.

[0042] Figure 4 The diagram shows a silicon substrate and a first metal layer provided in an embodiment of the present invention.

[0043] Figure 5 The diagram shown is a schematic diagram of the structure after a first insulating layer is formed on a silicon substrate, as provided in an embodiment of the present invention.

[0044] Figure 6 The diagram shows a silicon substrate, a first metal layer, a first insulating layer, and conductive pillars provided in an embodiment of the present invention.

[0045] Figure 7 The diagram shown is a schematic diagram of the structure after a second insulating layer is provided on the first insulating layer, as provided in an embodiment of the present invention.

[0046] Figure 8 The diagram shown is a schematic diagram of the structure after a through hole is formed on the second insulating layer, as provided in an embodiment of the present invention.

[0047] Figure 9 The flowchart shown is a method for fabricating a silicon-based inductor structure according to an embodiment of the present invention.

[0048] Figure Labels

[0049] 1. Silicon substrate; 11. Receptacle; 2. First metal layer; 21. First metal segment; 3. First insulating layer; 4. Second metal layer; 41. Second metal segment; 5. Conductive pillar; 51. Edge conductive pillar; 52. Middle conductive pillar; 6. Second insulating layer; 61. Through hole. Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0052] Example 1

[0053] This embodiment provides a silicon-based inductor structure, see reference. Figures 1 to 8 It includes a silicon substrate 1, a first metal layer 2, a first insulating layer 3, a second metal layer 4, and multiple conductive pillars 5.

[0054] Reference Figure 1 The thickness of the silicon-based inductor structure ranges from 120 μm to 200 μm, and can be adjusted according to design requirements. In an optional embodiment of this example, the thickness of the silicon-based inductor structure is 160 μm. The thickness of the silicon-based inductor structure in this embodiment achieves device thinning while ensuring performance, meeting the demand for lightweight and thin devices in modern electronic devices.

[0055] The silicon substrate 1 serves as the carrier substrate and is made of high-resistivity silicon material to reduce high-frequency losses.

[0056] Reference Figure 1 and Figure 4A first metal layer 2 is disposed on a silicon substrate 1, including a plurality of first metal segments 21 spaced apart along a first direction. In an optional embodiment of this embodiment, the silicon substrate 1 includes a plurality of receiving trenches 11, the number and shape of which correspond one-to-one with the number and shape of the first metal segments 21, to accommodate the first metal segments 21, with the upper end face of the first metal segment 21 flush with the upper end face of the silicon substrate 1. In this embodiment, a plurality of receiving trenches 11 are first formed on the silicon substrate 1, then the first metal segments 21 are filled into the receiving trenches 11, and then the upper end face of the first metal segment 21 is precisely flush with the upper end face of the silicon substrate 1 by deposition and chemical mechanical polishing (CMP) processes, thereby achieving a planarized surface, which facilitates subsequent processes. The design method of this embodiment effectively isolates and securely embeds the first metal segments 21 in the silicon substrate 1, reducing parasitic effects. In another optional embodiment of this embodiment, the first metal segments 21 are disposed above the silicon substrate 1. Specifically, by depositing a metal layer on the silicon substrate 1 and etching to form a plurality of first metal segments 21 spaced apart along a first direction, the first metal segments 21 and the silicon substrate 1 can be electrically isolated by a thin oxide layer (not shown in the figure).

[0057] The material of the first metal segment 21 is selected from any one or more combinations of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti). The width of the first metal segment 21 is between 0.8 μm and 2 μm to ensure low resistance and good process compatibility.

[0058] Reference Figure 1 and Figure 5 A first insulating layer 3 is disposed on the first metal layer 2, covering the planarized first metal segment 21 and the silicon substrate 1. The first insulating layer 3 is made of tetraethyl orthosilicate (TEOS) oxide material and is formed by plasma-enhanced chemical vapor deposition (PECVD), exhibiting good step coverage and dielectric properties. The stable dielectric constant of TEOS oxide effectively isolates the first metal layer 2 from the subsequently formed second metal layer 4, preventing interlayer crosstalk. The thickness of the first insulating layer 3 is designed according to design requirements and is not limited here. After deposition, the surface of the first insulating layer 3 undergoes chemical mechanical polishing (CMP) planarization to provide a smooth interface for the fabrication of the upper structure.

[0059] Reference Figure 1The second metal layer 4 is disposed above the first insulating layer 3 and includes a plurality of second metal segments 41 spaced apart along the first direction. The material of the second metal segments 41 is selected from any one or more combinations of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti). For example, copper can be used as the dominant material to reduce resistance, or titanium / titanium nitride can be used as a barrier layer in combination with copper. The second metal segments 41 are formed by metal deposition (such as physical vapor deposition or electroplating) and patterning etching processes, and the width of the second metal segments 41 is also between 0.8 μm and 2 μm.

[0060] Continue to refer to Figure 1 Multiple conductive pillars 5 vertically penetrate the first insulating layer 3. The position of the second metal segment 41 corresponds at least partially in the vertical direction to the first metal segment 21 below, so as to achieve precise electrical connection through the conductive pillars 5 penetrating the first insulating layer 3. In this embodiment, the upper end face of the conductive pillar 5 is flush with the upper end face of the first insulating layer 3. The material of the conductive pillar 5 is selected from any one or more combinations of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti). The height of the conductive pillar 5 is between 20 μm and 40 μm. This height range ensures sufficient interlayer isolation thickness to reduce parasitic capacitance and is compatible with the aspect ratio etching capability of standard CMOS processes. The width of the conductive pillar 5 is between 0.8 μm and 2 μm, consistent with the linewidth of the first metal segment 21 and the second metal segment 41, to ensure the process consistency of the overall structure. The cross-sectional shape of the conductive pillar 5 can be circular, square, or other polygonal, and its size selection needs to achieve a balance between resistance, filling difficulty, and process yield.

[0061] The first metal segment 21, the second metal segment 41, and the conductive pillars 5 are alternately connected to form a continuous three-dimensional spiral structure. Specifically, the multiple conductive pillars 5 include two edge conductive pillars 51 and multiple intermediate conductive pillars 52. The two edge conductive pillars 51 are respectively connected to the first metal segment 21 or the second metal segment 41 at the start and end positions of the three-dimensional spiral structure, and the multiple intermediate conductive pillars 52 alternately connect the first metal segment 21 and the second metal segment 41. That is, the lower end of an intermediate conductive pillar 52 is connected to one end of a certain first metal segment 21, and its upper end is connected to one end of an adjacent second metal segment 41; another intermediate conductive pillar 52 connects the other end of the second metal segment 41 to one end of the next first metal segment 21, and so on, forming a reciprocating connection path of "first metal segment - conductive pillar - second metal segment - conductive pillar - first metal segment". This breaks through the limitation of chip area occupied by traditional planar spiral inductors, and can achieve higher inductance in the same area, significantly improving the integration density per unit area.

[0062] In one optional embodiment of this example, refer to Figure 1The number of second metal segments 41 is n, and the number of first metal segments 21 is n+1 (n≥1). At this point, two edge conductive pillars 51 are respectively connected to the first metal segments 21 at the start and end positions of the three-dimensional spiral structure. That is, the entire spiral path begins with the first first metal segment 21, alternately connects to the first metal segment 21 and the second metal segment 41 via the intermediate conductive pillar 52, and finally terminates at the (n+1)th first metal segment 21. This structure makes the first metal layer 2 the starting and ending layer of the path.

[0063] In another optional embodiment of this example, the number of first metal segments 21 is n, and the number of second metal segments 41 is n+1 (n≥1). In this case, two edge conductive pillars 51 are respectively connected to the second metal segments 41 at the start and end positions of the three-dimensional spiral structure. That is, the spiral path begins with the first second metal segment 41, alternately connects to the first metal segment 21 via the intermediate conductive pillar 52, and finally terminates at the (n+1)th second metal segment 41. This scheme makes the second metal layer 4 the starting and ending layer of the path. Both optional schemes achieve three-dimensional stacking and alternating interconnection of the first metal layer 2 and the second metal layer 4. By adjusting the number and configuration of the first metal segments 21 and the second metal segments 41 and the connection positions of the edge conductive pillars 51, different chip layouts and performance requirements can be flexibly adapted to, while maintaining the continuity and integrity of the three-dimensional spiral structure. This design effectively improves the inductance and magnetic coupling efficiency per unit area.

[0064] Reference Figure 1 and Figure 8 The silicon-based inductor structure also includes a second insulating layer 6 and multiple through-holes 61. The second insulating layer 6 covers the first insulating layer 3 and is formed by deposition of TEOS oxide material, serving as interlayer isolation and protection. Multiple through-holes 61 vertically penetrate the second insulating layer 6, with the number and shape of the through-holes matching the number and shape of the second metal segments 41, to accommodate the second metal segments 41. The upper surface of the second metal segments 41 is flush with the upper surface of the second insulating layer 6. Specifically, multiple through-holes 61 are first formed on the second insulating layer 6. Then, the second metal segments 41 are filled into the through-holes 61. Finally, a chemical mechanical polishing (CMP) process is used to precisely flush the upper surface of the second metal segments 41 with the upper surface of the second insulating layer 6, forming a planarized surface. The design of the second insulating layer 6 achieves effective positioning and sidewall isolation of the second metal segments 41.

[0065] Optionally, the silicon-based inductor structure also includes a passivation protection layer (not shown in the figures) covering the second metal layer 4. The passivation protection layer prevents the second metal layer 4 from being corroded by external moisture and contaminants, and provides mechanical protection. The presence of the passivation protection layer further improves the reliability and long-term stability of the silicon-based inductor structure and is compatible with standard CMOS processes.

[0066] Example 2

[0067] This embodiment provides a method for fabricating a silicon-based inductor structure, used to prepare the silicon-based inductor structure described in Embodiment 1, referring to... Figure 9 This includes the following steps:

[0068] S100: Provides a silicon substrate;

[0069] S200: A first metal layer is formed on the silicon substrate, the first metal layer comprising a plurality of first metal segments spaced apart along a first direction;

[0070] S300: A first insulating layer is formed on the first metal layer;

[0071] S400: Multiple conductive pillars are vertically arranged in the first insulating layer;

[0072] S500: A second metal layer is disposed above the first insulating layer. The second metal layer includes a plurality of second metal segments arranged at intervals along the first direction. The first metal segments, the second metal segments and the conductive pillars are sequentially and alternately connected to form a continuous three-dimensional spiral structure. The plurality of conductive pillars include two edge conductive pillars and a plurality of intermediate conductive pillars. The two edge conductive pillars are respectively connected to the first metal segment or the second metal segment at the start and end positions of the three-dimensional spiral structure. The plurality of intermediate conductive pillars are alternately connected to the first metal segment and the second metal segment.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A silicon-based inductor structure, characterized in that, include: silicon substrate; A first metal layer is disposed on the silicon substrate and includes a plurality of first metal segments spaced apart along a first direction; A first insulating layer is disposed on the first metal layer; The second metal layer is disposed above the first insulating layer and includes a plurality of second metal segments spaced apart along the first direction; Multiple conductive pillars are vertically inserted into the first insulating layer. The first metal segment, the second metal segment, and the conductive pillars are sequentially and alternately connected to form a continuous three-dimensional spiral structure. The multiple conductive pillars include two edge conductive pillars and multiple intermediate conductive pillars. The two edge conductive pillars are respectively connected to the first metal segment or the second metal segment at the start and end positions of the three-dimensional spiral structure. The multiple intermediate conductive pillars are alternately connected to the first metal segment and the second metal segment.

2. The silicon-based inductor structure according to claim 1, characterized in that, The materials of the first metal segment, the second metal segment, and the conductive pillar are all selected from any one or more combinations of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and titanium (Ti).

3. The silicon-based inductor structure according to claim 1, characterized in that, The material of the first insulating layer is tetraethyl orthosilicate (TEOS) oxide.

4. The silicon-based inductor structure according to claim 1, characterized in that, The silicon substrate includes a plurality of receiving grooves, the number and shape of which are consistent with the number and shape of the first metal segments, for accommodating the first metal segments, wherein the upper end surface of the first metal segments is flush with the upper end surface of the silicon substrate.

5. The silicon-based inductor structure according to claim 1, characterized in that, The number of the second metal segments is n, the number of the first metal segments is n+1, the two edge conductive pillars are respectively connected to the first metal segments at the start and end positions of the three-dimensional spiral structure, and the multiple intermediate conductive pillars alternately connect the first metal segments and the second metal segments.

6. The silicon-based inductor structure according to claim 1, characterized in that, The number of the first metal segments is n, the number of the second metal segments is n+1, the two edge conductive pillars are respectively connected to the second metal segments at the start and end positions of the three-dimensional spiral structure, and the multiple intermediate conductive pillars alternately connect the first metal segments and the second metal segments.

7. The silicon-based inductor structure according to claim 1, characterized in that, The height of the conductive pillar is between 20 μm and 40 μm.

8. The silicon-based inductor structure according to claim 1, characterized in that, The widths of the first metal segment, the second metal segment, and the conductive pillar are all between 0.8 μm and 2 μm.

9. The silicon-based inductor structure according to claim 1, characterized in that, The thickness of the silicon-based inductor structure is between 120 μm and 200 μm.

10. The silicon-based inductor structure according to claim 1, characterized in that, Also includes: A second insulating layer covers the first insulating layer; Multiple through holes are vertically inserted into the second insulating layer. The number and shape of the through holes are consistent with the number and shape of the second metal segments to accommodate the second metal segments. The upper surface of the second metal segments is flush with the upper surface of the second insulating layer.

11. The silicon-based inductor structure according to claim 10, characterized in that, The material of the second insulating layer is tetraethyl orthosilicate (TEOS) oxide.

12. The silicon-based inductor structure according to claim 1, characterized in that, The first metal segment and the second metal segment at least partially overlap in a direction perpendicular to the silicon substrate.

13. The silicon-based inductor structure according to claim 1, characterized in that, Also includes: A passivation protective layer covers the second metal layer.

14. A method for fabricating a silicon-based inductor structure, characterized in that, Includes the following steps: Provide a silicon substrate; A first metal layer is disposed on the silicon substrate, the first metal layer comprising a plurality of first metal segments spaced apart along a first direction; A first insulating layer is disposed on the first metal layer; Multiple conductive pillars are vertically arranged in the first insulating layer; A second metal layer is disposed above the first insulating layer. The second metal layer includes a plurality of second metal segments arranged at intervals along the first direction. The first metal segments, the second metal segments and the conductive pillars are sequentially and alternately connected to form a continuous three-dimensional spiral structure. The plurality of conductive pillars include two edge conductive pillars and a plurality of intermediate conductive pillars. The two edge conductive pillars are respectively connected to the first metal segment or the second metal segment at the start and end positions of the three-dimensional spiral structure. The plurality of intermediate conductive pillars are alternately connected to the first metal segment and the second metal segment.

15. The method for fabricating a silicon-based inductor structure according to claim 14, characterized in that, Depositing a first metal layer on the silicon substrate includes the following steps: Multiple receiving trenches are formed on the silicon substrate, and the number and shape of the receiving trenches are consistent with the number and shape of the first metal segments; A metallic material is deposited in the receiving tank to form the first metal layer; The upper surface of the first metal layer is made flush with the upper surface of the silicon substrate by a chemical mechanical polishing process.

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