Semiconductor device and method of manufacturing the same

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a lifetime control portion located near a junction between a host layer and a carrier storage layer, where carrier lifetime control may not be applied at the junction between the carrier storage layer and the drift layer. In this way, the hole concentration near the host layer and the carrier storage layer in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the carrier storage layer and the drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Therefore, the reverse recovery performance of the semiconductor device can be improved in diode mode without significantly degrading the performance of the transistor region.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) and diodes are fundamental power semiconductors in inverter circuits, widely used in motor control applications for electric vehicles (EVs), industrial machinery, railway propulsion, and household appliances; power supply applications such as uninterruptible power supplies (UPSs), solar power conditioning systems (PSCs), flexible alternative current transmission systems (FACTS), and EV chargers, or other applications.

[0003] To improve the performance of IGBTs and diodes, a reverse conducting-insulated-gate bipolar transistor (RC-IGBT) integrating the IGBT and diode onto a single semiconductor chip has been proposed. The RC-IGBT allows heat to be dissipated either from the IGBT region to the diode region or vice versa within the same chip. This is because current flows alternately between the IGBT and diode regions, rather than simultaneously in both. This significantly reduces the thermal resistance between the die and the pad. However, improving the electrical performance of the IGBT and diode within the RC-IGBT remains a significant challenge. Summary of the Invention

[0004] This disclosure provides a semiconductor device and a method for manufacturing a semiconductor device, which can improve the electrical performance of the semiconductor device.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution:

[0006] According to a first aspect, a semiconductor device is described. The semiconductor device includes a semiconductor substrate. The semiconductor substrate has a transistor region and a diode region, and includes the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer (CSL) of the first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; and a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer. Each of the plurality of trench portions has a conductive portion inside. The semiconductor substrate includes lifetime control portions extending over both the transistor region and the diode region. The lifetime control portion is defined by a portion but not all of the carrier storage layer and / or at least a portion of the host layer, and includes a lifetime control body, the concentration of which in the lifetime control portion is higher than the concentration of which in the remaining region of the semiconductor substrate.

[0007] Based on this design, the lifetime control section is located near the junction between the body layer of the second conductivity type and the CSL of the first conductivity type. Carrier lifetime control is not required at the junction between the CSL and the drift layer of the first conductivity type. In this way, the hole concentration near the body layer and CSL in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the CSL and drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Therefore, the reverse recovery performance of the semiconductor device can be improved in diode mode without significantly degrading the performance of the transistor region.

[0008] In one possible design, the thickness of the lifetime control portion in the thickness direction of the semiconductor substrate is between 0 μm and the sum of half the thickness of the carrier storage layer and the thickness of the host layer.

[0009] Based on this design, the lifespan control section can have a more flexible thickness range near the CSL and the main body layer.

[0010] In one possible design, the lifetime control portion is obtained by low-temperature annealing within a temperature range of 330°C to 500°C after irradiation of the lifetime control body.

[0011] Based on this design, lattice damage caused by lifetime control volume irradiation in semiconductor substrates can be restored and eliminated through low-temperature annealing.

[0012] According to a second aspect, a semiconductor device including a semiconductor substrate is described. The semiconductor substrate has a transistor region and a diode region. The semiconductor substrate includes the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer of the first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; and a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer. Each of the plurality of trench portions has a conductive portion inside. The semiconductor substrate includes lifetime control portions extending over both the transistor region and the diode region, the lifetime control portions including a first lifetime control portion and a second lifetime control portion. The first lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer, and the second lifetime control portion is defined by a portion of the drift layer at a predetermined distance from the surface of the drift layer opposite to the carrier storage layer. The first lifetime control portion and the second lifetime control portion include lifetime control bodies. The concentration of the lifetime control agent in the first lifetime control portion and the second lifetime control portion is higher than the concentration of the lifetime control agent in the remaining region of the semiconductor substrate.

[0013] Based on this design, the lifetime control portion is located near the junction between the body layer of the second conductivity type and the CSL of the first conductivity type. Carrier lifetime control is not required at the junction between the CSL and the drift layer of the first conductivity type. This reduces the hole concentration near the body layer and CSL in the diode region, resulting in lower reverse recovery losses. Furthermore, the electron concentration near the CSL and drift layer in the transistor region may not change significantly, preventing a decrease in electron injection efficiency in the transistor region. Additionally, a second local carrier lifetime portion is located near the drift layer of the first conductivity type. This may shorten the carrier lifetime of the P / N-junction between the collector layer and the drift layer in the transistor region. Therefore, hole injection in the transistor region can be suppressed, which can improve turn-off performance in the transistor region by reducing the carrier concentration near the collector. The carrier lifetime may also be shortened in the N+ / N-junction between the cathode layer and the drift layer in the diode region. Therefore, electron injection in the diode region can be suppressed, which can improve the reverse recovery loss in the diode region by reducing the carrier concentration near the cathode.

[0014] In one possible design, the thickness of the first lifetime control portion in the thickness direction of the semiconductor substrate is between 0 μm and the sum of half the thickness of the carrier storage layer and the thickness of the host layer.

[0015] Based on this design, the first life control section can have a flexible thickness range near the CSL and the main body layer.

[0016] In one possible design, the thickness of the second lifetime control portion in the thickness direction of the semiconductor substrate is in the range of 0 μm to 30 μm.

[0017] Based on this design, the second lifetime control section can have a flexible range near the drift layer of the first conductive layer.

[0018] In one possible design, the lifetime control portion is obtained by low-temperature annealing within a temperature range of 330°C to 500°C after irradiation of the lifetime control body.

[0019] Based on this design, lattice damage caused by lifetime control volume irradiation in semiconductor substrates can be restored and eliminated through low-temperature annealing.

[0020] According to a third aspect, a method for manufacturing a semiconductor device is provided. The method includes: forming a semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer of the first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each trench portion having a conductive portion inside; and irradiating a lifetime control body on the surface of the semiconductor substrate to form a lifetime control portion extending over both the transistor region and the diode region, wherein the lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer, and includes a lifetime control body, the concentration of the lifetime control body in the lifetime control portion being higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

[0021] Based on this design, after forming the semiconductor substrate, a lifetime control portion is formed near the junction between the host layer of the second conductivity type and the CSL of the first conductivity type by irradiating a lifetime control body. In this way, the hole concentration near the host layer and the CSL in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the CSL and the drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Therefore, the reverse recovery performance of the semiconductor device can be improved in diode mode without significantly degrading the performance of the transistor region.

[0022] According to a fourth aspect, a method for manufacturing a semiconductor device is provided. The method includes: forming a semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer of the first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the plurality of trench portions having a conductive portion inside; and performing lifetime testing on the surface of the semiconductor substrate. The control body is irradiated to form lifetime control portions extending over both the transistor region and the diode region, wherein the lifetime control portions include a first lifetime control portion and a second lifetime control portion, wherein the first lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer, and the second lifetime control portion is defined by a portion of the drift layer at a predetermined distance from the surface of the drift layer opposite to the carrier storage layer, wherein the first lifetime control portion and the second lifetime control portion include a lifetime control body, and the concentration of the lifetime control body in the first lifetime control portion and the second lifetime control portion is higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

[0023] Based on this design, after forming the semiconductor substrate, the first lifetime control portion is formed near the junction between the host layer of the second conductivity type and the CSL of the first conductivity type. Carrier lifetime control is not required at the junction between the CSL of the first conductivity type and the drift layer of the first conductivity type. In this way, the hole concentration near the host layer and the CSL in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the CSL and the drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Additionally, the second lifetime control portion is formed near the drift layer of the first conductivity type. In this way, the carrier lifetime of the P / N-junction between the collector layer and the drift layer in the transistor region may be shortened. Therefore, hole injection in the transistor region can be suppressed, which can improve the turn-off performance in the transistor region by reducing the carrier concentration near the collector. The carrier lifetime may also be shortened in the N+ / N-junction between the cathode layer and the drift layer in the diode region. Therefore, electron injection in the diode region can be suppressed, which can improve the reverse recovery loss in the diode region by reducing the carrier concentration near the cathode.

[0024] In one possible design, after irradiating the surface of the semiconductor substrate with a lifetime control body, the method further includes: performing low-temperature annealing on the semiconductor substrate at a temperature below 500°C and above 330°C to form the lifetime control portion.

[0025] Based on this design, lattice damage caused by lifetime control irradiation in the semiconductor substrate can be recovered after low-temperature annealing, thereby ensuring the formation of an ideal lifetime control section without causing other significant adverse effects.

[0026] In one possible design, the irradiation lifetime controller used to form the lifetime control portion is one or a combination of electrons, protons, helium, oxygen, boron, or phosphorus.

[0027] Based on this design, the lifetime control portion can be obtained through irradiation in various ways, which allows for more options to be used to manufacture semiconductor devices with first and second aspects. Attached Figure Description

[0028] To better understand the various embodiments described, reference should be made to the following detailed description in conjunction with the accompanying drawings, wherein the same numbers throughout the drawings refer to corresponding parts.

[0029] Figure 1 An exemplary application is shown, in which an exemplary 3-phase inverter includes transistors and diodes.

[0030] Figure 2 An exemplary schematic diagram of the current-voltage curves for transistors, diodes, and combinations of transistors and diodes is shown.

[0031] Figure 3 A schematic diagram of a cross-section of an exemplary semiconductor device is shown.

[0032] Figure 4A It shows Figure 3 The image shows an enlarged view of the semiconductor device in the transistor region.

[0033] Figure 4B It shows Figure 3 The image shows an enlarged view of the semiconductor device in the diode region.

[0034] Figure 5A It shows Figure 3 The diagram shows the carrier flow direction in the transistor region of the semiconductor device.

[0035] Figure 5B It shows Figure 3 The diagram shows the carrier flow direction in the diode region of the semiconductor device.

[0036] Figure 6 A schematic cross-sectional view of a semiconductor device having a lifetime control portion according to some embodiments of the present disclosure is shown.

[0037] Figure 7 An exemplary hydrogen ion (i.e. proton) distribution and an exemplary net doping distribution are shown.

[0038] Figure 8 A comparison is shown between the hole density distribution along the thickness direction of the mesa region in transistor mode in an embodiment of this disclosure and the hole density distribution in a semiconductor device without lifetime control.

[0039] Figure 9 The output characteristics of a transistor region in transistor mode in embodiments of this disclosure are shown in comparison with the output characteristics in a semiconductor device without lifetime control.

[0040] Figure 10 A comparison is shown between the hole density distribution along the thickness direction of the mesa region in diode mode in embodiments of this disclosure and the hole density distribution in a semiconductor device without lifetime control.

[0041] Figure 11 The output characteristics of the diode region in diode mode in an implementation of an embodiment of this disclosure are shown in comparison with the output characteristics in a semiconductor device without lifetime control.

[0042] Figure 12 The output characteristics of a semiconductor device in transistor mode according to embodiments of this disclosure are shown in comparison with the output characteristics of a semiconductor device without lifetime control.

[0043] Figure 13 The forward current density shown in the embodiments of this disclosure is 300 A / cm². 2 A comparison of hole density distribution along the thickness direction of the mesa region in transistor mode with hole density distribution in a semiconductor device with lifetime control of 10 μm.

[0044] Figure 14 A schematic cross-section of a semiconductor device according to some embodiments is shown.

[0045] Figure 15 A comparison is shown between the surface carrier density in transistor mode in embodiments of this disclosure and the surface carrier density in a semiconductor device with full lifetime control.

[0046] Figure 16 The output characteristics in transistor mode in the embodiments of this disclosure are shown in comparison with the output characteristics in a semiconductor device with full lifetime control.

[0047] Figure 17 A comparison is shown between the surface carrier density in diode mode in embodiments of this disclosure and the surface carrier density in a semiconductor device with full lifetime control.

[0048] Figure 18 A comparison is shown between the reverse recovery waveform in diode mode and the reverse recovery waveform in a semiconductor device with full lifetime control in embodiments of this disclosure.

[0049] Figure 19 A wafer process flow diagram for manufacturing semiconductor devices according to embodiments of the present disclosure is shown.

[0050] Figure 20 A cross-section of a semiconductor device according to some embodiments is shown. Detailed Implementation

[0051] This document describes numerous details to provide a thorough understanding of the exemplary embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of these specific details, and the scope of the claims is defined only by the features and aspects specifically recited in the claims. Furthermore, well-known processes, components, and materials need not be described exhaustively to avoid obscuring relevant aspects of the embodiments described herein.

[0052] In this disclosure, the term "a" is defined to mean "at least one", that is, unless otherwise stated, these terms do not exclude multiple items.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" and its other forms, such as the third-person singular "comprising" and the participle form "comprising," are interpreted as having an open and inclusive meaning, i.e., "including but not limited to." In the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with one or more embodiments or examples is included in at least one embodiment or example of this disclosure. The illustrative representations of the foregoing terms do not necessarily refer to the same one or more embodiments or examples. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0054] In the following text, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or the number of technical features indicated. Therefore, a feature defined by "first" or "second" may explicitly or implicitly include one or more features. In the description of embodiments of this disclosure, unless otherwise stated, the terms "a / a plurality" and "a plurality" refer to two or more.

[0055] In the description of some embodiments, the terms "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0056] In this disclosure, "at least one" means one or more, and "multiple" means two or more. The term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three cases: only A exists, A and B exist simultaneously, and only B exists, where A and B can be singular or plural. The character " / " generally indicates an "OR" relationship between related objects. "At least one of the following items" or similar expressions refer to any combination of these items, including a single item or any combination of multiple items. For example, "at least one of A, B, and C" includes A, B, C, A and B, A and C, B and C, or A, B, and C; "at least one of A, B, and C" can also be understood as including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0057] In this disclosure, terms such as “substantially,” “generally,” and “about” that modify the value, condition, or characteristic of an exemplary embodiment are to be understood as meaning that the value, condition, or characteristic is defined within tolerances that are acceptable for appropriate operation of the intended application of the exemplary embodiment.

[0058] In various embodiments, for ease of description, the first conductivity type is shown as N-type and the second conductivity type as P-type. However, the first conductivity type can also be P-type and the second conductivity type can also be N-type. In this case, the substrate, layer, region, etc., have opposite polarities.

[0059] Furthermore, in this disclosure, "N" represents N-type and "P" represents P-type. "+" indicates heavy doping (high doping concentration) and "-" indicates light doping (low doping concentration).

[0060] In this disclosure, doping concentration can refer to the concentration of impurities that become donors or acceptors. For example, if the doping concentration of a doped region has a peak, the value of that peak can be used as the doping concentration of that doped region. Similarly, if the concentration distribution of a doped region is substantially uniform, the average doping concentration of that doped region can be used as the doping concentration of that doped region.

[0061] The semiconductor devices described in the various embodiments of this disclosure can be widely used in motor control applications such as electric vehicles (EVs), industrial machinery, railway propulsion, and household appliances; power supply applications such as uninterruptible power supplies (UPS), solar power conditioning systems (PSCs), flexible alternative current transmission systems (FACTS), and EV chargers, or other applications. For example, an inverter circuit may include multiple semiconductor devices described in the various embodiments of this disclosure, and the inverter circuit can generate an alternating current (AC) output with a desired frequency and desired power from a direct current (DC) voltage.

[0062] Figure 1 An exemplary application is shown, in which an exemplary 3-phase inverter includes a transistor 101 and a diode 102. Transistor 101 can control high current and high voltage at collector terminal 101A and emitter terminal 101B by providing a small voltage signal to gate terminal 101C. Diode 102 can allow current to flow in only one direction. Diode 102 is typically used in conjunction with transistor 101 in inverter circuits to allow current to flow in the inverter circuit when the transistor is off and to avoid generating high voltage in the motor inductor; hence it is called a freewheeling diode (FWD). The unit consisting of a pair of anti-parallel transistors and a diode always allows current to flow in the reverse direction (from emitter terminal 101B to collector terminal 101A) and controls current to flow in the forward direction (from collector terminal 101A to emitter terminal 101B), as... Figure 2 As shown.

[0063] Over the past few decades, the performance of transistors and diodes has continuously improved, while their die size and manufacturing cost per ampere have decreased accordingly. However, performance improvements are reaching physical limits. To overcome these limitations, a semiconductor device has been invented that integrates transistors and diodes onto a single semiconductor chip. This semiconductor allows heat generated to be dissipated from the transistor region to the diode region, or vice versa, within the same chip. This is because current flows alternately between the transistor and diode regions, rather than simultaneously in both regions. This significantly reduces the thermal resistance between the die and the pad. Therefore, under the same maximum junction temperature, this semiconductor device has a higher current rating for the same total die area compared to a conventional pair of transistors and diodes.

[0064] In various embodiments of this disclosure, the transistor may be an insulated gate bipolar transistor (IGBT) or other transistors. The diode may be a freewheeling diode (FWD) or other diodes.

[0065] Figure 3 A cross-section of an exemplary semiconductor device is shown. (e.g.) Figure 3 As shown, the semiconductor device 30 may include a semiconductor substrate 31, which may have a transistor region 31A and a diode region 31B. The semiconductor substrate 31 may be a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a nitride semiconductor substrate.

[0066] like Figure 3 As shown, the semiconductor device 30 may further include an insulating layer 32 disposed on one side of the semiconductor substrate 31 and an emitter electrode 33 disposed on one side of the semiconductor substrate 31 and the side of the insulating layer 32 opposite to the semiconductor substrate 31. Furthermore, the semiconductor device 30 may also include a collector electrode 34 disposed on the opposite side of the semiconductor substrate 31. The emitter electrode 33 may be made of a conductive material including metals such as aluminum or aluminum-silicon alloys. The collector electrode 34 may also be made of a conductive material including metals such as aluminum or aluminum-silicon alloys.

[0067] Figure 4A It shows Figure 3 An enlarged view of a local area marked with dashed lines in transistor region 31A. (See attached image.) Figure 3 and Figure 4A As shown, the semiconductor substrate 31 may include a body layer 311 of a second conductivity type (e.g., P-type) extending over both the transistor region 31A and the diode region 31B. The body layer 311 may be in contact with the emitter electrode 33. The body layer 311 may also be referred to as the base region, used to control the conduction and amplification of the transistor region.

[0068] The semiconductor substrate 31 may further include a carrier storage layer (CSL) 312 of a first conductivity type (e.g., N-type) extending over both the transistor region 31A and the diode region 31B, the CSL 312 being disposed on the side of the body layer 311 opposite to the emitter electrode 33. The CSL 312 is used to improve the carrier injection enhanced (IE) effect, thereby reducing the turn-on voltage. The doping concentration of the CSL 312 can be heavily doped, as indicated by the symbol "+".

[0069] The semiconductor substrate 31 may further include a drift layer 313 of a first conductivity type (e.g., N-type) extending over both the transistor region 31A and the diode region 31B, the drift layer 313 being disposed on the side of the CSL 312 opposite to the host layer 311. The doping concentration of the drift layer 313 may be lightly doped. The CSL 312 and the drift layer 313 may have the same dopant, and the doping concentration of the CSL 312 may be higher than that of the drift layer 313.

[0070] The semiconductor substrate 31 may further include a collector layer 314 of a second conductivity type (e.g., P-type) extending on the transistor region 31A, the collector layer 314 being disposed on the side of the drift layer 313 opposite to the CSL 312. The collector layer 314 may be in contact with the collector electrode 34.

[0071] In addition, such as Figure 3 As shown, the semiconductor substrate 31 may further include a plurality of trench portions 315 extending from the side of the semiconductor substrate 31 opposite to the drift layer 313 along the thickness direction of the semiconductor substrate 31, passing through the CSL 312 and the body layer 311. Furthermore, the plurality of trench portions 315 extend in both the transistor region 31A and the diode region 31B. The plurality of trench portions 315 are along a predetermined direction (e.g., Figure 3 The trench portions 315 (as shown in the X direction) are arranged at predetermined intervals. The trench portions 315 may be U-shaped. For example, the trench portions 315 may include a first portion 315A and a second portion 315B extending along a direction perpendicular to the arrangement direction of the plurality of trench portions 315 and parallel to the surface of the semiconductor substrate 31, and a third portion 315C connecting the first portion 315A and the second portion 315B. At least a portion of the third portion 315C is curved.

[0072] The trench portion 315 may include a trench 3151, a trench insulating film 3152, and a conductive portion 3153. The trench insulating film 3152 is arranged to cover the inner wall of the trench 3151. The trench insulating film 3152 insulates the conductive portion 3153 from the semiconductor substrate 31. The trench insulating film 3152 may be formed by semiconductor oxidation or nitriding of the inner wall of the trench portion 315. The conductive portion 3153 is disposed on the inner side of the trench portion 315. In the transistor region 31A, the conductive portion 3153 may be formed as a gate electrode. In the diode region 31B, the conductive portion 3152 may be formed as an emitter electrode. The conductive portion 3153 may be made of a conductive material, such as multi-product silicon (e.g., SiO2). The upper surface of the trench portion 315 is covered by an insulating layer 32. In the upper surface, there may be a source region with a first conductivity type (e.g., N-type) having a heavily doped concentration.

[0073] In this way, when the gate electrode formed in the trench portion 315 is forward biased, an electron inversion layer 316 can be generated on the sidewall of the trench portion 315, and when the gate electrode formed in the trench portion 315 is not forward biased, an electron accumulation layer 317 can be generated on the sidewall of the trench portion 315.

[0074] In this case, such as Figure 3 As shown, the semiconductor substrate 31 includes a mesa region 31C arranged to contact the trench portion 315. The mesa region 31C refers to a portion of the semiconductor substrate 31 sandwiched between two adjacent trench portions 315, and may be the depth from the upper surface of the semiconductor substrate 31 to the deepest bottom of each trench portion 315.

[0075] On the upper surface of the mesa region 31C, the emitter electrode 33 can be arranged to contact the trench portion 31C, or it can be disposed separately from the trench portion 31C. Figure 3 In the example shown, the emitter electrode 33 is arranged to contact the trench portion 31C. Furthermore, a contact region 31D of a second conductivity type (e.g., P-type) with a doping concentration higher than that of the host layer 311 is provided, and this contact region 31D may have an arcuate shape.

[0076] Figure 4B It shows Figure 3 An enlarged view of a portion of diode region 31B marked by dashed lines. (See attached image.) Figure 3 and Figure 4BAs shown, the semiconductor substrate 31 may further include a cathode layer 316 of a first conductivity type (e.g., N-type) extending over the diode region 31B, the cathode layer 316 being disposed on the side of the drift layer 313 opposite to the CSL 312. The cathode layer 316 may be disposed at the same depth as the collector layer 314. In power conversion circuits such as inverters, when the transistor region 31A of the semiconductor device 30 is turned off, the diode region 31B can be used as a freewheeling diode (FWD) that allows reverse-biased return current to flow.

[0077] The following is for reference. Figure 5A and Figure 5B The operation of semiconductor device 31 in transistor mode and diode mode is described.

[0078] See Figure 5A In transistor mode, current flows from collector electrode 34 to emitter electrode 33 in transistor region 31A. It is important to note that when the gate electrode formed in trench portion 315 is forward biased, an electron inversion layer 316 is generated on the outer wall of trench portion 315 in the body layer 311. If the gate electrode is not forward biased, the electron inversion layer 316 disappears. When both collector electrode 34 and gate electrode are forward biased against emitter electrode 33, electrons flow from emitter electrode 33 to source region 31D, the electron inversion layer 316 on the trench sidewall (i.e., body layer 311), CLS 312, drift layer 313, and finally to collector layer 314. Electrons flowing into collector layer 314 then inject holes into drift layer 313.

[0079] In transistor region 31A, in transistor mode, the important junctions are the N / N-junction between CSL 312 and drift layer 313, and the P / N-junction between collector layer 314 and drift layer 313. Furthermore, the electron inversion layer 316 at CSL and drift layer 313 form an N+ / N-junction and play an important role. However, the P / N junction between body layer 311 and CSL 312 is not important because it only collects holes from collector electrode 33 and has almost no impact on device performance in transistor mode.

[0080] Therefore, when the semiconductor device 30 is in forward conduction mode, i.e., in transistor mode, enhancing electron injection from the N / N-junction between CSL 312 and drift layer 313 can achieve a lower on-state voltage drop without increasing turn-off losses. Higher electron injection can result in a higher carrier density in drift layer 313 and improve transistor performance.

[0081] like Figure 5BAs shown, in diode mode, current flows from the emitter (anode) electrode 33 to the collector (cathode) electrode 34 in diode region 31B. When the emitter electrode 33 is forward biased against the collector electrode 34, holes are injected from the host layer 311 into CSL 312, the drift layer 313, and finally into the heavily doped cathode layer 316. Holes flowing into the cathode layer 316 can also allow electrons to be injected from the cathode layer 316 into the drift layer 313. In diode region 31B, the important junctions are the P / N junction between the host layer 311 and CSL 312, and the N+ / N- junction between the cathode layer 316 and the drift layer 313. Therefore, in diode mode, suppressing hole injection from the P / N junction between the host layer 311 and CSL 312 can result in lower reverse peak current, lower power loss, a softer recovery waveform, and a smaller surge voltage during reverse recovery. Lower hole injection can result in a lower carrier density on the side of the drift layer 313 opposite to the cathode layer 316, thus improving diode performance.

[0082] As can be seen, transistors may exhibit better performance when electron injection from the surface cells is enhanced, because transistors tend to employ higher carrier densities near the surface region to better balance on-state voltage drop and turn-off losses. On the other hand, diodes may exhibit better performance when hole injection from the surface cells is suppressed, because diodes tend to employ lower carrier densities near the surface region to better balance forward voltage drop and soft recovery characteristics.

[0083] To find a trade-off between transistor and diode performance, carrier lifetime control methods are commonly used. These methods can affect hole injection in diode mode and electron injection in transistor mode. In other words, by introducing lifetime killers to shorten the carrier lifetime of the junction, both hole and electron injection are reduced.

[0084] Some semiconductor devices employ carrier lifetime control methods such as electron irradiation, proton irradiation, or helium irradiation. These high-energy particle irradiation techniques shorten the carrier lifetime in power devices, acting as lifetime killers. For example, electron irradiation uniformly reduces carrier lifetime across the entire device region, thus improving diode performance but degrading transistor performance because it simultaneously reduces electron injection in transistor mode and hole injection in diode mode. Proton and helium irradiation locally control carrier lifetime. Irradiating the front side of a semiconductor device (i.e., the emitter electrode side) with protons or helium can improve diode performance but degrade transistor performance because the entire surface cell region, including the P / N junction and N / N-junction, is affected by a common local lifetime control (LLC) covering several micrometers or tens of micrometers along the thickness direction of the semiconductor device. LLC located on the back side (i.e., the collector electrode side) reduces the carrier density on the back of the drift layer, improving transistor performance but not diode performance.

[0085] Therefore, it is difficult to improve the electrical performance of semiconductor devices in both diode and IGBT modes. Typically, the performance of the transistor region is improved at the expense of the diode region, or vice versa. Due to the influence of traditional carrier lifetime control techniques on carrier distribution, the overall electrical performance of semiconductor devices may need to be improved for both transistors and diodes without affecting the performance of either individual transistor or diode.

[0086] In view of this, some embodiments of the present disclosure provide a semiconductor device. This semiconductor device includes a lifetime control portion located near the junction between the host layer and the CSL, where carrier lifetime control may not be performed at the junction between the CSL and the drift layer. In this way, the hole concentration near the host layer and CSL in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the CSL and drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Therefore, the reverse recovery performance of the semiconductor device can be improved in diode mode without significantly degrading the performance of the transistor region.

[0087] Figure 6 A cross-section of a semiconductor device according to some embodiments is shown. Figure 6As shown, the semiconductor device 60 includes a semiconductor substrate 61 having a transistor region 61A and a diode region 61B. The semiconductor substrate 61 includes the following portions extending on both the transistor region 61A and the diode region 61B: a drift layer 613 of a first conductivity type; a carrier storage layer (CSL) 612 of a first conductivity type disposed on one side of the drift layer 613; a host layer 611 of a second conductivity type disposed on the side of the carrier storage layer 612 opposite to the drift layer 613; and a plurality of trench portions 615 extending from the side of the semiconductor substrate 61 opposite to the drift layer 613 along the thickness direction of the semiconductor substrate 61 through the CSL 612 and the host layer 611. Each of the plurality of trench portions 615 has a conductive portion 6153 inside.

[0088] The descriptions of components such as the main body layer 611, CSL 612, drift layer 613, and multiple trench portions 615 are as described in the relevant descriptions herein and will not be repeated here. Furthermore, in these embodiments, for example, the first conductivity type is N-type and the second conductivity type is P-type.

[0089] In some embodiments, the semiconductor substrate 61 includes a lifetime control portion 61E extending over both the transistor region 61A and the diode region 61B. The lifetime control portion 61E is defined by a portion but not all of the CSL 612 and / or at least a portion of the body layer 611, and includes a lifetime control body. The concentration of the lifetime control body in the lifetime control portion 61E is higher than the concentration of the lifetime control body in the remaining regions of the semiconductor substrate 61.

[0090] Based on this design, the lifetime control section 61E is located near the junction between the second conductivity type body layer 611 and the first conductivity type CSL 612, while carrier lifetime control is not required at the junction between the first conductivity type CSL 612 and the first conductivity type drift layer 613. In this way, the hole concentration near the body layer 611 and CSL 612 in the diode region 61B can be reduced, resulting in lower reverse recovery losses. Furthermore, the electron concentration near CSL 612 and drift layer 613 in the transistor region 61A may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region 61A. Therefore, the reverse recovery performance of the semiconductor device 60 can be improved in diode mode without significantly degrading the performance of the transistor region.

[0091] For example, the life control unit 61E may exist in a part of CSL 612, a part of main body layer 611, the entire main body layer 611, both a part of CSL 612 and a part of main body layer 611, or both a part of CSL 612 and the entire main body layer 611, but may not exist in the entire CSL 612, may not exist in the entire CSL 612 and a part of main body layer 611, or may not exist in the entire CSL 612 and the entire main body layer 611.

[0092] For example, the lifetime control agent can be helium, protons (e.g., hydrogen ions), boron, etc., which is implanted into a predetermined depth in the semiconductor substrate 61, i.e., in the lifetime control portion 61E. By implanting helium, protons (e.g., hydrogen ions), boron, etc., crystal defects can be formed inside the semiconductor substrate 61. The crystal defects can trap charge carriers, thereby shortening the charge carrier lifetime and achieving lifetime control.

[0093] Therefore, the lifetime control section 61E can control the lifetime of charge carriers, including electrons and holes, and the carrier lifetime can be locally controlled using conventional techniques such as helium or proton irradiation. For example, the lifetime control section 61E (which can be a shallow and narrow short-lifetime region) can be formed using low accelerating energies below 1 MeV, because low-energy ion irradiation has a narrow range of lattice damage regions, thus avoiding shortening the carrier lifetime in other layers.

[0094] Figure 7 An exemplary hydrogen ion (i.e., proton) distribution and an exemplary net doping distribution are shown. Figure 7 As shown, the solid line represents the acceleration energy of 180 keV and 1 × 10⁻⁶ kilovolts. 12 cm -2 The distribution of hydrogen ions along the thickness direction of the semiconductor substrate 61 at the center of the mesa region 61C (representing the concentration of the lifetime control body) is shown by the irradiated hydrogen. The dashed line shows the net doping distribution along the thickness direction (representing the doping concentration of the host layer 611 and CSL 612). Hydrogen ions are located in a portion of the host layer 611 and a portion of CSL 612. After irradiation, protons collide with lattice silicon atoms, and silicon atoms are kicked out of their fixed positions in the lattice. The kicked-out silicon atoms also collide with other lattice silicon atoms, and then more silicon atoms are kicked out. Finally, many vacancies are formed in the fixed positions where silicon atoms were originally present in the lattice. After heat treatment, these vacancies and other impurity complexes act as carrier lifetime killers, which may enhance electron-hole recombination during device operation.

[0095] The concentration of the lifetime control medium can be the density of crystal defects formed by injecting helium, protons (such as hydrogen ions), boron, etc. If the density of crystal defects is basically uniform, the average density of crystal defects can be used as the concentration of the lifetime control medium.

[0096] The concentration of the lifetime control medium can be represented by a lifetime value. The lifetime value represents the lifetime of charge carriers; the longer the charge carrier lifetime, the higher the lifetime value. Therefore, the higher the concentration of the lifetime control medium, the shorter the charge carrier lifetime, and the lower the charge carrier value. In this way, the lifetime value of the remaining region of the semiconductor substrate 61 is higher than the lifetime value in the lifetime control portion 61E.

[0097] The arrangement of the semiconductor device 60 is illustrated below by giving an example of lifetime control of the remaining region of the semiconductor substrate 61 and lifetime control of the lifetime control section 61E.

[0098] In some embodiments, the lifetime control portion 61E is defined by a portion, but not all, of the CSL 612 and / or at least a portion of the body layer 611. The lifetime of the remaining region of the semiconductor substrate 61 is not controlled. For example, the lifetime value of the remaining region of the semiconductor substrate 61 is 10 μs, and the lifetime value of the lifetime control portion 61E is 2 ns.

[0099] In some examples, the thickness of the lifetime control portion 61E in the thickness direction of the semiconductor substrate 61 is between 0 μm and no more than half the thickness of CSL 612 plus the thickness of the host layer 611.

[0100] For example, when the lifetime control portion 61E is present in a portion of CSL 612, the thickness of the lifetime control portion 61E can be in the range of 0 μm to half the thickness of CSL 612. When the lifetime control portion 61E is present in the main body layer 611, the thickness of the lifetime control portion 61E can be in the range of 0 μm to the thickness of the main body layer 611. When the lifetime control portion 61E is present in both a portion of CSL 612 and the main body layer 611, the thickness of the lifetime control portion 61E can be in the range of 0 μm to no more than half the thickness of CSL 612 plus the sum of the thickness of the main body layer 611.

[0101] For example, such as Figure 6 As shown, the semiconductor substrate 61 has a lifetime control portion 61E defined by a portion of the host layer 611 and a portion of the CSL 612. The lifetime control portion 61E has a total thickness of 1.0 μm along the thickness direction of the semiconductor substrate 61. The portion of the host layer 611 has a thickness of 0.2 μm, and the portion of the CSL 612 has a thickness of 0.8 μm. The lifetime control portion 61E has a lifetime value of 2 ns, while the lifetime value of the remaining region of the semiconductor substrate 61 is as long as 10 μs when the lifetime is not controlled.

[0102] refer to Figures 8 to 11 This is illustrated by comparing its performance with that of semiconductor devices without lifetime control. Figure 6The performance of the semiconductor device 60 shown is illustrated. In this case, the transistor can be an IGBT, the diode can be a freewheeling diode, and the semiconductor device 60 can be an RC-IGBT.

[0103] When the semiconductor device 60 operates in transistor mode as described in the embodiments of this disclosure, holes enter the mesa region 61C between two adjacent trench portions 615 from the collector electrode 62. Significant hole-electron recombination does not occur until the holes reach the highly doped CSL 612 and then the lifetime control portion 61E, thus maintaining a large hole current density at the N / N-junction between the CSL 612 and the drift layer 613. The N / N-junction serves as a good electron injector. When a large hole current flows into the CSL 612, the electrons injected into the drift layer 613 are enhanced due to the forward bias of the N / N-junction. When a sufficient hole current density is provided in the mesa region 61C, the electron inversion layer formed on the sidewalls of the trench portion 615 can also serve as a good electron injector.

[0104] Figure 8 A comparison is shown between the hole density distribution along the thickness direction of the mesa region 61C in transistor mode in an embodiment of this disclosure and the hole density distribution in a semiconductor device without lifetime control. Figure 8 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device without lifetime control. From Figure 8 As can be seen, in transistor mode, the carrier density below CSL 612 in the embodiments of this disclosure is as high as that of a semiconductor device without lifetime control, because the carrier lifetime near the N / N-junction may not be shortened, so the electron injection effect may not decrease.

[0105] Figure 9 The output characteristics of transistor region 61A in transistor mode according to an embodiment of this disclosure are shown in comparison with the output characteristics in a semiconductor device without lifetime control. For example... Figure 9 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device without lifetime control. From Figure 9 As can be seen, in transistor mode, the output characteristics are almost indistinguishable between the embodiments of this disclosure and semiconductor devices without lifetime control, because carrier lifetime can remain unshortened near the N / N-junction and can be shortened only near the P / N junction between the body layer 611 and CSL 612. Therefore, precisely designed lifetime control techniques can avoid degradation of electron injection efficiency and transistor output performance.

[0106] In diode mode, electrons can be injected from the cathode layer (i.e., diode layer 616) into the drift layer 613 and flow into the P / N junction between the main layer 611 and CSL 612. Since the electron current flowing into the main layer 611 can be reduced by a shorter carrier lifetime, the forward bias applied to the P / N junction can be reduced.

[0107] Figure 10 A comparison is shown between the hole density distribution along the thickness direction of the mesa region 61C in diode mode in an embodiment of this disclosure and the hole density distribution in a semiconductor device without lifetime control. Figure 10 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device without lifetime control. From Figure 10 As can be seen, in the embodiments of this disclosure, hole injection from the P / N junction is suppressed, and in the implementation of the embodiments of this disclosure, the hole density near the junction can be significantly reduced.

[0108] Figure 11 The output characteristics of diode region 61B in diode mode in an implementation of an embodiment of this disclosure are shown in comparison with the output characteristics in a semiconductor device without lifetime control. For example... Figure 11 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device without lifetime control. From Figure 11 As can be seen, there is a clear difference between the semiconductor device in the embodiments of this disclosure and a semiconductor device without lifetime control, because there is no shortening of carrier lifetime near the N / N-junction between CSL 612 and drift layer 613, and the shortening of carrier lifetime only occurs near the P / N junction between body layer 611 and CSL 612. Therefore, a precisely designed lifetime control technique may promote a decrease in hole injection efficiency, thereby improving diode output performance.

[0109] refer to Figure 12 and Figure 13 This is illustrated by comparing its performance with that of a semiconductor device with a lifetime control of 10 μm. Figure 6 The performance of the semiconductor device 60 shown is illustrated. In this case, the transistor can be an IGBT, the diode can be a freewheeling diode, and the semiconductor device can be an RC-IGBT. As a comparative example, the semiconductor device can have a lifetime control section with a thickness of 10 μm and a lifetime value of 200 ns.

[0110] Figure 12 A comparison is shown between the output characteristics of a semiconductor device 60 in transistor mode according to an embodiment of this disclosure and the output characteristics of a comparative semiconductor device. For example... Figure 12As shown, solid lines illustrate the results of implementing embodiments of this disclosure, while dashed lines illustrate the results of achieving a semiconductor device with a lifetime control of 10 μm. From Figure 12 It can be seen that the semiconductor device with a lifetime control of 10 μm has a higher on-state voltage. The reason is as follows. As described above, for the semiconductor device 60 in transistor mode according to an embodiment of this disclosure, holes are injected from the collector layer 614 into the drift layer 613 and flow into the N / N-junction between CSL 612 and drift layer 613, where the carrier lifetime is not shortened. Therefore, the electron injection efficiency from CSL 612 is improved. However, due to the 10 μm lifetime control, the carrier lifetime around the N / N-junction between CSL 612 and drift layer 613 in the comparative semiconductor device may be shortened, and thus the electron injection efficiency may decrease. Therefore, the on-state voltage may increase.

[0111] Figure 13 The forward current density shown in the embodiments of this disclosure is 300 A / cm². 2 A comparison of the hole density distribution along the thickness direction of the mesa region 61C in transistor mode with the hole density distribution in a semiconductor device with a lifetime control of 10 μm. For example... Figure 13 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device with a lifetime control of 10 μm. In the implementation of embodiments of the present disclosure, carrier lifetime is controlled only near the P / N junction, thus avoiding undesirable signs of carrier density reduction. However, the semiconductor device with a lifetime control of 10 μm exhibits a significantly lower carrier density than semiconductor device 60 of embodiments of the present disclosure. This is because when carrier lifetime is controlled across the entire CSL 612 and a portion of the drift layer 613, the carrier density in the drift layer 613 can be significantly reduced, particularly around the substrate surface.

[0112] In some other embodiments, the lifetime control portion 61E is defined by a portion but not all of the CSL 612 and / or at least a portion of the body layer 611, and includes a lifetime control body of a first concentration. The remaining region of the semiconductor substrate 61 includes a lifetime control body of a second concentration. The first concentration is higher than the second concentration.

[0113] For a description of the life control section 61E, please refer to the relevant description, which will not be repeated here.

[0114] In this case, for example, the lifetime control section 61E can have a lifetime value of 2 ns, and the lifetime value of the remaining region of the semiconductor substrate 61 can be as long as 200 ns by uniform lifetime quenchers such as electron irradiation.

[0115] Figure 14A schematic cross-section of a semiconductor device according to some embodiments is shown. Figure 14 As shown, the lifetime control portion 141E is defined by a portion of the host layer 1411 and a portion of the CSL 1412. The lifetime control portion 141E has a total thickness of 1.8 μm along the thickness direction of the semiconductor substrate 141. A portion of the host layer 1411 has a thickness of 0.3 μm, and a portion of the CSL 1412 has a thickness of 1.5 μm. The lifetime control portion 141E has a lifetime value of 2 ns, and through uniform lifetime quenching agents such as electron irradiation, the lifetime value of the remaining region of the semiconductor substrate 141 can reach up to 200 ns.

[0116] For example, such as Figure 14 As shown, the thickness of the main layer 1411 can be 1 μm, the thickness of CSL 1412 can be 3 μm, the depth of the trench portion 1415 can be 5 μm, and the width of the mesa region 141C can be 0.5 μm. It should be noted that these parameters are just examples; other parameters are acceptable.

[0117] refer to Figures 15 to 18 This is illustrated by comparing its performance with that of semiconductor devices with full-lifetime control. Figure 14 The performance of the semiconductor device 140 is shown. In this case, the transistor can be an IGBT, the diode can be a freewheeling diode, and the semiconductor device 140 can be an RC-IGBT. The semiconductor device with full lifetime control can have a lifetime control section with a thickness of 10 μm and a lifetime value of 200 ns.

[0118] Figure 15 A comparison is shown between the surface carrier density in transistor mode in an implementation of embodiments of this disclosure and the surface carrier density in a semiconductor device with full lifetime control. For example... Figure 15 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device with full lifetime control. From Figure 15 It can be seen that there is no difference in the carrier density distribution between the two. This is because the carrier lifetime of the semiconductor device of the embodiments of this disclosure and the carrier lifetime of the semiconductor device with full lifetime control are the same in the main part of CSL 1412 and throughout the entire drift layer 1413. For the semiconductor device of the embodiments of this disclosure and the semiconductor device with full lifetime control, sufficient carriers are accumulated in the drift layer 1413 and high conductivity is maintained. Then, as Figure 16 As shown, the transistor-mode output performance can be the same for both devices. Figure 16 In the diagram, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device with full lifetime control. For example... Figure 12 and Figure 16 As shown, the on-state voltage is higher than that of the semiconductor device in the above embodiment because of the additional uniform lifetime control.

[0119] Figure 17 A comparison is shown between the surface carrier density in diode mode in embodiments of this disclosure and the surface carrier density in a semiconductor device with full lifetime control. For example... Figure 17 As shown, solid lines illustrate the results of implementing embodiments of the present disclosure, while dashed lines illustrate the results of implementing a semiconductor device with full lifetime control. Compared to a semiconductor device with full lifetime control, the surface carrier density can be well suppressed in the diode mode of the implementation of embodiments of the present disclosure because the P / N junction region is densely lifetime-controlled. Therefore, the number of carriers stored on the surface side may be reduced during reverse conduction in diode mode.

[0120] Figure 18 A comparison of reverse recovery waveforms is shown, where solid lines represent the results of implementing embodiments of the present disclosure, and dashed lines represent the results of implementing a semiconductor device with full lifetime control. During reverse recovery operation, the upper and lower arms of the half-bridge circuit use the same type of semiconductor device. Due to the shortened carrier lifetime, reduced stored charge in the base region, and accelerated loss of stored charge during reverse recovery, the reverse recovery peak current of the implementations of the embodiments of the present disclosure is significantly lower than that of the semiconductor device with full lifetime control. This can result in lower reverse recovery losses and a softer recovery waveform for the implementations of the embodiments of the present disclosure. Due to the soft recovery characteristics, surge voltage and voltage oscillations can be well suppressed for the semiconductor devices of the implementations of the embodiments of the present disclosure. As described above, this ideal diode performance can be obtained without sacrificing transistor performance.

[0121] In some embodiments, the lifetime control portion 61E is obtained by low-temperature annealing in a temperature range of 330°C to 500°C after irradiation of the lifetime control body.

[0122] Based on this design, lattice damage caused by lifetime control volume irradiation in semiconductor substrates can be restored and eliminated through low-temperature annealing.

[0123] In these embodiments, the doping concentration of CSL 612 gradually decreases with increasing depth, thus eliminating the presence of a distinct N / N-junction between CSL 612 and drift layer 613. In this case, the boundary location of CSL 612 can be defined as the position where the net doping density of CSL 612 is ten times the net doping density of drift layer 613. The doping concentration of drift layer 613 can be 7 × 10⁻⁶. 13 cm -3Then, the CSL boundary position, i.e., the N / N-junction position, can be 4.3 μm, at which point the doping concentration in CSL 612 is 7 × 10⁻⁶. 14 cm -3 Since lattice damage caused by helium or proton irradiation can be completely recovered and eliminated through high-temperature annealing processes above 450°C, the irradiation process must be performed after all high-temperature treatment processes have been completed. Particle irradiation can be performed before or after surface metal deposition.

[0124] Carrier lifetime can also be locally controlled using techniques other than helium or proton irradiation. For example, boron implantation following cryogenic annealing below 450°C can be used as a local lifetime control method because lattice damage caused by boron implantation cannot be fully recovered by such cryogenic annealing, and it also acts as a lifetime choke only locally in the host layer 611. Platinum implantation or sputtering, followed by a high-temperature diffusion process at around 900°C, can also be used for local lifetime control because platinum tends to accumulate near the surface.

[0125] The above description has introduced semiconductor devices; the following will combine... Figure 19 This section will introduce the method for manufacturing this semiconductor device.

[0126] The method of manufacturing the semiconductor device includes: forming a semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer of a first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each trench portion having a conductive portion inside, wherein a lifetime control body is irradiated on the surface of the semiconductor substrate to form a lifetime control portion extending over both the transistor region and the diode region, wherein the lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer, and includes a lifetime control body, the concentration of the lifetime control body in the lifetime control portion being higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

[0127] Based on this design, after the semiconductor substrate is formed, the lifetime control portion is located near the junction between the host layer of the second conductivity type and the CSL of the first conductivity type. Carrier lifetime control is not required at the junction between the CSL of the first conductivity type and the drift layer of the first conductivity type. In this way, the hole concentration near the host layer and CSL in the diode region can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near the CSL and drift layer in the transistor region may not change significantly, which avoids a decrease in electron injection efficiency in the transistor region. Therefore, the reverse recovery performance of the semiconductor device can be improved in diode mode without significantly degrading the performance of the transistor region.

[0128] In some embodiments, the method for manufacturing a semiconductor device may utilize Figure 19 The wafer fabrication process is illustrated. For example, after the wafer fabrication process begins, P-layers and N-layers are formed at approximately 1150°C through ion implantation and thermal diffusion, thereby forming the host layer, CSL layer, and drift layer of the semiconductor substrate. Subsequently, trench etching is performed on the P-layers and N-layers to form trenches. Then, gate oxidation at 900°C, polysilicon filling at 600°C, and interlayer oxide deposition at 800°C are performed on the trenches to form an interlayer insulating film. Furthermore, the thermal oxidation process for forming the trench insulating film can utilize a heated synthesis oxidation method, which uses water vapor as the oxidizing agent. Therefore, when using thermal oxidation, a trench insulating film containing a high moisture content can be formed. After forming the trenches with the interlayer insulating film, contact etching and P-type dopant implantation are performed to achieve good electrical contact between the emitter electrode and the P-type silicon. Activation annealing at 900°C is performed first to form a highly doped P-type region, followed by front-side metal deposition to form the emitter electrode in the active region and a field plate in the edge termination region. Then, metal annealing at 450°C and passivation film deposition at 400°C are performed to eliminate lattice damage caused by proton irradiation. A polyimide coating is then applied to provide good protection for the edge termination region. Polyimide curing at 380°C is performed to obtain better protective film performance. Backside metal deposition is then performed to form the current collector electrode. It should be noted that proton irradiation can be performed after activation annealing, frontside metal deposition, metal annealing, or passivation film deposition to form lifetime control sections with lattice damage.

[0129] The above description has been combined Figure 4A and Figures 4B to 19 This paper introduces semiconductor devices and their manufacturing methods. The following section will combine... Figure 20 Introducing another type of semiconductor device.

[0130] Figure 20 A cross-section of a semiconductor device according to some embodiments is shown. Figure 20As shown, the semiconductor device 200 includes a semiconductor substrate 201. The semiconductor substrate 201 has a transistor region 201A and a diode region 201B. The semiconductor substrate 201 includes the following portions extending on both the transistor region 201A and the diode region 201B: a drift layer 2013 of a first conductivity type; a carrier storage layer (CSL) 2012 of a first conductivity type disposed on one side of the drift layer 2013; a host layer 2011 of a second conductivity type disposed on the side of the carrier storage layer 2012 opposite to the drift layer 2013; and a plurality of trench portions 2015 extending from the side of the semiconductor substrate 201 opposite to the drift layer 2013 along the thickness direction of the semiconductor substrate 201 through the CSL 2012 and the host layer 2011. Each of the plurality of trench portions 2015 has a conductive portion 2015 inside.

[0131] The descriptions of components such as the main body layer 2011, CSL 2012, drift layer 2013, and multiple trench portions 2015 are as described in the relevant descriptions herein and will not be repeated here. It should be noted that these embodiments focus on describing the differences from the embodiments described above; the similarities are the same as in the embodiments described above and will not be repeated here. Furthermore, in these embodiments, for example, the first conductivity type is N-type and the second conductivity type is P-type.

[0132] In some embodiments, the semiconductor substrate 201 includes lifetime control portions 201E extending over both transistor region 201A and diode region 201B. The lifetime control portions 201E include a first lifetime control portion 201E1 and a second lifetime control portion 201E2. The first lifetime control portion 201E1 is defined by a portion of CSL 2012 and / or at least a portion of the host layer 2011. The second lifetime control portion 201E2 is defined by a portion of drift layer 2013 at a predetermined distance from the surface of drift layer 2013 facing away from CSL 2012. The first lifetime control portions 201E1 and the second lifetime control portions 201E2 include lifetime control bodies, the concentration of which is higher than the concentration of lifetime control bodies in the remaining regions of the semiconductor substrate 201.

[0133] Based on this design, the first lifetime control section 201E1 is located near the junction between the second conductivity type body layer 2011 and the first conductivity type CSL 2012, while carrier lifetime control is not required at the junction between the first conductivity type CSL 2012 and the first conductivity type drift layer 2013. In this way, the hole concentration near the body layer 2011 and CSL 2012 in diode region 201B can be reduced, thereby achieving lower reverse recovery losses. Furthermore, the electron concentration near CSL 2012 and drift layer 2013 in transistor region 201A may not change significantly, which avoids a decrease in electron injection efficiency in transistor region 201A. Additionally, the second lifetime control section 201E2 is located close to the first conductivity type drift layer 2013. In this way, the carrier lifetime of the P / N-junction between the collector layer and drift layer in the transistor region may be shortened. Therefore, hole injection in the transistor region can be suppressed, which can improve the turn-off performance in the transistor region by reducing the carrier concentration near the collector. In the N+ / N- junction between the cathode layer and the drift layer in the diode region, carrier lifetime may also be shortened. Therefore, electron injection in the diode region can be suppressed, which can improve the reverse recovery loss in the diode region by reducing the carrier concentration near the cathode.

[0134] The description of the first life control section 201E1 can be found in the description of the life control section 61E above, and will not be repeated here.

[0135] In some embodiments, the lifetime of the remaining region of the semiconductor substrate 201 (i.e., excluding the first lifetime control portion and the second lifetime control portion) is not controlled. For example, the lifetime of the remaining region of the semiconductor substrate 201 is 10 μs, the lifetime of the first lifetime control portion 201E1 is 2 ns, and the lifetime of the second lifetime control portion 201E2 is 200 ns. It should be noted that the carrier lifetime of the N+ / N- junction between the cathode layer and the drift layer in the diode region is shortened too much, making reverse recovery of the diode more difficult and generating a higher reverse surge voltage. However, in the embodiments of this disclosure, the second lifetime control portion 201E2 is defined by a portion of the drift layer 2013 at a predetermined distance from the surface of the drift layer 2013 facing away from the CSL 2012, and the lifetime of the second lifetime control portion 201E2 is 200 ns, thus the second lifetime control portion can have appropriate lifetime control.

[0136] In some embodiments, the thickness of the first lifetime control portion 201E1 in the thickness direction of the semiconductor substrate 201 is within the range of 0 μm to no more than half the thickness of the carrier storage layer 2012 and the sum of the thickness of the main layer 2011.

[0137] For a description of the thickness of the first life control unit 201E1, please refer to the description of the thickness of the life control unit 61E above, and it will not be repeated here.

[0138] For example, such as Figure 20 As shown, the first lifetime control portion 201E1 is defined by a portion of the main body layer 2011 and a portion of the CSL 2012. The first lifetime control portion 201E1 has a total thickness of 1.8 μm along the thickness direction of the semiconductor substrate 201. A portion of the main body layer 2011 has a thickness of 0.3 μm, and a portion of the CSL 2012 has a thickness of 1.5 μm. The distance from the top of the first lifetime control portion 201E1 to the upper surface of the semiconductor substrate 201 can be 0.7 μm, and the distance from the bottom of the first lifetime control portion 201E1 to the upper surface of the semiconductor substrate 201 can be 2.5 μm. The first lifetime control portion 201E1 has a lifetime value of 2 ns.

[0139] In some embodiments, the thickness of the second lifetime control portion 201E2 in the thickness direction of the semiconductor substrate 201 is in the range of 0 μm to 30 μm.

[0140] For example, Figure 20 The second lifetime control section 201E2 of the semiconductor device 200 shown has a thickness of 5 μm in the thickness direction of the semiconductor substrate 201. The distance from the bottom of the second lifetime control section 201E2 to the bottom surface of the semiconductor substrate 201 can be 0 μm, and the distance from the top of the second lifetime control section 201E2 to the bottom surface of the semiconductor substrate 201 can be 5 μm.

[0141] Under the control of the first lifetime control section 201E1, holes can enter the front mesa region 201C from the collector layer 2014 in transistor mode. Significant hole-electron recombination does not occur until the holes reach the highly doped CSL 2012 and then the first lifetime control section 201E1, thus maintaining a large hole current density at the N / N-junction between CSL 2012 and drift layer 2013. When a large hole current flows into CSL 2012, the electrons injected into the drift layer 2013 are enhanced due to the forward bias of the N / N-junction. Furthermore, the carrier lifetime near the N / N-junction between CSL 2012 and drift layer 2013 may not be shortened, the electron injection effect will not decrease, and the carrier density below CSL 2012 may be high. Therefore, a decrease in electron injection efficiency and transistor output performance can be avoided. Furthermore, in diode mode of the semiconductor device, electrons can be injected from the cathode layer 2016 into the drift layer 2013 and flow into the P / N junction between the main layer 2011 and CSL 2012. Since the electron current flowing into the main layer 2011 can be reduced by a shorter carrier lifetime, the forward bias voltage applied to the P / N junction can be reduced. Therefore, during reverse conduction in diode mode, hole injection from the P / N junction can also be suppressed, and the hole density near the junction can be significantly reduced. Thus, lower reverse recovery losses and a softer recovery waveform can be achieved, thereby improving the reverse recovery performance of the diode.

[0142] Furthermore, the second lifetime control portion 201E2 is defined by a portion of the drift layer 2013 at a predetermined distance from the surface of the drift layer 2013 opposite to the carrier storage layer 2012. In this way, the carrier lifetime of the P / N-junction between the collector layer and the drift layer in the transistor region may be shortened. Therefore, hole injection in the transistor region can be suppressed, which can improve the turn-off performance in the transistor region by reducing the carrier concentration near the collector. In the N+ / N-junction between the cathode layer and the drift layer in the diode region, the carrier lifetime may also be shortened. Therefore, electron injection in the diode region can be suppressed, which can improve the reverse recovery loss in the diode region by reducing the carrier concentration near the cathode.

[0143] Therefore, the combination of the first lifetime control section 201E1 and the second lifetime control section 201E2 can also be used to improve diode performance without reducing transistor performance.

[0144] In some embodiments, the lifetime control portion is obtained by low-temperature annealing in a temperature range of 330°C to 500°C after irradiation of the lifetime control body.

[0145] Based on this design, lattice damage caused by lifetime control body irradiation can be restored and eliminated through low-temperature annealing.

[0146] The above description has introduced another semiconductor device; the method for manufacturing this semiconductor device will be described below.

[0147] In some embodiments, the method of manufacturing the semiconductor device includes: forming a semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: a drift layer of a first conductivity type; a carrier storage layer of a first conductivity type disposed on one side of the drift layer; a host layer of a second conductivity type disposed on the side of the carrier storage layer opposite to the drift layer; and a plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the plurality of trench portions having a conductive portion inside, wherein in the semiconductor... A lifetime control body is irradiated on the surface of a bulk substrate to form lifetime control portions extending over both transistor and diode regions. The lifetime control portions include a first lifetime control portion and a second lifetime control portion. The first lifetime control portion is defined by a portion of a carrier storage layer and / or at least a portion of the main layer. The second lifetime control portion is defined by a portion of a drift layer at a predetermined distance from the surface of the drift layer opposite to the carrier storage layer. The first and second lifetime control portions include lifetime control bodies, and the concentration of lifetime control bodies in the first and second lifetime control portions is higher than the concentration of lifetime control bodies in the remaining regions of the semiconductor substrate.

[0148] Based on this design, after forming the semiconductor substrate, a first lifetime control portion is confined to the junction between the second conductivity type's host layer and the first conductivity type's CSL, while carrier lifetime control is not required at the junction between the first conductivity type's CSL and the first conductivity type's drift layer. This reduces the hole concentration near the host layer and CSL in the diode region, resulting in lower reverse recovery losses. Furthermore, the electron concentration near the CSL and drift layer in the transistor region may not change significantly, preventing a decrease in electron injection efficiency in the transistor region. Additionally, a second localized carrier lifetime portion is formed near the first conductivity type's drift layer. This may shorten the carrier lifetime of the P / N-junction between the collector layer and the drift layer in the transistor region. Therefore, hole injection in the transistor region can be suppressed, which can improve turn-off performance in the transistor region by reducing the carrier concentration near the collector. Carrier lifetime may also be shortened in the N+ / N-junction between the cathode layer and the drift layer in the diode region. Therefore, electron injection in the diode region can be suppressed, which can improve the reverse recovery loss in the diode region by reducing the carrier concentration near the cathode.

[0149] Similarly, in some embodiments, the method for manufacturing a semiconductor device can utilize... Figure 19 The wafer fabrication process shown is used to achieve this. However, it should be noted that proton irradiation can be further performed before or after backside metal deposition to form a second lifetime control portion, followed by metal annealing at 450°C to stabilize the lattice damage caused by proton irradiation.

[0150] In some embodiments, after irradiating the surface of a semiconductor substrate with a lifetime control body, the method further includes performing low-temperature annealing on the semiconductor substrate at a temperature below 500°C and above 330°C to form a lifetime control portion.

[0151] Based on this design, lattice damage caused by lifetime control irradiation can be recovered after low-temperature annealing, thereby ensuring the formation of an ideal lifetime control section without causing other significant adverse effects.

[0152] In some embodiments, the irradiation lifetime controller used to form the lifetime control portion is one or a combination of electrons, protons, helium, oxygen, boron, or phosphorus.

[0153] Based on this design, the lifetime control portion can be obtained through irradiation in various ways, which allows for a wider range of options for manufacturing semiconductor devices.

[0154] It should be noted that the technical solution disclosed herein primarily improves the performance of semiconductor devices made of silicon. However, this technical solution can also improve the performance of semiconductor materials made of other semiconductor materials (such as silicon carbide or gallium nitride).

[0155] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope of this disclosure should be included within the scope of protection of this disclosure for those skilled in the art. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. Numerous details are described in this disclosure to provide a thorough understanding of the exemplary embodiments shown in the figures. However, some embodiments may be implemented without many specific details. The scope of protection of the claims is limited only to the features and aspects specifically described in the claims. Furthermore, to avoid obscuring relevant aspects of the embodiments described in this disclosure, it is not necessary to describe well-known processes, components, and materials in detail.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: Drift layer of the first conductivity type; A carrier storage layer of the first conductivity type disposed on one side of the drift layer; A second conductivity type body layer is disposed on the side of the charge carrier storage layer opposite to the drift layer; Multiple trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the multiple trench portions having a conductive portion inside, wherein... The semiconductor substrate includes a lifetime control portion extending over both the transistor region and the diode region, the lifetime control portion being defined by a portion but not all of the carrier storage layer and / or at least a portion of the host layer, and including a lifetime control body, the concentration of the lifetime control body in the lifetime control portion being higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the lifetime control portion in the thickness direction of the semiconductor substrate is within the range of 0 μm to no more than half the thickness of the carrier storage layer and the sum of the thickness of the main layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, The life control component is obtained by low-temperature annealing within a temperature range of 330°C to 500°C after irradiation of the life control body.

4. A semiconductor device, characterized in that, include: A semiconductor substrate having a transistor region and a diode region, the semiconductor substrate including the following portions extending over both the transistor region and the diode region: Drift layer of the first conductivity type; A carrier storage layer of the first conductivity type disposed on one side of the drift layer; A second conductivity type body layer is disposed on the side of the charge carrier storage layer opposite to the drift layer; Multiple trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the multiple trench portions having a conductive portion inside, wherein... The semiconductor substrate includes lifetime control portions extending over both the transistor region and the diode region. Each lifetime control portion includes a first lifetime control portion and a second lifetime control portion. The first lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer. The second lifetime control portion is defined by a portion of the drift layer at a predetermined distance from the surface of the drift layer opposite to the carrier storage layer. Both the first and second lifetime control portions include lifetime control bodies, and the concentration of the lifetime control bodies in the first and second lifetime control portions is higher than the concentration of lifetime control bodies in the remaining regions of the semiconductor substrate.

5. The semiconductor device according to claim 4, characterized in that, The thickness of the first lifetime control portion in the thickness direction of the semiconductor substrate is within the range of 0 μm to no more than half the thickness of the carrier storage layer and the sum of the thickness of the host layer.

6. The semiconductor device according to claim 4 or 5, characterized in that, The thickness of the second lifetime control portion in the thickness direction of the semiconductor substrate is in the range of 0 μm to 30 μm.

7. The semiconductor device according to any one of claims 4 to 6, characterized in that, The life control component is obtained by low-temperature annealing within a temperature range of 330°C to 500°C after irradiation of the life control body.

8. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is formed, wherein the semiconductor substrate has a transistor region and a diode region, and the semiconductor substrate includes the following portions extending over both the transistor region and the diode region: Drift layer of the first conductivity type; A carrier storage layer of the first conductivity type disposed on one side of the drift layer; A second conductivity type body layer is disposed on the side of the charge carrier storage layer opposite to the drift layer; A plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the plurality of trench portions having a conductive portion inside; A lifetime control body is irradiated on the surface of the semiconductor substrate to form a lifetime control portion extending over both the transistor region and the diode region, wherein the lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer, and includes a lifetime control body, the concentration of the lifetime control body in the lifetime control portion being higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

9. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is formed, wherein the semiconductor substrate has a transistor region and a diode region, and the semiconductor substrate includes the following portions extending over both the transistor region and the diode region: Drift layer of the first conductivity type; A carrier storage layer of the first conductivity type disposed on one side of the drift layer; A second conductivity type body layer is disposed on the side of the charge carrier storage layer opposite to the drift layer; A plurality of trench portions extending from the side of the semiconductor substrate opposite to the drift layer along the thickness direction of the semiconductor substrate through the carrier storage layer and the host layer, each of the plurality of trench portions having a conductive portion inside; A lifetime control body is irradiated on the surface of the semiconductor substrate to form a lifetime control portion extending over both the transistor region and the diode region. The lifetime control portion includes a first lifetime control portion and a second lifetime control portion. The first lifetime control portion is defined by a portion of the carrier storage layer and / or at least a portion of the host layer. The second lifetime control portion is defined by a portion of the drift layer at a predetermined distance from the surface of the drift layer opposite to the carrier storage layer. The first and second lifetime control portions include a lifetime control body, and the concentration of the lifetime control body in the first and second lifetime control portions is higher than the concentration of the lifetime control body in the remaining region of the semiconductor substrate.

10. The method according to claim 8 or 9, characterized in that, After subjecting the surface of the semiconductor substrate to lifetime control volume irradiation, the method further includes: The semiconductor substrate is subjected to low-temperature annealing at a temperature below 500°C and above 330°C to form the lifetime control portion.

11. In the method of claims 8, 9, and 10, the irradiation lifetime controller used to form the lifetime control portion is one or a combination of electrons, protons, helium, oxygen, boron, or phosphorus.

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