A cluster-based polymorphic probabilistic bit device

Abstract

This invention discloses a cluster-based multi-state probabilistic bit device. The invention includes a substrate, with a SiO2 gate dielectric layer disposed on the substrate. A source electrode and a drain electrode are disposed on the SiO2 gate dielectric layer, and the source and drain electrodes are bridged by gold nanowires. SiO2 is removed from the four corner regions of the substrate to form windows, and gate electrodes are disposed on these windows, allowing the gate electrodes to make direct ohmic contact with the substrate. This invention simultaneously possesses ultra-small size, multi-state control capability, and probabilistic ergodic behavior.

Description

Technical Field

[0001] This invention relates to the field of cluster electronic devices and probability computing technology, specifically a cluster-based polymorphic probability bit device. Background Technology

[0002] The rapid development of cutting-edge fields such as big data, artificial intelligence, and scientific computing has placed higher demands on the comprehensive performance of information units. As the core carrier of information storage, processing, and transmission, the performance of information units determines the upper limit of information systems, requiring breakthroughs in size, functionality, and dynamic characteristics to adapt to various application scenarios.

[0003] The evolution of information units currently presents three key directions: first, miniaturization, constrained by the physical limits of Moore's Law, with single-atom and single-molecule level devices becoming the focus of research to achieve higher integration and lower power consumption; second, multi-state storage capability, breaking through the limitations of traditional binary systems, with devices such as floating-gate multi-state memories enabling multi-state control, improving storage density and computational efficiency; and third, probabilistic ergodic capability, with devices such as probabilistic bits enabling controllable probabilistic behavior, adapting to scenarios such as probabilistic reasoning and quantum simulation.

[0004] Traditional devices such as magnetic tunnel junctions and nanowires exhibit probabilistic behavior, but their size is relatively large; single-molecule devices, while small in size, struggle to achieve multi-state control and stable probabilistic behavior. Current information unit devices have not yet been able to simultaneously possess the three key characteristics of ultra-small size, multi-state control capability, and probabilistic ergodicity, making it difficult to meet the comprehensive needs of cutting-edge fields. Summary of the Invention

[0005] The purpose of this invention is to provide a cluster-based polymorphic probabilistic bit device, which aims to solve the problem that information units in the prior art are difficult to simultaneously possess ultra-small size, multi-state control capability, and probabilistic ergodic behavior.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A cluster-based multi-state probabilistic bit device includes a substrate, a SiO2 gate dielectric layer disposed on the substrate, a source electrode and a drain electrode disposed on the SiO2 gate dielectric layer, the source electrode and the drain electrode being bridged by gold nanowires, a cluster layer being deposited on the gold nanowires connecting the source electrode and the drain electrode, and nano-gap formed by single cluster bridging after negative feedback controlled electromigration, and SiO2 being removed from the four corner regions of the substrate to form windows, and gate electrodes being disposed on the windows so that the gate electrodes are in direct ohmic contact with the substrate.

[0007] Preferably, the substrate is a doped silicon substrate.

[0008] Preferably, the source electrode includes a source electrode transition layer and a source electrode outer layer, and the source electrode transition layer and the source electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

[0009] Preferably, the drain electrode includes a drain electrode transition layer and a drain electrode outer layer, and the drain electrode transition layer and the drain electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

[0010] Preferably, the source electrode and the drain electrode are symmetrically positioned at the center of the SiO2 gate dielectric, and the source electrode and the drain electrode have gaps for connecting gold nanowires.

[0011] Preferably, the gold nanowires have a width of 30-100 nm, a length of 50-400 nm, and a thickness of 20-30 nm.

[0012] Preferably, the two ends of the gold nanowire are connected to the source electrode and the drain electrode respectively through a connecting sheet structure.

[0013] Multistate probabilistic bit devices exhibit random switching between multiple conduction states under a specific bias voltage, and the switching behavior can be controlled by an electric field, thus possessing probabilistic ergodic capability.

[0014] Preferably, the polymorphic probability bit device can be used as a physical random number generator. The input voltage sequence is controlled by an algorithm, and the output current is converted into a 0 / 1 sequence by a comparator to represent the binary bits of the factor.

[0015] Preferably, the polymorphic probabilistic bit device can be based on the Markov property of the device state transition matrix.

[0016] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: This invention includes a substrate, a SiO2 gate dielectric layer disposed on the substrate, a source electrode and a drain electrode disposed on the SiO2 gate dielectric layer, and the source electrode and drain electrode are bridged by gold nanowires. SiO2 is removed from the four corner regions of the substrate to form windows, and gate electrodes are disposed on the windows, allowing the gate electrodes to make direct ohmic contact with the substrate. This invention simultaneously possesses ultra-small size, multi-state control capability, and probabilistic ergodic behavior. By adjusting the voltage applied to the device, the distribution of the device's conductance states can be significantly changed. Furthermore, by rationally grouping the device states, the device can be adjusted to any state within the [0,1] probability interval by voltage adjustment, realizing the probabilistic bit function. The device can be applied to tasks such as probability calculation, prime factorization, and matrix multiplication. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a structural diagram of a cluster-based polymorphic probability bit device according to the present invention; Figure 2 This is a diagram of the gold nanowire structure; Figure 3 It is a diagram showing the effect of six voltages on the cluster conductance state; Figure 4 It is a graph showing how voltage affects probability; Figure 5 This is a diagram showing the periodic response, state distribution, and transition matrix of a multi-state probability bit device under a bias voltage Vsd = 140mV. Figure 6 This is a diagram showing the periodic response, state distribution, and transition matrix of a multi-state probability bit device under a bias voltage Vsd = 160mV. Figure 7 This is a diagram showing the periodic response, state distribution, and transition matrix of a multi-state probability bit device during the switching of bias voltage Vsd between 140mV and 160mV. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1: The present invention provides a cluster-based multi-state probabilistic bit device, comprising using heavily doped silicon as substrate 1, and forming a SiO2 gate dielectric layer 2 on substrate 1 by atomic layer deposition; the source electrode and drain electrode made of metal are symmetrically located at the center of the SiO2 gate dielectric layer 2, and the source electrode and drain electrode have gaps for connecting gold nanowires.

[0020] Gold nanowires 8 with a thickness of 23 nm, a width of 50 nm, and a length of 400 nm were fabricated. The two ends of the gold nanowires 8 were connected to the source electrode and the drain electrode respectively via sheet-like structures 10. Figure 2 As shown.

[0021] The clusters were synthesized by arc discharge method, purified by HPLC, and deposited on the gold nanowires 8 connecting the source electrode and the drain electrode to achieve a cluster layer. After electromigration controlled by negative feedback, nano-gap between individual clusters was formed.

[0022] In addition, SiO2 is removed from the four corner regions of the substrate 1 to form windows, and gate electrodes 7 composed of metal stacks are provided so that the gate electrodes 7 are in direct ohmic contact with the heavily doped silicon substrate 1, thereby realizing gate voltage regulation of the device.

[0023] The source electrode includes a source electrode transition layer 3 made of Ti and a source electrode outer layer 4 made of Au. The source electrode transition layer and the source electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

[0024] The drain electrode includes a drain electrode transition layer 5 composed of Ti and a drain electrode outer layer 6 composed of Au. The drain electrode transition layer and the drain electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

[0025] An insulating layer 9 is wrapped around the outside of the SiO2 gate dielectric layer 2. The insulating layer is made of the same material as the gate dielectric layer, namely SiO2, and has a thickness of 300 nm, while the gate dielectric layer has a thickness of 30 nm. In the specific fabrication process, the insulating layer is fabricated first, then the gate window is etched out, and the gate dielectric layer is grown and deposited on the gate window.

[0026] Example 2: Prime factorization; The polymorphic probability bit device prepared in Example 1 can be used as a physical random number generator. An algorithm controls the input voltage sequence, and the output current is converted into a 0 / 1 sequence by a comparator to represent the binary bits of a factor. Specifically: Six voltages (150mV, 155mV, 160mV, 165mV, 170mV, and 175mV) were applied as input signals to the polymorphic probability bit device, and the output signals were transmitted to the computer via a circuit board. The entire process was controlled by a LabVIEW program that implemented an algorithm for minimizing the cost function E. In the experiment, the initial probability of the p-bit was set to 0.5. The voltages to be input to the device were stored in array form, applied sequentially to each p-bit unit, and the output of each p-bit unit was recorded in another array. The output results were then assigned to the corresponding bits of the two factors and further calculations were performed. The i-th bit can be driven by the input voltage Vi. After each learning iteration, the adjustment value of Vi is calculated according to the following formula: , Where m i It is the output of the i-th bit, represented in binary form.

[0027] Starting from the form of the cost function E, assume that the number F to be decomposed can be expressed as the product of two odd numbers X and Y, both of which are greater than or equal to 3 (because even numbers can be preprocessed quickly, and the factor of 1 is trivial). This is achieved through the following relationship: , , , Throughout the learning process, a probabilistic constraint was applied, limiting the probability range of the p-bits to [0.1, 0.9]. This ensured that even if the device entered a local minimum, it could successfully escape after several learning iterations. When the learning process reached E=0, the loop terminated and the result was output.

[0028] Using the above method, the modulation of cluster conductance states by six voltages (150mV, 155mV, 160mV, 165mV, 170mV, and 175mV) was obtained. Figure 3 As shown in the figure, it can be seen that as the voltage gradually increases, the probability of the high conductivity state decreases, while the probability of the low conductivity state increases. The voltage's effect on the probability is as follows: Figure 4 As shown, this illustrates the process by which a polymorphic probability bit device gradually shifts with voltage changes.

[0029] The 551 was decomposed using 8 bits, and the decomposition results were (19, 29) and (29, 19), which verified the device's probabilistic calculation capability.

[0030] Example 3: Using a Markov chain model, the state transitions of a polymorphic probabilistic bit device are represented as a state transition matrix. Assume the device has k states, and let the initial state probability distribution of the device be P0 = [P1, ..., P2]. k The state transition matrix of the device is: , Among them, T ij Let represent the probability of transitioning from initial state i to state j within a given time interval. After n time intervals, the final state probability distribution is: .

[0031] The properties of Markov processes provide a novel method for implementing matrix multiplication: Let the initial probability distribution of the device under voltage V1 be P0. After a time interval dt, the probability distributions for all states become... When the voltage switches to V2 and then waits for another dt, the distribution evolves as follows: By statistically determining the overall transition matrix T from P0 to P2, we can directly obtain the matrix product. .

[0032] Therefore, in the specific experimental process, to statistically determine the transition matrix, the corresponding physical process is repeatedly executed: the initial state S0 of the device is recorded, the device undergoes a complete physical process (i.e., voltage switching operation), the final state St after the process is completed is recorded, the count at position (S0, St) in the transition matrix T is incremented by 1, and these steps are repeated to collect sufficient data. Finally, by normalizing each row of matrix T (ensuring that the sum of the elements in each row is 1), the transition matrix representing the state transition probability is obtained. Therefore, matrix multiplication can be achieved by configuring the input voltage.

[0033] This embodiment is designed with bias voltage... ,bias and under bias voltage Voltage switching cycle experiment between 140mV and 160mV.

[0034] Recorded in bias voltage The initial state and the multi-state probability bit device undergo a physical process with a period of 1 second, and multiple periods are recorded. Among these, the bias voltage... Under these conditions, the state-cycle response curve of the device is as follows: Figure 5 As shown in 'a', by normalizing each row of matrix T (ensuring the sum of elements in each row is 1), we obtain the transition matrix representing the state transition probabilities, as shown in 'a'. Figure 5 As shown in c, the color in the matrix corresponds to the value of the matrix element, with larger values ​​indicating warmer colors and smaller values ​​indicating cooler colors. Figure 5 In the diagram, b represents the state distribution histogram derived from the state-periodic response.

[0035] Recorded in bias voltage The initial state and the multi-state probability bit device undergo a physical process with a period of 1 second, and multiple periods are recorded. Among these, the bias voltage... Under these conditions, the state-cycle response curve of the device is as follows: Figure 6 As shown in d in the diagram. By normalizing each row of matrix T (ensuring the sum of elements in each row is 1), we obtain the transition matrix representing the state transition probabilities, as shown in the diagram. Figure 6 As shown in f, the color in the matrix corresponds to the value of the matrix element, with larger values ​​indicating warmer colors and smaller values ​​indicating cooler colors. Figure 6 In this context, 'e' represents the state distribution histogram derived from the state-periodic response.

[0036] Record bias The device's state-cycle response curves were obtained by switching between 140mV and 160mV. The initial state of the device was recorded at 140mV, held for 1 second, then switched to 160mV and held for 1 second, recording the final state. This completed one cycle. Multiple cycles were recorded. The state-cycle response curves of the device during the switching process between 140mV and 160mV are shown below. Figure 7As shown in g in the diagram. By normalizing each row of matrix T (ensuring the sum of elements in each row is 1), we obtain the transition matrix representing the state transition probabilities, as shown in the diagram. Figure 7 As shown in i, the color in the matrix corresponds to the value of the matrix element, with larger values ​​indicating warmer colors and smaller values ​​indicating cooler colors. Figure 7 In this context, h represents the state distribution histogram derived from the state-periodic response.

[0037] The state transition probability transition matrix of bias voltage Vsd=140mV is compared with the bias voltage. The calculated value obtained by multiplying the state transition probability by the transition matrix and the bias voltage The transition matrix of the final state transition probability obtained by switching between 140mV and 160mV was compared, and the maximum error was less than 0.05 and the average error was less than 0.03, which verified its high-precision matrix operation capability.

[0038] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0039] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A cluster-based polymorphic probabilistic bit device, characterized in that, The device includes a substrate, on which a SiO2 gate dielectric layer is disposed. A source electrode and a drain electrode are disposed on the SiO2 gate dielectric layer. The source electrode and the drain electrode are bridged by gold nanowires. A cluster layer is deposited on the gold nanowires connecting the source electrode and the drain electrode. After negative feedback control electromigration, a nano-gap is formed between individual clusters. SiO2 is removed from the four corner regions of the substrate to form windows. Gate electrodes are disposed on the windows so that the gate electrodes are in direct ohmic contact with the substrate.

2. The cluster-based polymorphic probabilistic bit device according to claim 1, characterized in that, The substrate is a doped silicon substrate.

3. The cluster-based polymorphic probabilistic bit device according to claim 1, characterized in that, The source electrode includes a source electrode transition layer and a source electrode outer layer, and the source electrode transition layer and the source electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

4. A cluster-based polymorphic probabilistic bit device according to claim 1, characterized in that, The drain electrode includes a drain electrode transition layer and a drain electrode outer layer, and the drain electrode transition layer and the drain electrode outer layer are sequentially disposed on the SiO2 gate dielectric.

5. A cluster-based polymorphic probabilistic bit device according to claim 3, characterized in that, The source electrode and the drain electrode have a gap for connecting the gold nanowires.

6. A cluster-based polymorphic probabilistic bit device according to claim 1, characterized in that, The gold nanowires have a width of 30-100 nm, a length of 50-400 nm, and a thickness of 20-30 nm.

7. A cluster-based polymorphic probabilistic bit device according to claim 1, characterized in that, The gold nanowire is connected to the source electrode and the drain electrode at both ends by a connecting sheet structure, respectively.

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