Gallium nitride high electron mobility transistor and method of manufacturing the same

Abstract

The application relates to a gallium nitride high electron mobility transistor and a manufacturing method thereof. The transistor comprises a semiconductor layer and a gate structure, and further comprises a first stress layer and a second stress layer. The first stress layer is located on the upper surface of the semiconductor layer and extends to the gate structure to cover the sidewall thereof. The end of the first stress layer is recessed inward relative to the sidewall of the semiconductor layer to form a first step structure between the end of the first stress layer and the sidewall of the semiconductor layer. The second stress layer covers the outer side of the first stress layer and the sidewall of the semiconductor layer, and the second stress layer fills the first step structure. The application forms a step by recessing the first stress layer, provides a support platform for the second stress layer to grow from bottom to top, enables the second stress layer to completely cover the shoulder and the sidewall of the semiconductor layer and effectively cover the sidewall of the first stress layer, and thus significantly reduces gate leakage and improves device reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a gallium nitride high electron mobility transistor and a method for manufacturing the same. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, has wide applications in power devices. During the fabrication of the gate structure in GaN devices, the gate conductive layer needs to be protected to suppress the outward diffusion of metal atoms. However, existing manufacturing techniques are prone to causing gate leakage, affecting the device's off-state leakage performance and long-term reliability. Summary of the Invention

[0003] To address the above problems, this application provides a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate, and the band gap of the barrier layer is larger than the band gap of the channel layer; p-type doped III-V compound semiconductor layer, which is in contact with the barrier layer and located on the side of the barrier layer away from the channel layer; A gate structure is disposed on the p-type doped III-V compound semiconductor layer; A first stress layer is located on the upper surface of the p-type doped III-V compound semiconductor layer and extends to the gate structure to cover the sidewall of the gate structure. The end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer so that the end of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer form a first step structure. The second stress layer covers the outer side of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer, and the second stress layer fills the first step structure.

[0004] In one embodiment, a dielectric isolation layer is further included, disposed on the sidewall of the first stress layer away from the gate structure, with the lower surface of the dielectric isolation layer located on the upper surface of the first stress layer; the second stress layer continuously covers the outer sidewall of the dielectric isolation layer and the first stress layer.

[0005] In one embodiment, the first stress layer is recessed inward at its end on the upper surface of the p-type doped III-V compound semiconductor layer by a distance relative to the sidewall of the p-type doped III-V compound semiconductor layer, and the first recess distance ranges from 5 nm to 100 nm.

[0006] In one embodiment, the end face of the dielectric isolation layer near the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the first stress layer, so that the end face of the dielectric isolation layer and the sidewall of the first stress layer form a second step structure; the second stress layer fills the second step structure.

[0007] In one embodiment, the end face of the dielectric isolation layer near the p-type doped III-V compound semiconductor layer is recessed inward by a distance relative to the sidewall of the first stress layer, which is a second recess distance ranging from 5 nm to 150 nm.

[0008] In one embodiment, the second inward distance is greater than the first inward distance.

[0009] In one embodiment, the first step structure and the second step structure together form a stepped profile, and the second stress layer conformally covers the stepped profile.

[0010] In one embodiment, the angle between the end face of the dielectric isolation layer at the second step structure and the upper surface of the first stress layer is 90° to 135°; and / or The angle between the end face of the first stress layer at the first step and the upper surface of the p-type doped III-V compound semiconductor layer is 90° to 135°.

[0011] In one embodiment, the thickness of the first stress layer is less than the thickness of the second stress layer.

[0012] In one embodiment, the thickness of the first stress layer is 0.8 nm to 2.5 nm, and the thickness of the second stress layer is 0.5 nm to 1 nm.

[0013] In one embodiment, an oxide layer is further included, the oxide layer being disposed on the top surface of the gate structure, the first stress layer extending from the sidewall of the gate structure to the oxidized sidewall and covering the sidewall of the oxide layer; the second stress layer covering the surface of the oxide layer opposite to the gate structure.

[0014] In one embodiment, the materials of the first stress layer and the second stress layer are both aluminum-containing dielectric materials, including at least one of aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0015] This application also provides a method for manufacturing a gallium nitride high electron mobility transistor, comprising: A channel layer, a barrier layer, and a p-type doped III-V compound semiconductor layer are sequentially formed on a substrate. A gate structure is formed on the p-type doped III-V compound semiconductor layer; A first stress layer is deposited, such that the first stress layer covers the sidewalls of the gate structure and the upper surface of the p-type doped III-V compound semiconductor layer; The p-type doped III-V compound semiconductor layer is etched to expose the sidewalls of the p-type doped III-V compound semiconductor layer; The first stress layer is recessed so that the end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer to form a step. A second stress layer is deposited, covering the outer side of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer, and filling the step.

[0016] In one embodiment, after depositing the first stress layer and before etching the p-type doped III-V compound semiconductor layer, the method further includes: depositing a dielectric isolation material on the first stress layer and etching it to form a dielectric isolation layer located on both sides of the gate structure. The inward reduction process simultaneously causes the lower end face of the dielectric isolation layer to be recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer.

[0017] In one embodiment, prior to depositing the first stress layer, the method further includes depositing an oxide layer on the surface of the gate structure, such that the oxide layer covers the top surface of the gate structure.

[0018] In one embodiment, the shrinkage process employs an isotropic dry etching process or a wet etching process.

[0019] The technical solutions provided by the embodiments of this application may include the following beneficial effects: As can be seen from the above embodiments, this application relates to a gallium nitride high electron mobility transistor and a method for manufacturing the same. The gallium nitride high electron mobility transistor includes a substrate, on which a channel layer, a barrier layer, a p-type doped III-V compound semiconductor layer, and a gate structure are sequentially disposed. It also includes a first stress layer and a second stress layer. The first stress layer is located on the upper surface of the p-type doped III-V compound semiconductor layer and extends to the gate structure to cover the sidewalls of the gate structure. The end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewalls of the p-type doped III-V compound semiconductor layer, so that the end of the first stress layer and the sidewalls of the p-type doped III-V compound semiconductor layer form a first step structure. The second stress layer covers the outer side of the first stress layer and the sidewalls of the p-type doped III-V compound semiconductor layer, and the second stress layer fills the first step structure. This application forms a step by shrinking the first stress layer, providing a support platform for the growth of the second stress layer from bottom to top. This allows the second stress layer to completely cover the shoulder and sidewall of the p-type doped III-V compound semiconductor layer, as well as effectively cover the sidewall of the first stress layer, thereby significantly reducing gate leakage current and improving device reliability.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the description are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a structural diagram of the manufacturing process of prior art 1 provided in one embodiment of this application.

[0023] Figure 2 This is a structural diagram of the manufacturing process of prior art 2 provided in one embodiment of this application.

[0024] Figure 3 This is a structural diagram of the manufacturing process of a gallium nitride high electron mobility transistor provided in one embodiment of this application.

[0025] Figure 4 This is a schematic diagram of a gallium nitride high electron mobility transistor structure provided in one embodiment of this application.

[0026] Figure 5 This is a schematic diagram of a gallium nitride high electron mobility transistor structure provided in one embodiment of this application.

[0027] Figure 6 This is a schematic diagram of a gallium nitride high electron mobility transistor structure provided in one embodiment of this application.

[0028] Figure label: 100, Substrate; 101, Silicon substrate; 102, Gallium nitride layer; 103, Al gallium nitride layer; 110, Semiconductor layer; 120, Gate structure; 130, Oxide layer; 140, First stress layer; 150, Dielectric isolation layer; 160, Second stress layer; H1, first indentation distance; H2, second indentation distance. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. Various modifications, variations, and equivalents of the methods, apparatus, and / or circuits described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, descriptions of features known in the art may be omitted for clarity and brevity. The modes described in the following exemplary embodiments do not represent all modes consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0030] As described in the background section, gallium nitride (GaN) power devices are widely used in fast charging, radio frequency, and new energy vehicles due to their excellent characteristics such as high breakdown field strength and high electron mobility. In the gate structure of GaN enhancement-mode devices, a P-type gallium nitride layer is typically used in conjunction with a gate conductive layer to achieve normally-off characteristics. The manufacturing process and final morphology of the gate structure have a decisive impact on the leakage current performance and long-term reliability of the device. However, existing gate structure manufacturing processes generally suffer from the problem of outward diffusion of metal atoms in the gate conductive layer, resulting in high gate leakage current and insufficient device reliability. Examples are provided below with reference to the accompanying figures.

[0031] Figure 1 This illustrates a conventional method for forming a gate structure. Figure 1 part a to Figure 1 Part g shows a schematic diagram of the steps in the gate structure formation method of prior art 1.

[0032] like Figure 1As shown in part a, a substrate 10 is provided, on which a semiconductor layer 11 is formed. The substrate 10 includes a silicon substrate 101, a channel layer 102 (such as a gallium nitride layer), and a barrier layer 103 (such as an aluminum gallium nitride layer) stacked from bottom to top. The semiconductor layer 11 is a p-type gallium nitride layer formed on the barrier layer 103. All of the above layers are conventional epitaxial structures and will not be described in detail here.

[0033] like Figure 1 part b to Figure 1 As shown in section c, a gate conductive material is deposited on the semiconductor layer 11 and photolithography and etching are performed to form a gate conductive layer 12. An oxide layer 13 (such as silicon oxide) is formed on the gate conductive layer.

[0034] like Figure 1 As shown in section d, sidewall material is deposited on the top surface and sidewalls of the gate conductive layer 12 and the surface of the semiconductor layer 11, and anisotropic etching is performed to form sidewalls 14 located on both sides of the gate conductive layer 12. The sidewalls 14 cover the sidewalls of the gate conductive layer 12 and are used to protect the sidewalls of the gate conductive layer 12 from damage in subsequent etching processes.

[0035] like Figure 1 part e to Figure 1 As shown in part f, the semiconductor layer 11 is etched using the gate conductive layer 12 and the sidewall 14 as masks to remove the P-type gallium nitride material in the areas not covered by the mask, thereby exposing the sidewalls of the semiconductor layer 11.

[0036] like Figure 1 As shown in section g, sidewall 14 is removed. Subsequently, stress layer 15 (such as aluminum nitride) is deposited, so that stress layer 15 covers the surface and sidewalls of gate conductive layer 12, semiconductor layer 11.

[0037] In the prior art 1 described above, after the sidewall 14 is removed, the sidewall of the gate conductive layer 12 is completely exposed and directly exposed to the subsequent cleaning solution environment. The slight corrosion of the gate conductive layer 12 surface by the cleaning solution causes titanium atoms to detach and form titanium residue. These titanium residues are widely adhered to the shoulders and sidewalls of the semiconductor layer 11, and even diffuse into the drift region. During subsequent high-temperature processes or device operation, the titanium residues further diffuse into the contact corner region between the semiconductor layer 11 and the gate conductive layer 12, forming leakage channels and severely affecting the off-state leakage performance of the gate.

[0038] To overcome Figure 1 The above-mentioned defects of the proposed solution, Figure 2 An improved solution is shown. Figure 2 part a to Figure 2Part g shows a schematic diagram of the steps in the gate structure formation method of prior art 2. Prior art 2 aims to overcome the problem of titanium residue caused by the exposure of the sidewalls of the gate conductive layer after sidewall removal in prior art 1.

[0039] like Figure 2 As shown in part a, a substrate 20 is provided, on which a semiconductor layer 21 is formed. Similar to the prior art 1, the substrate 20 includes a silicon substrate 201, a channel layer 202 (such as a gallium nitride layer) and a barrier layer 203 (such as an aluminum gallium nitride layer) stacked from bottom to top, and the semiconductor layer 21 is a p-type gallium nitride layer formed on the barrier layer.

[0040] like Figure 2 Part b - Figure 2 As shown in section c, a gate conductive material is deposited on the semiconductor layer 21 and then photolithography and etching are performed to form a gate conductive layer 22 and an oxide layer 23. The material of the gate conductive layer 22 is generally titanium nitride.

[0041] like Figure 2 As shown in section d, a first stress layer 24 is deposited on the top surface and sidewalls of the gate conductive layer 22 and on the surface of the semiconductor layer 21. The first stress layer 24 conformally covers the exposed surfaces of the gate conductive layer 22 and the semiconductor layer 21, and is used for preliminary stress regulation and sealing protection of the gate conductive layer 22.

[0042] like Figure 2 As shown in section e, sidewall material is deposited on the surface of the first stress layer 24, and anisotropic etching is performed to form sidewalls 25 located on both sides of the gate conductive layer 22. The sidewalls 25 are in close contact with the sidewalls of the first stress layer 24 on the side away from the gate conductive layer 22, and are used to provide structural support and mask protection in subsequent etching processes.

[0043] like Figure 2 As shown in part f, the semiconductor layer 21 is etched using the gate conductive layer 22, the first stress layer 24 and the sidewall 25 as masks to remove the P-type gallium nitride material in the areas not covered by the mask, so as to expose the sidewall of the semiconductor layer 21.

[0044] like Figure 2 As shown in part g, a second stress layer 26 is deposited, such that the second stress layer 26 covers the outer sidewall C1 of the sidewall 25, the exposed sidewall C2 of the first stress layer 24, the sidewall C3 of the semiconductor layer 21, and the surface C4 of the substrate 20.

[0045] The prior art 2 provides double-layer sealing and passivation protection for the gate conductive layer 22 by retaining the sidewall 25 and depositing the first stress layer 24 and the second stress layer 26 before and after etching the semiconductor layer 21, which to a certain extent suppresses the outward diffusion of titanium atoms in the gate conductive layer 22.

[0046] However, prior art 2 still has significant drawbacks. During the deposition of the second stress layer 26, the first stress layer 24 and the sidewall 25 form a vertical wall structure at the sidewall of the semiconductor layer 21. This can be understood as the upper vertical wall formed by the outer sidewall C1 of the sidewall 25 and the exposed sidewall C2 of the first stress layer 24, together with the sidewall C3 of the semiconductor layer 21, forming a continuous vertical contour line. Constrained by this continuous vertical contour line, the second stress layer 26 can only grow along this vertical sidewall. Near the interface between the first stress layer 24 and the sidewall of the semiconductor layer 21, due to the directional deposition and the shading effect of the vertical morphology, the growth of the second stress layer 26 is poor, forming a poorly covered area that cannot effectively cover the interface region. This poorly covered area becomes the main source of gate-off leakage current, resulting in a still high gate leakage current in the device.

[0047] Based on this, this application provides a gallium nitride high electron mobility transistor, referring to... Figure 3 , Figure 4 and Figure 5 It includes a substrate 100 and a semiconductor layer 110 and a gate structure 120 located on the substrate 100.

[0048] Specifically, substrate 100 can be understood as the epitaxial wafer mentioned above, generally including a silicon substrate 1001, a channel layer 1002 (such as a gallium nitride layer), and a barrier layer 1003 (such as an aluminum gallium nitride layer) stacked sequentially. Semiconductor layer 110 in this application can be understood as a P-type gallium nitride layer (PGaN) located on barrier layer 1003. Channel layer 1002 (GaN) and barrier layer 1003 (AlGaN) are used to form a heterojunction structure to generate a two-dimensional electron gas (2DEG), both of which are conventional basic structures for gallium nitride power devices and will not be elaborated further here. Similarly, gate structure 120 is a conductive layer used to control the switching on and off of the channel, generally using metallic materials such as titanium nitride (TiN), and will not be elaborated further here either.

[0049] Specifically, continue to refer to Figure 5 The gallium nitride high electron mobility transistor provided in this application further includes a first stress layer 140 and a second stress layer 160 located on the upper surface of the semiconductor layer 110. The first stress layer 140 extends upward from the upper surface of the semiconductor layer 110, covers the junction gap between the semiconductor layer 110 and the gate structure 120, and extends to the gate structure 120 to cover the sidewalls of the gate structure 120.

[0050] The first stress layer 140 and the second stress layer 160 are used to perform stress regulation, sealing, and passivation protection on the gate structure 120. They are made of aluminum-containing dielectric materials, including at least one of aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0051] Furthermore, in conjunction with reference Figure 4 The end D1 of the first stress layer 140 on the upper surface of the semiconductor layer 110 is recessed inward relative to the sidewall D2 of the semiconductor layer 110, so that the end D1 of the first stress layer 140 and the sidewall D2 of the semiconductor layer 110 form a first step structure T1. The second stress layer 160 covers the end D1 of the first stress layer 140 and the sidewall D2 of the semiconductor layer 110, and the second stress layer 160 fills the first step structure T1.

[0052] Understandably, the second stress layer 160 needs to provide complete coverage protection for the gate structure 120 and the semiconductor layer 110. In this application, the second stress layer 160 starts from the sidewall D2 of the semiconductor layer 110, extends upward through the first step structure T1 to the end D1 of the first stress layer 140, and finally covers the upper surface of the gate structure 120, forming a continuous and complete coverage contour.

[0053] This application provides a reliable support platform for the deposition of the second stress layer 160 by forming a first step structure T1 through the inward indentation of the end of the first stress layer 140 on the upper surface of the semiconductor layer 110. This allows the second stress layer 160 to completely cover the shoulder and sidewall of the semiconductor layer 110 and effectively encapsulate the sidewall of the first stress layer 140, thereby significantly reducing the gate off-state leakage current and improving the reliability and withstand voltage performance of the device.

[0054] In some embodiments, the thickness of the first stress layer 140 is less than the thickness of the second stress layer 160.

[0055] Specifically, the first stress layer 140, as an inner protective film directly covering the sidewalls of the gate structure 120, is relatively thin to allow for precise control of the shrinkage amount during subsequent shrinkage processing, forming the first step structure T1. Simultaneously, the thinner first stress layer 140 helps reduce stress accumulation at the sidewalls of the gate structure 120, preventing excessive stress concentration at the corners of the gate structure 120 due to an excessively thick stress layer, thereby protecting the interface quality between the gate structure 120 and the semiconductor layer 110. The second stress layer 160, as the outer main protective layer, is relatively thick, providing sufficient mechanical strength and chemical stability. It forms a thick protective coating on the sidewalls of the gate structure 120 and the semiconductor layer 110, effectively blocking the intrusion of external moisture and impurity ions, and further enhancing the ability to prevent the outward diffusion of metal atoms within the gate structure 120.

[0056] Furthermore, the thickness of the first stress layer 140 can range from 0.8 nm to 2.5 nm, and the thickness of the second stress layer 160 can range from 2 nm to 10 nm. The minimum thickness of 0.8 nm for the first stress layer 140 ensures a continuous, pinhole-free basic coverage of the sidewalls of the gate structure 120, while the maximum thickness of 2.5 nm avoids excessive etch during shrinkage and difficulty in precisely controlling the step morphology due to excessive thickness. The thickness of the second stress layer 160 is set to ensure reliable shielding against the external environment.

[0057] In some embodiments, the gallium nitride high electron mobility transistor further includes a dielectric isolation layer 150. The dielectric isolation layer 150 is disposed on a sidewall of the first stress layer 140 opposite to the gate structure 120, and the lower surface of the dielectric isolation layer 150 is in contact with the upper surface of the first stress layer 140. A second stress layer 160 continuously covers the dielectric isolation layer 150 and the outer sidewall of the first stress layer 140.

[0058] Specifically, the dielectric isolation layer 150 is formed after the deposition of the first stress layer 140 and before the deposition of the second stress layer 160, serving to provide additional insulating protection and structural support on the outside of the first stress layer 140. The dielectric isolation layer 150 covers the sidewall of the first stress layer 140 facing away from the gate structure 120 and extends upward from the upper surface of the first stress layer 140. The second stress layer 160 starts from the sidewall D2 of the semiconductor layer 110 and extends upward along the end D1 of the first stress layer 140, thus wrapping around the outer sidewall and upper surface of the dielectric isolation layer 150 to form a complete cover.

[0059] Specifically, continuous coverage can be understood as the second stress layer 160 rising uninterruptedly and seamlessly from the sidewall of the semiconductor layer 110 through the first step structure T1 to the end D1 of the first stress layer 140, and then continuing to extend upwards to cover the sidewall of the dielectric isolation layer 150 until its top surface. There are no unfilled gaps between the end D3 of the dielectric isolation layer 150 and the sidewall D1 of the first stress layer 140, and the interfaces between the second stress layer 160 and each layer achieve seamless adhesion.

[0060] In one embodiment, refer to Figure 6 The end D3 of the dielectric isolation layer 150 near the semiconductor layer 110 is recessed inward relative to the sidewall D1 of the first stress layer 140, so that the end D3 of the dielectric isolation layer 150 and the sidewall D1 of the first stress layer 140 form a second step structure T2. The second stress layer 160 fills the second step structure T2.

[0061] Specifically, the first step structure T1 and the second step structure T2 together form a stepped profile, and the second stress layer 160 conformally covers the stepped profile. It can be understood that conformal coverage means that the second stress layer 160, with a substantially uniform thickness, is deposited along the undulations of the stepped profile, filling the recessed areas of the steps and extending along the vertical and flat surfaces of the steps, ultimately forming a continuous protective layer that matches the stepped profile. This arrangement ensures that during the growth of the second stress layer 160, the horizontal plane of each step serves as a platform for the next vertical coverage segment, effectively avoiding the problem of weak coverage caused by the shading effect when growing on a single vertical sidewall, thereby achieving all-around coverage of the sidewalls of the gate structure 120 and the shoulder of the semiconductor layer 110.

[0062] In some embodiments, the first stress layer 140 is recessed inward at its end on the upper surface of the semiconductor layer 110 by a distance relative to the sidewall of the semiconductor layer 110, which is a first recess distance H1 ranging from 5 nm to 100 nm.

[0063] Specifically, the first inward shrinkage distance H1 refers to the horizontal distance measured along a direction parallel to the upper surface of the semiconductor layer 110, between the end face position of the first stress layer 140 on the upper surface of the semiconductor layer 110 and the boundary position of the sidewall of the semiconductor layer 110 on the upper surface. The selection of this distance needs to consider two aspects: firstly, if the inward shrinkage distance is too small, an effective step cannot be formed, resulting in insufficient growth platform for the second stress layer 160; secondly, if the inward shrinkage distance is too large, the protection area of ​​the first stress layer 140 over the sidewall of the gate structure 120 will be excessively reduced, potentially affecting the sealing effect of the gate structure 120. This application controls the first inward shrinkage distance H1 within the range of 5nm to 100nm, ensuring that the step structure provides sufficient growth support for the second stress layer 160 while maintaining effective coverage of the sidewall of the gate structure 120 by the first stress layer 140.

[0064] This setup, through precise control of the first inward distance H1, optimizes the width of the first step structure T1, enabling the second stress layer 160 to smoothly begin growth and climb upward on the horizontal surface of the step.

[0065] In some embodiments, the end face of the dielectric isolation layer 150 near the semiconductor layer 110 is recessed inward by a distance relative to the sidewall of the first stress layer 140, which is a second recess distance H2, and the second recess distance H2 ranges from 5 nm to 150 nm.

[0066] Specifically, the second indentation distance H2 refers to the horizontal distance measured between the end face of the dielectric isolation layer 150 near the semiconductor layer 110 and the boundary position of the sidewall of the first stress layer 140 at that end face height. The lower limit of the second indentation distance H2 is set to 5 nm to ensure that the end face of the dielectric isolation layer 150 has a identifiable indentation relative to the sidewall of the first stress layer 140, forming a clear second step structure T2. The upper limit of the second indentation distance H2 is set to 150 nm to prevent excessive indentation from resulting in insufficient protection area of ​​the dielectric isolation layer 150 for the sidewall of the first stress layer 140. This setting provides a reasonable width range for the second step structure T2, allowing the second stress layer 160 to have a gradually transitioning gradient profile when sequentially filling the first step structure T1 and the second step structure T2, further optimizing the coverage quality.

[0067] In some implementations, the second inward distance H2 is greater than the first inward distance H1.

[0068] This configuration causes the inward shrinkage of the end face of the dielectric isolation layer 150 to exceed the inward shrinkage of the end face of the first stress layer 140, forming a stepped profile that gradually decreases from the sidewall of the semiconductor layer 110 towards the gate structure 120. This gradually decreasing stepped morphology effectively reduces the deposition stress concentration of the second stress layer 160 at each step corner, while also ensuring that the second stress layer 160 can obtain a stable deposition starting point on the horizontal plane of each step. This is beneficial for improving the uniformity of overall coverage and further enhancing the sealing and passivation effect on the gate structure 120.

[0069] In some implementations, the second indentation distance H2 is equal to the first indentation distance H1. This setting simplifies process control and allows for simultaneous indentation of the first stress layer 140 and the dielectric isolation layer 150 with only one indentation setting. It is suitable for applications where step gradient requirements are not high, while still maintaining the improvement effect on the stress layer coverage quality.

[0070] In some embodiments, the angle α1 between the end face of the first stress layer 140 at the first step structure T1 and the upper surface of the semiconductor layer 110 is 90° to 135°.

[0071] Understandably, the end face D1 of the first stress layer 140 at the first step structure T1 is inclined, with the end face inclined inward from the upper surface of the first stress layer 140 towards the sidewall of the semiconductor layer 110. Furthermore, the cross-sectional shape of this end face can be a straight line, an arc, or a combination thereof. When the included angle is 90°, the end face has a vertical cross-section; when the included angle is greater than 90° but not exceeding 135°, the end face has an inwardly inclined slope-shaped cross-section, that is, the closer to the upper surface of the semiconductor layer 110, the greater the degree of inward inclination of the end face.

[0072] This configuration provides the second stress layer 160 with a sloped deposition surface at the first step structure T1. Compared to a completely vertical end face, the sloped end face allows the second stress layer 160 to grow downwards along the slope and fill the step during deposition, effectively avoiding stress concentration and weak coverage caused by abrupt changes in deposition angle at vertical corners. Simultaneously, the sloped end face increases the contact area between the first stress layer 140 and the second stress layer 160 at the interface, which helps to improve the interfacial bonding strength between the two layers and further improves the overall coverage quality of the second stress layer 160.

[0073] Furthermore, when the included angle is 135°, the end face tilt is the gentlest, the deposition transition of the second stress layer 160 is the smoothest, and the coverage effect is optimal.

[0074] In some embodiments, the angle α2 between the end face of the dielectric isolation layer 150 at the second step structure T2 and the upper surface of the first stress layer 140 is 90° to 135°.

[0075] Similarly, the dielectric isolation layer 150 has an inclined cross-section at the second step structure T2, which slopes inward from the outside of the dielectric isolation layer 150 toward the sidewall of the first stress layer 140. Its cross-sectional shape can be a straight line, an arc, or a combination thereof to adapt to different process conditions and performance requirements.

[0076] This configuration allows the end face of the dielectric isolation layer 150 to provide an inclined deposition support surface for the second stress layer 160. When the second stress layer 160 covers the second step structure T2, it can achieve a smooth morphological transition along the inclined end face, reducing the deposition shadow effect at the corner of the second step, and enabling the second stress layer 160 to grow uniformly and continuously in this area.

[0077] Furthermore, when the inclined end face at the first step structure T1 and the inclined end face at the second step structure T2 are co-located, the first step structure T1 and the second step structure T2 together form a stepped morphology with a gradient inclined profile. The second stress layer 160 starts from the sidewall of the semiconductor layer 110, passes sequentially through the inclined end faces of the first step and the second step, and climbs upwards step by step to the outer sidewall of the dielectric isolation layer 150. The entire growth path forms a continuous and stable overall protective layer, minimizing the gate off-state leakage current and improving the long-term reliability and withstand voltage performance of the device.

[0078] In some implementations, refer to Figures 4 to 6The gallium nitride high electron mobility transistor also includes an oxide layer 130. The oxide layer 130 is disposed on the top surface of the gate structure 120, and a first stress layer 140 extends from the sidewall of the gate structure 120 to the sidewall of the oxide layer 130 and covers the sidewall of the oxide layer 130; a second stress layer 160 covers the surface of the oxide layer 130 away from the gate structure 120.

[0079] Specifically, the oxide layer 130 is formed after the gate structure 120 is deposited and patterned, and before the first stress layer 140 is deposited, to provide insulation protection and chemical passivation for the top surface of the gate structure 120. The oxide layer 130 covers the top surface of the gate structure 120, preventing direct contact and corrosion damage to the top surface of the gate structure 120 by etching or cleaning solutions in subsequent process steps. The first stress layer 140 extends upward from the sidewall of the gate structure 120 to the sidewall of the oxide layer 130, encapsulating both the sidewall of the oxide layer 130 and the sidewall of the gate structure 120, forming a continuous protective connection from the sidewall of the gate structure 120 to the sidewall of the oxide layer 130.

[0080] Furthermore, the second stress layer 160 covers the surface of the oxide layer 130 facing away from the gate structure 120, that is, it covers the upper surface of the oxide layer 130, and is connected to the first stress layer 140 covering the sidewall of the oxide layer 130, thereby achieving a complete enclosure of the gate structure 120 and the oxide layer 130. The oxide layer 130 can be made of insulating dielectric materials such as silicon oxide, aluminum oxide, or silicon oxynitride, and its thickness can range from 2nm to 20nm, so as to provide sufficient insulation protection without significantly increasing the overall size of the gate structure 120.

[0081] This application also provides a method for manufacturing a gallium nitride high electron mobility transistor, referring to... Figure 3 The steps include S100 to S600.

[0082] Step S100, refer to Figure 3 In part a, a semiconductor layer 110 is formed on substrate 100.

[0083] As described above, the substrate 100 is the epitaxial wafer mentioned above, generally comprising a silicon substrate 101, a channel layer 102, a barrier layer 103, etc., stacked sequentially. The semiconductor layer 110 is a P-type gallium nitride layer located on the barrier layer 103. The above layers can be formed sequentially by epitaxial growth processes such as metal-organic chemical vapor deposition or molecular beam epitaxy, which are all conventional basic structures for gallium nitride power devices, and will not be described in detail here.

[0084] Step S200, refer to Figure 3 part b in Figure 3 In part c, a gate structure 120 is formed on semiconductor layer 110.

[0085] Specifically, a gate conductive material layer is deposited on the semiconductor layer 110, typically using a metal material such as titanium nitride. Subsequently, a gate pattern is defined using photolithography, and then the gate conductive material layer is etched to remove excess material outside the pattern, ultimately forming the gate structure 120 located on the semiconductor layer 110. Etching can employ dry etching processes such as reactive ion etching or inductively coupled plasma etching to obtain steep and precise gate sidewall morphologies.

[0086] Step S300, refer to Figure 3 In the d portion, a first stress layer 140 is deposited, such that the first stress layer 140 covers the sidewalls of the gate structure 120 and the upper surface of the semiconductor layer 110.

[0087] Specifically, after patterning the gate structure 120, a first stress layer 140 is conformally deposited on the upper surface of the semiconductor layer 110, the top surface of the gate structure 120, and the sidewalls using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition. The material of the first stress layer 140 is an aluminum-containing dielectric material, including at least one of aluminum nitride, aluminum oxide, or aluminum oxynitride. The deposition thickness can be from 0.8 nm to 2.5 nm. At this point, the first stress layer 140 forms a continuous arc-shaped coating at the corner where the sidewalls of the gate structure 120 and the upper surface of the semiconductor layer 110 intersect, achieving preliminary sealing of the sidewalls of the gate structure 120.

[0088] Step S400, refer to Figure 3 part e in Figure 3 In part f, the semiconductor layer 110 is etched to expose the sidewalls of the semiconductor layer 110.

[0089] Specifically, using the gate structure 120 and the first stress layer 140 on its sidewalls as a mask, anisotropic etching is performed on the P-type gallium nitride semiconductor layer 110 to remove the P-type gallium nitride material in areas not covered by the mask until the upper surface of the underlying barrier layer is exposed, thereby forming the sidewalls of the semiconductor layer 110 that are substantially aligned with the sidewalls of the gate structure 120. The etching process can employ dry etching with chlorine-based plasma to ensure the perpendicularity of the sidewalls and the etching selectivity.

[0090] Step S500, refer to Figure 4 The first stress layer 140 is recessed, so that the end of the first stress layer 140 on the upper surface of the semiconductor layer 110 is recessed inward relative to the sidewall of the semiconductor layer 110 to form a step.

[0091] Specifically, the inward retraction process refers to lateral etching of the end region of the first stress layer 140 on the upper surface of the semiconductor layer 110, causing it to retract inward relative to the sidewall of the semiconductor layer 110, thereby exposing a horizontal platform on the upper surface of the semiconductor layer 110 near the sidewall. This platform, together with the end face of the first stress layer 140, forms a stepped structure.

[0092] The shrinkage process generally employs isotropic dry etching or wet etching. For example, when using dry etching, a fluorine-containing gas plasma can be used for isotropic etching under low bias power conditions, and the shrinkage distance can be precisely controlled by adjusting the etching time and gas flow rate. When using wet etching, chemical solutions such as dilute hydrofluoric acid or hot phosphoric acid can be used. Utilizing the etching selectivity between the aluminum-containing dielectric material and the semiconductor layer 110, selective lateral etching of the end of the first stress layer 140 can be achieved, forming a regular shrinkage step.

[0093] In some embodiments, the etching conditions during the shrinkage process can be configured such that the shrinkage end face of the first stress layer 140 is inclined, and the angle between the inclined end face and the upper surface of the semiconductor layer 110 is 90° to 135°. The specific angle of the inclined end face can be controlled by adjusting the ratio of isotropic and anisotropic components during the etching process, or by adjusting the solution concentration and temperature of the wet etching.

[0094] Step S600, refer to Figure 5 A second stress layer 160 is deposited, which covers the outer side of the first stress layer 140 and the sidewall of the semiconductor layer 110, and fills the steps.

[0095] Specifically, after the shrinkage process, a second stress layer 160 is deposited using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition. The material of the second stress layer 160 is also an aluminum-containing dielectric material, including at least one of aluminum nitride, aluminum oxide, or aluminum oxynitride, and the deposition thickness can be from 2 nm to 10 nm. The second stress layer 160 starts from the sidewall of the semiconductor layer 110, fills the step formed by the shrinkage upwards, and covers the outer sidewall of the first stress layer 140, finally extending to cover the area above the gate structure 120, forming a complete sealing coverage of the gate structure 120 and the surface of the semiconductor layer 110.

[0096] In some implementations, steps S301 to S302 are included after step S300 and before step S400.

[0097] Step S301, refer to Figure 3 In part e, a dielectric isolation material is deposited and etched on the first stress layer 140 to form a dielectric isolation layer 150 located on both sides of the gate structure 120.

[0098] Specifically, a dielectric isolation material, which can be silicon nitride or silicon oxide, is deposited on the surface of the first stress layer 140. Subsequently, anisotropic etching is performed to remove the dielectric isolation material on the horizontal plane, retaining only the vertical portions on the sidewalls of the first stress layer 140 on both sides of the gate structure 120, forming a dielectric isolation layer 150. The lower surface of the dielectric isolation layer 150 sits on the upper surface of the first stress layer 140, and its upper surface can be flush with, slightly lower than, or slightly higher than the top surface of the gate structure 120 as needed.

[0099] Step S302, refer to Figure 6 The inward shrinkage process simultaneously causes the end face of the dielectric isolation layer 150 near the semiconductor layer 110 to be recessed inward relative to the sidewall of the first stress layer 140.

[0100] Specifically, during the shrinkage process in step S500, the etching medium acts simultaneously on the ends of the first stress layer 140 and the dielectric isolation layer 150. By selecting an etching formula capable of simultaneously etching the aluminum-containing dielectric material and the dielectric isolation layer 150 material, the first stress layer 140 and the dielectric isolation layer 150 can be shrunk synchronously in the same step.

[0101] In some embodiments, when wet etching is used, by selecting chemical solutions with different etching rates for aluminum-containing dielectric materials and for silicon nitride or silicon oxide, the recess distance of the dielectric isolation layer 150 can be different from the recess distance of the first stress layer 140. For example, when the etching rate of the etching solution on the dielectric isolation layer 150 material is greater than the etching rate on the first stress layer 140 material, the recess amount of the dielectric isolation layer 150 will be greater than the recess amount of the first stress layer 140, thereby forming a stepped profile with a deeper recess in the second step structure T2.

[0102] When using dry etching, the differential control of the shrinkage distance between the two materials can also be achieved by adjusting the proportion of isotropic gases in the etching gas composition. For example, by increasing the oxygen-containing gas composition, the lateral etching rate of silicon nitride can be accelerated, while the effect on the lateral etching rate of aluminum nitride is relatively small, thus achieving a differential shrinkage distance.

[0103] In some embodiments, by precisely controlling the process parameters of the shrinkage process, the end face of the shrunken dielectric isolation layer 150 can also be inclined, and the angle between the inclined end face and the upper surface of the first stress layer 140 is 90° to 135°.

[0104] In some implementations, step S201 is included after step S200 and before step S300.

[0105] Step S201, refer to Figure 3In part b, an oxide layer 130 is deposited on the surface of the gate structure 120, so that the oxide layer 130 covers the top surface of the gate structure 120.

[0106] Specifically, after the gate structure 120 is patterned, an oxide layer 130 is selectively or fully deposited and patterned on the top surface of the gate structure 120. The material of the oxide layer 130 can be an insulating dielectric material such as silicon oxide, aluminum oxide, or silicon oxynitride. The oxide layer 130 covers the top surface of the gate structure 120 to protect the top surface of the gate structure 120 from damage during subsequent etching and cleaning processes. Subsequently, the first stress layer 140, during deposition, simultaneously covers the sidewalls of the gate structure 120 and the sidewalls of the oxide layer 130, encapsulating the oxide layer 130 and the gate structure 120 together to form a continuous protective connection in the sidewall direction.

[0107] In some embodiments, the shrinkage process in step S500 can also be performed in a step-by-step manner. Specifically, the first stress layer 140 is first etched using a first etching condition to perform a first shrinkage process, forming an initial step; then, the dielectric isolation layer 150 is etched using a second etching condition to perform a second shrinkage process, causing its end face to be further recessed inward relative to the sidewall of the first stress layer 140. Step-by-step shrinkage allows for more precise control over the shrinkage distance and end face angle of each of the two steps, achieving a more complex stepped contour.

[0108] In some embodiments, after depositing the second stress layer 160 in step S600, the process may further include forming an ohmic contact electrode and a field plate on the semiconductor layer 110. Because the second stress layer 160 forms a thickened cladding profile at the sidewalls of the gate structure 120, the subsequently fabricated ohmic contact electrodes and field plates can be positioned further away from the gate structure 120, thereby increasing the physical distance between the gate and the ohmic contact and field plate, reducing the electric field concentration effect at the gate edge, and improving the device's breakdown voltage and long-term reliability.

[0109] In some embodiments, both the first stress layer 140 and the second stress layer 160 are prepared using atomic layer deposition (ALD) technology, and both are completed continuously in the same deposition equipment, with only one interruption after the shrinkage process. This arrangement can reduce interface contamination caused by transferring the device between different equipment and improve the interfacial bonding quality between the two stress layers.

[0110] In the above detailed description, reference has been made to the accompanying drawings, which illustrate specific aspects of how this disclosure can be practiced. In this regard, terms indicating direction or positional relationship, such as “thickness,” “upper,” “lower,” “top,” “bottom,” “inner,” and “outer,” can be used with reference to the orientation of the described figures. Since components of the described device can be positioned in several different orientations, these directional terms are for illustrative purposes and not for limitation. It should be understood that other aspects can be utilized and structural or logical changes can be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0111] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0112] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.

[0113] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A gallium nitride high electron mobility transistor, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate, and the band gap of the barrier layer is larger than the band gap of the channel layer; p-type doped III-V compound semiconductor layer, which is in contact with the barrier layer and located on the side of the barrier layer away from the channel layer; A gate structure is disposed on the p-type doped III-V compound semiconductor layer; A first stress layer is located on the upper surface of the p-type doped III-V compound semiconductor layer and extends to the gate structure to cover the sidewall of the gate structure. The end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer so that the end of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer form a first step structure. The second stress layer covers the outer side of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer, and the second stress layer fills the first step structure.

2. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, It also includes a dielectric isolation layer disposed on the sidewall of the first stress layer opposite to the gate structure, wherein the lower surface of the dielectric isolation layer is located on the upper surface of the first stress layer; wherein, The second stress layer continuously covers the outer wall of the dielectric isolation layer and the first stress layer.

3. The gallium nitride high electron mobility transistor according to claim 2, characterized in that, The first indentation distance is the distance at which the end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer, and the first indentation distance ranges from 5 nm to 100 nm.

4. The gallium nitride high electron mobility transistor according to claim 3, characterized in that, The end face of the dielectric isolation layer near the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the first stress layer, so that the end face of the dielectric isolation layer and the sidewall of the first stress layer form a second step structure; the second stress layer fills the second step structure.

5. The gallium nitride high electron mobility transistor according to claim 4, characterized in that, The end face of the dielectric isolation layer near the p-type doped III-V compound semiconductor layer is recessed inward by a distance relative to the sidewall of the first stress layer, which is the second inward distance, and the range of the second inward distance is 5nm to 150nm.

6. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The second inward distance is greater than the first inward distance.

7. The gallium nitride high electron mobility transistor according to claim 4, characterized in that, The first step structure and the second step structure together form a stepped profile, and the second stress layer conformally covers the stepped profile.

8. The gallium nitride high electron mobility transistor according to claim 7, characterized in that, The angle between the end face of the dielectric isolation layer at the second step structure and the upper surface of the first stress layer is 90° to 135°; and / or The angle between the end face of the first stress layer at the first step and the upper surface of the semiconductor layer is 90° to 135°.

9. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The thickness of the first stress layer is less than the thickness of the second stress layer.

10. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The thickness of the first stress layer is 0.8 nm to 2.5 nm, and the thickness of the second stress layer is 0.5 nm to 1 nm.

11. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, It also includes an oxide layer disposed on the top surface of the gate structure, a first stress layer extending from the sidewall of the gate structure to the sidewall of the oxide layer and covering the sidewall of the oxide layer; and a second stress layer covering the surface of the oxide layer away from the gate structure.

12. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The materials of the first stress layer and the second stress layer are both aluminum-containing dielectric materials, including at least one of aluminum nitride, aluminum oxide, or aluminum oxynitride.

13. A method for manufacturing a gallium nitride high electron mobility transistor, characterized in that, include: A channel layer, a barrier layer, and a p-type doped III-V compound semiconductor layer are sequentially formed on a substrate. A gate structure is formed on the p-type doped III-V compound semiconductor layer; A first stress layer is deposited, such that the first stress layer covers the sidewalls of the gate structure and the upper surface of the semiconductor layer; The p-type doped III-V compound semiconductor layer is etched to expose the sidewalls of the p-type doped III-V compound semiconductor layer; The first stress layer is recessed so that the end of the first stress layer on the upper surface of the p-type doped III-V compound semiconductor layer is recessed inward relative to the sidewall of the p-type doped III-V compound semiconductor layer to form a step. A second stress layer is deposited, covering the outer side of the first stress layer and the sidewall of the p-type doped III-V compound semiconductor layer, and filling the step.

14. The method according to claim 13, characterized in that, After depositing the first stress layer and before etching the p-type doped III-V compound semiconductor layer, the method further includes: depositing a dielectric isolation material on the first stress layer and etching it to form a dielectric isolation layer located on both sides of the gate structure. The inward reduction process simultaneously causes the lower end face of the dielectric isolation layer to be recessed inward relative to the sidewall of the semiconductor layer.

15. The method according to claim 14, characterized in that: Before depositing the first stress layer, the method further includes depositing an oxide layer on the surface of the gate structure, such that the oxide layer covers the top surface of the gate structure.

16. The method according to claim 14, characterized in that: The shrinkage process employs an isotropic dry etching process or a wet etching process.

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