Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the method for manufacturing the semiconductor device may include: patterning an SOI substrate to form a fin structure, wherein the SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an alternating stack of semiconductor and oxide layers on the buried oxide layer; forming a sacrificial gate intersecting the fin structure on the SOI substrate, and forming gate sidewalls on the sidewalls of the sacrificial gate; forming source / drain portions on opposite sides of the gate sidewalls; removing the sacrificial gate to expose the alternating stack of semiconductor and oxide layers in the space between the gate sidewalls; selectively etching away the oxide layers to expose the surfaces of the semiconductor layers; and forming a gate stack in the space between the gate sidewalls.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising multiple semiconductor layers and a method for manufacturing the same. Background Technology

[0002] Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) offer excellent control over short-channel effects and enable further miniaturization of devices. However, manufacturing GAA MOSFETs is complex and costly. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device comprising multiple semiconductor layers and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: patterning a semiconductor-on-insulator (SOI) substrate to form a fin structure, wherein the SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an alternating stack of semiconductor layers and oxide layers on the buried oxide layer; forming a sacrificial gate intersecting the fin structure on the SOI substrate, and forming gate sidewalls on the sidewalls of the sacrificial gate; forming source / drain portions on opposite sides of the gate sidewalls; removing the sacrificial gate to expose the alternating stack of semiconductor layers and oxide layers in the space between the gate sidewalls; selectively etching away the oxide layers to expose the surfaces of the semiconductor layers; and forming a gate stack in the space between the gate sidewalls.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a substrate; a buried oxide layer on the substrate; a channel including a plurality of semiconductor layers stacked above the buried oxide layer at intervals from each other; a source / drain portion above the buried oxide layer and disposed at opposite ends of the channel; and a gate stack intersecting the channel on the buried oxide layer.

[0006] According to embodiments of this disclosure, multiple alternating stacks of semiconductor layers and oxide layers can be formed on a buried oxide layer using multiple smart-cut processes, thereby fabricating a semiconductor device including a channel portion (e.g., a nanosheet) corresponding to the semiconductor layer. Therefore, the performance, such as stability, of the semiconductor device can be improved. Furthermore, the method for fabricating a semiconductor device according to embodiments of this disclosure can be simpler and has lower cost. Attached Figure Description

[0007] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figures 1 to 13(b)The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0009] Figure 14 This schematically illustrates multiple smart-cut processes.

[0010] in, Figure 1 , 3(a) Figures 4(a), 5(a), 6 to 10, 11(a), 12(a), 13(a), and 14 are cross-sectional views along line AA'.

[0011] Figure 3(b) , 4(b) Figures 5(b), 11(b), 12(b), and 13(b) are cross-sectional views along line BB'.

[0012] Figure 2 It is a top view. Figure 2 The positions of lines AA' and BB' are shown in the diagram. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0015] According to embodiments of this disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include a channel portion and source / drain portions disposed on opposite sides of the channel portion. The channel portion may include multiple semiconductor layers, wherein each semiconductor layer may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe). Each semiconductor layer may have a thickness in the range of about 10 nm to about 200 nm.

[0016] The semiconductor device can be disposed on a semiconductor-on-insulator (SOI) substrate. The semiconductor layers can be suspended relative to the substrate of the SOI substrate or a buried oxide layer on the substrate, and can extend substantially parallel to the surface of the substrate or buried oxide layer, and can be in the form of nanosheets. The semiconductor layers are spaced apart from each other in a vertical direction (e.g., substantially perpendicular to the surface of the substrate or buried oxide layer), and the spacing between adjacent semiconductor layers can range from about 20 nm to about 400 nm.

[0017] The channel portion may extend in a first direction, and its opposite ends in the first direction may be connected to the source / drain portion. The width of the channel portion between the source / drain portion (i.e., the length of the channel portion in the first direction) may be less than 3 times the spacing between adjacent semiconductor layers in a plurality of semiconductor layers, preferably less than 2 times that spacing.

[0018] The gate stack can extend along a second direction intersecting (e.g., perpendicular to) the first direction to intersect the channel portion, and thus can surround the outer periphery of the channel portion to form a gate all-around (GAA) structure. The gate stack may include a gate dielectric layer and a work function layer on the gate dielectric layer.

[0019] This semiconductor device can be fabricated as follows. An SOI substrate can be patterned to form a fin-shaped structure extending in a first direction. The SOI substrate may include a base substrate, a buried oxide layer on the base substrate, and alternating stacks of semiconductor and oxide layers on the buried oxide layer. The SOI substrate can be formed using SOI fabrication processes such as multiple smart-cut processes. Unlike conventional processes where semiconductor layers are formed through epitaxial growth, according to embodiments of this disclosure, semiconductor layers can be formed based on a smart-cut process (with the oxide layer serving as a sacrificial layer). Therefore, manufacturing costs can be reduced, and fabrication is easier.

[0020] Fin-shaped structures can protrude relative to the buried oxide layer. For the purpose of electrical isolation, shallow trench isolation (STI) can be formed between fin-shaped structures.

[0021] A sacrificial gate extending along a second direction intersecting the first direction and thus intersecting the fin structure can be formed on the SOI substrate. Considering the limitation of the gate stack space and the isolation between the gate stack and the source / drain portions, gate sidewalls can be formed on the sidewalls of the sacrificial gate. Additionally, inner sidewalls can also be formed. For example, the sacrificial gate and gate sidewalls can be used as etching masks to anisotropically etch the fin structure to expose the sidewalls of the semiconductor layer and oxide layer. Through the exposed sidewalls of the oxide layer, the oxide layer can be selectively etched to free up space for the inner sidewalls. The inner sidewalls can then be formed in this freed space. Subsequently, source / drain portions can be formed on opposite sides of the gate sidewalls in the first direction.

[0022] To form the gate stack, the sacrificial gate can be removed to expose an alternating stack of semiconductor and oxide layers within the space between the gate sidewalls. Subsequently, the oxide layer can be selectively etched away to expose the surface of the semiconductor layer. In this selective etching, the etch rate of the oxide layer can be greater than twice the etch rate of STI.

[0023] After removing the oxide layer, the gate dielectric layer and the work function layer can be stacked sequentially in the space between the gate sidewalls to form a gate stack.

[0024] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0025] Figures 1 to 13(b) The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0026] like Figure 1 As shown, an SOI substrate 100 is provided. The SOI substrate 100 may include a base substrate 1001, a buried oxide layer 1003 on the base substrate 1001, and an alternating stack of oxide layers 1005, 1009 and semiconductor layers 1007, 1011 on the buried oxide layer 1003. The oxide layers 1005, 1009 may define the location of the gate stack to be subsequently formed. In this example, two semiconductor layers 1007, 1011 are formed, and thus two nanosheets can ultimately be formed in the semiconductor device as a channel. However, this disclosure is not limited to this; the number of semiconductor layers to be formed and the number of oxide layers to be formed may be determined according to the number of nanosheets (which may be one or more) in the final channel to be formed.

[0027] The SOI substrate 100 can be formed using, for example, an SOI fabrication process such as a multi-step smart-cut process. The substrate 1001 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Here, a silicon wafer is used as an example to describe the substrate 1001. The buried oxide layer 1003 may include an oxide (e.g., silicon oxide). Semiconductor layers 1007 and 1011 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Each of the semiconductor layers 1007 and 1011 may have a thickness ranging from about 10 nm to about 200 nm. Each of the oxide layers 1005 and 1009 may have a thickness ranging from about 20 nm to about 400 nm. The greater the thickness of the oxide layers 1005 and 1009, the easier it is to remove them in a subsequent alternative gate process. To provide etching selectivity in subsequent processes, such as etching selectivity relative to the buried oxide layer 1003 and the subsequently formed shallow trench isolation (STI), an oxide, such as a phosphorus-doped oxide, may be included that has different etching characteristics relative to the buried oxide layer 1003 and the STI. According to other embodiments, the oxide layer 1005 may also be omitted.

[0028] In one example, the semiconductor layers 1007 and 1011 in different regions of the SOI substrate 100 may include different materials. For instance, in a first region forming an n-type field-effect transistor (FET), semiconductor layers 1007 and 1011 may include Si, while in a second region forming a p-type FET, semiconductor layers 1007 and 1011 may include SiGe to optimize the carrier mobility of the n-type FET and the p-type FET, respectively. The SiGe material of semiconductor layers 1007 and 1011 in the second region can be obtained by the Ge-condensation method. The Ge-condensation method itself is well known in FDSOI (fully depleted silicon-on-insulator) processes and will not be described further here.

[0029] In another example, the lower semiconductor layer 1007 and the upper semiconductor layer 1011 on the SOI substrate 100 may comprise different materials. For example, FETs may be formed on the SOI substrate 100, stacked on top of each other, with the lower semiconductor layer 1007 used for the lower FET and the upper semiconductor layer 1011 used for the upper FET. When the stacked FETs have different types, the semiconductor layers 1007 and 1011 may comprise different materials to optimize the carrier mobility of the upper and lower FETs respectively.

[0030] In another example, at least two of the semiconductor layers 1007 and 1011 (and the substrate of the SOI substrate 100) above the buried oxide layer 1003 may have different crystal structures from each other. According to related technologies, the semiconductor layers 1007 and 1011 used to form nanosheets are disposed on the substrate by an epitaxial growth process, and therefore have substantially the same or only slightly different crystal structures from each other. For example, homologous semiconductor materials can be grown, such as silicon-germanium or germanium grown on silicon. According to embodiments of this disclosure, since the SOI substrate is formed by an SOI fabrication process, the materials of the semiconductor layers 1007 and 1011 are not limited to materials achievable through epitaxial growth; for example, they may have different crystal phases or significantly different lattice constants, such as semiconductor materials of different systems (e.g., some of the substrate of the SOI substrate 100 and some of the semiconductor layers 1007 and 1011 may be silicon-based materials such as silicon, silicon-germanium, or germanium, while others may be semiconductor materials of other systems, such as III-V compound semiconductors, II-VI compound semiconductors, etc.).

[0031] In another example, at least two of the semiconductor layers 1007 and 1011 (and the substrate of the SOI substrate 100) above the buried oxide layer 1003 may have different crystal orientations from each other. In related techniques utilizing epitaxial growth, an upper layer grown on a lower layer has a substantially the same crystal orientation as the lower layer. According to embodiments of this disclosure, since the SOI substrate is formed via an SOI fabrication process, the crystal orientations of the semiconductor layers 1007 and 1011 can be rotated as needed (relative to the crystal orientation of the substrate), for example, during the bonding stage of the SOI fabrication process. Different crystal orientations can optimize device performance.

[0032] Next, the SOI substrate 100 can be patterned to form the channel portion.

[0033] For example, such as Figure 2 As shown, a mask such as photoresist 1013 can be formed on the SOI substrate, and the photoresist 1013 can be patterned into a form corresponding to the channel portion to be formed by photolithography. For example, in Figure 2 In the example shown, the photoresist 1013 can be in the form of a strip extending along a first direction (the horizontal direction within the plane of the paper in the figure).

[0034] For convenience, hard mask structures that may be used in the patterning process, such as hard masks in the form of stacked oxide / nitride layers, are not shown here. Furthermore, instead of being limited to examples using photoresist (+hard mask), spacer image transfer (SIT) processes can also be used. For example, sidewalls, such as nitride (e.g., silicon nitride), extending along a first direction can be formed on the SOI substrate 100 using a sidewall forming process, and these sidewalls can be used as patterning masks.

[0035] Then, as Figure 3(a) and 3(b) As shown, photoresist 1013 can be used as a mask to sequentially etch each layer using anisotropic etching, such as vertical reactive ion etching (RIE). According to an embodiment, the etching can penetrate into the substrate 1001. This forms a protruding structure (which may be referred to as a "fin structure") corresponding to the pattern of the photoresist 1013 on the substrate 1001. The photoresist 1013 can then be removed.

[0036] For electrical isolation purposes, such as Figure 4(a) and 4(b) As shown, isolation portions 1015, such as shallow trench isolation (STI), can be formed between the fin structures on the substrate 1001. For example, high-density plasma (HDP) oxide can be deposited on the substrate 1001, the deposited HDP oxide can be planarized (e.g., chemical mechanical polishing (CMP), and the planarized HDP oxide can be etched back to form the isolation portions 1015. An example is shown in the figures where the top surface of the isolation portion 1015 is substantially flush with the top surface of the buried oxide layer 1003. However, this disclosure is not limited thereto. For example, the top surface of the isolation portion 1015 can be at the height between the top and bottom surfaces of the buried oxide layer 1003. Each semiconductor layer 1007, 1011 protrudes outward relative to the top surface of the isolation portion 1015.

[0037] After that, as Figure 5(a) and 5(b) As shown, a sacrificial gate 1017 can be formed on the SOI substrate extending along a second direction intersecting the first direction (e.g., a direction perpendicular to the plane of the paper in FIG. 5(a), or a horizontal direction within the plane of the paper in FIG. 5(b), thus intersecting the aforementioned fin structure. For example, the sacrificial gate 1017 may include an oxide layer and polysilicon on the oxide layer. Similarly, for convenience, a hard mask that may exist on the sacrificial gate 1017 is not shown. On the sidewalls of the sacrificial gate 1017, a gate sidewall 1019 can be formed by a sidewall forming process. For example, the gate sidewall 1019 may include a nitride. The gate sidewall 1019 may sometimes also be referred to as an outer sidewall.

[0038] like Figure 6 As shown, the sacrificial gate 1017 and gate sidewall 1019 can be used as etching masks to perform anisotropic etching, such as vertical RIE, on the semiconductor layers 1007, 1011 and oxide layers 1005, 1009. The RIE can stop at the buried oxide layer 1003. Thus, the etched semiconductor layers 1007, 1011 can form a channel portion self-aligned with the sacrificial gate 1017.

[0039] According to embodiments of this disclosure, an inner sidewall can also be formed.

[0040] For example, such as Figure 7 As shown, oxide layers 1005 and 1009 can be selectively etched relative to semiconductor layers 1007 and 1011, such that their sidewalls are recessed inward to a certain depth relative to the sidewall of gate sidewall 1019 or the sidewall of semiconductor layers 1007 and 1011. Preferably, the recess depths of oxide layers 1005 and 1009 are substantially the same and can be substantially equal to the thickness (in the first direction) of gate sidewall 1019, so that the subsequently formed inner sidewall can have substantially the same thickness as gate sidewall 1019.

[0041] In such a recess, an inner wall can be formed. For example... Figure 8 As shown, a dielectric material layer of a certain thickness can be formed on the substrate 1001 by, for example, deposition. The thickness of the deposited dielectric material layer is sufficient to fill the aforementioned recess. For example, the dielectric material layer may include SiC, etc. Subsequently, the deposited dielectric material layer can be etched back by, for example, a vertical RIE, to form the inner sidewall 1021. The inner sidewall 1021 may also include the same material as the gate sidewall 1019.

[0042] like Figure 8 As shown, in the first direction ( Figure 8 In the horizontal direction within the paper (as shown), the sidewalls of each semiconductor layer 1007 and 1011 are exposed. For example... Figure 9 As shown, the sidewalls of the exposed semiconductor layers 1007 and 1011 serve as seeds, and source / drain portions 1023 are formed through selective epitaxial growth, for example. The source / drain portions 1023 can be formed to be in contact with the exposed sidewalls of the semiconductor layers 1007 and 1011. The source / drain portions 1023 can comprise various suitable semiconductor materials, for example, Si for n-type FETs and SiGe for p-type FETs. The source / drain portions 1023 can be doped to the desired conductivity type (n-type doping for n-type FETs and p-type doping for p-type FETs) through, for example, in-situ doping or ion implantation.

[0043] Next, an alternative gate process can be implemented.

[0044] For example, such as Figure 10 As shown, an interlayer dielectric layer 1025 can be formed on the substrate 1001. For example, the interlayer dielectric layer 1025 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed up to expose the sacrificial gate 1017 inside the gate sidewall 1019.

[0045] like Figure 11(a) and 11(b)As shown, the sacrificial gate 1017 can be selectively etched away to expose the alternating stacking of semiconductor layers 1007, 1011 and oxide layers 1005, 1009 in the space between the gate sidewalls 1019. It can be seen that the sidewalls of oxide layers 1005, 1009 are exposed in the second direction (see Figure 11(b)).

[0046] After that, as Figure 12(a) and 12(b) As shown, the oxide layers 1005 and 1009 can be selectively etched to expose the surfaces of the semiconductor layers 1007 and 1011. As described above, since the oxide layers 1005 and 1009 may include phosphorus-doped oxides and the isolation portion 1015 may include HDP oxides, the etching rate of the oxide layers 1005 and 1009 during selective etching to remove them can be twice or more than the etching rate of the isolation portion 1015. Therefore, the oxide layers 1005 and 1009 can be substantially completely removed without substantially affecting the isolation portion 1015.

[0047] Next, as Figure 13(a) and 13(b) As shown, a gate stack can be formed within the space between the gate sidewalls 1019. For example, a gate dielectric layer 1027 and a gate conductor layer 1029 can be formed sequentially to obtain the final gate stack. For example, the gate dielectric layer 1027 may include a high-k gate dielectric such as hafnium oxide (HfO2). The gate conductor layer 1029 may include a work function layer and a gate electrode metal such as tungsten (W). The work function layer can have a suitable work function, for example, an n-type work function for an n-type FET and a p-type work function for a p-type FET.

[0048] like Figure 13(a) and 13(b) As shown, the semiconductor device according to the embodiment may include semiconductor layers 1007, 1011 (the number may be fewer or more), and a gate stack surrounding the semiconductor layers 1007, 1011, the gate stack including a gate dielectric layer 1027 and a gate conductor layer 1029. In the case where the oxide layer 1005 is omitted as described above, the gate stack may not extend below the bottommost semiconductor layer 1007.

[0049] Compared to conventional methods, the method for manufacturing semiconductor devices according to the embodiments is simpler and has lower costs. Furthermore, due to the semiconductor layer, the semiconductor devices according to the embodiments can have improved performance.

[0050] The following will refer to Figure 14Here is a brief description of a multi-step smart-cut process. Wafer 1001 and wafer 200 can be provided. On wafer 200, an oxide layer can be formed, for example, by oxidation, and phosphorus can be doped in a portion of this oxide layer, for example, by ion implantation. Therefore, a stack of phosphorus-doped oxide layer 1005 and buried oxide layer 1003 can be formed on wafer 200. Hydrogen ion implantation can be performed on wafer 200 to define dicing locations therein. Wafer 200 can be bonded to wafer 1001 with the buried oxide layer 1003 facing the surface of wafer 1001 (the surface of wafer 1001 can also have an oxide layer, such as a thin intrinsic oxide layer). Wafer 200 is divided based on the dicing locations defined by hydrogen ion implantation, and a polishing process is performed on the semiconductor layer remaining on wafer 200 to form semiconductor layer 1007. Subsequently, the aforementioned smart-cut process can be performed again on a (single-batch) SOI substrate formed in this way, thereby forming a (multi-batch) SOI substrate, for example... Figure 1 SOI substrate 100.

[0051] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0052] In addition, the work function layer includes metallic materials such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: The SOI substrate is patterned to form a fin structure, wherein the SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an alternating stack of semiconductor layers and oxide layers on the buried oxide layer; A sacrificial gate intersecting with the fin structure is formed on the SOI substrate, and a gate sidewall is formed on the sidewall of the sacrificial gate; Source / drain portions are formed on opposite sides of the gate sidewall; Remove the sacrificial gate to expose the alternating stack of the semiconductor layer and the oxide layer in the space between the gate sidewalls; The oxide layer is selectively etched away to expose the surface of the semiconductor layer; and A grid stack is formed in the space between the grid sidewalls.

2. The method of claim 1, wherein, The SOI substrate is formed through multiple smart-cut processes.

3. The method of claim 1, wherein, The thickness of each of the semiconductor layers is 10 nm to 200 nm, and the thickness of each of the oxide layers is 20 nm to 400 nm.

4. The method of claim 1, wherein, The fin-shaped structure protrudes relative to the buried oxide layer, and the method further includes: Shallow grooves are formed between the fin-shaped structures to isolate STIs. In the selective etching, the etching rate of the oxide layer is greater than twice the etching rate of the STI.

5. The method of claim 4, wherein, The oxide layer comprises phosphorus-doped oxide, and the STI comprises high-density plasma HDP oxide.

6. The method of claim 1, wherein, The gate stack includes a gate dielectric layer and a work function layer on the gate dielectric layer.

7. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; The channel portion includes multiple semiconductor layers stacked on top of the buried oxide layer at intervals from each other; Source / drain portion, located above the buried oxygen layer and at opposite ends of the channel portion; as well as The grid stack intersects with the channel portion on the buried oxide layer.

8. The semiconductor device of claim 7, wherein, The thickness of each of the plurality of semiconductor layers is from 10 nm to 200 nm.

9. The semiconductor device of claim 7, wherein, The spacing between adjacent semiconductor layers in the plurality of semiconductor layers is in the range of 20 nm to 400 nm.

10. The semiconductor device of claim 7, wherein, At least two of the plurality of semiconductor layers and the substrate have different crystal structures and / or crystal orientations from each other.

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