Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. The semiconductor device of the embodiment includes a semiconductor layer and first to third FP insulating films disposed in a columnar shape within a first semiconductor region of a first conductivity type in the semiconductor layer, and wherein first to third field plate (FP) electrodes are respectively disposed therein. A second FP insulating film is arranged with the first FP insulating film along a second direction orthogonal to a first direction from a first main surface of the semiconductor layer toward a second main surface. A third FP insulating film is arranged with the first FP insulating film along a third direction orthogonal to the first direction and different from the second direction. A first distance between the first FP electrode and the second FP electrode is less than a second distance between the first FP electrode and the third FP electrode. The first FP insulating film includes a first portion located on a line connecting the first FP electrode and the second FP electrode, and a second portion located on the line connecting the first FP electrode and the third FP electrode, having a dielectric constant higher than the first portion.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2024-223123 (filed on December 18, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0004] Known devices include so-called point-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which have multiple columnar field plate electrodes (FP electrodes). In such semiconductor devices, a high breakdown voltage is preferred. However, in point-type MOSFETs, the distance between the FP electrode and the gate electrode is not constant. Therefore, in the portion where the distance from the FP electrode to the gate electrode is relatively long, the drift region is not sufficiently exhausted compared to the portion where the distance is relatively short, and in some cases, the target breakdown voltage cannot be guaranteed. Summary of the Invention

[0005] The semiconductor device of the embodiment includes a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a first field plate insulating film, a second field plate insulating film, and a third field plate insulating film. The semiconductor layer has a first main surface and a second main surface. The first electrode is disposed on the first main surface. The second electrode is disposed on the second main surface. The first semiconductor region is disposed within the semiconductor layer and electrically connected to the first electrode. The second semiconductor region is disposed within the semiconductor layer and located above the first semiconductor region. The third semiconductor region is disposed within the semiconductor layer and located above the second semiconductor region. The gate electrode is disposed within the second semiconductor region via a gate insulating film. The first field plate insulating film is configured in a columnar shape within the first semiconductor region, and a first field plate electrode is disposed therein. The second field plate insulating film is configured in a columnar shape within the first semiconductor region, and a second field plate electrode is disposed therein, and is arranged along a second direction orthogonal to a first direction from the first main surface toward the second main surface, and is aligned with the first field plate insulating film. The third field plate insulating film is configured in a columnar shape within the first semiconductor region, and a third field plate electrode is disposed therein, arranged along a third direction orthogonal to the first direction and different from the second direction. A first distance between the first field plate electrode and the second field plate electrode is less than a second distance between the first field plate electrode and the third field plate electrode. The first field plate insulating film has a first portion located on the line connecting the first field plate electrode and the second field plate electrode, and a second portion located on the line connecting the first field plate electrode and the third field plate electrode. The dielectric constant of the second portion of the first field plate insulating film is higher than the dielectric constant of the first portion of the first field plate insulating film.

[0006] The semiconductor device of the embodiment includes: a semiconductor layer having a first main surface and a second main surface; a first electrode disposed on the first main surface; a second electrode disposed on the second main surface; a first semiconductor region of a first conductivity type disposed within the semiconductor layer and electrically connected to the first electrode; a second semiconductor region of a second conductivity type disposed within the semiconductor layer and located above the first semiconductor region; a third semiconductor region of a first conductivity type disposed within the semiconductor layer and located above the second semiconductor region; and a gate electrode disposed within the second semiconductor region via a gate insulating film, extending along a path from the first main surface toward the second main surface. The first surface extends orthogonally in a first direction; and a first field plate insulating film is disposed in a columnar shape within the first semiconductor region, and a first field plate electrode is disposed therein; the distance between the first field plate electrode and a first position of the gate electrode is smaller than the distance between the first field plate electrode and a second position of the gate electrode, the first field plate insulating film having a first portion located on a line connecting the first field plate electrode and the first position and a second portion located on a line connecting the first field plate electrode and the second position, the dielectric constant of the second portion of the first field plate insulating film being higher than the dielectric constant of the first portion of the first field plate insulating film.

[0007] The method for manufacturing the semiconductor device according to the embodiment includes the following steps:

[0008] A semiconductor layer is prepared, the semiconductor layer having a first main surface and a second main surface, and comprising: a first semiconductor region of a first conductivity type; a first field plate insulating film disposed in a columnar shape within the first semiconductor region, with a first field plate electrode disposed therein; a second field plate insulating film disposed in a columnar shape within the first semiconductor region, with a second field plate electrode disposed therein, and arranged with the first field plate insulating film along a second direction orthogonal to a first direction from the first main surface toward the second main surface; and a third field plate insulating film disposed in a columnar shape within the first semiconductor region, with a third field plate electrode disposed therein, and arranged with the first field plate insulating film along a third direction orthogonal to the first direction and different from the second direction; a first distance between the first field plate electrode and the second field plate electrode is smaller than a second distance between the first field plate electrode and the third field plate electrode;

[0009] A trench is formed in the first field plate insulating film by removing at least halfway from the second main surface to the middle of the first field plate insulating film on the line connecting the first field plate electrode and the third field plate electrode; and

[0010] The trenches are filled with a material whose dielectric constant is higher than that of the silicon oxide film.

[0011] The method for manufacturing the semiconductor device according to the embodiment includes the following steps:

[0012] A semiconductor layer is prepared, the semiconductor layer having a first main surface and a second main surface, and comprising: a first semiconductor region of a first conductivity type; a first field plate insulating film disposed in a columnar shape within the first semiconductor region, with a first field plate electrode disposed therein; a second field plate insulating film disposed in a columnar shape within the first semiconductor region, with a second field plate electrode disposed therein, and arranged with the first field plate insulating film along a second direction orthogonal to a first direction from the first main surface toward the second main surface; and a third field plate insulating film disposed in a columnar shape within the first semiconductor region, with a third field plate electrode disposed therein, and arranged with the first field plate insulating film along a third direction orthogonal to the first direction and different from the second direction; a first distance between the first field plate electrode and the second field plate electrode is smaller than a second distance between the first field plate electrode and the third field plate electrode;

[0013] A trench is formed in the first field plate insulating film by removing at least halfway from the second main surface to the middle of the first field plate insulating film, on the portion of the line connecting the first field plate electrode and the second field plate electrode; and

[0014] The trenches are filled with a material having a lower dielectric constant than the silicon oxide film, or an insulating material is deposited in the trenches in a manner that forms voids.

[0015] According to embodiments of the present invention, a semiconductor device capable of improving voltage withstand capability can be provided. Attached Figure Description

[0016] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0017] Figure 2 yes Figure 1 Enlarged image.

[0018] Figure 3 The semiconductor device of the first embodiment is along Figure 1 A cross-sectional view along the U-axis.

[0019] Figure 4 The semiconductor device of the first embodiment is along Figure 1 A cross-sectional view along the V-axis.

[0020] Figure 5A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0021] Figure 5B It continues Figure 5AA cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0022] Figure 5C It continues Figure 5B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0023] Figure 5D yes Figure 5C A schematic top view of a semiconductor device according to a first embodiment of the manufacturing process shown.

[0024] Figure 5E It continues Figure 5C A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0025] Figure 5F It continues Figure 5E A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0026] Figure 5G It continues Figure 5F A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0027] Figure 5H It continues Figure 5G A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0028] Figure 5I It continues Figure 5H A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0029] Figure 6 The semiconductor device of the modified embodiment of the first embodiment is along Figure 1 A cross-sectional view along the U-axis.

[0030] Figure 7 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device in a modified embodiment of the first embodiment.

[0031] Figure 8 This is a top view of the semiconductor device according to the second embodiment.

[0032] Figure 9 yes Figure 8 Enlarged image.

[0033] Figure 10 The semiconductor device of the second embodiment is along Figure 8 A cross-sectional view along the U-axis.

[0034] Figure 11 The semiconductor device of the second embodiment is along Figure 8 A cross-sectional view along the V-axis.

[0035] Figure 12A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0036] Figure 12B yes Figure 12A A schematic top view of a semiconductor device according to the second embodiment in the manufacturing process shown.

[0037] Figure 12C It continues Figure 12A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0038] Figure 12D It continues Figure 12C A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0039] Figure 12E It continues Figure 12D A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0040] Figure 12F It continues Figure 12E A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0041] Figure 13 The semiconductor device of the third embodiment is along Figure 8 A cross-sectional view along the U-axis.

[0042] Figure 14 This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the third embodiment.

[0043] Figure 15 This is a top view of a semiconductor device of another variation of the embodiment 1.

[0044] Figure 16 This is a top view of a semiconductor device of another variation of the embodiment, Example 2.

[0045] Figure 17 This is a top view of a semiconductor device of another variation of the embodiment, 3.

[0046] Figure 18 This is a top view of a semiconductor device of another variation of the embodiment, 4.

[0047] Figure 19This is a top view of a semiconductor device of another variation of the embodiment, 5. Detailed Implementation

[0048] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, elements identical to those described in previously existing drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0049] Additionally, in the following explanation, to indicate the relative levels of impurity concentration for each conductivity type, n is sometimes used. + n, n - and p + p, p - These statements. That is, n + This indicates that the concentration of n-type impurities is relatively high compared to n. - This indicates that the concentration of n-type impurities is relatively low compared to n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively high compared to p-type impurities. - This indicates that the concentration of p-type impurities is relatively low compared to p-type impurities. When both p-type and n-type impurities are present in various regions, these expressions represent the relative levels of net impurity concentration after these impurities compensate for each other. n-type, n... + type and n - p-type is an example of the first conductivity type in the claims. + Type and p - The n-type is an example of the second conductivity type in the claims. Furthermore, in the following description, the n-type and p-type may be reversed. That is, the first conductivity type may also be p-type.

[0050] Furthermore, the impurity concentration in the semiconductor region can be determined, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of the impurity concentration can also be determined, for example, by the level of the carrier concentration obtained using scanning capacitance microscopy (SCM).

[0051] In addition, dimensions such as the thickness of the field plate insulating film can be determined, for example, by surface and / or cross-sectional analysis using methods such as transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), and scanning electron microscopy (SEM).

[0052] In addition, the composition of the field plate insulating film can be analyzed, for example, by X-ray photoelectron spectroscopy (XPS) and secondary ion mass analysis.

[0053] Furthermore, the terms used in this specification, such as “same,” “identical,” “equal,” etc., which determine their degree, as well as the values ​​of dimensions and physical properties, are not limited to a strict meaning but should be interpreted as encompassing a range of degrees to which the same function can be expected.

[0054] (First Implementation)

[0055] Reference Figures 1-4 The semiconductor device 1 of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device 1 according to the first embodiment. Figure 1 In the diagram, the U-axis direction is from FP trench FT1 towards FP trench FT2. The V-axis direction is from FP trench FT1 towards FP trench FT3. The Z-axis direction is the stacking direction (thickness direction) of semiconductor device 1. Both the U-axis and V-axis directions are orthogonal to the Z-axis direction. Furthermore, the source electrode side in the Z-axis direction is also referred to as "upper," and the drain electrode side is also referred to as "lower." However, this expression is for convenience and is unrelated to the direction of gravity. The Z-axis direction is the first direction in the claims. The U-axis direction is the second direction in the claims. The V-axis direction is the third direction in the claims. Additionally, in... Figure 1 In the original text, the source electrode 12, the source region 24, and the interlayer insulating film 60 are omitted. Figure 2 yes Figure 1 The enlarged view shows the periphery of FP trenches FT1, FT2, and FT3. Figure 3 Along the semiconductor device 1 of the first embodiment Figure 1 A cross-sectional view along the U-axis. Figure 4 Along the semiconductor device 1 of the first embodiment Figure 1 A cross-sectional view along the V-axis. Furthermore, in Figure 3In the diagram, FP electrodes 31 and 32 are shown as FP electrode 30. Figure 4 In the figure, FP electrodes 31 and 33 are shown as FP electrode 30.

[0056] Semiconductor device 1 is, for example, a MOSFET. More specifically, semiconductor device 1 is a so-called point-type MOSFET having multiple field plate electrodes (FP electrodes) arranged in a columnar shape, that is, extending along the Z-axis direction. Alternatively, semiconductor device 1 can also be a point-type IGBT (Insulated Gate Bipolar Transistor), etc.

[0057] like Figure 1 As shown, the semiconductor device 1 includes multiple field plate trenches (FP trenches) FT. Within each FP trench FT, an FP electrode 30 and a field plate insulating film (FP insulating film) 40 surrounding the FP electrode 30 are disposed. Each FP insulating film 40 includes a first portion 40a and a second portion 40b with a dielectric constant higher than that of the first portion 40a, as detailed later.

[0058] Furthermore, a semiconductor region (e.g., substrate region 23) is disposed around the FP insulating film 40, and a gate insulating film 50 is disposed around the semiconductor region. Additionally, a mesh of gate electrodes 13 bonded together is disposed around the gate insulating film 50.

[0059] Next, the cross-sectional structure of the semiconductor device 1 in this embodiment will be described.

[0060] In the following explanation, regarding Figure 1 The FP trenches FT1, FP trench FT2, and FP trench FT3 shown are described. In this embodiment, the multiple FP trenches FT, such as FP trenches FT1, FT2, and FT3, all have the same structure.

[0061] In addition, such as Figure 2 As shown, in the following description, to distinguish the FP electrodes 30 within each FP trench FT1, FT2, and FT3, the FP electrodes 30 within FP trenches FT1, FT2, and FT3 are referred to as FP electrodes 31, 32, and 33, respectively. Similarly, the FP insulating films 40 within FP trenches FT1, FT2, and FT3 are referred to as FP insulating films 41, 42, and 43, respectively. Furthermore, the first portion 40a within FP insulating films 41, 42, and 43 are referred to as first portions 41a, 42a, and 43a, respectively. Similarly, the second portion 40b within FP insulating films 41, 42, and 43 are referred to as second portions 41b, 42b, and 43b, respectively.

[0062] like Figure 3 and Figure 4As shown, the semiconductor device 1 of this embodiment includes a semiconductor layer 2, a drain electrode 11, and a source electrode 12.

[0063] Semiconductor layer 2 is disposed between drain electrode 11 and source electrode 12. Semiconductor layer 2 has a lower surface (first main surface) 2a and an upper surface (second main surface) 2b opposite to the lower surface 2a. Various semiconductor regions, etc., described later, are disposed within semiconductor layer 2.

[0064] Semiconductor layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity. Alternatively, semiconductor layer 2 can also be composed of compound semiconductors such as silicon carbide (SiC) or gallium nitride (GaN).

[0065] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2. The drain electrode 11 is connected to the drain region 22, for example, in an ohmic contact with the drain region 22. The drain electrode 11 is an example of the first electrode in the claims. The drain electrode 11 may contain at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al).

[0066] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2. The source electrode 12 is connected to the source region 24, for example, in an ohmic contact with the source region 24. The source electrode 12 is an example of the second electrode described in the claims. The source electrode 12 may contain at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al).

[0067] The structure within semiconductor layer 2 will be described below.

[0068] Within the semiconductor layer 2, for example, a drift region 21, a drain region 22, a substrate region 23, a source region 24, a gate electrode 13, FP electrodes 30 (FP electrodes 31, 32, 33), FP insulating films 40 (FP insulating films 41, 42, 43), a gate insulating film 50, and an interlayer insulating film 60 are provided.

[0069] Drift region 21 functions as the drift region of the MOSFET. Drift region 21 is positioned above drain region 22 (above drain electrode 11). Drift region 21 is, for example, n - The n-type semiconductor region. The n-type impurity concentration in drift region 21 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 2×1016 cm -3 the following.

[0070] Drain region 22 functions as the drain region of the MOSFET. Drain region 22 is located above drain electrode 11, positioned between drift region 21 and drain electrode 11. Drain region 22 is connected to and electrically connected to drain electrode 11. For example, drain region 22 is n... + The n-type semiconductor region. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0071] Both the drift region 21 and the drain region 22 are examples of the first semiconductor region in the claims. Alternatively, the drain region 22 may not be provided. In this case, the drift region 21 is directly disposed on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 may not be provided. In this case, for example, the drain region 22 is also disposed at the location of the drift region 21.

[0072] Substrate region 23 functions as the substrate region of the MOSFET. Substrate region 23 is located above drift region 21. Substrate region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of substrate region 23 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 20 cm -3 Below, substrate region 23 is an example of a second semiconductor region in the claims.

[0073] Source region 24 functions as the source region of the MOSFET. Source region 24 is located above substrate region 23. Source region 24 is connected to and electrically connected to source electrode 12. Source region 24 is, for example, n + The source region 24 is a semiconductor region of type n. The n-type impurity concentration is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 22 cm -3 Below, source region 24 is an example of a third semiconductor region in the claims.

[0074] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is disposed within the substrate region 23 via a gate insulating film 50. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the gate insulating film 50. The gate electrode 13 is made, for example, of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the substrate region 23, and charge carriers flow between the drift region 21 and the source region 24. This turns the MOSFET on.

[0075] The FP electrode 30 is disposed in a columnar shape within the drift region 21 via the FP insulating film 40. Figure 3 In the diagram, FP electrodes 31 and 32 are shown as FP electrode 30. Figure 4 In the figure, FP electrodes 31 and 33 are shown as FP electrode 30. FP electrode 31, FP electrode 32 and FP electrode 33 are examples of the first field plate electrode, the second field plate electrode and the third field plate electrode in the claims, respectively.

[0076] The FP electrode 30 is electrically insulated from the semiconductor layer 2 through the FP insulating film 40 and is electrically connected to the source electrode 12. Figure 3 and Figure 4 In this example, the source electrode 12 has a portion that protrudes downward from the upper surface 2b of the semiconductor layer 2 and is in contact with the FP electrode 30. The FP electrode 30 is, for example, made of polycrystalline silicon containing p-type or n-type impurities.

[0077] In this embodiment, the FP electrode 30 is configured to be adjacent to both the drift region 21 and the substrate region 23. That is, the upper end of the FP electrode 30 is higher than the lower end of the substrate region 23. Alternatively, the upper end of the FP electrode 30 may be lower than the lower end of the substrate region 23.

[0078] The FP insulating film 40 is columnar within the drift region 21, and an FP electrode 30 is disposed therein. More specifically, the FP insulating film 41 is columnar within the drift region 21, and an FP electrode 31 is disposed therein. The FP insulating film 42 is columnar within the drift region 21, and an FP electrode 32 is disposed therein. The FP insulating film 43 is columnar within the drift region 21, and an FP electrode 33 is disposed therein. The FP insulating films 41, 42, and 43 are examples of the first, second, and third field plate insulating films as described in the claims.

[0079] like Figure 1 As shown, the FP insulating film 40 has a first portion 40a and a second portion 40b. As... Figure 2 As shown, for example, the FP insulating film 41 includes a first portion 41a and a second portion 41b. Furthermore, in Figure 3In the diagram, the first portion 41a of the FP insulating film 41 and the first portion 42a of the FP insulating film 42 are illustrated as the first portion 40a of the FP insulating film 40. Additionally, in Figure 4 In the figure, as the second part 40b of FP insulating film 40, the second part 41b of FP insulating film 41 and the second part 43b of FP insulating film 43 are illustrated.

[0080] The dielectric constant of the second portion 40b in the FP insulating film 40 is higher than that of the first portion 40a in the FP insulating film 40. For example, the dielectric constant of the second portion 41b in the FP insulating film 41 is higher than that of the first portion 41a in the FP insulating film 41. In this embodiment, the first portion 40a of the FP insulating film 40 is a silicon oxide film, and the second portion 40b of the FP insulating film 40 is made of a material with a higher dielectric constant than that of the silicon oxide film. The second portion 40b may, for example, contain a silicon nitride film. In this case, for example, the relative dielectric constant of the first portion 41a is about 3.9, and the relative dielectric constant of the second portion 40b is about 7.0.

[0081] In addition, such as Figure 4 As shown, in this embodiment, the FP insulating film 40 includes a third portion 40c located below the second portion 40b and disposed above the drift region 21. For example, the FP insulating film 41 includes a third portion 41c located below the second portion 41b and disposed above the drift region 21. Figure 4 In the illustration, the third portion 40c of the FP insulating film 40 is shown as the third portion 41c of the FP insulating film 41 and the third portion 43c of the FP insulating film 43. The third portion 40c is, for example, made of the same material as the first portion 40a. The third portion 40c is, for example, a silicon oxide film.

[0082] The gate insulating film 50 electrically insulates the gate electrode 13 from the semiconductor layer 2 and the source electrode 12. The gate insulating film 50 may contain, for example, silicon oxide or silicon nitride.

[0083] An interlayer insulating film 60 is disposed on the FP insulating film 40. The interlayer insulating film 60 may comprise, for example, silicon oxide or silicon nitride. Furthermore, the thickness of the interlayer insulating film 60 and the position of its lower end are not limited to... Figure 3 and Figure 4 The example shown is arbitrary. Additionally, the interlayer insulating film 60 can also be disposed on the gate electrode 13.

[0084] Next, refer to Figure 2 The planar structure of the semiconductor device 1 in this embodiment will be described in more detail.

[0085] like Figure 2As shown, in this embodiment, the FP insulating film 40 is hexagonal in a plane orthogonal to the Z-axis, that is, in a plane containing the U-axis and V-axis (UV plane). For example, the FP insulating film 41 in the FP trench FT1 is hexagonal in the UV plane.

[0086] The FP trench FT2 is arranged in a manner that is perpendicular to the Z-axis direction and aligned with the FP trench FT1. That is, the FP electrode 32 is aligned with the FP electrode 31 along the U-axis direction. In addition, the FP insulating film 42 is aligned with the FP insulating film 41 along the U-axis direction.

[0087] The FP trench FT3 is arranged with the FP trench FT1 along the V-axis direction, which is orthogonal to the Z-axis direction and different from the U-axis direction. That is, the FP electrode 33 is arranged with the FP electrode 31 along the V-axis direction. In addition, the FP insulating film 43 is arranged with the FP insulating film 41 along the V-axis direction.

[0088] Furthermore, the FP trench FT2 is positioned closer to the FP trench FT1 than the FP trench FT3. That is, the distance d1 between the FP electrode 31 and the FP electrode 32 is less than the distance d2 between the FP electrode 31 and the FP electrode 33. Distances d1 and d2 are examples of the first and second distances stated in the claims, respectively.

[0089] exist Figure 2 In the example, distance d1 is defined by the distance between the center C of FP electrode 31 and the center C of FP electrode 32 in the UV plane. Similarly, distance d2 is defined by the distance between the center C of FP electrode 31 and the center C of FP electrode 33 in the UV plane. Furthermore, the definitions of distances d1 and d2 are not limited to the above definitions. For example, distance d1 can also be defined by the distance between the end of FP electrode 31 and the end of FP electrode 32 in the UV plane.

[0090] Furthermore, the first portion 41a of the FP insulating film 41 is located on the line connecting the FP electrode 31 and the FP electrode 32. The second portion 41b of the FP insulating film 41 is located on the line connecting the FP electrode 31 and the FP electrode 33. That is, the first portion 41a of the FP insulating film 41 is located at the edge of the FP insulating film 41 in the UV plane. Additionally, the second portion 41b of the FP insulating film 41 is located at the corner of the FP insulating film 41 in the UV plane. Moreover, the planar shapes of the first portion 40a and the second portion 40b are not limited to... Figure 2 The example shown is arbitrary. For instance, the width of the first part 40a can be greater than... Figure 2 The example shown is large, and can also be larger than Figure 2 The example shown is small.

[0091] Furthermore, the positions of the first portion 41a and the second portion 41b of the FP insulating film 41 are also related to the gate electrode 13 in the following manner: The gate electrode 13 extends at least a predetermined length along a direction orthogonal to the Z-axis. For example, in... Figure 2 In this configuration, the gate electrode 13 between the FP insulating film 41 and the FP insulating film 42 extends for at least a predetermined length along a direction orthogonal to the U-axis. In this direction, positions P1 and P2 on the gate electrode 13 are located at different distances from the FP insulating film 41. More specifically, the distance between position P1 of the FP electrode 31 and the gate electrode 13 is smaller than the distance between position P2 of the FP electrode 31 and the gate electrode 13. Furthermore, a first portion 41a of the FP insulating film 41 is located on the line connecting the FP electrode 31 and position P1, and a second portion 41b of the FP insulating film 41 is located on the line connecting the FP electrode 31 and position P2. Figure 2 In the example, position P1 corresponds to the position of the gate electrode 13 between the FP insulating films 41 and 42 that is closest to the center C of the FP electrode 31. Conversely, position P2 corresponds to the position of the gate electrode 13 between the FP insulating films 41 and 42 that is furthest from the center C. In other words, for example, position P2 is located between the FP electrodes 31, 32, and... Figure 2 The geometric centroid of the FP electrode 30 shown below the FP electrode 32. Position P1 is an example of a first position in the claims. Position P2 is an example of a second position in the claims.

[0092] As described above, the semiconductor device 1 of this embodiment includes: an FP insulating film 41, which is columnar in a drift region 21 and has an FP electrode 31 disposed therein; an FP insulating film 42, which is columnar in a drift region 21 and has an FP electrode 32 disposed therein, and is arranged with the FP insulating film 41 along a U-axis direction orthogonal to the Z-axis direction from the lower surface 2a to the upper surface 2b of the semiconductor layer 2; and an FP insulating film 43, which is columnar in a drift region 21 and has an FP electrode 33 disposed therein, and is arranged with the FP insulating film 41 along a V-axis direction orthogonal to the Z-axis direction and different from the U-axis direction. The distance d1 between the FP electrode 31 and the FP electrode 32 is smaller than the distance d2 between the FP electrode 31 and the FP electrode 33. The FP insulating film 41 has a first portion 41a located on the line connecting the FP electrode 31 and the FP electrode 32 and a second portion 42b located on the line connecting the FP electrode 31 and the FP electrode 33. The dielectric constant of the second portion 42b in the FP insulating film 41 is higher than that of the first portion 41a in the FP insulating film 41.

[0093] According to this embodiment, the withstand voltage of the semiconductor device 1 can be improved. The effects of this embodiment will be explained below.

[0094] Generally, in a semiconductor device with a point-type FP electrode, when a reverse bias is applied between the drain electrode 11 and the source electrode 12, the depletion layer extending from the FP insulating film 40 surrounding the FP electrode 30 towards the drift region 21 forms first in the portion near the FP electrode 30, and the depletion layer reaches (depletes) more slowly in the portion farther from the FP electrode 30. For example, at a certain point in time, the depletion layer from the FP electrode 31 (32) reaches... Figure 2 The depletion layer from the FP electrode 31 has not yet reached the area below the Z-axis at position P2. Thus, if the arrival of the depletion layer creates a difference, the electric field concentrates on the undepleted portion, reducing the breakdown voltage of the semiconductor device 1.

[0095] On the other hand, in the semiconductor device 1 according to this embodiment, the dielectric constant of the second portion 40b in the FP insulating film 40 is higher than that of the first portion 40a in the FP insulating film 40. Therefore, in the region of the drift region 21 that is in contact with the second portion 40b, the formation of the depletion layer is promoted compared to the region that is in contact with the first portion 40a. This suppresses the difference in the arrival of the depletion layer depending on its position within the drift region 21. Therefore, the breakdown voltage of the semiconductor device 1 can be improved.

[0096] Furthermore, the above-mentioned effects can be achieved without reducing the impurity concentration in the drift region 21. Therefore, according to this embodiment, the withstand voltage of the semiconductor device 1 can be improved without reducing the impurity concentration in the drift region 21. That is, the trade-off between withstand voltage and on-resistance in the semiconductor device 1 can be improved.

[0097] Furthermore, in this embodiment, by providing a third portion 40c below the second portion 40b, the leakage characteristics of the semiconductor device 1 can be improved.

[0098] Furthermore, in the example described above, second portions 40b are provided at all corners of the FP insulating film 40 in the UV plane. However, this is not a limitation; the second portions 40b may also be provided at at least one corner of the FP insulating film 40. In this case, the corners where the second portions 40b are not provided may be made of, for example, the same material as the first portions 40a.

[0099] <Manufacturing Method of Semiconductor Device 1>

[0100] Next, refer to Figures 5A to 5I An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 5A-5C and Figures 5E to 5I This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment, along... Figure 2 A cross-sectional view along line AA in the diagram. Figure 5D yes Figure 5C A schematic top view of the semiconductor device 1 according to the first embodiment in the manufacturing process shown.

[0101] First, prepare Figure 5A The semiconductor layer shown has a semiconductor region 101 of a first conductivity type and an insulating region 103. The semiconductor region 101 corresponds to the aforementioned drift region 21. The insulating region 103 corresponds to the aforementioned FP insulating film 40. The insulating region 103 is, for example, a silicon oxide film. Furthermore, a plurality of insulating regions 103, each corresponding to the aforementioned FP insulating films 41, 42, and 43, are provided within the semiconductor region 101. The planar shape and positional relationship of the plurality of insulating regions 103 are the same as those of the FP insulating films 41, 42, and 43. In addition, although not shown, the aforementioned FP electrode 30 is disposed inside each insulating region 103.

[0102] Next, as Figure 5B As shown, an insulating material is deposited on the upper surface of the semiconductor layer using chemical vapor deposition (CVD), such as reduced pressure CVD (LPCVD), thereby forming an insulating region 105. The insulating material is, for example, silicon nitride, and the insulating region 105 is a silicon nitride film.

[0103] Next, as Figure 5C As shown, an opening 105a is formed in the insulating region 105 through photolithography and reactive ion etching (RIE). Figure 5D As shown, the opening 105a is formed above the corner of the insulating region 103.

[0104] Next, as Figure 5E As shown, a trench T1 is formed in the insulating region 103 by using a RIE (Rigid Interchange Air) or the like, which serves as a mask (hard mask) for the insulating region 105. In this embodiment, the trench T1 is formed by removing at least halfway from the upper surface of the semiconductor layer to the insulating region 103. As a result, an insulating region 103a, which is part of the insulating region 103, remains at the bottom of the trench T1. The insulating region 103a corresponds to the aforementioned third portion 40c (e.g., the third portion 41c).

[0105] Next, as Figure 5F As shown, the insulating region 105 is removed by wet etching or the like. Furthermore, if the insulating region 105 is made of the same material as the insulating region 107 described later, this step may be omitted.

[0106] Next, as Figure 5GAs shown, an insulating material is deposited on the upper surface of a semiconductor layer using LPCVD or the like. This fills the trench T1, forming an insulating region 107 covering the upper surface of the semiconductor layer. The insulating material is a material with a higher dielectric constant than silicon oxide, such as silicon nitride. Alternatively, the insulating region 107 may be, for example, a silicon nitride film.

[0107] Next, as Figure 5H As shown, the portion of the insulating region 107 above the upper surface of the semiconductor layer is removed by wet etching or the like. More specifically, the portion of the insulating region 107 above the semiconductor region 101, the portion above the insulating region 103, and the portion protruding upward from the trench T1 are removed. Thus, the portion of the insulating region 107 filling the trench T1 remains as the insulating region 109. The insulating region 109 corresponds to the aforementioned second portion 40b (e.g., second portion 41b). Furthermore, the portions of the insulating region 103 located on both sides of the insulating region 109 correspond to the aforementioned first portion 40a (e.g., first portion 41a).

[0108] Next, as Figure 5I As shown, an insulating material is deposited on the upper surface of the semiconductor layer using methods such as CVD, thereby forming an insulating region 111. The insulating material is, for example, silicon oxide, and the insulating region 111 is a silicon oxide film. The insulating region 111 corresponds to the aforementioned interlayer insulating film 60.

[0109] Subsequently, although not shown in the diagram, a gate electrode 13 and a gate insulating film 50 are formed on the upper surface of the semiconductor layer using methods such as RIE and CVD. Additionally, p-type impurities are ion-implanted onto the upper surface of the semiconductor layer to form a substrate region 23. Next, n-type impurities are ion-implanted onto the upper surface of the semiconductor layer to form a source region 24. Then, n-type impurities are ion-implanted onto the lower surface of the semiconductor layer to form a drain region 22. Finally, a drain electrode 11 is formed on the lower surface of the semiconductor layer, and a source electrode 12 is formed on the upper surface of the semiconductor layer.

[0110] Semiconductor device 1 is manufactured through the above processes.

[0111] Furthermore, in the above-described method for manufacturing the semiconductor device 1, after forming the trench T1 and filling the trench T1 with the insulating region 109, the substrate region 23 and the source region 24 are formed. However, it is not limited to this; alternatively, the trench T1 may be formed after forming the substrate region 23 and the source region 24, and the trench T1 may be filled with the insulating region 109.

[0112] (A variation of the first embodiment)

[0113] In the manufacturing method of the first embodiment described above, in Figure 5HIn the process shown, the portion of the insulating region 107 above the upper surface of the semiconductor layer is removed. However, this process may also be omitted. Hereinafter, a variation of the first embodiment obtained by omitting this process in the manufacturing method of the first embodiment will be described, focusing on the differences from the first embodiment.

[0114] Figure 6 Along the semiconductor device 1A of the modified embodiment of the first embodiment Figure 1 A cross-sectional view along the U-axis. For example... Figure 6 As shown, in this modified example, the FP insulating film 40 further includes a fourth portion 40Ad located above the first portion 40a. That is, the fourth portion 40Ad is disposed between the first portion 40a and the interlayer insulating film 60. Figure 6 In the diagram, the fourth portion 40Ad is shown as the fourth portion 41Ad of the FP insulating film 41 and the fourth portion 42Ad of the FP insulating film 42. The fourth portion 40Ad includes a silicon nitride film. Furthermore, although not shown, the fourth portion 40Ad may also be disposed on at least one of the source region 24 and the gate insulating film 50.

[0115] <Manufacturing Method of Semiconductor Device 1A>

[0116] Figure 7 This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1, a variation of the first embodiment, corresponding to a view along... Figure 2 A cross-sectional view along line AA in the diagram.

[0117] like Figure 7 As shown, in this modified example, after forming the insulating region 107, a portion of the insulating region 107 is not removed; instead, an insulating region 111 corresponding to the interlayer insulating film 60 is formed. Furthermore, if the fourth portion 40Ad is not provided above the source region 24 and the gate insulating film 50, the portion of the insulating region 107 located above the semiconductor region 101 is removed before forming the insulating region 111.

[0118] The subsequent procedures are the same as in the first implementation method.

[0119] According to the manufacturing method of the semiconductor device 1A of this modification, it is possible to suppress the infiltration of moisture from the insulating region 111, which serves as an interlayer insulating film, into the semiconductor layer. Therefore, according to this modification, the reliability of the semiconductor device 1A can be improved.

[0120] (Second Implementation)

[0121] In the first embodiment described above, a silicon oxide film is provided in the first portion 40a of the FP insulating film 40, and a material with a higher dielectric constant than the silicon oxide film is provided in the second portion 40b. On the other hand, in the second embodiment described below, a silicon oxide film is provided in the second portion 40b of the FP insulating film 40, and a material with a lower dielectric constant than the silicon oxide film is provided in the first portion 40a. Hereinafter, the second embodiment will be described focusing on the differences from the first embodiment.

[0122] Figure 8 This is a top view of the semiconductor device 1B according to the second embodiment. Figure 9 yes Figure 8 The enlarged view shows the periphery of FP trenches FT1, FT2, and FT3. For example... Figure 8 and Figure 9 As shown, in this embodiment, the second portion 40Bb of the FP insulating film 40 is a silicon oxide film, and the first portion 40Ba of the FP insulating film 40 is made of a material with a lower dielectric constant than the silicon oxide film. The first portion 40Ba may, for example, comprise a spin-coated glass film (SOG film). The SOG film material may be quartz glass, alkylsiloxane polymer, alkylsilylsilsesquioxane polymer, hydrogenated silicon silsesquioxane polymer, hydrogenated alkylsilylsilsesquioxane polymer, etc. In this case, for example, the relative dielectric constant of the first portion 40Bb is approximately 2.9, and the relative dielectric constant of the second portion 40Bb is approximately 3.9.

[0123] Figure 10 Along the semiconductor device 1B of the second embodiment Figure 8 A cross-sectional view along the U-axis. Figure 11 Along the semiconductor device 1B of the second embodiment Figure 8 A cross-sectional view along the V-axis. For example... Figure 10 As shown, in this embodiment, a fifth portion 40Bc is provided, located below the first portion 40Ba and disposed above the drift region 21. Figure 10 In the illustration, the fifth portion 40Bc of FP insulating film 40 is shown as the fifth portion 41Bc of FP insulating film 41 and the fifth portion 42Bc of FP insulating film 42. The fifth portion 40Bc is, for example, made of the same material as the second portion 40Bb. The fifth portion 40Bc is, for example, a silicon oxide film.

[0124] In this embodiment, unlike the first embodiment, the formation of the depletion layer is suppressed in the region of the drift region 21 that is connected to the first portion 40Ba, compared to the region that is connected to the second portion 40Bb. Therefore, similar to the first embodiment, it is possible to suppress the difference in the arrival of the depletion layer depending on its position within the drift region 21. Consequently, the breakdown voltage of the semiconductor device 1B can be improved.

[0125] Furthermore, in this embodiment, by providing a fifth portion 40Bc below the first portion 41Ba, the leakage characteristics of the semiconductor device 1B can be improved.

[0126] Furthermore, in the example described above, the first portion 40Ba is provided at all corners of the FP insulating film 40 in the UV plane. However, it is not limited to this; the first portion 40Ba may also be provided at at least one edge of the FP insulating film 40. In this case, the corners where the first portion 40Ba is not provided may be made of, for example, the same material as the second portion 40Bb.

[0127] Alternatively, this embodiment can also be combined with the first embodiment. For example, it can be that: in the UV plane, a first portion made of a material with a lower dielectric constant than the silicon oxide film is provided at the edge of the FP insulating film 40, a second portion made of a material with a higher dielectric constant than the silicon oxide film is provided at the corner of the FP insulating film 40, and a portion serving as the silicon oxide film is provided between the first portion and the second portion.

[0128] <Manufacturing Method of Semiconductor Device 1B>

[0129] Next, refer to Figures 12A to 12F An example of a method for manufacturing the semiconductor device 1B according to this embodiment will be described. Figure 12A and Figures 12C to 12F This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1B according to the second embodiment, along... Figure 9 A cross-sectional view of the BB line. Figure 12B yes Figure 12A A schematic top view of the semiconductor device 1B according to the second embodiment in the manufacturing process shown.

[0130] First, similar to the manufacturing method of the first embodiment, a semiconductor layer having a semiconductor region 101 of a first conductivity type and an insulating region 103 is prepared. Then, an insulating material is deposited on the upper surface of the semiconductor layer using LPCVD or the like, thereby forming the insulating region 105.

[0131] Next, as Figure 12A As shown, an opening 105b is formed in the insulating region 105 using photolithography and RIE. Figure 12B As shown, the opening 105b is formed above the edge of the insulating region 103.

[0132] Next, as Figure 12CAs shown, a trench T2 is formed in the insulating region 103 by using an RIE (Radio Interchange Equipment) or the like, which serves as a mask for the insulating region 105. In this embodiment, the trench T2 is formed such that an insulating region 103b, which is part of the insulating region 103, remains at the bottom of the trench T2. The insulating region 103b corresponds to the aforementioned fifth portion 40Bc (e.g., fifth portion 41Bc).

[0133] Next, as Figure 12D As shown, the insulating area 105 is removed by wet etching or the like.

[0134] Next, as Figure 12E As shown, trench T2 is filled using a material with a lower dielectric constant than silicon oxide. For example, an insulating region filling trench T2 is formed using a spin-coating glass method. Then, the portion of the insulating region above the upper surface of the semiconductor layer is removed using a wet etching process. This forms an insulating region 113 filling trench T2. Insulating region 113 corresponds to the aforementioned first portion 40Ba (e.g., first portion 41Ba). Furthermore, the portions of insulating region 103 located on either side of insulating region 113 correspond to the aforementioned second portion 40Bb (e.g., second portion 41Bb).

[0135] Next, as Figure 12F As shown, insulating materials are deposited using methods such as CVD, thereby forming the insulating region 111. Subsequent processes are the same as in the first embodiment.

[0136] Semiconductor device 1B is manufactured through the above processes.

[0137] (Third Implementation)

[0138] In the second embodiment described above, a material with a lower dielectric constant than the silicon oxide film is provided in the first portion 40Ba of the FP insulating film 40. However, it is not limited to this; the first portion of the FP insulating film may also be made into a void. The void has a lower dielectric constant compared to the silicon oxide film. Hereinafter, a third embodiment in which the first portion is made into a void will be described, focusing on the differences from the second embodiment.

[0139] Figure 13 Along the semiconductor device 1C of the third embodiment Figure 8 A cross-sectional view along the U-axis. For example... Figure 13 As shown, in this embodiment, the first portion 40Ca of the FP insulating film 40 is a void. Figure 13 In the figure, as the first part 40Ca of FP insulating film 40, the first part 41Ca of FP insulating film 41 and the first part 42Ca of FP insulating film 42 are also shown.

[0140] Furthermore, in this embodiment, the FP insulating film 40 includes a sixth portion 40Cd surrounding the first portion 40Ca. Figure 13 In the illustration, the sixth portion 40Cd of FP insulating film 40 is shown as the sixth portion 41Cd of FP insulating film 41 and the sixth portion 42Cd of FP insulating film 42. The sixth portion 40Cd is, for example, made of the same material as the interlayer insulating film 60. Specifically, the sixth portion 40Cd is, for example, a silicon oxide film. Alternatively, the sixth portion 40Cd may also be made of a material with a lower dielectric constant than silicon oxide film.

[0141] According to this embodiment, similar to the first and second embodiments, the difference in the arrival of the depletion layer depending on its position within the drift region 21 can be suppressed, thereby improving the withstand voltage of the semiconductor device 1C.

[0142] <Method for Manufacturing Semiconductor Device 1C>

[0143] Next, refer to Figure 14 An example of a method for manufacturing the semiconductor device 1C according to this embodiment will be described. Figure 14 This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1C according to the third embodiment, corresponding to a view along... Figure 9 A cross-sectional view of the BB line.

[0144] like Figure 14 As shown, in this embodiment, after forming the trench T2, when depositing an insulating material using CVD or similar methods, an insulating region 111A is formed in such a way that a void 115 is formed within the trench T2. The insulating material is, for example, silicon oxide, and the insulating region 111A is a silicon oxide film. The insulating region 111A corresponds to the aforementioned sixth portion 40Cd (e.g., the sixth portion 41Cd) and the interlayer insulating film 60. More specifically, the portion of the insulating region 111A sandwiched between insulating regions 103 corresponds to the sixth portion 40Cd, and the portion located above the insulating regions 103 corresponds to the interlayer insulating film 60. Furthermore, the void 115 corresponds to the aforementioned first portion 40Ca (e.g., the first portion 41Ca). The subsequent processes are the same as in the second embodiment.

[0145] The above processes are used to manufacture semiconductor device 1C.

[0146] In the first to third embodiments described above, the FP insulating film 40 (e.g., FP insulating film 41) is hexagonal in the UV plane. However, this is not a limitation; any shape that varies in distance between the FP electrode 30 and the gate electrode 13 is acceptable, and the shape of the FP insulating film 40 in the UV plane is not limited to hexagonal. Hereinafter, other variations 1 to 5 of embodiments in which the shape of the FP insulating film 40 in the UV plane is changed will be described. Furthermore, in any of these variations, the difference in the arrival of the depletion layer depending on its position within the drift region 21 can be suppressed, thereby improving the breakdown voltage of the semiconductor device.

[0147] (Other variations of the implementation method 1)

[0148] Figure 15 This is a top view of the semiconductor device 1D of another variation of the embodiment 1. This variation is equivalent to applying the first embodiment described above to a quadrilateral FP insulating film 40D. Hereinafter, this variation will be described focusing on the differences from the first embodiment.

[0149] like Figure 15 As shown, in this modified example, the FP insulating film 40D (e.g., FP insulating film 41D) is quadrilateral in the UV plane. A quadrilateral FP electrode 30D (e.g., FP electrode 31D) is disposed inside each FP insulating film 40D.

[0150] In this modified example, the gate electrode 13D and the gate insulating film 50D have a strip-like shape. That is, the gate electrode 13D and the gate insulating film 50D extend for at least a predetermined length along a direction orthogonal to the Z-axis direction.

[0151] Furthermore, in this modified example, the first portion 40Da (e.g., the first portion 41Da) of the FP insulating film 40D is located at the edge of the FP insulating film 40D in the UV plane. The second portion 40Db (e.g., the second portion 41Db) of the FP insulating film 40D is located at the corner of the FP insulating film 40D in the UV plane.

[0152] Furthermore, in this modified example, the positions of the first portion 41Da and the second portion 41Db of the FP insulating film 41D are also related to the gate electrode 13D as follows. For example, in Figure 15 In this configuration, the gate electrode 13D between the FP insulating films 41D and 42D extends for at least a predetermined length along a direction orthogonal to the U-axis. Furthermore, the distance between the FP electrode 31D and the gate electrode 13D at position P1 is smaller than the distance between the FP electrode 31D and the gate electrode 13D at position P2.

[0153] According to this variation, the structure of the first embodiment can also be applied to the quadrilateral FP insulating film 40D. Furthermore, the portion of the first portion 40Da that sandwiches the FP electrode 30D along the extending direction of the gate electrode 13D (e.g., Figure 15 The first part 41Da located to the left and right of the FP electrode 31D can also be replaced with the second part 40Db.

[0154] (Another variation of the implementation method 2)

[0155] Figure 16 This is a top view of the semiconductor device 1E of another variation 2 of the embodiment. This variation corresponds to the case where the second embodiment is applied to a quadrilateral FP insulating film. That is, this variation corresponds to the case where the structure of the FP insulating film in the second embodiment is applied in another variation 1 of the embodiment. Hereinafter, this variation will be described focusing on the differences from other variation 1 of the embodiment.

[0156] like Figure 16 As shown, in this modified example, the first portion 40Ea (e.g., the first portion 41Ea) of the FP insulating film 40E (e.g., the FP insulating film 41E) is located at the edge of the FP insulating film 40E in the UV plane. The second portion 40Eb (e.g., the second portion 41Eb) of the FP insulating film 40E is located at the corner of the FP insulating film 40E in the same plane.

[0157] According to this modified example, the structure of the second embodiment can also be applied to the quadrilateral FP insulating film 40E.

[0158] (3 other variations of the implementation)

[0159] Figure 17 This is a top view of the semiconductor device 1F of another variation of the embodiment 3. This variation is equivalent to applying another variation of the embodiment 1 to a circular FP insulating film 40F. Hereinafter, this variation will be described focusing on the differences from other variation 1 of the embodiment.

[0160] like Figure 17 As shown, in this modified example, the FP insulating film 40F (e.g., FP insulating film 41F) is circular in the UV plane. A circular FP electrode 30F (e.g., FP electrode 31F) is disposed inside the FP insulating film 40F.

[0161] In this modified example, the first portion 40Fa and the second portion 40Fb of the FP insulating film 40F (e.g., the first portion 41Fa and the second portion 41Fb of the FP insulating film 41F) are alternately arranged in the UV plane along the circumference of the FP insulating film 40F. For example, the first portion 41Fa is located on the line connecting the FP electrode 31F and the FP electrode 32F, and the second portion 41Fb is located on the line connecting the FP electrode 31F and the FP electrode 33F.

[0162] According to this modified example, the structure of the first embodiment can also be applied to the circular FP insulating film 40F. Furthermore, the portion of the first portion 40Fa that sandwiches the FP electrode 30F along the extending direction of the gate electrode 13D (e.g., Figure 17 The first portion 41Fa located to the left and right of the FP electrode 31F can also be replaced by the second portion 40Fb. Alternatively, this modification can also be applied to the structure of the second embodiment.

[0163] (Another variation of the implementation method 4)

[0164] Figure 18 This is a top view of the semiconductor device 1G of another variation of the embodiment 4. This variation corresponds to the case in another variation of the embodiment 1 where the quadrilateral FP insulating film 40D is biasedly disposed along the extending direction of the gate electrode 13D. In this variation, also as in other variation 1 of the embodiment, the FP insulating film 40G (e.g., FP insulating film 41G) has a first portion 40Ga and a second portion 40Gb (e.g., a first portion 41Ga and a second portion 41Gb).

[0165] According to this modification, the structure of the first embodiment can also be applied to the FP insulating film 40G disposed in an offset manner. Furthermore, this modification can be applied to the structure of the second embodiment, and also to a circular FP insulating film.

[0166] (5 other variations of the implementation method)

[0167] Figure 19 This is a top view of the semiconductor device 1H of another variation of the embodiment, 5. This variation corresponds to the case where a mesh gate electrode is provided in another variation of the embodiment, 4. Hereinafter, this variation will be described focusing on the differences from other variation of the embodiment, 4.

[0168] In this modified example, the gate insulating film 50H is configured to surround the FP insulating film 40H (e.g., the FP insulating film 41H). Additionally, a mesh of gate electrodes 13H bonded together is disposed around the gate insulating film 50H.

[0169] According to this modification, the structure of the first embodiment can also be applied to a semiconductor device 1H having a gate electrode 13H configured as a quadrilateral mesh. Furthermore, this modification can also be applied to the structure of the second embodiment. Alternatively, a circular FP insulating film may be provided inside the gate electrode 13H configured as a quadrilateral mesh.

[0170] (Other variations)

[0171] In the above-described embodiments and variations, the FP trenches FT all have the same structure. Furthermore, at least one FP trench FT may have a structure different from the other FP trenches FT. For example, the FP insulating films 41 and 42 within FP trenches FT1 and FT2 may have the same structure as in the first embodiment, while the FP insulating film 43 within FP trench FT3 may have a first portion 43a and a second portion 43b made of the same material.

[0172] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor layer having a first main surface and a second main surface; A first electrode is disposed on the first main surface; The second electrode is disposed on the second main surface; A first semiconductor region of a first conductivity type is disposed within the semiconductor layer and electrically connected to the first electrode; A second semiconductor region of a second conductivity type is disposed within the semiconductor layer and located above the first semiconductor region; A third semiconductor region of a first conductivity type is disposed within the semiconductor layer and located above the second semiconductor region; A gate electrode is disposed within the second semiconductor region via a gate insulating film; The first field plate insulating film is arranged in a columnar shape within the first semiconductor region, and the first field plate electrode is disposed inside it; The second field plate insulating film is arranged in a columnar shape within the first semiconductor region, with a second field plate electrode disposed inside, and is arranged with the first field plate insulating film along a second direction orthogonal to a first direction from the first main surface toward the second main surface; as well as The third field plate insulating film is arranged in a columnar shape within the first semiconductor region, with a third field plate electrode disposed inside, and is arranged with the first field plate insulating film along a third direction orthogonal to the first direction and different from the second direction. The first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode. The first field plate insulating film has a first portion located on the line connecting the first field plate electrode and the second field plate electrode, and a second portion located on the line connecting the first field plate electrode and the third field plate electrode. The dielectric constant of the second portion of the first field plate insulating film is higher than that of the first portion of the first field plate insulating film.

2. The semiconductor device according to claim 1, characterized in that, The first portion of the insulating film of the first field plate is a silicon oxide film. The second portion of the first field plate insulating film is made of a material with a higher dielectric constant than that of the silicon oxide film.

3. The semiconductor device according to claim 2, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

4. The semiconductor device according to claim 2, characterized in that, The second portion of the first field plate insulating film comprises a silicon nitride film.

5. The semiconductor device according to claim 2, characterized in that, The first field plate insulating film further includes a third portion located below the second portion of the first field plate insulating film and disposed above the first semiconductor region, the third portion being a silicon oxide film.

6. The semiconductor device according to claim 5, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

7. The semiconductor device according to claim 2, characterized in that, The first field plate insulating film also has a fourth portion located on the first portion and comprising a silicon nitride film.

8. The semiconductor device according to claim 1, characterized in that, The second portion of the insulating film of the first field plate is a silicon oxide film. The first portion of the first field plate insulating film is made of a material with a lower dielectric constant than that of silicon oxide film.

9. The semiconductor device according to claim 8, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

10. The semiconductor device according to claim 8, characterized in that, The first portion of the first field plate insulating film comprises a spin-coated glass film.

11. The semiconductor device according to claim 8, characterized in that, The first field plate insulating film further includes a fifth portion located below the first portion of the first field plate insulating film and disposed above the first semiconductor region, the fifth portion being a silicon oxide film.

12. The semiconductor device according to claim 11, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

13. The semiconductor device according to claim 1, characterized in that, The second portion of the insulating film of the first field plate is a silicon oxide film. The first portion of the insulating film of the first field plate is a void.

14. The semiconductor device according to claim 13, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

15. The semiconductor device according to claim 1, characterized in that, The insulating film of the first field plate is hexagonal in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

16. The semiconductor device according to claim 1, characterized in that, The insulating film of the first field plate is quadrilateral in a plane orthogonal to the first direction. The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane. The second portion of the first field plate insulating film is located at a corner of the first field plate insulating film in the plane.

17. The semiconductor device according to claim 1, characterized in that, The insulating film of the first field plate is circular in a plane orthogonal to the first direction. The first portion and the second portion of the first field plate insulating film are alternately arranged in the plane along the circumference of the first field plate insulating film.

18. A semiconductor device, characterized in that, have: A semiconductor layer having a first main surface and a second main surface; A first electrode is disposed on the first main surface; The second electrode is disposed on the second main surface; A first semiconductor region of a first conductivity type is disposed within the semiconductor layer and electrically connected to the first electrode; A second semiconductor region of a second conductivity type is disposed within the semiconductor layer and located above the first semiconductor region; A third semiconductor region of a first conductivity type is disposed within the semiconductor layer and located above the second semiconductor region; A gate electrode is disposed within the second semiconductor region via a gate insulating film and extends along a direction orthogonal to a first direction from the first main surface toward the second main surface; as well as The first field plate insulating film is arranged in a columnar shape within the first semiconductor region, and the first field plate electrode is disposed inside it; The distance between the first field plate electrode and the first position of the gate electrode is smaller than the distance between the first field plate electrode and the second position of the gate electrode. The first field plate insulating film has a first portion located on the line connecting the first field plate electrode and the first position, and a second portion located on the line connecting the first field plate electrode and the second position. The dielectric constant of the second portion of the first field plate insulating film is higher than that of the first portion of the first field plate insulating film.

19. A method for manufacturing a semiconductor device, characterized in that, The following procedures will be performed: A semiconductor layer is prepared, the semiconductor layer having a first main surface and a second main surface, and comprising: a first semiconductor region of a first conductivity type; a first field plate insulating film disposed in a columnar shape within the first semiconductor region, and having a first field plate electrode disposed therein; and a second field plate insulating film disposed in a columnar shape within the first semiconductor region, having a second field plate electrode disposed therein, and arranged along a second direction orthogonal to a first direction from the first main surface toward the second main surface and the first field plate insulating film. And a third field plate insulating film, which is columnar in the first semiconductor region, has a third field plate electrode disposed inside, and is arranged with the first field plate insulating film along a third direction orthogonal to the first direction and different from the second direction; the first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode; A trench is formed in the first field plate insulating film by removing at least from the second main surface to the middle of the first field plate insulating film on the line connecting the first field plate electrode and the third field plate electrode. as well as The trenches are filled with a material whose dielectric constant is higher than that of the silicon oxide film.

20. A method for manufacturing a semiconductor device, characterized in that, The following procedures will be performed: A semiconductor layer is prepared, the semiconductor layer having a first main surface and a second main surface, and comprising: a first semiconductor region of a first conductivity type; a first field plate insulating film disposed in a columnar shape within the first semiconductor region, and having a first field plate electrode disposed therein; and a second field plate insulating film disposed in a columnar shape within the first semiconductor region, having a second field plate electrode disposed therein, and arranged along a second direction orthogonal to a first direction from the first main surface toward the second main surface and the first field plate insulating film. And a third field plate insulating film, which is columnar in the first semiconductor region, has a third field plate electrode disposed inside, and is arranged with the first field plate insulating film along a third direction orthogonal to the first direction and different from the second direction; the first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode; A trench is formed in the first field plate insulating film by removing at least from the second main surface to the middle of the first field plate insulating film along the line connecting the first field plate electrode and the second field plate electrode. as well as The trenches are filled with a material having a lower dielectric constant than the silicon oxide film, or an insulating material is deposited in the trenches in a manner that forms voids.

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