Dual gate trench lateral mosfet and method of manufacturing the same
By designing a dual-gate trench lateral MOSFET, the source and drain are integrated on the same surface, solving the integration difficulties of existing trench MOSFETs on lithium battery protection boards, expanding the scope of application and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES HUAJING MICROELECTRONICS
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Existing trench MOSFETs are difficult to integrate on lithium battery protection boards. The source and drain are not on the same surface, making it impossible to connect them in series. Furthermore, parasitic NPN transistors are prone to conduction, making it difficult to meet the application requirements of battery management systems.
Design a dual-gate trench lateral MOSFET, including a first gate and a second gate spaced apart, and a first source electrode and a second source electrode, all of which are located on the same surface. The current is turned on on one side by independently controlling the gate, thus avoiding current flow on the back of the chip.
This technology enables the integration of trench MOSFETs onto battery protection boards, expanding the applicability, meeting the needs of battery management systems, and reducing manufacturing costs and dynamic losses.
Smart Images
Figure CN122248769A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a dual-gate trench lateral MOSFET and its manufacturing method. Background Technology
[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in low-to-medium power electronic products, such as power supplies and drives, due to their characteristics of fast switching speed, low dynamic loss, and good high-frequency characteristics. In recent years, with the increasing demand for lithium battery protection applications, it is necessary to integrate ICs, MOSFETs, resistors, and capacitors on lithium battery protection boards. Among these, the MOSFETs need to be connected in series in the circuit, and their electrodes need to be located on the same surface. Such applications place higher demands on the integration and interconnection capabilities of power MOSFETs. In the field of low-to-medium voltage MOSFETs, trench MOSFETs, compared to planar MOSFETs, have a vertical channel, allowing for smaller cell sizes and improved current density and chip area utilization, making them the mainstream structure for power MOSFETs.
[0003] Figure 1 This is a schematic diagram of a traditional trench-type VDMOS device. Figure 1 As shown, the traditional trench-type VDMOS device has a drain 21 on the back and a source 22 on the front. When turned on, the channel turn-on current flows vertically from the source 22 to the drain 21. Since the source 22 and drain 21 are not on the same surface, it is limited in applications such as lithium battery protection with high power integration requirements.
[0004] Patent publication number CN114388613A discloses a power MOS device. Figure 2 The structure of this power MOS device is shown, as follows: Figure 2 As shown, in this power MOS device, the second conductivity type lightly doped region 12, the first conductivity type lightly doped region 13, and the first conductivity type heavily doped region 14 are stacked sequentially from bottom to top on the first conductivity type lightly doped epitaxial layer 11. The second conductivity type lightly doped region 12 and the first conductivity type heavily doped region 14 are not short-circuited. When the device is working, the parasitic NPN transistor is prone to conduction, leading to device failure. The control gate polysilicon 31 is a left-right separated gate, and there is also a polysilicon 32 above the control gate polysilicon 31. The fabrication process of the control gate polysilicon 31 and polysilicon 32 is complex and difficult to achieve. In addition, compared with... Figure 1 The device shown is the same, but the source 22 and drain 21 of this power MOS device are located on the front and back sides respectively and are not on the same surface. They cannot be connected in series in the circuit. Moreover, this power MOS device has only one source 22, and its discrete polysilicon gate can only be turned on and off at the same time. This does not meet the requirement of single-on and single-off gate electrodes in the application circuit, and is not suitable for battery management system applications.
[0005] Therefore, it is urgent to solve the problem of how to expand the application range of trench MOSFETs. Summary of the Invention
[0006] One of the objectives of this invention is to enable the integration of trench MOSFETs onto battery protection boards, thereby expanding the applicability of trench MOSFETs.
[0007] To achieve the above objectives, the present invention provides a dual-gate trench lateral MOSFET. The dual-gate trench lateral MOSFET includes: a substrate in which a trench is formed; a first gate and a second gate, the first gate and the second gate being disposed at a distance from each other within the trench and arranged side-by-side in the width direction of the trench; and a discrete first source electrode and a second source electrode, each having one end embedded in the substrate and the other end located above the substrate. The first source electrode and the second source electrode are disposed on opposite sides of the trench, with the first source electrode located on the side of the first gate away from the second gate, and the second source electrode located on the side of the second gate away from the first gate.
[0008] Optionally, the dual-gate trench lateral MOSFET further includes: a first gate oxide layer, which fills the bottom of the trench, and the first gate and the second gate are located above the first gate oxide layer; and a second gate oxide layer, which covers the trench sidewall located above the first gate oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
[0009] Optionally, the dual-gate trench lateral MOSFET further includes a gate oxide layer of uniform thickness, the gate oxide layer covering the sidewalls and bottom surface of the trench, and the first gate and the second gate are located above the gate oxide layer.
[0010] Optionally, a first body region and a second body region, both of which are of a first conductivity type, are formed in the substrate, and a first source region and a second source region, both of which are of a second conductivity type, are formed on the top of the substrate, wherein the first conductivity type and the second conductivity type are opposite; the first body region and the second body region are located on both sides of the trench, the first source region is located above the first body region and is connected to the first body region, the first source electrode penetrates the first source region and extends into the first body region, the second source region is located above the second body region and is connected to the second body region, and the second source electrode penetrates the second source region and extends into the second body region.
[0011] Optionally, the dual-gate trench lateral MOSFET further includes a dielectric layer that fills the trench and covers at least a portion of the top surface of the first gate, the second gate, and the substrate, wherein the first source electrode and the second source electrode penetrate the dielectric layer.
[0012] Optionally, when an enable voltage is applied to the first gate, a positive voltage is applied to the first source electrode, and a zero-volt voltage is applied to the second source electrode, the dual-gate trench lateral MOSFET is turned on, and current flows from the first source electrode along the side and bottom of the trench to the second source electrode.
[0013] The present invention also provides a method for manufacturing a dual-gate trench lateral MOSFET. The method includes: providing a substrate; forming a trench in the substrate; forming a first gate and a second gate within the trench, the first gate and the second gate being spaced apart within the trench and arranged side-by-side in the width direction of the trench; and forming a discrete first source electrode and a second source electrode on the substrate, each source electrode having one end embedded in the substrate and the other end located above the substrate, the first source electrode and the second source electrode being disposed on opposite sides of the trench, the first source electrode being located on the side of the first gate away from the second gate, and the second source electrode being located on the side of the second gate away from the first gate.
[0014] Optionally, the method for manufacturing the dual-gate trench lateral MOSFET further includes: after forming a trench in the substrate and before forming a first gate and a second gate in the trench, forming a first gate oxide layer at the bottom of the trench, the first gate oxide layer filling the bottom of the trench; and forming a second gate oxide layer on the substrate, the second gate oxide layer covering the trench sidewall above the first gate oxide layer, the thickness of the first gate oxide layer being greater than the thickness of the second gate oxide layer.
[0015] Optionally, the method for forming the first gate and the second gate in the trench includes: forming a gate material layer on the substrate, the gate material layer covering the top surface of the substrate and the inner surface of the trench; and etching away the gate material layer on the top surface of the substrate and a portion of the gate material layer on the bottom surface of the trench using an anisotropic etching process, retaining the gate material layers on the two opposite sidewalls of the trench as the first gate and the second gate.
[0016] Optionally, the manufacturing method of the dual-gate trench lateral MOSFET further includes: after forming a first gate and a second gate in the trench, forming a first body region and a second body region in the substrate by ion implantation, wherein the first body region and the second body region are both of a first conductivity type and are located on both sides of the trench; forming a first source region and a second source region on the top of the substrate by ion implantation, wherein the first source region and the second source region are both of a second conductivity type, the first conductivity type and the second conductivity type are opposite, the first source region and the second source region are located on both sides of the trench, the first source region is located above the first body region and is connected to the first body region, and the second source region is located above the second body region and is connected to the second body region; forming a dielectric layer on the substrate, wherein the dielectric layer fills the trench and covers the first gate, the second gate and the top surface of the substrate.
[0017] Optionally, the method for forming discrete first and second source electrodes on the substrate includes: etching away a portion of the dielectric layer and a portion of the substrate to form a first via and a second via, both of which penetrate the dielectric layer and have their bottoms located in the substrate; forming a metal material layer on the dielectric layer, the metal material layer covering the dielectric layer and the inner surfaces of the first and second vias; and etching away a portion of the metal material layer on the top surface of the dielectric layer to form the first and second source electrodes.
[0018] In the dual-gate trench lateral MOSFET provided by this invention, a first gate and a second gate are spaced apart within a trench and arranged side-by-side along the width of the trench. Two discrete source electrodes, a first source electrode and a second source electrode, are disposed on a substrate. Each source electrode has one end embedded in the substrate and the other end located above the substrate. The first and second source electrodes are respectively disposed on opposite sides of the trench. The first source electrode is located on the side of the first gate away from the second gate, and the second source electrode is located on the side of the second gate away from the first gate. The fabrication process of this dual-gate trench lateral MOSFET is fully compatible with that of a traditional trench VDMOS. The two source electrodes of this dual-gate trench lateral MOSFET are located on the same surface. The dual-gate trench lateral MOSFET can be connected in series as a power MOSFET in the control circuit, achieving integration between the dual-gate trench lateral MOSFET and the control circuit. Furthermore, the first and second gates of the dual-gate trench lateral MOSFET can be controlled separately. When the device is working, only one gate can be turned on, and the conduction current flows from one source electrode through the bottom of the trench to the other source electrode, meeting the requirements of battery management application circuits. That is, the dual-gate trench lateral MOSFET is suitable for battery management systems, expanding the application range of trench MOSFETs. Since the current of the dual-gate trench lateral MOSFET does not pass through the back of the chip when it is working, the impact of chip thinning can be ignored in actual processes, and the back metallization process can be reduced, saving manufacturing costs to a certain extent.
[0019] Furthermore, the dual-gate trench lateral MOSFET also includes a first gate oxide layer with a thickness greater than that of the second gate oxide layer. The first gate oxide layer fills the bottom of the trench, and the first gate and the second gate are located above the first gate oxide layer. This improves the voltage withstand capability of the device, reduces the gate leakage charge (Qgd) of the device, and reduces the dynamic loss of the device. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a traditional trench-type VDMOS device.
[0021] Figure 2 This is a schematic diagram of the structure of a power MOS device.
[0022] Figure 3 A flowchart illustrating a method for manufacturing a dual-gate trench lateral MOSFET according to an embodiment of the present invention.
[0023] Figures 4 to 8 This is a step-by-step schematic diagram of a method for manufacturing a dual-gate trench lateral MOSFET according to an embodiment of the present invention.
[0024] Figure 9 This is a schematic diagram of the structure of a dual-gate trench lateral MOSFET provided in an embodiment of the present invention.
[0025] Figure 10 This is a schematic diagram of the structure of a dual-gate trench lateral MOSFET provided in another embodiment of the present invention.
[0026] Figure 11 This is a schematic diagram of a dual-gate trench lateral MOSFET with no thick gate oxide layer at the bottom of the trench, provided in an embodiment of the present invention.
[0027] Figure 12 The equivalent circuit diagram of a dual-gate trench lateral MOSFET provided in an embodiment of the present invention is shown.
[0028] Figure 13 This is a current flow path distribution diagram of a dual-gate trench lateral MOSFET during forward conduction, provided in an embodiment of the present invention.
[0029] Figure 14 This is a potential distribution diagram of a traditional trench DMOS structure under the blocking state.
[0030] Figure 15 This is a potential distribution diagram of a dual-gate trench lateral MOSFET in the blocking state with no thick gate oxide layer at the bottom of the trench, provided in an embodiment of the present invention.
[0031] Figure 16 This is a potential distribution diagram of a dual-gate trench lateral MOSFET with a thick gate oxide layer at the bottom of the trench in a blocking state, provided as an embodiment of the present invention. Figure 17 The voltage withstand curves are shown for a traditional trench DMOS structure, a dual-gate trench lateral MOSFET with no thick gate oxide layer at the bottom of the trench provided by the present invention, and a dual-gate trench lateral MOSFET with a thick gate oxide layer at the bottom of the trench provided by the present invention.
[0032] Explanation of reference numerals in the attached figures: 11-Lightly doped epitaxial layer of the first conductivity type; 12-Lightly doped region of the second conductivity type; 13-Lightly doped region of the first conductivity type; 14-Heavily doped region of the first conductivity type; 21-Drain; 22-Source; 31-Control gate polysilicon; 32-Polysilicon; 101-Substrate; 102-Trench; 103-First gate oxide layer; 104-Second gate oxide layer; 105-Gate material layer; 106-First gate; 107-Second gate; 108-First body region; 109-Second body region; 110-First source region; 111-Second source region; 113-First via; 114-Second via; 115-First source electrode; 116-Second source electrode; 117-Gate oxide layer. Detailed Implementation
[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the dual-gate trench lateral MOSFET and its manufacturing method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0034] It should be noted that the terminology used in this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar words used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "comprising" or "including," and similar words, indicate that the elements or structures preceding "comprising" or "including" encompass the elements or structures listed following "comprising" or "including" and their equivalents, and do not exclude other elements or structures.
[0035] It should be recognized that relative terms such as “above,” “below,” “top,” “bottom,” “upper,” and “lower” shown in the accompanying drawings are used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being “above” another element would now be below that element.
[0036] To expand the application range of trench MOSFETs, this invention provides a dual-gate trench lateral MOSFET and its manufacturing method.
[0037] Figure 3 This is a flowchart illustrating a method for manufacturing a dual-gate trench lateral MOSFET according to an embodiment of the present invention. Figure 3 As shown, the manufacturing method of the dual-gate trench lateral MOSFET provided in this embodiment includes:
[0038] Step S1: Provide a substrate and form trenches in the substrate;
[0039] Step S2: A first gate and a second gate are formed in the trench, the first gate and the second gate being disposed at a distance from each other in the trench and arranged side by side in the width direction of the trench;
[0040] Step S3: A discrete first source electrode and a second source electrode are formed on the substrate. One end of the first source electrode and the second source electrode are embedded in the substrate and the other end is located above the substrate. The first source electrode and the second source electrode are disposed on both sides of the trench. The first source electrode is located on the side of the first gate away from the second gate, and the second source electrode is located on the side of the second gate away from the first gate.
[0041] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0042] Figures 4 to 8 This is a step-by-step schematic diagram of a method for manufacturing a dual-gate trench lateral MOSFET according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of a dual-gate trench lateral MOSFET provided in an embodiment of the present invention.
[0043] The following combination Figure 3 , Figures 4 to 9 The fabrication method of the dual-gate trench lateral MOSFET provided in this embodiment will be described.
[0044] like Figure 4 As shown, step S1 is performed by providing a substrate 101 and forming a trench 102 in the substrate 101. Exemplarily, the method for forming the trench 102 in the substrate 101 may include: forming a patterned mask layer on the substrate 101, the patterned mask layer defining the formation location of the trench 102; and etching the substrate 101 using the patterned mask layer as a mask to form the trench 102. The patterned mask layer may be a photoresist layer or a hard mask layer.
[0045] In this embodiment, the material of the substrate 101 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon on insulator, germanium on insulator; or it can be other materials, such as gallium arsenide or other III-V compounds.
[0046] Figure 10This is a schematic diagram of a dual-gate trench lateral MOSFET provided in another embodiment of the present invention. In another embodiment of the present invention, the substrate may include a substrate and an epitaxial layer, specifically, see [reference]. Figure 10 As shown, the substrate 101 includes a substrate 101a and an epitaxial layer 101b located on the substrate 101a. A trench 102 can be fabricated in the epitaxial layer 101b to form a dual-gate trench lateral MOSFET. Since there are fewer lattice defects in the epitaxial layer 101b, fabricating a dual-gate trench lateral MOSFET on the epitaxial layer 101b helps to improve device performance.
[0047] In this embodiment, after forming the trench 102 in the etched substrate 101, a sacrificial oxide layer can be formed on the substrate 101 and then removed. This helps to eliminate the defects generated when forming the trench 102 in the etched substrate 101.
[0048] Continue to refer to Figure 4 As shown, in this embodiment, after forming a trench 102 in the substrate 101, a first gate oxide layer 103 is formed at the bottom of the trench 102, and the first gate oxide layer 103 fills the bottom of the trench 102. Specifically, the first gate oxide layer 103 is a thick gate oxide layer, and the first gate oxide layer 103 covers the bottom surface of the trench 102 and the sidewalls of the bottom of the trench 102.
[0049] For example, a method for forming a first gate oxide layer 103 at the bottom of the trench 102 may include: depositing an oxide material layer on a substrate 101, the oxide material layer covering both the top surface of the substrate 102 and the bottom surface of the trench 102; removing the oxide material layer on the top surface of the substrate 101, retaining the oxide material layer on the bottom surface of the trench 102 as the first gate oxide layer 103. For example, the oxide material layer may be formed using a chemical vapor deposition process, but is not limited thereto. Those skilled in the art may also form the first gate oxide layer 103 using other methods known in the art.
[0050] refer to Figure 5 As shown, after forming a first gate oxide layer 103 at the bottom of trench 102, a second gate oxide layer 104 is formed on the substrate 101. The second gate oxide layer 104 covers the trench sidewalls above the first gate oxide layer 103, and the thickness of the first gate oxide layer 103 is greater than the thickness of the second gate oxide layer 104. The first gate oxide layer 103 and the second gate oxide layer 104 together cover the inner surface of trench 102 to isolate the substrate 101 from the subsequently formed gate.
[0051] It should be noted that in this embodiment, the first gate oxide layer 103 and the second gate oxide layer 104 are made of the same material; therefore, no boundary line is shown between the first gate oxide layer 103 and the second gate oxide layer 104 in the accompanying drawings. The materials of the first gate oxide layer 103 and the second gate oxide layer 104 include, but are not limited to, silicon oxide.
[0052] For example, the second gate oxide layer 104 can be formed by a thermal oxidation process, but is not limited thereto. The second gate oxide layer 104 can also cover the top surface of the substrate 101.
[0053] Figure 11 This is a schematic diagram of a dual-gate trench lateral MOSFET with no thick gate oxide layer at the bottom of the trench, according to one embodiment of the present invention. In another embodiment of this application, refer to... Figure 11 As shown, after forming a trench 102 in the substrate 101, a gate oxide layer 117 can be formed directly by a thermal oxidation process. The gate oxide layer 117 covers the bottom surface and sidewalls of the trench. At this time, the thickness of the gate oxide layer on the bottom surface of the trench and the gate oxide layer on the sidewalls of the trench are the same or have no significant difference. That is, the thickness of the gate oxide layer 117 is uniform. Thus, the bottom of the trench of the dual-gate trench lateral MOSFET formed in this way does not have a thick gate oxide layer.
[0054] like Figure 7 As shown, in step S2, a first gate 106 and a second gate 107 are formed within the trench 102. The first gate 106 and the second gate 107 are spaced apart within the trench 102 and arranged side-by-side in the width direction of the trench 102. The width direction of the trench 102 is perpendicular to the depth direction of the trench 102, and the depth direction of the trench is... Figure 7 The vertical direction, the width direction of the trench is Figure 7 The horizontal direction.
[0055] like Figure 7 As shown, the first gate 106 and the second gate 107 are gates symmetrically arranged from left to right. The trench 102 has opposing left and right side walls. The first gate 106 can be disposed near the left side wall of the trench 102, and the second gate 107 can be disposed near the right side wall of the trench 102. For example, the width of the first gate 106 and the width of the second gate 107 can be the same, and the height of the first gate 106 (i.e.,...) can be... Figure 7 The vertical dimension) and the height of the second gate 107 can be the same, but are not limited to this.
[0056] In this embodiment, the top ends of the first gate 106 and the second gate 107 are located below the top surface of the substrate 101, that is, the first gate 106 and the second gate 107 do not protrude outside the trench 102.
[0057] Exemplary, a method for forming a first gate 106 and a second gate 107 within the trench 102 may include: as follows Figure 6 As shown, a gate material layer 105 is formed on the substrate 101, the gate material layer 105 covering the top surface of the substrate 101 and the inner surface of the trench 102; as Figure 7 As shown, an anisotropic etching process is used to etch away the gate material layer 105 on the top surface of the substrate 101 and a portion of the gate material layer 105 on the bottom surface of the trench 102, leaving the gate material layers 105 on the two opposite sidewalls of the trench 102 as the first gate 106 and the second gate 107. Specifically, when etching the gate material layers using the anisotropic etching process, etching stops when the second gate oxide layer 104 on the top surface of the substrate 101 is exposed and the first gate oxide layer 103 on the bottom surface of the trench is exposed.
[0058] The materials for the first gate 106 and the second gate 107 include, but are not limited to, polysilicon. The gate material layer 105 can be formed using methods known to those skilled in the art, such as pyrolysis, chemical vapor deposition, and silicon decomposition compound methods. Anisotropic etching processes include, but are not limited to, dry etching processes.
[0059] refer to Figure 8 As shown, after forming the first gate 106 and the second gate 107 within the trench 102, a first body region 108 and a second body region 109 can be formed in the substrate 101 via ion implantation. Both the first body region 108 and the second body region 109 are of the first conductivity type and are located on opposite sides of the trench 102. In this embodiment, the first body region 108 and the second body region 109 can be contacted with two opposite sidewalls of the trench 102, for example, the first body region 108 contacts the left sidewall of the trench 102, and the second body region 109 contacts the right sidewall of the trench 102.
[0060] refer to Figure 8 As shown, a first source region 110 and a second source region 111 can be formed on the top of the substrate 101 using an ion implantation process. Both the first source region 110 and the second source region 111 are of the second conductivity type. The first source region 110 and the second source region 111 are located on both sides of the trench 102. The first source region 110 is located above and connected to the first body region 108, and the second source region 111 is located above and connected to the second body region 109. The first source region 110 and the second source region 111 can also be connected to two opposite sidewalls of the trench 102, for example, the first source region 110 is in contact with the left sidewall of the trench 102, and the second source region 111 is in contact with the right sidewall of the trench 102.
[0061] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, the first conductivity type is P-type and the second conductivity type is N-type, but it is not limited to this.
[0062] Continue to refer to Figure 8 As shown, after forming the body region and the source region, a dielectric layer 112 is formed on the substrate 101. The dielectric layer 112 fills the trench 102 and covers the first gate 106, the second gate 107 and the top surface of the substrate 101.
[0063] Next, proceed to step S3, as follows: Figure 9 As shown, a discrete first source electrode 115 and a second source electrode 116 are formed on a substrate 101. One end of each source electrode 115 and the other end are embedded in the substrate 101, and the first source electrode 115 and the second source electrode 116 are located on opposite sides of a trench 102. The first source electrode 115 is located on the side of the first gate 106 away from the second gate 107, and the second source electrode 116 is located on the side of the second gate 107 away from the first gate 106. Alternatively, the first source electrode 115 is located near the left side wall of the trench 102, and the second source electrode 116 is located near the right side wall of the trench 102.
[0064] For example, a method for forming discrete first source electrode 115 and second source electrode 116 on substrate 102 may include: as Figure 8 As shown, etching removes a portion of the dielectric layer 112 and a portion of the substrate 101 to form a first via 113 and a second via 114. Both the first via 113 and the second via 114 penetrate the dielectric layer 112 and their bottoms are located within the substrate 101. Specifically, the first via 113 penetrates the dielectric layer 112 and the first source region 110 and its bottom is located within the first body region 108, while the second via 114 penetrates the dielectric layer 112 and the second source region 111 and its bottom is located within the second body region 109. A metal material layer is formed on the dielectric layer 112, covering the dielectric layer 112 and the inner surfaces of the first via 113 and the second via 114. Etching removes a portion of the metal material layer on the top surface of the dielectric layer 112 to form the first source electrode 115 and the second source electrode 116.
[0065] This embodiment also provides a dual-gate trench lateral MOSFET. The dual-gate trench lateral MOSFET can be manufactured using the above-described manufacturing method for dual-gate trench lateral MOSFETs, but is not limited thereto.
[0066] refer to Figure 9As shown, the dual-gate trench lateral MOSFET includes a substrate 101, a first gate 106, a second gate 107, a first source electrode 115, and a second source electrode 116. A trench 102 is formed in the substrate 101. The first gate 106 and the second gate 107 are spaced apart within the trench 102 and arranged side-by-side in the width direction of the trench 102. The first source electrode 115 and the second source electrode 116 are two separate (i.e., non-contacting) source electrodes. One end of each source electrode is embedded in the substrate 101, and the other end is located above the substrate 101. The first source electrode 115 and the second source electrode 116 are located on opposite sides of the trench 102. The first source electrode 115 is located on the side of the first gate 106 away from the second gate 107, and the second source electrode 116 is located on the side of the second gate 107 away from the first gate 106.
[0067] In one embodiment of this application, reference is made to... Figure 9 As shown, substrate 101 may consist only of a substrate. In another embodiment of the invention, reference is made to... Figure 10 As shown, the substrate 101 may include a substrate 101a and an epitaxial layer 101b located on the substrate 101a. A trench 102 can be formed in the epitaxial layer 101b to form a dual-gate trench lateral MOSFET. Since there are fewer lattice defects in the epitaxial layer 101b, fabricating a dual-gate trench lateral MOSFET on the epitaxial layer 101b helps improve device performance. It should be noted that... Figure 9 and Figure 10 The dual-gate trench lateral MOSFET shown is identical in all aspects except for its substrate structure.
[0068] like Figure 9 As shown, the first gate 106 and the second gate 107 are gates symmetrically arranged from left to right. The trench 102 has opposing left and right side walls. The first gate 106 can be disposed near the left side wall of the trench 102, and the second gate 107 can be disposed near the right side wall of the trench 102. For example, the width of the first gate 106 and the width of the second gate 107 can be the same, and the height of the first gate 106 (i.e.,...) can be... Figure 9 The vertical dimension) and the height of the second gate 107 can be the same, but are not limited to this.
[0069] In this embodiment, both the first gate 106 and the second gate 107 can be polysilicon gates. The first gate 106 and the second gate 107 can be controlled separately by different controllers to achieve independent control of the first gate 106 and the second gate 107.
[0070] In this embodiment, the first source electrode 115 and the second source electrode 116 can be made of the same material. The materials of the first source electrode 115 and the second source electrode 116 include, but are not limited to, Cu.
[0071] Continue to refer to Figure 9 As shown, in this embodiment, the dual-gate trench lateral MOSFET further includes a first gate oxide layer 103 and a second gate oxide layer 104. The first gate oxide layer 103 fills the bottom of the trench 102, covering the bottom surface and bottom sidewalls of the trench 102; the first gate 106 and the second gate 107 are located above the first gate oxide layer 103. The second gate oxide layer 104 covers the trench sidewalls located above the first gate oxide layer 103. The thickness of the first gate oxide layer 103 is greater than the thickness of the second gate oxide layer 104, that is, the first gate oxide layer 103 is a thick gate oxide layer.
[0072] In this embodiment, the materials of the first gate oxide layer 103 and the second gate oxide layer 104 can be the same, but are not limited to this. The materials of the first gate oxide layer 103 and the second gate oxide layer 104 include, but are not limited to, silicon oxide.
[0073] In another embodiment of this application, such as Figure 11 As shown, the dual-gate trench lateral MOSFET has a gate oxide layer 117 with uniform thickness, that is, the gate oxide layer on the bottom surface of the trench 102 and the gate oxide layer on the sidewall of the trench have the same thickness or a small difference. At this time, the first gate 106 and the second gate 107 are located above the gate oxide layer 117. The dual-gate trench lateral MOSFET is a dual-gate trench lateral MOSFET without a thick gate oxide layer at the bottom of the trench.
[0074] refer to Figure 9 As shown, a first body region 108 and a second body region 109, both of which are of a first conductivity type, are formed in the substrate 101, and a first source region 110 and a second source region 111, both of which are of a second conductivity type, are formed on the top of the substrate 101. The first conductivity type and the second conductivity type are opposite. For example, the first conductivity type is P-type and the second conductivity type is N-type, but it is not limited to this.
[0075] The first body region 108 and the second body region 109 are located on opposite sides of the trench 102. The first source region 110 is located above and connected to the first body region 108, and the first source electrode 115 penetrates the first source region 110 and extends into the first body region 108. The second source region 111 is located above and connected to the second body region 109, and the second source electrode 116 penetrates the second source region 111 and extends into the second body region 109.
[0076] It should be noted that in this embodiment, the first body region 108 and the first source region 110 are in contact (i.e. short-circuited), and the second body region 109 and the second source region 111 are short-circuited, which helps to improve the reliability of the device.
[0077] Continue to refer to Figure 9 As shown, the dual-gate trench lateral MOSFET may further include a dielectric layer 112, which is located on the substrate 101, fills the trench 102 and covers at least a portion of the top surface of the first gate 106, the second gate 107 and the substrate 101, and the first source electrode 115 and the second source electrode 116 penetrate the dielectric layer 112.
[0078] For example, the material of the dielectric layer 112 includes, but is not limited to, silicon oxide.
[0079] It should be noted that when an enable voltage is applied to one of the two gates (i.e., the first gate 106 and the second gate 107), and a positive voltage is applied to one of the two source electrodes (i.e., the first source electrode 115 and the second source electrode 116) while the other is applied with a zero-volt voltage, the dual-gate trench lateral MOSFET can be turned on. Current can flow from one source electrode along the side and bottom of the trench 102 to the other source electrode, so that the current flows from the chip surface rather than vertically from the top to the bottom of the chip.
[0080] Figure 12 The equivalent circuit diagram of a dual-gate trench lateral MOSFET provided in an embodiment of the present invention is shown. Figure 13 This is a current flow path distribution diagram of a dual-gate trench lateral MOSFET during forward conduction according to an embodiment of the present invention. Figure 12 and Figure 13 In the diagram, G1 represents the first gate, G2 represents the second gate, S1 represents the first source electrode, and S2 represents the second source electrode.
[0081] refer to Figure 12 and Figure 13 As shown, exemplarily, when an enable voltage is applied to the first gate G1, a positive voltage is applied to the first source electrode S1, and a zero-volt voltage is applied to the second source electrode S2, the dual-gate trench lateral MOSFET is turned on, and current flows from the first source electrode S1 along the side and bottom of the trench to the second source electrode S2.
[0082] Figure 14 This is a potential distribution diagram of a traditional trench DMOS structure under the blocking state. Figure 14 In this diagram, G represents the gate electrode, S represents the source electrode, and the source electrodes on both sides of the gate electrode are connected. Figure 15 This is a potential distribution diagram of a dual-gate trench lateral MOSFET in the blocking state with no thick gate oxide layer at the bottom of the trench, provided in an embodiment of the present invention. Figure 16 This is a potential distribution diagram of a dual-gate trench lateral MOSFET with a thick gate oxide layer at the bottom of the trench in a blocking state, provided as an embodiment of the present invention. Figure 15 and Figure 16 In the diagram, G1 represents the first gate, G2 represents the second gate, S1 represents the first source electrode, and S2 represents the second source electrode.
[0083] refer to Figure 14 As shown, in a traditional trench DMOS structure, the potential lines are concentrated near the bottom of the trench. (Reference) Figure 15 As shown, the dual-gate trench lateral MOSFET with no thick gate oxide layer at the bottom of the trench provided by this invention has its second source electrode S2 connected to zero potential, and the right gate oxide layer and the bottom of the trench bear the withstand voltage. The potential line is concentrated in the right gate oxide layer and at the bottom of the trench. (Reference) Figure 16 As shown, the dual-gate trench lateral MOSFET with a thick gate oxide layer at the bottom provided by the present invention has a thick gate oxide layer at the bottom of the trench, which can withstand the voltage, and the potential lines are concentrated in the right gate oxide layer and the bottom thick gate oxide layer.
[0084] Figure 17 The figures show the breakdown voltage curves for a traditional trench DMOS structure, a dual-gate trench lateral MOSFET with no thick gate oxide layer at the bottom of the trench, and a dual-gate trench lateral MOSFET with a thick gate oxide layer at the bottom of the trench. (Reference) Figure 17 As shown, the conventional trench-type DMOS structure has a breakdown voltage of 14.5V. The dual-gate trench-type lateral MOSFET with no thick gate oxide layer at the bottom of the trench provided by this invention has a breakdown voltage of 12V. The dual-gate trench-type lateral MOSFET with a thick gate oxide layer at the bottom of the trench provided by this invention has a breakdown voltage increased to 17V. Therefore, forming a thick gate oxide layer at the bottom of the trench, that is, forming a first gate oxide layer with a thickness greater than that of the second gate oxide layer at the bottom of the trench, helps to improve the breakdown voltage capability of the dual-gate trench-type lateral MOSFET.
[0085] In the dual-gate trench lateral MOSFET provided by this invention, a first gate 106 and a second gate 107 are spaced apart within a trench 102 and arranged side-by-side along the width of the trench 102. Two discrete source electrodes, a first source electrode 115 and a second source electrode 116, are disposed on a substrate 101. One end of each source electrode 115 and source electrode 116 is embedded in the substrate 101, and the other end is located above the substrate 101. The first source electrode 115 and the second source electrode 116 are respectively disposed on opposite sides of the trench 102. The first source electrode 115 is located on the side of the first gate 106 away from the second gate 107, and the second source electrode 116 is located on the side of the second gate 107 away from the first gate 106. The fabrication process of this dual-gate trench lateral MOSFET is completely different from that of a traditional trench VDMOS. Fully compatible, this dual-gate trench lateral MOSFET has its two source electrodes located on the same surface, allowing it to be connected in series as a power MOSFET in the control circuit. This enables the integration of the dual-gate trench lateral MOSFET with the control circuit. Furthermore, the first gate 106 and the second gate 107 of the dual-gate trench lateral MOSFET can be controlled separately. When the device is working, only one gate can be turned on, and the conduction current flows from one source electrode through the bottom of the trench to the other source electrode, meeting the requirements of battery management application circuits. In other words, this dual-gate trench lateral MOSFET is suitable for battery management systems, expanding the application range of trench MOSFETs. Since the current of this dual-gate trench lateral MOSFET does not pass through the back of the chip during operation, the impact of chip thinning thickness does not need to be considered in actual processes, and the back metallization process can be reduced, saving manufacturing costs to a certain extent.
[0086] Furthermore, the dual-gate trench lateral MOSFET also includes a first gate oxide layer 103 with a thickness greater than that of the second gate oxide layer 104. The first gate oxide layer 103 fills the bottom of the trench 102, and the first gate 103 and the second gate 106 are located above the first gate oxide layer 103. This improves the voltage withstand capability of the device, reduces the gate leakage charge (Qgd) of the device, and reduces the dynamic loss of the device.
[0087] It should be noted that this specification adopts a progressive approach. The later descriptions of the dual-gate trench lateral MOSFET focus on the differences in manufacturing methods between them and the dual-gate trench lateral MOSFETs described earlier. For similarities and similarities between the different parts, please refer to each other.
[0088] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A dual-gate trench lateral MOSFET, characterized in that, include: A substrate in which grooves are formed; A first gate and a second gate are disposed at a distance within the trench and are arranged side by side in the width direction of the trench; as well as A first source electrode and a second source electrode are discrete, each having one end embedded in the substrate and the other end located above the substrate. The first source electrode and the second source electrode are disposed on both sides of the trench, with the first source electrode located on the side of the first gate away from the second gate and the second source electrode located on the side of the second gate away from the first gate.
2. The dual-gate trench lateral MOSFET as described in claim 1, characterized in that, Also includes: A first gate oxide layer is filled at the bottom of the trench, and the first gate and the second gate are located above the first gate oxide layer; as well as A second gate oxide layer covers the trench sidewall located above the first gate oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
3. The dual-gate trench lateral MOSFET as described in claim 1, characterized in that, It also includes a gate oxide layer of uniform thickness, which covers the sidewalls and bottom of the trench, with the first gate and the second gate located above the gate oxide layer.
4. The dual-gate trench lateral MOSFET as described in claim 1, characterized in that, The substrate has a first body region and a second body region, both of which are of a first conductivity type. The top of the substrate has a first source region and a second source region, both of which are of a second conductivity type. The first conductivity type and the second conductivity type are opposite. The first body region and the second body region are located on both sides of the trench. The first source region is located above the first body region and is connected to the first body region. The first source electrode penetrates the first source region and extends into the first body region. The second source region is located above the second body region and is connected to the second body region. The second source electrode penetrates the second source region and extends into the second body region.
5. The dual-gate trench lateral MOSFET as described in claim 1, characterized in that, It also includes a dielectric layer that fills the trench and covers at least a portion of the top surface of the first gate, the second gate, and the substrate, wherein the first source electrode and the second source electrode penetrate the dielectric layer.
6. The dual-gate trench lateral MOSFET as described in claim 1, characterized in that, When an enable voltage is applied to the first gate, a positive voltage is applied to the first source electrode, and a zero-volt voltage is applied to the second source electrode, the dual-gate trench lateral MOSFET is turned on, and current flows from the first source electrode along the side and bottom of the trench to the second source electrode.
7. A method for manufacturing a dual-gate trench lateral MOSFET, characterized in that, include: Provide a substrate in which trenches are formed; A first gate and a second gate are formed in the trench, the first gate and the second gate being disposed at a distance from each other in the trench and arranged side by side in the width direction of the trench; as well as A discrete first source electrode and a second source electrode are formed on the substrate. One end of the first source electrode and the second source electrode are embedded in the substrate and the other end is located above the substrate. The first source electrode and the second source electrode are disposed on both sides of the trench. The first source electrode is located on the side of the first gate away from the second gate, and the second source electrode is located on the side of the second gate away from the first gate.
8. The method for manufacturing a dual-gate trench lateral MOSFET as described in claim 7, characterized in that, Also includes: After forming a trench in the substrate and before forming a first gate and a second gate within the trench, a first gate oxide layer is formed at the bottom of the trench, the first gate oxide layer filling the bottom of the trench; and A second gate oxide layer is formed on the substrate, the second gate oxide layer covering the trench sidewall above the first gate oxide layer, and the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.
9. The method for manufacturing a dual-gate trench lateral MOSFET as described in claim 7, characterized in that, The method of forming the first gate and the second gate in the trench includes: A gate material layer is formed on the substrate, the gate material layer covering the top surface of the substrate and the inner surface of the trench; and An anisotropic etching process is used to etch away the gate material layer on the top surface of the substrate and a portion of the gate material layer on the bottom surface of the trench, leaving the gate material layers on the two opposite sidewalls of the trench as the first gate and the second gate.
10. The method for manufacturing a dual-gate trench lateral MOSFET as described in claim 7, characterized in that, Also includes: After forming the first gate and the second gate in the trench, a first body region and a second body region are formed in the substrate by ion implantation. The first body region and the second body region are both of the first conductivity type and are located on both sides of the trench. A first source region and a second source region are formed on the top of the substrate by ion implantation. Both the first source region and the second source region are of the second conductivity type. The first conductivity type and the second conductivity type are opposite. The first source region and the second source region are located on both sides of the trench. The first source region is located above the first body region and is connected to the first body region. The second source region is located above the second body region and is connected to the second body region. A dielectric layer is formed on the substrate, the dielectric layer filling the trench and covering the first gate, the second gate, and the top surface of the substrate.
11. The method for manufacturing a dual-gate trench lateral MOSFET as described in claim 10, characterized in that, The method for forming discrete first and second source electrodes on the substrate includes: Etching removes a portion of the dielectric layer and a portion of the substrate to form a first via and a second via, both of which penetrate the dielectric layer and have their bottoms located in the substrate; A metal material layer is formed on the dielectric layer, the metal material layer covering the dielectric layer and the inner surfaces of the first through-hole and the second through-hole; and Etching removes a portion of the metal material layer on the top surface of the dielectric layer to form the first source electrode and the second source electrode.