Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

This application discloses a semiconductor device and its manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body comprising a first surface, a second surface, a well region, a first region, a channel layer, and a second region; the first region and the channel layer are in contact with each other; the first region is configured with a first conductivity type and is located on the first surface; the channel layer is configured with a first conductivity type and is located on the first surface; the well region is configured with a second conductivity type and is located on the side of the first region and channel layer away from the first surface, and the well region encloses the second region; the second region is configured with a second conductivity type; a first trench is formed on the first surface, and the bottom surface of the first trench is in contact with the second region; an insulating layer is located on the first surface; a gate; a source; and a drain. The technical solution of this application embodiment can reduce cell size, reduce the conduction loss of the semiconductor device, and improve response speed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC), as representatives of third-generation semiconductor materials, have advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency scenarios.

[0003] Existing SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are enhancement-mode devices, which are normally non-conductive. To conduct, a positive voltage needs to be applied between the gate and source. However, enhancement-mode devices have higher conduction losses, larger cell sizes, and slower response times. Summary of the Invention

[0004] This application provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle, to reduce cell size, decrease conduction loss of the semiconductor device, and improve response speed.

[0005] According to one aspect of this application, a semiconductor device is provided, the semiconductor device comprising: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a channel layer, and a second region; the first region and the channel layer are in contact with each other, the first region is configured with the first conductivity type and is located on the first surface; the channel layer is configured with the first conductivity type and is located on the first surface; the well region is configured with the second conductivity type and is located on the side of the first region and the channel layer away from the first surface, and the well region surrounds the second region; the second region is configured with the second conductivity type; a first trench is provided on the first surface, and the bottom surface of the first trench is in contact with the second region; the first conductivity type and the second conductivity type are different; An insulating layer is located on the first surface; The gate is located on the side of the insulating layer away from the first surface; The source electrode is located on the first surface and is in contact with the second region through the first trench; The drain electrode is located on the second surface.

[0006] Optionally, the semiconductor body includes a first sub-semiconductor body and a second sub-semiconductor body; both the first sub-semiconductor body and the second sub-semiconductor body are configured with a first conductivity type; the first sub-semiconductor body includes a third surface and a fourth surface disposed opposite to each other; the fourth surface and the second surface are the same surface; the second region is located on the third surface; The second sub-semiconductor body is located on the side of the second region away from the fourth surface; the second sub-semiconductor body includes a fifth surface and a sixth surface; the fifth surface is the same as the first surface; the second sub-semiconductor body also includes a well region, a first region, a channel layer and a first trench; the first region and the channel layer are both located on the fifth surface and are in contact with each other; the well region is located on the side of the first region and the channel layer away from the fifth surface and surrounds the second region; the first trench is located on the fifth surface and the bottom surface of the first trench is in contact with the second region.

[0007] Optionally, the thickness of the trench layer is less than the thickness of the first region.

[0008] Optionally, the ion concentration in the channel layer is lower than the ion concentration in the first region.

[0009] Optionally, the semiconductor body further includes a third region, which is configured with a first conductivity type and located on the first surface; the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and the third region and the well region do not overlap in the orthographic projection of the semiconductor body.

[0010] Optionally, the semiconductor device further includes: an interlayer insulating layer; the interlayer insulating layer is located on the side of the gate away from the insulating layer; The interlayer insulation layer is provided with a first through hole and a second through hole; the first through hole is connected to the first trench; The source electrode reaches the second region through the first through-hole and the first trench; Semiconductor devices also include: gate electrode; The gate electrode reaches the gate through the second via.

[0011] Optionally, the semiconductor device further includes: a first metal layer and a second metal layer; The first metal layer is located on the sidewall of the first via, the bottom and sidewall of the second via and the first trench, and on the side of the interlayer insulating layer away from the gate. The second metal layer is located on the side away from the first metal layer within the first via, the second via, and the first trench; the source electrode contacts the second region through the second metal layer and the first metal layer.

[0012] Optionally, the semiconductor body may include a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0013] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising: A semiconductor body is provided, which is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, a channel layer, and a second region. The first region and the channel layer are in contact with each other. The first region is configured with the first conductivity type and is located on the first surface. The channel layer is configured with the first conductivity type and is located on the side of the first region and the channel layer away from the first surface, and the well region surrounds the second region. The second region is configured with the second conductivity type. A first trench is provided on the first surface, and the bottom surface of the first trench is in contact with the second region. The first conductivity type and the second conductivity type are different. An insulating layer is formed on the first surface; A gate is formed on the side of the insulating layer away from the first surface; A source electrode is formed on the first surface; the source electrode contacts the second region through a first trench; A drain electrode is formed on the second surface.

[0014] Optionally, the semiconductor body includes: A first sub-semiconductor body is provided, the first sub-semiconductor body is configured with a first conductivity type; the first sub-semiconductor body includes a third surface and a fourth surface disposed opposite to each other; the fourth surface is the same surface as the second surface. A second region is formed on the third surface; A second sub-semiconductor body is formed on the side of the second region away from the fourth surface; the second sub-semiconductor body includes a fifth surface and a sixth surface; the fifth surface is the same as the first surface; A first mask layer is formed on the fifth surface; the first mask layer is provided with a third through-hole; A transition well region is formed on the fifth surface exposed by the third through hole; the transition well region is configured as the second conductivity type and encloses the second region; A transition channel layer is formed on the fifth surface exposed by the third through hole; Remove the first mask layer; A second mask layer is formed on the fifth surface; the second mask layer is provided with a fourth through hole; A transition first region is formed on the fifth surface exposed by the fourth through hole; Remove the second mask layer; A first trench is formed on the fifth surface; the bottom surface of the first trench contacts the second region; the transition trap region retained after the formation of the first trench is used as the trap region; the transition first region retained after the formation of the first trench is used as the first region; and the transition channel layer retained after the formation of the first trench is used as the channel layer.

[0015] Optionally, the semiconductor body includes: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0016] According to another aspect of this application, a power module is provided, the power module including a substrate and at least one of the above-described semiconductor devices, the substrate being used to support the semiconductor devices.

[0017] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one of the aforementioned semiconductor devices, which are electrically connected to the circuit board.

[0018] According to another aspect of this application, a vehicle is provided, the vehicle including a load and the aforementioned power conversion circuit, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0019] The technical solution of this application embodiment places the second buried layer on the side of the first region and channel layer away from the first surface and is wrapped by the well region. This shifts the second region, which originally needed a large contact area with the source electrode in a horizontal position, to a vertical direction, reducing the horizontal size of the contact hole and thus the cell size, optimizing the performance of the semiconductor device. Simultaneously, a channel layer with the opposite conductivity type to the well region is provided on the side of the well region away from the second surface. This eliminates the need to apply a gate-source voltage to the semiconductor device, allowing the presence of carriers of the first conductivity type under normal conditions, making the semiconductor device a depletion-type semiconductor device. It is normally in a conducting state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared to enhancement-mode semiconductor devices, the technical solution provided in this application embodiment reduces the conduction loss of the semiconductor device, improves the response speed and the speed of current flow control, and is more suitable for high-frequency circuits and switching circuits.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application; Figure 2This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 3-5 These are cross-sectional views corresponding to each step of a semiconductor device manufacturing method provided according to embodiments of this application; Figure 6 Provided according to the embodiments of this application Figure 2 The flowchart included in S110; Figures 7-13 Provided according to the embodiments of this application Figure 6 Cross-sectional views corresponding to each step in the process. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. For example... Figure 1As shown, the semiconductor device includes: a semiconductor body 100 configured for a first conductivity type, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103, a first region 104, a channel layer 105, and a second region 106; the first region 104 and the channel layer 105 are in contact with each other, the first region 104 is configured for the first conductivity type and is located on the first surface 101; the channel layer 105 is configured for the first conductivity type and is located on the first surface 101; the well region 103 is configured for the second conductivity type and is located on the first region 104 and the channel layer 106. 05 is located on the side away from the first surface 101, and the well region 103 encloses the second region 106; the second region 106 is configured with a second conductivity type; the first surface 101 is provided with a first trench 107, and the bottom surface of the first trench 107 contacts the second region 106; the first conductivity type and the second conductivity type are different; an insulating layer 30 is located on the first surface 101; a gate 40 is located on the side of the insulating layer 30 away from the first surface 101; a source 50 is located on the first surface 101 and contacts the second region 106 through the first trench 107; and a drain 60 is located on the second surface 102.

[0026] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0027] For example, in an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions can be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, where the P-type dopant ions can be aluminum (Al) ions or boron (B) ions. The conductivity type of the second region 106 is the same as that of the well region 103, both being set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, with a doping concentration greater than that of the well region 103, allowing for good ohmic contact with the source 50. The first trench 107 can be formed by photolithography and etching processes.

[0028] like Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0029] The insulating layer 30 can be a gate oxide layer. The insulating layer 30 is used to insulate and isolate the semiconductor body 100 and the gate 40. The material of the gate 40 can be polysilicon. The source 50 and drain 60 can both be formed by depositing metal. The deposited metal can be aluminum (Al), nickel (Ni), or silver (Ag).

[0030] The technical solution of this application embodiment involves burying a second region 106 on the side of the first region 104 and the channel layer 105 away from the first surface 101 and encasing it in the well region 103. This shifts the second region 106, which originally needed to have a large contact area with the source electrode 50 in a horizontal position, to a vertical direction, reducing the horizontal size of the contact hole and thus the cell size, optimizing the performance of the semiconductor device. Simultaneously, a channel layer 105 with the opposite conductivity type to the well region 103 is provided on the side of the well region 103 away from the second surface 102. This eliminates the need to apply a gate-source voltage to the semiconductor device, as it contains carriers of the first conductivity type under normal conditions, making the semiconductor device a depletion-type semiconductor device. It is normally in a conducting state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared to enhancement-mode semiconductor devices, the technical solution provided in this application embodiment reduces the conduction loss of the semiconductor device, improves the response speed and the speed of current flow control, and is more suitable for high-frequency circuits and switching circuits.

[0031] In an optional embodiment of this application, the semiconductor body 100 includes a first sub-semiconductor body 11 and a second sub-semiconductor body 12; both the first sub-semiconductor body 11 and the second sub-semiconductor body 12 are configured with a first conductivity type; the first sub-semiconductor body 11 includes a third surface 111 and a fourth surface 112 disposed opposite to each other; the fourth surface 112 and the second surface 102 are the same surface; the second region 106 is located on the third surface 111; the second sub-semiconductor body 12 is located on the side of the second region 106 away from the fourth surface 112; the second sub-semiconductor body 12 includes a first sub-semiconductor body 111 and a second sub-semiconductor body 12. The fifth surface 121 and the sixth surface 122; the fifth surface 121 is the same surface as the first surface 101; the second sub-semiconductor body 12 also includes a well region 103, a first region 104, a channel layer 105 and a first trench 107; the first region 104 and the channel layer 105 are both located on the fifth surface 121 and are in contact with each other; the well region 103 is located on the side of the first region 104 and the channel layer 105 away from the fifth surface 121 and surrounds the second region 106; the first trench 107 is located on the fifth surface 121 and the bottom surface of the first trench 107 is in contact with the second region 106.

[0032] Specifically, such as Figure 1 As shown, the first sub-semiconductor body 11 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the first sub-semiconductor body 11 may also include only the epitaxial layer 20. In other embodiments of this application, the first sub-semiconductor body 11 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process. A second sub-semiconductor body 12 can be formed on the third surface 111 of the first sub-semiconductor body 11 by an epitaxial process.

[0033] In optional embodiments of this application, reference is made to Figure 1 The thickness of the channel layer 105 is less than the thickness of the first region 104.

[0034] Specifically, the thickness of the channel layer 105 does not need to be too thick. The thickness of the channel layer 105 is less than the thickness of the first region 104, which can meet the requirements for serving as a channel.

[0035] In optional embodiments of this application, reference is made to Figure 1 The ion concentration in the channel layer 105 is lower than the ion concentration in the first region 104.

[0036] Specifically, the ion implantation concentration of the channel layer 105 is lower than that of the first region 104, which can reduce the manufacturing cost of semiconductor devices.

[0037] In optional embodiments of this application, reference is made to Figure 1The semiconductor body 100 also includes a third region 108, which is configured as a first conductivity type and located on the first surface 101; the doping concentration of the third region 108 is greater than the doping concentration of the semiconductor body 100, and the third region 108 and the well region 103 do not overlap in the orthographic projection of the semiconductor body 100.

[0038] Specifically, the setting of the third region 108 reduces the resistance of the junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the MOSFET device.

[0039] In optional embodiments of this application, reference is made to Figure 1 The semiconductor device further includes: an interlayer insulating layer 70; the interlayer insulating layer 70 is located on the side of the gate 40 away from the insulating layer 30; the interlayer insulating layer 70 is provided with a first via 71 and a second via 72; the first via 71 communicates with the first trench 107; the source electrode 50 reaches the second region 106 through the first via 71 and the first trench 107; the semiconductor device further includes: a gate electrode 80; the gate electrode 80 reaches the gate 40 through the second via 72.

[0040] Specifically, the interlayer insulating layer 70 is used to insulate the gate 40 and the source 50. The interlayer insulating layer 70 has a first via 71, through which the source 50 passes to contact the first region 104 and the second region 106. The interlayer insulating layer 70 also has a second via 72, through which the gate electrode 80 can directly connect to the gate 40, and the gate electrode 80 is used to provide an electrical signal to the gate 40.

[0041] In optional embodiments of this application, reference is made to Figure 1 The semiconductor device further includes: a first metal layer 91 and a second metal layer 92; the first metal layer 91 is located on the sidewall of the first via 71, the bottom surface and sidewall of the second via 72 and the first trench 107, and on the side of the interlayer insulating layer 70 away from the gate 40; the second metal layer 92 is located on the side of the first via 71, the second via 72 and the first trench 107 away from the first metal layer 91; the source 50 is in contact with the second region 106 through the second metal layer 92 and the first metal layer 91.

[0042] Specifically, the first metal layer 91 includes, but is not limited to, titanium or titanium nitride. The second metal layer 92 includes, but is not limited to, tungsten. Nickel metal may also be deposited before forming the first metal layer 91. By setting the first metal layer 91 and the second metal layer 92, better contact can be achieved between the source 50 and the first region 104 and the second region 106.

[0043] In optional embodiments of this application, reference is made to Figure 1The semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0044] The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0045] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0046] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 2 As shown, the method for manufacturing this semiconductor device includes: S110. A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a channel layer, and a second region; the first region and the channel layer are in contact with each other, the first region being configured with the first conductivity type and located on the first surface; the channel layer being configured with the first conductivity type and located on the first surface; the well region being configured with the second conductivity type and located on the side of the first region and the channel layer away from the first surface, and the well region enclosing the second region; the second region being configured with the second conductivity type; a first trench is provided on the first surface, the bottom surface of the first trench being in contact with the second region; the first conductivity type and the second conductivity type are different.

[0047] refer to Figure 3 A semiconductor body 100 is provided, which is configured as a first conductivity type and includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104, a channel layer 105, and a second region 106. The first region 104 and the channel layer 105 are in contact with each other. The first region 104 is configured as a first conductivity type and is located on the first surface 101. The channel layer 105 is configured as a first conductivity type and is located on the first surface 101. The well region 103 is configured as a second conductivity type and is located on the side of the first region 104 and the channel layer 105 away from the first surface 101, and the well region 103 surrounds the second region 106. The second region 106 is configured as a second conductivity type. The first surface 101 is provided with a first trench 107, and the bottom surface of the first trench 107 is in contact with the second region 106. The first conductivity type and the second conductivity type are different.

[0048] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0049] For example, in an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions can be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, where the P-type dopant ions can be aluminum (Al) ions or boron (B) ions. The conductivity type of the second region 106 is the same as that of the well region 103, both being set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, with a doping concentration greater than that of the well region 103, allowing for good ohmic contact with the source 50. The first trench 107 can be formed by photolithography and etching processes.

[0050] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0051] In optional embodiments of this application, reference is made to Figure 3 The semiconductor body 100 also includes a third region 108, which is configured with a first conductivity type and located on the first surface 101. The doping concentration of the third region 108 is greater than that of the semiconductor body 100, and the third region 108 and the well region 103 do not overlap in their orthographic projections onto the semiconductor body 100. The configuration of the third region 108 reduces the resistance of the JFET region, thereby reducing the on-resistance of the MOSFET device.

[0052] S120, An insulating layer is formed on the first surface.

[0053] refer to Figure 4 An insulating layer 30 is formed on the first surface 101 using a high-temperature oxidation or deposition process. The insulating layer 30 may be a gate oxide layer.

[0054] S130, A gate is formed on the side of the insulating layer away from the first surface.

[0055] refer to Figure 4 On the side of the insulating layer 30 away from the first surface 101, the gate 40 is formed by a polysilicon thin film deposition process.

[0056] In optional embodiments of this application, reference is made to Figure 4 An interlayer insulating layer 70 is formed on the side of the gate 40 away from the insulating layer 30. The interlayer insulating layer 70 is provided with a first through-hole 71 and a second through-hole 72.

[0057] S140, A source electrode is formed on the first surface; the source electrode contacts the second region through a first trench.

[0058] refer to Figure 5 A metal is deposited on the first surface 101 to form a source electrode 50; the source electrode 50 contacts the second region 106 through a first trench 107. A gate electrode 80 is also formed concurrently with the source electrode 50. The gate electrode 80 can be directly connected to the gate 40 through a second via 72, and the gate electrode 80 is used to provide an electrical signal to the gate 40. The source electrode 50 and the gate electrode 80 are isolated by vias.

[0059] In an optional embodiment of this application, before forming the source 50, a first metal layer 91 and a second metal layer 92 are further formed. The first metal layer 91 is located on the sidewall of the first via 71, the bottom surface and sidewall of the second via 72 and the first trench 107, and on the side of the interlayer insulating layer 70 away from the gate 40. The second metal layer 92 is located on the side of the first via 71, the second via 72 and the first trench 107 away from the first metal layer 91. The source 50 contacts the second region 106 through the second metal layer 92 and the first metal layer 91. The first metal layer 91 includes, but is not limited to, titanium or titanium nitride. The second metal layer 92 includes, but is not limited to, tungsten.

[0060] S150, a drain electrode is formed on the second surface.

[0061] refer to Figure 1 Metal is deposited on the second surface 102 to form the drain electrode 60.

[0062] The technical solution of this application embodiment forms a second region 106 on the side of the first region 104 and the channel layer 105 away from the first surface 101 using buried layer technology and is enclosed by the well region 103. This shifts the second region 106, which originally needed to have a large contact area with the source electrode 50 in a horizontal position, to a vertical direction, reducing the horizontal size of the contact hole and thus reducing the cell size, thereby optimizing the performance of the formed semiconductor device. Simultaneously, a channel layer 105 with the opposite conductivity type to the well region 103 is formed on the side of the well region 103 away from the second surface 102. Without applying a gate-source voltage to the semiconductor device, carriers of the first conductivity type are present under normal conditions, making the semiconductor device a depletion-type semiconductor device. It is normally in a conducting state, and a negative gate-source voltage is required to cut off the channel in the off state. Compared to enhancement-mode semiconductor devices, the technical solution provided in this application embodiment reduces the conduction loss of the formed semiconductor device, improves the response speed and the speed of current flow control, and is more suitable for high-frequency circuits and switching circuits.

[0063] Figure 6 Provided according to the embodiments of this application Figure 2 The flowchart included in S110. For example... Figure 6 As shown, S110, providing a semiconductor body includes: S1101. A first sub-semiconductor body is provided, the first sub-semiconductor body is configured with a first conductivity type; the first sub-semiconductor body includes a third surface and a fourth surface disposed opposite to each other; the fourth surface and the second surface are the same surface.

[0064] refer to Figure 7 A first sub-semiconductor body 11 is provided, and the first sub-semiconductor body 11 is configured with a first conductivity type. The first sub-semiconductor body 11 includes a third surface 111 and a fourth surface 112 disposed opposite to each other; the fourth surface 112 is the same surface as the second surface 102. The first sub-semiconductor body 11 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the first sub-semiconductor body 11 may also include only the epitaxial layer 20. In other embodiments of this application, the first sub-semiconductor body 11 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process.

[0065] S1102, A second region is formed on the third surface.

[0066] refer to Figure 8 Photoresist is coated on the third surface 111, and the second region 106 is formed by processes such as exposure, development, etching and ion implantation.

[0067] S1103, a second sub-semiconductor body is formed on the side of the second region away from the fourth surface; the second sub-semiconductor body includes a fifth surface and a sixth surface; the fifth surface is the same as the first surface.

[0068] refer to Figure 9 A second sub-semiconductor body 12 is formed on the side of the second region 106 away from the fourth surface 112; the second sub-semiconductor body 12 includes a fifth surface 121 and a sixth surface 122; the fifth surface 121 is the same surface as the first surface 101.

[0069] Based on the third surface 111 of the first sub-semiconductor body 11, the second sub-semiconductor body 12 can be formed by epitaxial process.

[0070] S1104. A first mask layer is formed on the fifth surface; the first mask layer is provided with a third through hole.

[0071] refer to Figure 10 A first mask layer 21 is formed on the fifth surface 121; the first mask layer 21 has a third via CT3. The first mask layer 21 is formed on the fifth surface 121 using a hard mask (HM) process. Alternatively, silicon dioxide can be deposited to form the first mask layer 21 using plasma-enhanced chemical vapor deposition (PECVD). The first mask layer 21 is then patterned using photolithography to form the third via CT3.

[0072] S1105, A transition well region is formed on the fifth surface exposed by the third through hole; the transition well region is configured as a second conductivity type and encloses the second region.

[0073] refer to Figure 10 Ion implantation is performed on the fifth surface 121 exposed by the third through-hole CT3 to form a transition well region 1031; the transition well region 1031 is set to the second conductivity type and surrounds the second region 106.

[0074] S1106, A transition channel layer is formed on the fifth surface exposed by the third through hole.

[0075] refer to Figure 10 Ion implantation is performed on the fifth surface 121 exposed by the third through-hole CT3 to form a transition channel layer 1051.

[0076] S1107, Remove the first mask layer.

[0077] refer to Figure 11 The first mask layer 21 should be removed by wet etching.

[0078] S1108. A second mask layer is formed on the fifth surface; the second mask layer is provided with a fourth through hole.

[0079] refer to Figure 12 A second mask layer 22 is formed by depositing silicon dioxide on the fifth surface 121 using HM process or PECVD; the second mask layer 22 is provided with a fourth through hole CT4.

[0080] S1109, A transition first region is formed on the fifth surface exposed by the fourth through hole.

[0081] refer to Figure 12 A transitional first region 1041 is formed on the fifth surface 121 exposed by the fourth through hole CT4 through an ion implantation process.

[0082] S1110, Remove the second mask layer.

[0083] refer to Figure 13 The second mask layer 22 should be removed by wet etching.

[0084] S1111. A first trench is formed on the fifth surface; the bottom surface of the first trench is in contact with the second region; the transition trap region retained after the formation of the first trench is used as the trap region, the transition first region retained after the formation of the first trench is used as the first region, and the transition channel layer retained after the formation of the first trench is used as the channel layer.

[0085] refer to Figure 13 and Figure 3 A first trench 107 is formed on the fifth surface 121; the bottom surface of the first trench 107 contacts the second region 106; the transition trap region 1031 retained after the formation of the first trench 107 is used as trap region 103; the transition first region 1041 retained after the formation of the first trench 107 is used as first region 104; and the transition channel layer 1051 retained after the formation of the first trench 107 is used as channel layer 105.

[0086] It should be noted that the first trench 107 can be formed at this location, or it can be formed simultaneously with the first through hole through etching or other processes after the interlayer insulating layer is formed. This application embodiment does not make specific limitations here.

[0087] In optional embodiments of this application, S110, providing a semiconductor body includes: providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0088] For details, please refer to Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0089] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0090] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this application will not be elaborated further here.

[0091] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0092] Therefore, the power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of this application, which will not be elaborated further here.

[0093] This application embodiment also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0094] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of this application will not be repeated here.

[0095] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, configured for a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a channel layer, and a second region; the first region and the channel layer are in contact with each other, the first region is configured for the first conductivity type and is located on the first surface; the channel layer is configured for the first conductivity type and is located on the first surface; the well region is configured for a second conductivity type and is located on the side of the first region and the channel layer away from the first surface, and the well region encloses the second region; the second region is configured for the second conductivity type; a first trench is provided on the first surface, and the bottom surface of the first trench is in contact with the second region; The first conductivity type and the second conductivity type are different; An insulating layer is located on the first surface; The gate is located on the side of the insulating layer away from the first surface; The source electrode is located on the first surface and contacts the second region through the first trench; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes a first sub-semiconductor body and a second sub-semiconductor body; both the first sub-semiconductor body and the second sub-semiconductor body are configured with a first conductivity type; the first sub-semiconductor body includes a third surface and a fourth surface disposed opposite to each other; the fourth surface and the second surface are the same surface; the second region is located on the third surface; The second sub-semiconductor body is located on the side of the second region away from the fourth surface; the second sub-semiconductor body includes a fifth surface and a sixth surface; the fifth surface is the same as the first surface; the second sub-semiconductor body also includes a well region, a first region, a channel layer, and a first trench; the first region and the channel layer are both located on the fifth surface and are in contact with each other; the well region is located on the side of the first region and the channel layer away from the fifth surface and encloses the second region; the first trench is located on the fifth surface, and the bottom surface of the first trench is in contact with the second region.

3. The semiconductor device according to claim 1, characterized in that, The thickness of the channel layer is less than the thickness of the first region.

4. The semiconductor device according to claim 1, characterized in that, The ion concentration in the channel layer is lower than that in the first region.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a third region, which is configured with a first conductivity type and located on the first surface; the doping concentration of the third region is greater than the doping concentration of the semiconductor body, and the third region and the well region do not overlap in their orthogonal projections onto the semiconductor body.

6. The semiconductor device according to claim 1, characterized in that, Also includes: Interlayer insulation layer; The interlayer insulating layer is located on the side of the gate away from the insulating layer; The interlayer insulation layer is provided with a first through hole and a second through hole; The first through hole is connected to the first trench; The source electrode reaches the second region through the first through-hole and the first trench; The semiconductor device further includes: a gate electrode; The gate electrode reaches the gate through the second via.

7. The semiconductor device according to claim 6, characterized in that, Also includes: First metal layer and second metal layer; The first metal layer is located on the sidewall of the first via, the bottom and sidewall of the second via and the first trench, and on the side of the interlayer insulating layer away from the gate. The second metal layer is located on the side away from the first metal layer within the first via, the second via, and the first trench; the source electrode contacts the second region through the second metal layer and the first metal layer.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

9. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a channel layer, and a second region; the first region and the channel layer are in contact with each other, the first region being configured with the first conductivity type and located on the first surface; the channel layer being configured with the first conductivity type and located on the first surface; the well region being configured with a second conductivity type and located on the side of the first region and the channel layer away from the first surface, and the well region enclosing the second region; the second region being configured with a second conductivity type; a first trench is provided on the first surface, the bottom surface of the first trench being in contact with the second region; the first conductivity type and the second conductivity type are different; An insulating layer is formed on the first surface; A gate is formed on the side of the insulating layer away from the first surface; A source electrode is formed on the first surface; The source electrode is in contact with the second region through the first trench; A drain electrode is formed on the second surface.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The semiconductor body includes: A first sub-semiconductor body is provided, the first sub-semiconductor body is configured with a first conductivity type; the first sub-semiconductor body includes a third surface and a fourth surface disposed opposite to each other; the fourth surface is the same surface as the second surface. The second region is formed on the third surface; A second sub-semiconductor body is formed on the side of the second region away from the fourth surface; the second sub-semiconductor body includes a fifth surface and a sixth surface; the fifth surface is the same as the first surface; A first mask layer is formed on the fifth surface; the first mask layer is provided with a third through hole; A transition well region is formed on the fifth surface exposed by the third through hole; the transition well region is configured with a second conductivity type and encloses the second region; A transition channel layer is formed on the fifth surface exposed by the third through hole; Remove the first mask layer; A second mask layer is formed on the fifth surface; the second mask layer is provided with a fourth through hole; A transition first region is formed on the fifth surface exposed by the fourth through hole; Remove the second mask layer; A first trench is formed on the fifth surface; the bottom surface of the first trench contacts the second region; the transition well region retained after the formation of the first trench is used as a well region; the transition first region retained after the formation of the first trench is used as a first region; and the transition channel layer retained after the formation of the first trench is used as a channel layer.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The semiconductor body includes: Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

12. A power module, characterized in that, The device includes a substrate and the semiconductor device according to any one of claims 1-8, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-8, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 13, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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