Solar cell, cell assembly, photovoltaic system and solar cell manufacturing method

Abstract

This invention provides a solar cell, a solar cell module, a photovoltaic system, and a method for fabricating a solar cell. The solar cell includes a silicon substrate, a first doped layer, and a second doped layer. A first surface of the silicon substrate includes multiple first regions and multiple second regions. The first and second regions are arranged alternately along a first direction. Each second region includes an isolation trench and a second doped region. Each first region includes a central region and an edge region, with the edge region located on the side of the central region adjacent to the isolation trench. The first doped layer is disposed in the central region, and the second doped layer is disposed in the second doped region and the edge region. The doping types of the first and second doped layers are opposite. This invention simplifies the fabrication process and improves the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a solar cell, a cell module, a photovoltaic system, and a method for preparing a solar cell. Background Technology

[0002] With the increasing scarcity of traditional energy sources and the escalating environmental pollution, solar energy, as a clean and renewable energy source, is being widely used. Solar cells are the core devices for photoelectric conversion. A solar cell consists of a silicon substrate and P-type and N-type doped regions disposed on the silicon substrate. The P-type and N-type doped regions work together to form a PN junction, utilizing the photovoltaic effect to convert solar energy into electrical energy. However, existing solar cell fabrication processes are complex. Summary of the Invention

[0003] This invention provides a solar cell, a solar cell module, a photovoltaic system, and a method for preparing a solar cell, which simplifies the preparation process and improves the photoelectric conversion efficiency of the solar cell.

[0004] According to one aspect of the present invention, a solar cell is provided, the solar cell comprising: Silicon substrate, first doped layer, and second doped layer; The first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions; the first regions and the second regions are arranged alternately along a first direction, and the second regions include isolation trenches and second doped regions. The first region includes a central region and an edge region, the edge region being disposed on the side of the central region adjacent to the isolation trench, the first doped layer being disposed in the central region, and the second doped layer being disposed in the second region and the edge region; wherein the doping types of the first doped layer and the second doped layer are opposite.

[0005] Optionally, the second doped layer in the edge region includes a first sub-part and a second sub-part, the first sub-part being disposed on the side of the second sub-part adjacent to the first doped layer, the thickness of the first sub-part being greater than the thickness of the second sub-part, and the distance between the surface of the first sub-part away from the silicon substrate and the silicon substrate being greater than the distance between the surface of the first doped layer away from the silicon substrate and the silicon substrate; or, the surface of the second doped layer in the edge region away from the silicon substrate is planar.

[0006] Optionally, the first sub-part extends to the surface of the first doped layer away from the silicon substrate, and a tunneling layer and a dielectric layer are disposed between the first doped layer and the first sub-part, the dielectric layer being disposed on the side of the tunneling layer adjacent to the first doped layer.

[0007] Optionally, the distance between the edge region of the first surface and the second surface of the silicon substrate is less than the distance between the central region of the first surface and the second surface of the silicon substrate, wherein the second surface is disposed opposite to the first surface.

[0008] Optionally, along the first direction, the width of the second doped layer in the edge region is 1 μm-2 μm.

[0009] Optionally, the size of the isolation groove along the first direction ranges from 50μm to 150μm.

[0010] Optionally, the first doped layer includes an edge portion, which is disposed adjacent to the second doped layer. The edge portion includes a first doping element and a second doping element; wherein the first doping element is an element doped in the first doped layer, and the second doping element is an element doped in the second doped layer.

[0011] Optionally, the doping concentration of the second doped element in the edge portion is greater than or equal to 10. 17 atoms / cm 3 And less than or equal to 5 × 10 20 atoms / cm 3 ; The width of the edge portion along the first direction is 50nm-1μm; The doping concentration of the second doped element in the second doped layer is greater than or equal to 10. 17 atoms / cm 3 and less than or equal to 10 21 atoms / cm 3 ; The doping concentration of the first doped element in the first doped layer is greater than or equal to 2 × 10⁻⁶. 16 atoms / cm 3 And less than or equal to 2×10 19 atoms / cm 3 ; The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer.

[0012] Optional: tunneling layer, passivation layer, and antireflection layer; The tunneling layer is disposed between the first doped layer and the silicon substrate, and between the second doped layer and the silicon substrate; The passivation layer is disposed on the side of the first doped layer and the second doped layer away from the silicon substrate; The antireflection layer is disposed on the side of the passivation layer away from the silicon substrate.

[0013] According to another aspect of the present invention, a battery module is provided, wherein the photovoltaic module includes a solar cell in any embodiment.

[0014] According to another aspect of the present invention, a photovoltaic system is provided, the photovoltaic system including a battery module.

[0015] According to another aspect of the present invention, a method for preparing a solar cell is provided, the method comprising: Provide silicon substrate; A first doped layer and a second doped layer are formed on a first surface of a silicon substrate; wherein the first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions; the first regions and the second regions are arranged alternately along a first direction, and the second regions include isolation trenches and second doped regions; the first regions include a central region and an edge region, the edge region is disposed on the side of the central region adjacent to the isolation trench, the first doped layer is disposed in the central region, and the second doped layer is disposed in the second doped region and the edge region; wherein the doping types of the first doped layer and the second doped layer are opposite.

[0016] Optionally, a first doped layer and a second doped layer are formed on a first surface of a silicon substrate, including: S11. A first doped layer and a first mask layer are formed in a first region and a second region on the first surface of the silicon substrate, wherein the first mask layer is disposed on the side of the first doped layer away from the silicon substrate. S12. Remove the first doped layer and the prime number first mask layer except for the central region to expose the silicon substrate; S13. A second silicon material layer is formed on the surface of the first mask layer, the edge region, and the second region; S14. Anneal and doping the second silicon material layer to form a second doped layer and a second mask layer; S15. Remove a portion of the second mask layer in the second region and at least a portion of the second mask layer in the central region; S16. Etch the second doped layer exposed in the central region and the second doped layer and silicon substrate exposed in the second region to form an isolation trench; S17. Remove the first mask layer and the second mask layer.

[0017] Optionally, a first doped layer and a second doped layer are formed on a first surface of a silicon substrate, including: S21. An intrinsic amorphous silicon layer is formed in the first region and the second region of the first surface of the silicon substrate; S22. A barrier layer is provided on the side of the intrinsic amorphous silicon layer away from the silicon substrate, and the barrier layer covers the intrinsic amorphous silicon layer; S23. Remove the blocking layer in the central region; S24. The intrinsic amorphous silicon layer in the central region is doped and annealed to form a first doped layer and a first mask layer, wherein the first mask layer is disposed on the side of the first doped layer away from the silicon substrate. S25. Remove the blocking layer from the edge area and the second region; S26. The intrinsic amorphous silicon layer of the edge region and the second region is doped and annealed to form a second doped layer and a second mask layer, wherein the second mask layer is disposed on the side of the second doped layer away from the silicon substrate. S27. Remove part of the second mask layer in the second region; S28. Etch the second doped layer and the silicon substrate exposed in the second region to form an isolation trench; S29. Remove the first mask layer and the second mask layer.

[0018] The solar cell provided in this embodiment of the invention includes a silicon substrate, a first doped layer, and a second doped layer. The first surface of the silicon substrate includes multiple first regions, multiple second regions, and multiple isolation trenches. Each first region includes a central region and an edge region. The edge region is located on one side of the central region adjacent to the isolation trench. The first doped layer is located in the central region, and the second doped layer is located in the second regions and the edge region. This embodiment of the invention achieves the demarcation of the second doped layer and the isolation between the second doped layer and the first doped layer in the second doped region through a single etching process, simplifying the process. Furthermore, only a narrower isolation trench is needed to separate the second doped layer in the edge region and the second doped region, reducing the width of the isolation trench and eliminating the need for a traditional wide isolation region to isolate the first and second doped layers. This can increase the effective photoelectric conversion area of ​​the cell, reduce the dead zone area, and improve the photoelectric conversion efficiency.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a solar cell structure provided in an embodiment of the present invention; Figure 2This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another type of solar cell provided in an embodiment of the present invention; Figure 6 This is a flowchart of a method for preparing a solar cell according to an embodiment of the present invention; Figure 7 This is a flowchart of another method for preparing a solar cell provided in an embodiment of the present invention; Figure 8 This is a schematic diagram showing the setting of the first doped layer and the first mask layer; Figure 9 This is a schematic diagram of the first doped layer and mask layer after removing the non-central region; Figure 10 This is a schematic diagram showing the setting of the second silicon material layer; Figure 11 This is a schematic diagram of the formation of the second doped layer and the second mask layer; Figure 12 This is a schematic diagram showing the removal of part of the second mask layer; Figure 13 This is a schematic diagram of the formation of the isolation trench; Figure 14 This is a flowchart of another method for preparing a solar cell provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of setting an intrinsic amorphous silicon layer; Figure 16 This is a schematic diagram of setting up a barrier layer; Figure 17 This is a schematic diagram of removing the central area barrier layer; Figure 18 This is another schematic diagram of forming the first doped layer and the first mask layer; Figure 19 This is a schematic diagram showing the removal of the blocking layer in the edge area and the second area; Figure 20 This is another schematic diagram of forming a second doped layer and a second mask layer; Figure 21 This is a schematic diagram showing the removal of part of the second mask layer in the second region; Figure 22 This is another schematic diagram of forming an isolation groove. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] This invention provides a solar cell. Figure 1 This is a schematic diagram of a solar cell structure provided in an embodiment of the present invention, with reference to... Figure 1 The solar cell includes: a silicon substrate 10, a first doped layer 20, and a second doped layer 30; The first surface of the silicon substrate 10 includes a plurality of first regions 40 and a plurality of second regions 50; the first regions 40 and the second regions 50 are arranged alternately along a first direction X, and the second region 50 includes an isolation trench 60 and a second doped region 51. The first region 40 includes a central region 41 and an edge region 42. The edge region 42 is located on the side of the central region 41 adjacent to the isolation trench 60. The first doped layer 20 is located in the central region 41, and the second doped layer 30 is located in the second doped region 51 and the edge region 42. The doping types of the first doped layer 20 and the second doped layer 30 are opposite.

[0025] Specifically, the silicon substrate 10 has a front side and a back side. The front side is the side of the solar cell that receives light when it is working, and the back side is the side that is backlit when the solar cell is working. The first surface is the backlit surface of the silicon substrate 10. The silicon substrate 10 can be a monocrystalline silicon wafer or a polycrystalline silicon wafer, and it can be a P-type silicon wafer or an N-type silicon wafer; the specific type is not limited here. The first doped layer 20 and the second doped layer 30 can be a P-type doped layer and an N-type doped layer, respectively. An isolation trench 60 is disposed between the first region 40 and the second doped region 51, and the isolation trench 60 separates the adjacent first region 40 and second doped region 51. Figure 1 The illustration only shows an edge region 42 on one side of the central region 41 and is not intended to limit the scope of this application. In other embodiments, when there are second regions 50 on both sides of the first region 40 along the first direction X, edge regions 42 are provided on both sides of the central region 41 along the first direction X, and second doped layers 30 are provided on both sides of the first doped layer 20.

[0026] The first doped layer 20 and the second doped layer 30 have different doping types. The second doped layer 30 in the edge region 42 and the first doped layer 20 in the central region 41 are in contact. An isolation trench 60 is disposed between the second doped layer 30 in the edge region 42 and the second doped region 51. The boundary of the second doped layer 30 and the formation of the isolation trench 60 can be achieved through a single etching process. That is, the boundary of the second doped layer 30 and the isolation between the second doped layer 30 in the second doped region 51 and the first doped layer 20 can be achieved through a single etching process, simplifying the process. Furthermore, only a narrower isolation trench 60 is needed to separate the second doped layer 30 in the edge region 42 and the second doped region 51, reducing the width of the isolation trench 60 and eliminating the need for a traditional wide isolation region to isolate the first doped layer 20 and the second doped layer 30. This can increase the effective photoelectric conversion area of ​​the battery, reduce the dead area, and improve the photoelectric conversion efficiency.

[0027] The solar cell of this invention includes a silicon substrate 10, a first doped layer 20, and a second doped layer 30. The first surface of the silicon substrate 10 includes multiple first regions 40 and multiple second regions 50. Each second region 50 includes an isolation trench 60 and a second doped region 51. Each first region includes a central region 41 and an edge region 42. The edge region 42 is located on the side of the central region 41 adjacent to the isolation trench 60. The first doped layer 20 is located in the central region 41, and the second doped layer 20 is located in the second doped region 51 and the edge region 42. This invention simplifies the process by achieving the demarcation of the second doped layer 30 and the isolation between the second doped layer 30 and the first doped layer 20 in the second doped region 51 through a single etching process. Furthermore, only a narrower isolation trench 60 is needed to separate the second doped layer 30 in the edge region 42 and the second doped region 51, reducing the width of the isolation trench 60 and eliminating the need for a traditional wide isolation region to isolate the first doped layer 20 and the second doped layer 30. This increases the effective photoelectric conversion area of ​​the cell, reduces the dead zone area, and improves the photoelectric conversion efficiency.

[0028] Figure 2 This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention, with reference to... Figure 1As shown in Figure 2, optionally, the second doped layer 30 of the edge region 42 includes a first sub-part 31 and a second sub-part 32. The first sub-part 31 is disposed on the side of the second sub-part 32 adjacent to the first doped layer 20. The thickness of the first sub-part 31 is greater than the thickness of the second sub-part 32, and the distance between the surface of the first sub-part 31 away from the silicon substrate 10 and the silicon substrate 10 is greater than the distance between the surface of the first doped layer 20 away from the silicon substrate 10 and the silicon substrate 10. Figure 1 Alternatively, the surface of the second doped layer 30 in the edge region 42 away from the silicon substrate 10 is planar. Figure 2 ).

[0029] For details, please refer to Figure 1 First, a first doped layer 20 can be formed in the central region 41 of the silicon substrate 10. During the formation of the first doped layer 20, a mask layer (silicon dioxide layer) is formed on the surface of the first doped layer 20. Then, a silicon material layer is formed over the entire surface, covering the mask layer on the surface of the first doped layer 20, as well as the second region 50 and the edge region 42 of the silicon substrate 10. The silicon material layer is then doped and annealed to form a second doped layer 30. The second doped layer 30 on the surface of the first doped layer 20 is then removed. Since the second doped layer 30 extends from the edge region 42 to the surface of the first doped layer 20, the portion of the second doped layer 30 adjacent to the first doped layer 20 is thicker after removal, i.e., the first sub-section 31 is thicker. When removing the second doped layer 40 on the surface of the first doped layer 20, an isolation trench 60 is simultaneously etched, eliminating the need for a separate mask for forming the isolation trench 60 and the need for a separate etching process, thus reducing the number of process steps.

[0030] refer to Figure 2 Alternatively, an entire surface of intrinsic amorphous silicon can be formed on the first surface of the silicon substrate 10. Then, the intrinsic amorphous silicon is partitioned, doped, and annealed to form a first doped layer 20 and a second doped layer 30. The second doped layer 30 and the silicon substrate 10 are then etched to form an isolation trench 60. In this case, the surface of the second doped layer 30 in the edge region 42 away from the silicon substrate 10 is planar. Furthermore, when forming the second doped layer 30, a mask is simultaneously formed on its surface. By etching this mask, the location where the isolation trench 60 needs to be formed is exposed. The isolation trench 60 is formed by etching the exposed second doped layer 30 and the silicon substrate 10, eliminating the need to separately prepare a mask for forming the isolation trench 60, thus reducing process steps.

[0031] Figure 3 This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention, with reference to... Figure 3Optionally, the first sub-part 31 extends to the surface of the first doped layer 20 away from the silicon substrate 10, and a tunneling layer 70 and a dielectric layer 101 are disposed between the first doped layer 20 and the first sub-part 31, with the dielectric layer 101 disposed on the side of the tunneling layer 70 adjacent to the first doped layer 20.

[0032] and Figure 1 The formation process is similar. After the second doped layer 30 is formed, it extends from the edge region 42 to the surface of the first doped layer 20. When the second doped layer 30 on the surface of the first doped layer 20 is removed, a portion of the second doped layer 30 located on the surface of the first doped layer 20 is retained, thus forming the structure. Figure 3 The structure shown reduces the precision requirements of the etching process and lowers the process difficulty. The dielectric layer 101 is the silicon dioxide layer formed when the first doped layer 20 is formed, and the tunneling layer 70 extends from between the second doped layer 30 and the silicon substrate 10 to the surface of the dielectric layer 101.

[0033] It should be noted that, Figure 1 and Figure 2 The tunneling layers are shown in the diagram and are not intended to limit the scope of the invention. A tunneling layer is also included between the first doped layer 20 and the silicon substrate 10, and a tunneling layer is also included between the second doped layer 30 and the silicon substrate 10.

[0034] Optionally, the distance between the edge region 42 of the first surface and the second surface 102 of the silicon substrate 10 is less than the distance between the central region 41 of the first surface and the second surface 102 of the silicon substrate 10, wherein the second surface 102 is disposed opposite to the first surface. That is, the edge region 42 is lower than the central region 41.

[0035] Specifically, when forming the first doped layer 20, a whole silicon material layer is first formed on the surface of the silicon substrate 10, and then the silicon material layer is doped and annealed to form the first doped layer 20. Then the first doped layer 20 of the second region 50 and the edge region 42 is removed. During the removal process, the silicon substrate 10 is cleaned so that the edge region 42 and the second region 50 are cleaned away to a certain thickness, so that the edge region 42 and the second region 50 are lower than the central region 41.

[0036] Continue to refer to Figure 1 Optionally, along the first direction X, the width L of the second doped layer 30 of the edge region 42 is 1μm-2μm.

[0037] Specifically, if the width L of the second doped layer 30 in the edge region 42 is too small along the first direction X, the positional requirements for the isolation trench 60 are too stringent, and the process requirements for etching the isolation trench 60 are also too demanding. If the width L of the second doped layer in the edge region 42 is too large along the first direction X, the edge region 42 occupies too much space, affecting the space available for the second doped layer 30 on the first doped layer 20 and the second region 50. By setting the width L of the second doped layer in the edge region 42 to 1μm-2μm, the process difficulty can be reduced, and the space occupied by the edge region 42 can be kept small, thereby improving the space utilization of the solar cell and increasing the photoelectric conversion efficiency of the solar cell. Optionally, the size of the isolation trench 60 along the first direction X can range from 50μm to 150μm.

[0038] Specifically, if the size of the isolation trench 60 along the first direction X is too small, it cannot effectively isolate the first region 40 and the second doped region 51. If the size of the isolation trench 60 along the first direction X is too large, it occupies too much space, affecting the effective photoelectric conversion area of ​​the solar cell. In this embodiment, by setting the size of the isolation trench 60 along the first direction X to a range of 50μm-150μm, it can ensure better isolation of the first region 40 and the second region 50, while increasing the effective photoelectric conversion area of ​​the solar cell, reducing the dead zone area, and improving the photoelectric conversion efficiency. For example, the size of the isolation trench 60 along the first direction X can be 60μm, 70μm, or 80μm, etc.

[0039] Figure 4 This is a schematic diagram of another solar cell structure provided in an embodiment of the present invention, with reference to... Figure 4 Optionally, the first doped layer 20 includes an edge portion 21, which is disposed adjacent to the second doped layer 30. The edge portion 21 includes a first doping element and a second doping element. The first doping element is the element doped in the first doped layer 20, and the second doping element is the element doped in the second doped layer 30.

[0040] Specifically, since the concentration of the second dopant element in the second doped layer 30 is greater than that in the first doped layer 20, the second dopant element diffuses into the first doped layer 20, resulting in an edge portion 21 adjacent to the second doped layer 20. This edge portion 21 forms a depletion region with the first doped layer 20, which can passivate the first doped layer 20 and reduce carrier recombination. Simultaneously, the presence of the edge portion 21 increases the optical path length of light propagating within the first doped layer 20, increasing the probability of light being reflected or refracted back into the silicon substrate 10 and improving light absorption.

[0041] Optionally, the doping concentration of the second doped element in the edge portion 21 is greater than or equal to 10. 17 atoms / cm 3 And less than or equal to 5 × 10 20atoms / cm 3 ; The width of the edge portion 21 along the first direction X is 50 nm-1 μm; The doping concentration of the second doped element in the second doped layer 30 is greater than or equal to 10. 17 atoms / cm 3 and less than or equal to 10 21 atoms / cm 3 ; The doping concentration of the first doped element in the first doped layer 20 is greater than or equal to 2 × 10⁻⁶. 16 atoms / cm 3 And less than or equal to 2×10 19 atoms / cm 3 ; The first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer.

[0042] Specifically, along the first direction X, the width of the edge portion 21 can be 60nm, 70nm, 80nm, 100nm, 200nm, 500nm, or 800nm, etc. The doping concentration of the second doped element in the second doped layer 30 can be 10. 17 atoms / cm 3 10 18 atoms / cm 3 10 19 atoms / cm 3 Or 10 20 atoms / cm 3 The doping concentration of the first doped element in the first doped layer 20 can be 10. 16 atoms / cm 3 10 17 atoms / cm 3 10 18 atoms / cm 3 Or 10 19 atoms / cm 3 wait.

[0043] Specifically, if the first doped layer 20 is a P-type doped layer, then the first doping element can be boron; if the second doped layer 30 is an N-type doped layer, then the second doping element can be phosphorus.

[0044] Figure 5 This is a schematic diagram of another type of solar cell provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, the solar cell may also include: a tunneling layer 70, a passivation layer 80, and an antireflection layer 90; The tunneling layer 70 is disposed between the first doped layer 20 and the silicon substrate 10, and between the second doped layer 30 and the silicon substrate 10; The passivation layer 80 is disposed on the side of the first doped layer 20 and the second doped layer 30 away from the silicon substrate 10; The antireflection layer 90 is disposed on the side of the passivation layer 80 away from the silicon substrate 10.

[0045] Specifically, the tunneling layer 70 allows electrons or holes to tunnel across multiple interfaces, achieving efficient charge transport. The passivation layer 80 reduces the recombination rate of charge carriers on the solar cell surface, minimizing charge loss and protecting the stability of the first doped layer 20 and the second doped layer 30. The passivation layer 80 can be a film layer with passivation properties, such as an alumina layer. The antireflection layer 90 reduces sunlight reflection, allowing more sunlight to be absorbed inside the back-contact solar cell. The antireflection layer 90 can be a film layer such as a silicon nitride layer.

[0046] This invention provides a battery assembly, which includes a solar cell in any embodiment.

[0047] A battery module may include multiple solar cells, which can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current output. For example, the connection between individual cells can be achieved by welding ribbons, or the connection between battery strings can be achieved by busbars.

[0048] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film can be filled between the light-facing side of the solar cell and the photovoltaic glass, the back-facing side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance; for example, EVA film or POE film can be used, and the choice is based on the specific circumstances and is not limited here. The photovoltaic glass can cover the encapsulating film on the light-facing side of the solar cell. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, the light transmittance of ultra-clear glass can reach over 92%, which can protect the solar cell while minimizing the impact on its efficiency. Simultaneously, the encapsulating film can bond the photovoltaic glass and the solar cell together, and its presence provides sealing, insulation, waterproofing, and moisture protection for the solar cell.

[0049] The backsheet can be attached to the encapsulating film on the back side of the solar cell. The backsheet protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite encapsulating film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell, encapsulating film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0050] The battery module of this invention belongs to the same inventive concept as the solar cell described in the above embodiments of this invention and has corresponding beneficial effects. For technical details not detailed in this embodiment, please refer to the solar cell described in any embodiment of this invention.

[0051] This invention provides a photovoltaic system, which includes the battery module described in the above embodiments.

[0052] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0053] This invention provides a method for preparing a solar cell. Figure 6 This is a flowchart illustrating a method for fabricating a solar cell according to an embodiment of the present invention. (Refer to...) Figure 1 and Figure 6 The methods for preparing solar cells include: S101 provides a silicon substrate.

[0054] The silicon substrate has a front side and a back side. The front side is the side of the solar cell that receives light when it is working, and the back side is the side that is not illuminated when the solar cell is working. The silicon substrate can be a monocrystalline silicon wafer or a polycrystalline silicon wafer, and it can be a P-type silicon wafer or an N-type silicon wafer. The specific type is not limited here.

[0055] S102. A first doped layer 20 and a second doped layer 30 are formed on the first surface of a silicon substrate 10; wherein, the first surface of the silicon substrate includes a plurality of first regions 40 and a plurality of second regions 50; the first regions 40 and the second regions 50 are arranged alternately along a first direction X, and the second region 50 includes an isolation trench 60 and a second doped region 51; the first region 40 includes a central region 41 and an edge region 42, the edge region 42 is disposed on the side of the central region 41 adjacent to the isolation trench 60, the first doped layer 20 is disposed in the central region 41, and the second doped layer 20 is disposed in the second doped region 51 and the edge region 42; wherein, the doping types of the first doped layer 20 and the second doped layer 30 are opposite.

[0056] The method for fabricating a solar cell according to this invention first provides a silicon substrate, and then forms a first doped layer 20 and a second doped layer 30 on the first surface of the silicon substrate 10. The first doped layer 20 is disposed in the central region 41, and the second doped layer 30 is disposed in the second doped region 51 and the edge region 42. This invention simplifies the process by achieving the demarcation of the second doped layer 30 and the isolation between the second doped layer 30 and the first doped layer 20 in the second doped region 51 through a single etching process. Furthermore, only a narrower isolation trench 60 is needed to separate the second doped layer 30 in the edge region 42 and the second doped region 51, reducing the width of the isolation trench 60 and eliminating the need for a traditional wide isolation region to isolate the first doped layer 20 and the second doped layer 30. This increases the effective photoelectric conversion area of ​​the cell, reduces the dead zone area, and improves the photoelectric conversion efficiency.

[0057] Figure 7 This is a flowchart of another method for preparing a solar cell according to an embodiment of the present invention. Figures 8-13 This is a schematic diagram of the steps in a method for preparing solar energy according to an embodiment of the present invention. (Refer to...) Figures 5-12 This embodiment refines step S102, which involves forming a first doped layer, a second doped layer, and an isolation trench on the first surface of a silicon substrate. The refined method for fabricating a solar cell includes: S10 provides a silicon substrate 10.

[0058] S11. A first doped layer 20 and a first mask layer 100 are formed in a first region 40 and a second region 50 on the first surface of the silicon substrate 10, wherein the first mask layer 100 is disposed on the side of the first doped layer 20 away from the silicon substrate 10.

[0059] Specifically, Figure 8 For a schematic diagram of setting the first doped layer and the first mask layer, refer to... Figure 1 and Figure 8First, a first silicon material layer can be formed on a silicon substrate 10. The first silicon material layer is then doped and annealed to form a full-layer first doped layer 20 and a first mask layer 100. The first mask layer 100 can be a silicon oxide layer. For example, when the first doped layer 20 is a P-type doped layer, the first mask layer 100 is a BSG layer.

[0060] S12, Remove the first doped layer 20 and the first mask layer 100 from the non-central region 41 to expose the silicon substrate 10.

[0061] Specifically, Figure 9 For a schematic diagram of the first doped layer and mask layer without the central region, refer to... Figure 9 The first doped layer 20 and the first mask layer 100 outside the central region 41 are removed to form the first doped layer 20 and the first mask layer 100 located in the central region 41, and the silicon substrate 10 is cleaned so that the area of ​​the first surface other than the central region 41 is lower than the central region 41.

[0062] S13. A second silicon material layer 110 is formed on the surface of the first mask layer 100, the edge region 42, and the second region 50.

[0063] Specifically, Figure 10 A schematic diagram of the second silicon material layer is shown below. Figure 10 The second silicon material layer 110 can be an amorphous silicon layer or a microcrystalline silicon layer, etc., which can form a polycrystalline silicon film.

[0064] S14. Annealing and doping the second silicon material layer 110 to form the second doped layer 30 and the second mask layer 120.

[0065] Specifically, Figure 11 For a schematic diagram of the formation of the second doped layer and the second mask layer, refer to Figure 10 and Figure 11 The second silicon material layer 110 is annealed and doped to form a second doped layer 30 and a second mask layer 120. The second mask layer 120 is a silicon oxide layer; for example, when the second doped layer 30 is an N-type doped layer, the second mask layer 120 is a PSG layer. The annealing process can be a high-temperature oxidation process.

[0066] S15. Remove a portion of the second mask layer 120 in the second region 50 and at least a portion of the second mask layer 120 in the central region 41.

[0067] Specifically, Figure 12 A schematic diagram showing the removal of part of the second mask layer, see reference. Figure 12 A laser etching process is used to remove part of the second mask layer 120 in the second region 50 and the second mask layer 120 in the central region 41.

[0068] S16, etching the second doped layer 20 exposed in the central region 41 and the second doped layer 20 and silicon substrate 10 exposed in the second region 50 to form an isolation trench 60.

[0069] Specifically, Figure 13 For a schematic diagram of the isolation trench, refer to Figure 13 The exposed second doped layer 20 and silicon substrate 10 can be etched using a wet etching process to form an isolation trench 60. When forming the isolation trench 60, etching is performed directly on the flat surface of the second doped layer 30, which facilitates control of the etching depth and time, reducing the complexity of the process. The wet etching solution can be a solution of acid / alkali solutions and additives. Furthermore, the formation of the isolation trench 60 and the demarcation of the second doped layer 30 are completed in the same process, simplifying the process.

[0070] It should be noted that when all the second mask layers 120 in the central region 41 are removed, the following is formed: Figure 1 The structure shown, when a portion of the second mask layer 120 in the central region 41 is removed, forms Figure 3 The structure shown. Figure 3 The intermediate dielectric layer 101 is the remaining second mask layer 120 in the central region 41.

[0071] S17. Remove the first mask layer 100 and the second mask layer 120.

[0072] For details, please refer to Figure 1 The first mask layer 100 and the second mask layer 120 are removed using laser etching. After removing the first mask layer 100 and the second mask layer 120, texturing is performed on the front side of the solar cell, and a pyramid structure is fabricated in the trenches. Multiple films are deposited on the front or back side of the solar cell using atomic layer deposition (ALD) to form a passivation layer with a thickness of 10nm-50nm. Then, multiple films are deposited on the front or back side of the solar cell using plasma-enhanced chemical vapor deposition (PECVD) to form an anti-reflection layer. Finally, grid lines are printed on the back side of the solar cell and sintered to form the finished solar cell.

[0073] The deposition of multiple films on the front side of the solar cell includes: pretreating the front side of the cell with NH3, depositing a first SiNx film with a thickness of 12 nm and a refractive index of 2.15; depositing a second SiNx film with a thickness of 11 nm and a refractive index of 2.07; depositing a third SiNx film with a thickness of 11 nm and a refractive index of 2.01; depositing a fourth SiNx film with a thickness of 11 nm and a refractive index of 1.97; depositing a SiNxOy film with a thickness of 40 nm and a refractive index of 1.79; and depositing a SiOx film with a thickness of 39 nm and a refractive index of 1.53.

[0074] The back of the solar cell is deposited with multiple films including: a first SiNx film with a thickness of 25 nm and a refractive index of 2.07; a second SiNx film with a thickness of 90 nm and a refractive index of 2.04; a first SiNxOy film with a thickness of 3 nm and a refractive index of 1.85; a second SiNxOy film with a thickness of 2 nm and a refractive index of 1.79; and a SiOx film with a thickness of 55 nm and a refractive index of 1.51.

[0075] Figure 14 This is a flowchart illustrating another method for fabricating a solar cell according to an embodiment of the present invention. Figures 15-22 This is a schematic diagram of another method for preparing solar energy provided in an embodiment of the present invention, referred to... Figure 6 ,as well as Figures 14-22 This embodiment further refines step S102, which involves forming a first doped layer and a second doped layer on the first surface of a silicon substrate. The refined method for fabricating a solar cell includes: S20 provides a silicon substrate.

[0076] S21. An intrinsic amorphous silicon layer 130 is formed in a first region 40 and a second region on the first surface of the silicon substrate 10.

[0077] Specifically, Figure 15 A schematic diagram of the intrinsic amorphous silicon layer is shown below. Figure 14 The intrinsic amorphous silicon layer 130 is a film layer that can form polycrystalline silicon.

[0078] S22. A barrier layer 140 is provided on the side of the intrinsic amorphous silicon layer 130 away from the silicon substrate, and the barrier layer covers the intrinsic amorphous silicon layer 130.

[0079] Specifically, Figure 16 For a schematic diagram of the barrier layer setup, please refer to... Figure 15 The barrier layer 140 can be a silicon dioxide layer.

[0080] S23, Remove the blocking layer 140 from the central area 41.

[0081] Specifically, Figure 17 For a schematic diagram of removing the central blocking layer, refer to... Figure 17 The barrier layer 140 of the central region 41 can be removed by laser etching, exposing the intrinsic amorphous silicon layer 130 of the central region 41.

[0082] S24. The intrinsic amorphous silicon layer 130 in the central region 41 is doped and annealed to form a first doped layer 20 and a first mask layer 100. The first mask layer 100 is disposed on the side of the first doped layer 20 away from the silicon substrate 10.

[0083] Specifically, Figure 18 This is another schematic diagram of forming the first doped layer and the first mask layer, see reference. Figure 18 The intrinsic amorphous silicon layer 130 in the central region 41 is doped with boron to form a first doped layer 20, which can be a P-type doped layer. The intrinsic amorphous silicon layer 130 in the central region 41 is annealed to form a first mask layer 100, which can be a BSG layer.

[0084] S25, Remove the blocking layer 140 from the edge area 42 and the second area 50.

[0085] Specifically, Figure 19 For a schematic diagram of removing the blocking layer in the edge area and the second region, refer to... Figure 18 The remaining barrier layer 140 is removed using a laser etching process.

[0086] S26. The intrinsic amorphous silicon layer 130 of the edge region 42 and the second region 50 is doped and annealed to form a second doped layer 30 and a second mask layer 120. The second mask layer 120 is disposed on the side of the second doped layer 20 away from the silicon substrate 10.

[0087] Specifically, Figure 20 This is a schematic diagram of another method for forming a second doped layer and a second mask layer, see reference. Figure 20 The remaining intrinsic amorphous silicon layer 130 is doped with phosphorus to form a second doped layer 30, which can be an N-type doped layer. The remaining intrinsic amorphous silicon layer 130 is then annealed to form a second mask layer 120, which can be a PSG layer.

[0088] S27. Remove part of the second mask layer 120 in the second region 50.

[0089] Specifically, Figure 21 A schematic diagram showing the removal of a portion of the second mask layer in the second region, refer to... Figure 21 A portion of the second mask layer 120 in the second region 50 can be removed using a laser etching process.

[0090] S28. Etch the second doped layer 30 and silicon substrate 10 exposed in the second region to form an isolation trench 60.

[0091] Specifically, Figure 22 This is another schematic diagram of forming an isolation trench, see reference. Figure 22A wet etching process is used to remove the exposed second doped layer 30 and silicon substrate 10 to form an isolation trench 60. When forming the isolation trench 60, etching is performed directly on the flat surface of the second doped layer 30, which facilitates control of the etching depth and etching time, reducing the complexity of the process. The wet etching solution can be a solution of acid / alkali solution and additives. The second mask layer 120 formed during the formation of the second doped layer 30 directly serves as the mask for forming the isolation trench 60, eliminating the need for an additional mask and simplifying the process.

[0092] S29. Remove the first mask layer 100 and the second mask layer 120.

[0093] For details, please refer to Figure 2 The first mask layer 100 and the second mask layer 120 are removed by a wet etching process. The wet etching solution can be an acid-base solution with additives.

[0094] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A solar cell, characterized in that, include: Silicon substrate, first doped layer, and second doped layer; The first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions; the first regions and the second regions are arranged alternately along a first direction, and the second regions include isolation trenches and second doped regions. The first region includes a central region and an edge region. The edge region is located on the side of the central region adjacent to the isolation trench. The first doped layer is located in the central region, and the second doped layer is located in the second doped region and the edge region. The doping types of the first doped layer and the second doped layer are opposite.

2. The solar cell according to claim 1, characterized in that: The second doped layer in the edge region includes a first sub-part and a second sub-part. The first sub-part is disposed on the side of the second sub-part adjacent to the first doped layer. The thickness of the first sub-part is greater than the thickness of the second sub-part, and the distance between the surface of the first sub-part away from the silicon substrate and the silicon substrate is greater than the distance between the surface of the first doped layer away from the silicon substrate and the silicon substrate; or, the surface of the second doped layer in the edge region away from the silicon substrate is planar.

3. The solar cell according to claim 2, characterized in that: The first sub-part extends to the surface of the first doped layer away from the silicon substrate, and a tunneling layer and a dielectric layer are disposed between the first doped layer and the first sub-part, wherein the dielectric layer is disposed on the side of the tunneling layer adjacent to the first doped layer.

4. The solar cell according to claim 1, characterized in that: The distance between the edge region of the first surface and the second surface of the silicon substrate is less than the distance between the central region of the first surface and the second surface of the silicon substrate, wherein the second surface is disposed opposite to the first surface.

5. The solar cell according to claim 1, characterized in that: Along the first direction, the width of the second doped layer in the edge region is 1 μm-2 μm.

6. The solar cell according to claim 1, characterized in that: The size of the isolation groove along the first direction ranges from 50μm to 150μm.

7. The solar cell according to claim 1, characterized in that: The first doped layer includes an edge portion, which is disposed adjacent to the second doped layer. The edge portion includes a first doping element and a second doping element. The first doping element is an element doped in the first doped layer, and the second doping element is an element doped in the second doped layer.

8. The solar cell according to claim 7, characterized in that: The doping concentration of the second doping element in the edge portion is greater than or equal to 10 17 atoms / cm 3 , and less than or equal to 5×10 20 atoms / cm 3 ; The width of the edge portion along the first direction is 50nm-1μm; The doping concentration of the second doping element in the second doping layer is greater than or equal to 10 17 atoms / cm 3 , and less than or equal to 10 21 atoms / cm 3 ; The doping concentration of the first doped element in the first doped layer is greater than or equal to 2 × 10⁻⁶. 16 atoms / cm 3 And less than or equal to 2×10 19 atoms / cm 3 ; The first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer.

9. The solar cell according to claim 1, characterized in that, Also includes: Tunneling layer, passivation layer, and antireflection layer; The tunneling layer is disposed between the first doped layer and the silicon substrate, and between the second doped layer and the silicon substrate; The passivation layer is disposed on the side of the first doped layer and the second doped layer away from the silicon substrate; The antireflection layer is disposed on the side of the passivation layer away from the silicon substrate.

10. A battery assembly, characterized in that, Includes the solar cell described in any one of claims 1-9.

11. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 10.

12. A method for preparing a solar cell, characterized in that, include: Provide silicon substrate; A first doped layer and a second doped layer are formed on a first surface of a silicon substrate; wherein the first surface of the silicon substrate includes a plurality of first regions and a plurality of second regions; the first regions and the second regions are arranged alternately along a first direction, and the second regions include isolation trenches and second doped regions; the first regions include a central region and an edge region, the edge region is disposed on the side of the central region adjacent to the isolation trench, the first doped layer is disposed in the central region, and the second doped layer is disposed in the second doped region and the edge region; wherein the doping types of the first doped layer and the second doped layer are opposite.

13. The method for preparing a solar cell according to claim 12, characterized in that, A first doped layer and a second doped layer are formed on a first surface of a silicon substrate, including: S11. A first doped layer and a first mask layer are formed in a first region and a second region on the first surface of the silicon substrate, wherein the first mask layer is disposed on the side of the first doped layer away from the silicon substrate. S12. Remove the first doped layer and the first mask layer except for the central region to expose the silicon substrate; S13. A second silicon material layer is formed on the surface of the first mask layer, the edge region, and the second region; S14. Anneal and doping the second silicon material layer to form a second doped layer and a second mask layer; S15. Remove a portion of the second mask layer in the second region and at least a portion of the second mask layer in the central region; S16. Etch the second doped layer exposed in the central region and the second doped layer and silicon substrate exposed in the second region to form an isolation trench; S17. Remove the first mask layer and the second mask layer.

14. The method for preparing a solar cell according to claim 12, characterized in that, A first doped layer and a second doped layer are formed on a first surface of a silicon substrate, including: S21. An intrinsic amorphous silicon layer is formed in the first region and the second region of the first surface of the silicon substrate; S22. A barrier layer is provided on the side of the intrinsic amorphous silicon layer away from the silicon substrate, and the barrier layer covers the intrinsic amorphous silicon layer; S23. Remove the blocking layer in the central region; S24. The intrinsic amorphous silicon layer in the central region is doped and annealed to form a first doped layer and a first mask layer, wherein the first mask layer is disposed on the side of the first doped layer away from the silicon substrate. S25. Remove the blocking layer from the edge area and the second region; S26. The intrinsic amorphous silicon layer of the edge region and the second region is doped and annealed to form a second doped layer and a second mask layer, wherein the second mask layer is disposed on the side of the second doped layer away from the silicon substrate. S27. Remove part of the second mask layer in the second region; S28. Etch the second doped layer and the silicon substrate exposed in the second region to form an isolation trench; S29. Remove the first mask layer and the second mask layer.

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