Pixel structure and method of forming the same

Abstract

A pixel structure and a method for forming the same are provided. The pixel structure includes a semiconductor substrate, a trench isolator, a semiconductor layer, and a doped region. The trench isolator is disposed in the semiconductor substrate. The semiconductor layer is disposed in the semiconductor substrate and surrounded by the trench isolator. The semiconductor layer has a first conductivity type, and a photodiode is formed in the semiconductor layer. The doped region is disposed between the trench isolator and the semiconductor layer and has a second conductivity type opposite to the first conductivity type. The doped region extends between a first surface of the semiconductor substrate and a second surface opposite to the first surface, and the width of the doped region decreases as the doped region gets closer to the first surface. The pixel structure can optimize full-well capacity and charge transfer efficiency.

Description

Technical Field

[0001] This invention relates to a pixel structure of an image sensor and a method for forming the same. Background Technology

[0002] To meet the need for increased resolution of image sensors mounted on mobile devices, the area of ​​photodiodes can be reduced to increase the number of pixels.

[0003] Back-illuminated photodiodes must transfer the charge generated by photoelectric conversion from the rear surface side (e.g., the illumination side) to the front surface side (e.g., the non-illumination side) of the photodiode so that the transistor formed on the front surface side can read out the charge. One known method is to facilitate the movement of the generated charge by creating a gradient in the impurity concentration (e.g., n-type impurities) of the photodiode in the depth direction.

[0004] However, to form a photodiode with a gradient impurity concentration from the front surface to the back surface, the impurity doping process must be performed multiple times with different doses and implantation energies. Under deep doping conditions near the back surface, the doped region also extends laterally. This makes it difficult to generate the optimal concentration gradient for charge movement, especially for photodiodes with small areas. Furthermore, the extended doping process time can lead to increased lead times and reduced throughput. Summary of the Invention

[0005] In some embodiments, the image sensor includes a pixel array having a pixel structure that provides full deep trench isolation between adjacent pixel / pixel units within a semiconductor material (e.g., a semiconductor substrate, a wafer, an epitaxial layer).

[0006] In some embodiments of the present invention, the pixel structure includes a semiconductor substrate, a trench isolator, a semiconductor layer, and a doped region. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The trench isolator is disposed in the semiconductor substrate. The semiconductor layer is disposed in the semiconductor substrate and surrounded by the trench isolator, wherein the semiconductor layer has a first conductivity type and a photodiode is formed in the semiconductor layer. The doped region is disposed between the trench isolator and the semiconductor layer, the doped region having a second conductivity type opposite to the first conductivity type, wherein the doped region extends between the first and second surfaces, and the width of the doped region decreases as the doped region gets closer to the first surface.

[0007] In one embodiment, the doped region includes a first portion and a second portion. The first portion of the doped region extends along a first direction from a first surface to a first depth relative to the first surface, and the first portion has a first width in a second direction substantially perpendicular to the first direction. The second portion is disposed between the first portion and the second surface, and the second portion has a second width in the second direction, wherein the first width is smaller than the second width.

[0008] In one embodiment, the first portion has a first width that is substantially constant from a first surface to a first depth, and the second portion has a second width that is substantially constant from the first depth to a second surface.

[0009] In one embodiment, the semiconductor layer includes a first region and a second region. The first region of the semiconductor layer is surrounded by a first portion of a doped region, and the first region of the semiconductor layer has a first region impurity concentration of a first conductivity type. The second region of the semiconductor layer is surrounded by a second portion of a doped region, and the second region of the semiconductor layer has a second region impurity concentration of a first conductivity type, wherein the second region impurity concentration of the second region is lower than the first region impurity concentration of the first region.

[0010] In one embodiment, a first portion of the doped region has a first impurity concentration of a second conductivity type, a second portion of the doped region has a second impurity concentration of a second conductivity type, and the first impurity concentration of the first portion is less than the second impurity concentration of the second portion.

[0011] In some embodiments, a second portion of the doped region is in direct contact with a first portion of the doped region. The second portion may extend perpendicularly from the first portion of the doped region toward a second surface of the semiconductor layer. In the same or different embodiments, a second portion of the semiconductor layer is in direct contact with a first portion of the semiconductor layer.

[0012] In one embodiment, the doped region further includes at least one third portion between the first portion and the second portion of the doped region. The at least one third portion of the doped region has a third width in a second direction, wherein the third width may be within a range between the first width and the second width.

[0013] In the same or different embodiments, the first portion of the doped region has a first impurity concentration of the second conductivity type, the second portion of the doped region has a second impurity concentration of the second conductivity type, and the third portion of the doped region has a third impurity concentration of the second conductivity type, and each of the first impurity concentration, the second impurity concentration, and the third impurity concentration is greater than the second conductivity type impurity concentration of the semiconductor layer.

[0014] In one embodiment, the concentration of the first impurity is less than the concentration of the second impurity, and the concentration of the third impurity is between the concentrations of the first and second impurities.

[0015] In one embodiment, the semiconductor layer further includes at least one third region between a first region and a second region of the semiconductor layer, the at least one third region of the semiconductor layer having a third region width in a second direction, and the third region width being between the first region width of the first region of the semiconductor layer and the second region width of the second region of the semiconductor layer.

[0016] In one embodiment, the doped region has a width inflection point at a first depth in the semiconductor layer.

[0017] In one embodiment, the semiconductor layer has a stepped boundary at the interface with the doped region.

[0018] In one embodiment, the surfaces of the doped region, the trench isolation element, and the semiconductor layer are substantially coplanar.

[0019] In one embodiment, the doped region is in direct contact with the trench isolation element and the semiconductor layer.

[0020] In one embodiment, the pixel structure further includes a transfer gate and a floating diffusion region. The transfer gate is disposed near a first surface of the semiconductor layer. The floating diffusion region is disposed in the semiconductor substrate and adjacent to the first surface, wherein the transfer gate couples a photodiode to the floating diffusion region.

[0021] In one embodiment, the doped region has a vertical thickness relative to the trench depth of the first surface and the trench separator.

[0022] In some embodiments of the present invention, the method of forming a pixel structure includes the following steps: Forming a trench and a semiconductor layer of a first conductivity type in a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to the first surface, and the semiconductor layer is surrounded by the trench. Forming a doped region adjacent to the trench in the semiconductor layer, wherein the doped region is of a second conductivity type opposite to the first conductivity type and is configured to extend from a first depth to the second surface. Diffusion of a first impurity of the second conductivity type into the semiconductor layer between the doped region and the first surface and into the doped region to form a first doped region between the first surface and the first depth and a second doped region between the first depth and the second surface. Forming a trench separator in the trench.

[0023] In one embodiment, forming a doped region in a semiconductor layer includes the following steps: forming a barrier layer adjacent to a first trench portion of a trench to line the sidewalls of the first trench between a first surface and a first depth, while a second trench portion of the trench between the first depth and a second surface does not have a barrier layer. A second impurity of a second conductivity type diffuses into the semiconductor layer through the second trench portion of the trench.

[0024] In one embodiment, diffusing a second impurity of a second conductivity type into a semiconductor layer includes the following steps: forming a second impurity of a second conductivity type at a second trench portion adjacent to the trench using a plasma doping process; and diffusing the second impurity of the second conductivity type into the semiconductor layer using an annealing process.

[0025] In one embodiment, diffusing a second impurity of a second conductivity type into a semiconductor layer includes the following steps: forming a layer comprising the second impurity of the second conductivity type, the layer being adjacent to a first trench portion and a second trench portion of a trench; and diffusing the second impurity of the second conductivity type into the semiconductor layer by an annealing process.

[0026] According to some embodiments of the invention, forming a doped region with varying width allows the semiconductor layer to have an impurity concentration gradient. In one embodiment, the doped region is p-type (also referred to as a p-type doped region) and the semiconductor layer is n-type (also referred to as an n-type semiconductor layer). In this embodiment, the p-type doped region is configured to have a varying thickness along the depth direction, which causes the n-type semiconductor layer to have a concentration gradient. The n-type semiconductor layer surrounded by the p-type doped region can be configured to have a potential gradient from a second surface (e.g., the back surface) to a first surface (e.g., the front surface) per unit pixel. Therefore, it is possible to facilitate the movement of charge (e.g., electrons) accumulated in the photodiode from photoelectric conversion in response to incident light from the second surface (e.g., the back surface) to the first surface (e.g., the front surface).

[0027] To make the foregoing more understandable, several embodiments accompanied by the accompanying drawings are described in detail below. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0029] Figure 1A This is a cross-sectional view of a pixel structure according to some embodiments of the present invention. Figure 1B This describes the different regions along a first direction from the first surface to the second surface according to some embodiments of the present invention. Figure 1A The concentration and potential of the first conductivity type impurity in the semiconductor layer of the pixel in the second direction, and Figure 1C This describes the first direction from the first surface to the second surface according to some embodiments of the present invention. Figure 1A The potential of the semiconductor layer 14 near the center of the pixel in the second direction.

[0030] Figures 2A to 2J A cross-sectional view illustrating the method for forming the pixel structure.

[0031] Figure 3This is a cross-sectional view of a pixel structure according to some embodiments of the present invention.

[0032] Figure 4 This is a cross-sectional view of a pixel structure according to some embodiments of the present invention.

[0033] Figure 5 This is a cross-sectional view of an image sensor according to some embodiments of the present invention.

[0034] Symbol Explanation: 10, 10A, 10B: Pixel; 12: Semiconductor substrate; 14: Semiconductor layer; 14-1: First region; 14-2: Second region; 14-3: Third region; 15: Photodiode; 16, 30: Doped region; 18: Front surface region / Front surface p-type region; 20: Floating diffusion region; 22: Well region / Well isolation; 24: Transfer gate; 24a: Planar gate electrode; 24b: Vertical gate electrode; 26: Trench isolation; 30-1, 30-2, 30-3: Partial; 34: Shallow trench isolation; 40: Hard mask ; 50: trench; 50L: second trench section; 50U: first trench section; 52: barrier layer; 54, 58: second conductive impurities; A: first surface; B: second surface; AF: anti-reflection layer; CF: color filter; CFL: color filter layer; D1: first direction; D2: second direction; Dp1: first depth; Dp2: second depth; Dp3: third depth; ML: microlens layer; SP: separation pattern; TN: inflection point / width conversion point; TP: dashed line; W1, W1', W2, W2', W3, W3': width.

[0035] Corresponding symbols indicate the corresponding components in several views of the accompanying drawings. Those skilled in the art will understand that the components in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some components may be exaggerated relative to others to aid in understanding the various embodiments of the invention. Furthermore, common but well-known components that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a less obstructed view of these various embodiments of the invention. Detailed Implementation

[0036] Embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, those skilled in the art will recognize that the techniques described herein can be implemented without one or more specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. It should be noted that the following embodiments do not limit the invention. Furthermore, configurations obtained by selectively combining multiple examples are also included in the invention.

[0037] In this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] The term “configured (or set) as” is used interchangeably with terms such as “suitable for,” “capable,” “designed for,” “adapted to,” “made of,” or “capable of.” The term “configured (or set) as” does not necessarily mean “specifically designed for.” In some cases, the term “device configured as” may indicate that the device can “perform” together with other devices or components. For example, the term “processor configured (or set) as performing A, B, and C” may refer to a dedicated processor (e.g., an embedded processor) for performing the corresponding operations, or a general-purpose processor (e.g., a CPU (central processing unit) or application processor) for executing at least one software or program stored in a storage device to perform the corresponding operations.

[0039] It should be understood that the terms "about" and "substantially" can refer to a given quantity or manufacturing parameter that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" can refer to the percentage of values ​​as interpreted by those skilled in the art according to the teachings of the present invention.

[0040] It should be understood that although the terms first, second, third, etc., may be used in the invention and claims to describe various components, these components should not be limited by these terms and should not be used to determine the process sequence or formation sequence of the related components. Unless otherwise indicated, these terms are used only to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of the inventive embodiments.

[0041] Spatial relative terms, such as “below,” “under,” “above,” “lower,” “upper,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc., may be used herein for descriptive convenience to describe the relationship of one component or feature to another component or feature as shown in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figures. For example, if the device in the figures is rotated or flipped, a component described as “below,” “under,” or “lower” to other components or features will be oriented as “above” to other components or features. Thus, the exemplary terms “below” and “lower” may cover the orientations of above and below. The device may be oriented in other ways (rotated ninety degrees or other orientations), and the spatial relative descriptors used herein will be interpreted accordingly. Furthermore, it should be understood that when a component is also referred to as being “between” two other components, it may be the only component between the two other components, or one or more intermediate components may also be present.

[0042] Several technical terms are used throughout this specification. These terms should be used with their usual meaning in the technical field from which they originate, unless otherwise specifically defined herein or the context in which they are used clearly suggests otherwise. Note that component names and symbols may be used interchangeably in this document (e.g., Si vs. silicon); however, both have the same meaning.

[0043] Figure 1A This is a cross-sectional view of a pixel structure according to some embodiments of the present invention. The pixel structure shown includes two pixels 10 of a pixel array of an image sensor, and the pixel array (not shown) may include multiple pixels 10 arranged in multiple columns and multiple rows. The image sensor may be a backside illumination (BSI) sensor and / or a solid-state image sensor. In some embodiments, the pixel 10 is disposed in a pixel region and formed in a semiconductor substrate 12. The pixel 10 has a first surface A and a second surface B opposite to the first surface A. In the illustrated embodiment, the first surface A is also referred to as the front surface, and the second surface B is also referred to as the rear surface or back surface opposite to the front surface. In embodiments where the image sensor is a backside illumination image sensor, the first surface may also be referred to as the non-illuminated surface, and the second surface may be referred to as the illuminated surface. Figure 1A This can be a cross-sectional view taken in a plane perpendicular to the first surface A (e.g., the front surface). The plane can be formed by a first direction D1 and a second direction D2 substantially perpendicular to the first direction D1. For example, each of the first direction D1 and the second direction D2 is substantially perpendicular to the first surface A and the second surface B. The first direction D1 can also be referred to as the depth direction or the vertical direction, and the second direction D2 can also be referred to as the lateral direction, the width direction, or the horizontal direction.

[0044] It should be understood that the semiconductor substrate 12 may be a semiconductor wafer (e.g., a silicon wafer). In some embodiments, the semiconductor substrate 12 includes silicon (e.g., single-crystal silicon), silicon-germanium alloy, germanium, silicon carbide (SiC), silicon carbide alloy, indium gallium arsenide alloy, any other alloy formed of group III-V compounds, combinations thereof, one or more epitaxial layers of the foregoing materials, or a bulk substrate thereof, or formed of the foregoing materials. More specifically, the semiconductor substrate 12 may be any semiconductor material or combination of materials that can be doped or configured to facilitate the formation of photosensitive regions of individual pixels. In some embodiments, the semiconductor substrate 12 may include or be one or more epitaxial layers (e.g., p-type or n-type doped silicon) formed on a carrier or substrate wafer (e.g., a support wafer). In such embodiments, photodiodes, floating diffusion regions, source / drain regions, or the like included in individual pixels or pixel units may be formed in or in the semiconductor substrate 12 or in the one or more epitaxial layers, and the carrier or substrate wafer (e.g., the support wafer) may be removed or thinned during manufacturing.

[0045] In the illustrated example, the semiconductor substrate 12 includes a semiconductor layer 14. The semiconductor layer 14 may be a doped region, a semiconductor layer epitaxially grown on the semiconductor substrate 12, or the like of the semiconductor substrate 12. The semiconductor layer 14 may include a first conductivity type impurity, and therefore the semiconductor layer 14 may be of the first conductivity type. The first conductivity type may be n-type, and the n-type impurity may be phosphorus (P), arsenic (As), antimony (Sb), etc. In some embodiments, the semiconductor layer 14 may be a doped region formed by performing an n-type impurity doping process on the semiconductor substrate 12. For example, the semiconductor layer 14 is a deep n-type region. In some embodiments, the semiconductor layer 14 may be a single crystal layer formed by an epitaxial growth process and an in-situ n-type impurity doping process. For example, the semiconductor layer 14 is an n-type doped epitaxial layer. The semiconductor layer 14 may also be a portion or region of a photodiode 15 and configured to generate charge (e.g., electrons) in response to incident light. In other words, the semiconductor layer 14 may be a photosensitive region of the photodiode or a portion of a photodiode region. The photodiode can be configured to receive incident light through a second surface (e.g., the rear surface or back side) B.

[0046] Pixel 10 further includes a doped region 16. The doped region 16 may be of a first conductivity type. In other words, the semiconductor layer 14 and the doped region 16 are of the same conductivity type, such as n-type. In some embodiments, the doped region 16 is formed above the semiconductor layer 14 (e.g., on the upper surface side of the semiconductor layer 14). In other words, the doped region 16 may be disposed or formed between the first surface A and the semiconductor layer 14. In some embodiments, the doped region 16 has an impurity concentration greater than that of the semiconductor layer 14 (e.g., an n-type impurity concentration).

[0047] In some embodiments, pixel 10 further includes a front surface region 18, which may be formed above semiconductor layer 14 (e.g., on the upper surface side of semiconductor layer 14). For example, the front surface region 18 may be disposed or formed between the first surface A and semiconductor layer 14. The front surface region 18 may be a second conductivity type opposite to the first conductivity type. In some embodiments, the front surface region 18 may be grounded. The second conductivity type may be p-type, and the p-type impurity may be boron (B), aluminum (Al), gallium (Ga), indium (In), etc. For example, semiconductor layer 14 and doped region 16 are n-type, while front surface region 18 is p-type. Therefore, semiconductor layer 14 and doped region 16 may also be referred to as n-type semiconductor layer 14 and p-type doped region 16, and front surface region 18 may also be referred to as front surface p-type region 18. In some embodiments, pixel 10 further includes a floating diffusion region 20. The floating diffusion region 20 may be formed or disposed in a portion of the front surface region 18. The floating diffusion region 20 may be of a first conductivity type, and may have an impurity concentration greater than that of the semiconductor layer 14. For example, the floating diffusion region 20 may have an n-type impurity concentration greater than that of the semiconductor layer 14. In some embodiments, the pixel 10 further includes a well region 22. The well region 22 may be disposed between the floating diffusion region 20 and the semiconductor layer 14. For example, the well region 22 may be disposed below the floating diffusion region 20 (e.g., on the lower surface side of the floating diffusion region 20). The well region 22 may be of a second conductivity type; in other words, the well region 22 may have a conductivity type opposite to that of the semiconductor layer 14, the doped region 16, and the floating diffusion region 20. The well region 22 may be configured to provide isolation between the floating diffusion region 20 and the photodiode. The well region 22 may also be referred to as a unit well region. In some embodiments, the doped region 16 and the well region 22 are disposed on opposite sides of the pixel 10 and at similar depths. For example, the well region 22 and the doped region 16 are deep wells, while the front surface region 18 is a shallow well. However, the invention is not limited thereto. In other words, pixel 10 can have any suitable configuration.

[0048] Pixel 10 further includes a transfer gate 24 disposed near a first surface A of semiconductor substrate 12. The transfer gate 24 is configured to selectively couple the doped region 16 to a floating diffusion region 20 upon receiving a transfer control signal (e.g., a positive bias voltage) to transfer photogenerated charge from the photodiode to the floating diffusion region 20. The transfer gate 24 may include a planar gate electrode 24a disposed near the first surface A of semiconductor substrate 12 and a vertical gate electrode 24b extending from the first surface A into semiconductor layer 14. For example, the planar gate electrode 24a and the vertical gate electrode 24b are physically connected and electrically connected. The planar gate electrode 24a may extend along a second direction D2 on the first surface A. For example, the planar gate electrode 24a extends over and covers a portion of the front surface region 18. The vertical gate electrode 24b may extend into semiconductor layer 14 at a gate depth along a first direction D1 and may be disposed between the doped region 16 and the well region 22. The bottom surface of the vertical gate electrode 24b may be higher than the bottom surfaces of the doped region 16 and the well region 22. For example, the bottom surface of the vertical gate electrode 24b is disposed between the first surface A and the bottom surfaces of the doped region 16 and the well region 22. This configuration allows the sidewall of the transfer gate 24 located between the doped region 16 and the floating diffusion region 20 to function as a channel region. Furthermore, this configuration serves as a transfer transistor, which can be turned on and off according to the bias voltage applied to the transfer gate 24. For example, the well region 22 can be configured to prevent electrons from flowing from the semiconductor layer 14 to the floating diffusion region 20 by adjusting the impurity concentration. The planar gate electrode 24a and the vertical gate electrode 24b can be electrically isolated from the substrate region of the semiconductor substrate 12 by an insulating layer (not shown) serving as the gate dielectric.

[0049] In some embodiments, trench isolators 26 are disposed or formed in semiconductor layer 14 to surround each pixel and define a corresponding photosensitive area. From a top view, trench isolators 26 are portions of an interconnected (continuous) trench isolator grid, which divides semiconductor layer 14 into multiple pixel regions (e.g., surrounding regions) corresponding to each individual pixel 10. For example, trench isolators 26 are deep trench isolation (DTI). Figure 1AAs shown, trench isolation member 26 surrounds and encloses the photosensitive area or photodiode area of ​​the photodiode of pixel 10. Trench isolation member 26 extends from a first surface A toward a second surface B. In some embodiments, trench isolation member 26 includes an insulating material, such as silicon nitride or silicon oxide, to provide isolation between adjacent pixels. Alternatively, trench isolation member 26 can be formed by forming an insulating liner on the trench surface and filling the trench with a dielectric material (e.g., an oxide-based material). In other embodiments, trench isolation member 26 can be formed by forming an insulating liner on the trench surface and filling the trench with a polycrystalline silicon material or a suitable conductive material and maintaining it at a predetermined potential. In some embodiments, semiconductor substrate 12 may be removed or thinned during manufacturing such that trench isolation member 26 extends from the first surface (e.g., the front surface) A and penetrates through semiconductor layer 14 along a first direction D1. In other words, trench isolation member 26 may have an isolation depth substantially the same as the vertical thickness of semiconductor layer 14.

[0050] In some embodiments, a doped region 30 is disposed or formed on the side of the trench isolator 26 within the pixel region. That is, the doped region 30 is disposed between the trench isolator 26 and the semiconductor layer 14. The doped region 30 may be in direct contact with the trench isolator 26 and the semiconductor layer 14. In some embodiments, the doped region 30 is disposed around the semiconductor layer 14 of the pixel 10 to separate the trench isolator 26 from the semiconductor layer 14 of the pixel 10. In some embodiments, the doped region 30 is doped with an impurity of a conductivity type opposite to that of the semiconductor layer 14. For example, the semiconductor layer 14 is of a first conductivity type, while the doped region 30 is of a second conductivity type. In some embodiments, the doped region 30 is doped with a second conductivity type impurity (e.g., p-type impurity such as boron). The doped region 30 may also be referred to as a p-type doped region or a deep p-type well. The doped region 30 is configured to have a varying width along the second direction D2. In some embodiments, the widths W1 and W2 of the doped region 30 along the second direction D2 decrease as the doped region 30 gets closer to the first surface A.

[0051] In the illustrated embodiment, the doped region 30 includes a first portion (e.g., an upper portion) 30-1 and a second portion (e.g., a lower portion) 30-2. The first portion 30-1 of the doped region 30 is disposed or formed to extend along a first direction D1 from a first surface A toward a second surface B to a first depth Dp1 relative to the first surface A, and the second portion 30-2 of the doped region 30 is disposed or formed between the first portion 30-1 and the second surface B along the first direction D1. In some embodiments, the second portion 30-2 of the doped region 30 extends from the first depth Dp1 to the second surface B, that is, the second portion 30-2 is in direct contact with the first portion 30-1 (e.g., the second portion 30-2 is directly below the first portion 30-1). In some embodiments, the first portion 30-1 and the second portion 30-2 of the doped region 30 are integrally formed. In some embodiments, the second surface B is also referred to as a second depth Dp2 relative to the first surface A. For example, the second portion 30-2 of the doped region extends from the first depth Dp1 to the second depth Dp2. In the second direction D2, the first width W1 of the first portion 30-1 is configured to be smaller than the second width W2 of the second portion 30-2. In some embodiments, the first width W1 and the second width W2 of the first portion 30-1 may also be referred to as the lateral thickness along the second direction D2 on the trench separator 26. The first portion 30-1 may have a constant or uniform width, that is, the first width W1 of the first portion 30-1 is substantially constant from the first surface A to the first depth Dp1. Similarly, the second portion 30-2 may have a constant width, that is, the second width W2 of the second portion 30-2 is substantially constant from the first depth Dp1 to the second surface B (e.g., the second depth Dp2). In some embodiments, the first depth Dp1 relative to the first surface A is approximately half the second depth Dp2 relative to the first surface A. For example, in the first direction D1, the vertical thickness of the first portion 30-1 is substantially equal to the vertical thickness of the second portion 30-2. However, the invention is not limited thereto.

[0052] In some embodiments, the trench separator 26 is disposed between adjacent doped regions 30 to separate adjacent pixels 10. Alternatively, as... Figure 1AAs shown, trench isolation member 26 is sandwiched between adjacent doped regions 30. In some embodiments, trench isolation member 26 is configured to surround the doped region 30 and the photosensitive region of the photodiode within a pixel region of pixel 10. The doped region 30 is configured to surround the semiconductor layer 14 within a pixel region and passivate the sidewall surface of trench isolation member 26 of trench isolation member mesh. Therefore, doped region 30 may also be referred to as a well isolation structure (e.g., p-well isolation structure). In some embodiments, in a first direction (e.g., depth direction) D1, the thickness (e.g., vertical thickness) of doped region 30 (i.e., the combined thickness of the first portion 30-1 and the second portion 30-2) is substantially the same as the isolation depth of trench isolation member 26. In some embodiments, the surfaces (e.g., bottom surfaces) of doped region 30, trench isolation member 26, and semiconductor layer 14 are substantially coplanar. For example, the doped region 30, trench isolation member 26, and semiconductor layer 14, as well as their surfaces (e.g., bottom surfaces), are substantially coplanar with second surface B. In some embodiments, the surfaces (e.g., the top surface) of the trench separator 26, the front surface region 18, and the floating diffusion region 20 are substantially coplanar. For example, the surfaces (e.g., the top surface) of the trench separator 26, the front surface region 18, and the floating diffusion region 20 are substantially coplanar with the first surface A.

[0053] In some embodiments, the trench isolation member 26 may be surrounded by doped regions 30 of two adjacent pixels 10. In some embodiments, the semiconductor layer 14 is surrounded by doped regions 30. In some embodiments, the widths W1', W2' of the semiconductor layer 14 along the second direction D2 increase as the semiconductor layer 14 gets closer to the first surface A. In the illustrated embodiment, the semiconductor layer 14 includes a first region 14-1 (e.g., an upper layer portion) surrounded by a first portion 30-1 of the doped regions 30 and a second region 14-2 (e.g., a lower layer portion) surrounded by a second portion 30-2 of the doped regions 30. The first region 14-1 of the semiconductor layer 14 is disposed or formed to extend along the first direction D1 from the first surface A toward the second surface B to a first depth Dp1, and the second region 14-2 of the semiconductor layer 14 is disposed or formed to extend along the first direction D1 between the first region 14-1 and the second surface B. For example, the second region 14-2 extends from a first depth Dp1 to a second surface B (e.g., a second depth Dp2), meaning the second region 14-2 contacts the first region 14-1 (e.g., the second region 14-2 is directly below the first region 14-1). The first region 14-1 of the semiconductor layer 14 may be disposed at substantially the same depth as the first portion 30-1 of the doped region relative to the first surface A. The second region 14-2 of the semiconductor layer 14 may be disposed at substantially the same depth as the second portion 30-2. In the second direction D2, the first width W1' of the first region 14-1 is configured to be greater than the second width W2' of the second region 14-2. In some embodiments, in the second direction D2, the combined lateral width of the first portion 30-1 of the doped region and the first region 14-1 of the semiconductor layer 14 is substantially equal to the combined lateral width of the second portion 30-2 of the doped region and the second region 14-2 of the semiconductor layer 14, i.e., W1 + W1' = W2 + W2'. The first region 14-1 may have a constant width, that is, the first width W1' of the first region 14-1 is substantially constant from the first surface A to the first depth Dp1. Similarly, the second region 14-2 may have a constant width, that is, the second width W2' of the second region 14-2 is substantially constant from the first depth Dp1 to the second surface B (e.g., the second depth Dp2).

[0054] The doped region 30 has an inner boundary that interfaces with the semiconductor layer 14 and an outer boundary that interfaces with the trench isolator 26, the inner boundary being formed by the interface between the doped region 30 and the semiconductor layer 14. In some embodiments, due to width differences between multiple portions of the doped region 30 (e.g., the first portion 30-1 and the second portion 30-2), the inner boundary of the doped region 30 may have a transition point TN or a width transition point TN between the multiple portions (e.g., the first portion 30-1 and the second portion 30-2), wherein the lateral width of the doped region changes at the transition point TN or the width transition point TN. Similarly, the semiconductor layer 14 also has width variations at the transition point TN between the multiple portions (e.g., the first region 14-1 and the second region 14-2). In such embodiments, the boundaries of the doped region 30 and the semiconductor layer 14 have a stepped profile; in other words, the doped region 30 and the semiconductor layer 14 have a stepped or staircase-like boundary. Alternatively, the interface between the doped region 30 and the semiconductor layer 14 has a stepped profile.

[0055] As described below, a doped region 30 can be formed by doping the semiconductor layer 14 with a second conductivity type impurity (e.g., a p-type impurity). In some embodiments, a first portion 30-1 has a first impurity concentration of the second conductivity type, a second portion 30-2 has a second impurity concentration of the second conductivity type, and each of the first and second impurity concentrations is greater than the impurity concentration of the semiconductor layer 14. In some embodiments, the second impurity concentration of the second portion 30-2 is higher than the first impurity concentration of the first portion 30-1. Therefore, in some embodiments where the doped region 30 is formed by doping the semiconductor layer 14 with a second conductivity type impurity, reverse doping causes the impurity concentration of the second region 14-2 surrounded by the second portion 30-2 to be lower than the impurity concentration of the first region 14-1 surrounded by the first portion 30-1. For example, the impurity concentration of the first conductivity type region of the second region 14-2 closer to the second surface B is lower than the impurity concentration of the first conductivity type region of the first region 14-1 disposed further away from the second surface B. In alternative embodiments, the second impurity concentration of the second portion 30-2 is substantially equal to the first impurity concentration of the first portion 30-1.

[0056] In some embodiments, a second region 14-2 of the semiconductor layer 14 (e.g., n-type impurity concentration) has a lower impurity concentration than other regions of the semiconductor layer 14, and a first region 14-1 of the semiconductor layer 14 (e.g., n-type impurity concentration) has a higher impurity concentration. In embodiments where the semiconductor layer 14 is formed by epitaxial growth, the semiconductor layer 14 is doped with n-type impurities by an in-situ doping process. In this embodiment, additional steps such as high-energy ion implantation (e.g., deep n-type impurity implantation) can be omitted. Furthermore, in some embodiments, the formation of doped regions 30 (e.g., including first and second portions 30-1 and 30-2) allows the semiconductor layer 14 to have an impurity concentration gradient (e.g., an n-type impurity concentration gradient). In other words, the formation of a doped portion (e.g., the second portion 30-2) with a larger width (e.g., width W2) allows the adjacent semiconductor layer 14 to have a relatively low n-type impurity concentration. Conversely, the formation of a doped portion (e.g., the first portion 30-1) with a smaller thickness (e.g., width W1) allows for a relatively high n-type impurity concentration in the adjacent semiconductor layer 14. For example, the first region 14-1 has a higher n-type impurity concentration than the second region 14-2. Thus, the potential of the photodiode region can be configured. In some embodiments, the width W1 of the first portion 30-1 and the width W2 of the second portion 30-2 can be configured to modulate the potential of the semiconductor layer 14 to optimize full-well capacity and charge transfer efficiency.

[0057] Figure 1B According to some embodiments of the present invention, Figure 1A The semiconductor layer of the pixel has a first conductivity type impurity concentration and potential in different regions along a first direction (e.g., a depth direction Y-Y') from the first surface to the second surface in a second direction (e.g., a lateral direction X-X'). For example, the semiconductor layer of the pixel has a first conductivity type impurity concentration and potential in different regions along a first direction (e.g., a depth direction Y-Y' from the front surface (first surface A) to the rear surface or back surface (second surface B). Figure 1B As shown, the concentration of the first conductivity type impurity (e.g., n-type impurity concentration) increases toward the first surface A (e.g., the front surface), and the potential also increases toward the first surface A (e.g., the front surface). Furthermore, the potential of the semiconductor layer 14 approaches zero as the doped region 30 approaches closer to it.

[0058] Figure 1C According to some embodiments of the present invention, Figure 1A The semiconductor layer 14 of the pixel is located near the center of the pixel in the second direction (e.g., the lateral direction X-X') at a potential on the first direction (from the first surface to the second surface (e.g., from the front surface to the rear surface or the back side depth direction Y-Y')) D1. Figure 1C Indicates a positive value. For example... Figure 1C As shown, the potential increases in the positive direction toward the first surface A (e.g., the front surface) to achieve the target full-well capacity.

[0059] In some embodiments, the concentration of a first conductivity type impurity (e.g., n-type impurity concentration) in the semiconductor layer 14 increases from the back surface toward the front surface, forming a potential gradient. Therefore, when photo-generated charges (e.g., electrons) are accumulated in the charge accumulation region formed by the semiconductor layer 14 in response to incident light, the charges (e.g., electrons) can easily move to the front surface according to the potential gradient. Figure 1A As shown by the dashed line TP, charge (e.g., electrons) is transported from semiconductor layer 14 to floating diffusion region 20 via a transfer transistor (including doped region 16 and front surface region 18). In this configuration, biasing transfer gate 24 at a high level (e.g., a positive bias voltage) causes the transfer transistor to turn on and allows charge (e.g., electrons) to be transported from doped region 16 to floating diffusion region 20. Conversely, biasing transfer gate 24 at a low level (e.g., zero or negative bias voltage) causes the transfer transistor to turn off and prevents charge (e.g., electrons) from being transported to floating diffusion region 20.

[0060] Figures 2A to 2J A cross-sectional view illustrating the method for forming the pixel structure. Figure 2J The pixel structure is similar to Figure 1A The pixel structure, therefore Figures 2A to 2J Components (e.g., floating diffusion region 20, transfer gate 24, well isolation 22, semiconductor layer 14, trench isolation 26, etc.) may include those with... Figure 1A Component-like features (e.g., composition, shape, structure, arrangement, distribution, combination, etc.) can be omitted in detail.

[0061] Reference Figure 2AA trench 50 and a semiconductor layer 14 of a first conductivity type are formed in a semiconductor substrate 12, wherein the semiconductor layer 14 is surrounded by the trench 50. In some embodiments, the semiconductor substrate 12 includes a semiconductor layer 14 formed by epitaxial growth and in-situ doping with a predetermined concentration of a first conductivity type impurity (e.g., n-type impurity). The semiconductor layer 14 is of the first conductivity type, for example, n-type. Then, a hard mask 40 and photoresist (not shown) are sequentially formed on a first surface A of the semiconductor substrate 12 (e.g., semiconductor layer 14), exposing a portion of the semiconductor layer 14 at the first surface (e.g., front surface) A. Subsequently, the portion of the semiconductor layer 14 exposed by the hard mask 40 is removed by wet etching and / or dry etching to form the trench 50 in the semiconductor layer 14. The trench 50 is an interconnected (continuous) trench that divides the semiconductor substrate 12 into multiple pixel regions, for example, for pixels. The trench 50 may have a first depth (e.g., an initial depth) Dp1 relative to the first surface A along a first direction D1, and the first depth Dp1 is less than the thickness of the semiconductor substrate 12 (e.g., semiconductor layer 14). In some embodiments, the first depth Dp1 is substantially no greater than half the total depth of the photodiode formed along the depth direction. In some embodiments, the first depth Dp1 is approximately half the total vertical depth of the photodiode formed along the depth direction.

[0062] Reference Figure 2B A barrier layer 52 is formed on the sidewalls of the trench 50. In some embodiments, the barrier layer 52 may be a liner conformally formed on the exposed surfaces of the trench 50 and the hard mask 40. For example, the barrier layer 52 is conformally formed on the bottom surface and sidewalls of the trench 50 and the top surface and sidewalls of the hard mask 40. The material of the barrier layer 52 may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. The barrier layer 52 may be formed at a suitable lateral thickness along the second direction D2 by a deposition process, coating process, or similar process. The barrier layer 52 may also be referred to as a barrier element, a barrier liner, a dopant diffusion barrier layer, or similar names.

[0063] Reference Figure 2C and Figure 2D The barrier layer 52 is partially removed. For example, portions of the barrier layer 52 on the bottom surface of the trench 50 and the top surface of the hard mask 40 are removed. The barrier layer 52 can be removed by an etching process in a first direction (e.g., the depth direction) D1. For example, the etching process is a vertical etching process. In some embodiments, during the partial removal of the barrier layer 52, portions of the semiconductor layer 14 are also removed in the first direction (e.g., the depth direction) D1. Thus, as Figure 2DAs shown, in the first direction D1, the trench 50 further extends to a second depth Dp2 relative to the first surface A of the semiconductor substrate 12 (e.g., semiconductor layer 14). The second depth Dp2 relative to the first surface A is greater than the first depth Dp1 and less than the total vertical thickness of the semiconductor substrate 12 (e.g., semiconductor layer 14). In some embodiments, the second depth Dp2 is substantially equal to the depth of the formed photodiode.

[0064] like Figure 2D As shown, the trench 50 includes a first trench portion (e.g., an upper trench portion) 50U between a first surface A and a first depth Dp1, and a second trench portion (e.g., a lower trench portion) 50L between the first depth Dp1 and the second surface B. In some embodiments, a barrier layer 52 is formed on the inner wall of the first trench portion (e.g., the upper trench portion) 50U, but not on the inner wall of the second trench portion (e.g., the lower trench portion) 50L. In other words, the second trench portion (e.g., the lower trench portion) 50L of the trench 50 does not have a barrier layer 52.

[0065] Reference Figure 2E-1 and Figure 2E-2 After the barrier layer 52 is formed, a second conductive impurity 54 is formed near the trench 50. The second conductive impurity 54 is, for example, a p-type impurity. In some embodiments, such as... Figure 2D and Figure 2E-1 As shown, the second trench portion (e.g., the lower trench portion) 50L of trench 50 without the barrier layer 52 undergoes a plasma doping process with a second conductivity type impurity (e.g., a p-type impurity such as boron). In such embodiments, a second conductivity type impurity (e.g., a p-type impurity) 54 is formed in the lower trench portion (e.g., the lower trench portion) 50L of the second trench portion (e.g., the lower trench portion) of semiconductor layer 14 adjacent to the trench 50. In alternative embodiments, such as Figure 2D and Figure 2E-2 As shown, a semiconductor layer including a second conductivity type impurity 54 is formed on the entire sidewall of trench 50. For example, by a deposition process such as solid phase deposition, a semiconductor layer including a second conductivity type impurity 54 is formed on the inner sidewall of a first trench portion (e.g., upper trench portion) 50U having a barrier layer 52 and on the inner sidewall of a second trench portion (e.g., lower trench portion) 50L without a barrier layer 52. The semiconductor layer 14 having the second conductivity type impurity 54 is also referred to as a second conductivity type doped layer (e.g., p-type doped layer) or a semiconductor layer doped with a second conductivity type impurity (e.g., a semiconductor layer doped with a p-type impurity).

[0066] Reference Figure 2FA second portion 30-2 of a second conductivity type is formed in the semiconductor layer 14 adjacent to the trench 50. For example, a second conductivity type impurity 54 (e.g., ...) is introduced through the sidewalls of the trench 50. Figure 2E-1 or Figure 2E-2 The second portion 30-2 is diffused into the semiconductor layer 14 to form the second portion 30-2. For example, the second portion 30-2 extends from the first depth Dp1 to the second surface B. The second conductivity type impurity 54 can be diffused by a process such as annealing. Therefore, the second portion 30-2 is formed in the semiconductor layer 14 adjacent to the second trench portion (e.g., the lower trench portion) 50L of the trench 50. In some embodiments, such as Figure 2E-1 and Figure 2F As shown, a second conductivity type impurity 54, doped along a second trench portion 50L (e.g., the lower trench portion) without a barrier layer 52, diffuses into the lower region (e.g., the second region 14-2) of the semiconductor layer 14 to form the second portion 30-2. In an alternative embodiment, as... Figure 2E-2 and Figure 2F As shown, a second conductivity type impurity 54 in a second trench portion (e.g., a lower trench portion) 50L adjacent to trench 50 without a blocking layer 52 diffuses into the lower portion of semiconductor layer 14 to form a second portion 30-2, while the diffusion of the second conductivity type impurity 54 adjacent to the first trench portion (e.g., an upper trench portion) 50U is blocked by the blocking layer 52. In some embodiments, due to the anti-doping of the second conductivity type impurity (e.g., p-type impurity), the concentration of the first conductivity type impurity (e.g., n-type impurity concentration) of semiconductor layer 14 between the second portions 30-2 is lower than the concentration of the first conductivity type impurity (e.g., n-type impurity concentration) of semiconductor layer 14 above it.

[0067] Reference Figure 2G Next, the barrier layer 52 inside the trench 50 is removed. The barrier layer 52 can be removed by etching processes such as wet etching or dry etching.

[0068] Reference Figure 2H-1 and Figure 2H-2 A second conductive impurity 58 is formed near the trench 50. For example, the second conductive impurity 58 is formed adjacent to a first trench portion (e.g., upper trench portion) 50U and a second trench portion (e.g., lower trench portion) 50L of the trench 50. In some embodiments, such as Figure 2G and Figure 2H-1 As shown, a second conductivity type impurity (e.g., a p-type impurity (e.g., boron)) 58 is formed in a portion of the semiconductor layer 14 adjacent to the entire sidewall of the trench 50 by a plasma doping process. In an alternative embodiment, as... Figure 2G and Figure 2H-2As shown, a semiconductor layer including a second conductivity type impurity 58 can be formed on the entire sidewall of the trench 50 by a solid phase deposition process. For example, the semiconductor layer including the second conductivity type impurity 58 is also referred to as a second conductivity type doped layer (e.g., a p-type doped layer) or a semiconductor layer doped with a second conductivity type impurity (e.g., a semiconductor layer doped with a p-type impurity).

[0069] Reference Figure 2I Second conductivity type impurity 58 (e.g., Figure 2H-1 or Figure 2H-2 The material diffuses into the semiconductor layer 14 to form a first portion 30-1. The first portion 30-1 and the second portion 30-2 form a doped region 30. In some embodiments, such as... Figure 2H-1 or Figure 2H-2 and Figure 2I As shown, through an annealing process, a second conductivity type impurity 58 adjacent to the first trench portion (e.g., the upper trench portion) 50U can diffuse into the surrounding region of the semiconductor layer 14 between the second portion 30-2 and the first surface A to form the first portion 30-1 of the doped region 30. In some embodiments, Figure 2I The width of the second part 30-2 can be compared with Figure 2H-1 or Figure 2H-2 The width of the second portion 30-2 is substantially the same. However, the invention is not limited thereto. In an alternative embodiment, a second conductivity type impurity in the second portion 30-2 may also diffuse into the semiconductor layer 14; in other words, the second portion 30-2 may extend along the second direction D2. In such embodiments, Figure 2I The width of the second part 30-2 can be compared with Figure 2H-1 or Figure 2H-2The width of the second portion 30-2 is (e.g., slightly) different. In some embodiments where the second conductivity type is p-type, the first portion 30-1 and the second portion 30-2 of the doped region 30 are p-type doped regions and are collectively referred to as p-type doped region 30. The above method allows the second portion 30-2 to have different widths and impurity concentrations than the first portion 30-1. Therefore, the doped region 30 may have at least two portions 30-1 and 30-2 with different widths and impurity concentrations. In some embodiments, the second portion (e.g., the wide portion) 30-2 is formed on the underside of the doped region 30 adjacent to the second trench portion (e.g., the lower trench portion) 50L of the trench 50, and the first portion (e.g., the narrow portion) 30-1 is formed on the upper side of the doped region 30 adjacent to the first trench portion (e.g., the upper trench portion) 50U of the trench 50. The first portion 30-1 is disposed on the second portion 30-2 in the first direction (e.g., the depth direction) D1. The first portion 30-1 and the second portion 30-2 may be integrally formed within the semiconductor layer 14 of the semiconductor substrate 12, and there is no interface between them or no interface is observable between them. In some embodiments, compared to the first portion 30-1, more implantation and annealing processes may be used to form the second portion 30-2 of the doped region 30, such that the width (e.g., region width) and / or impurity concentration of the second portion 30-2 is greater than the width and / or impurity concentration of the first portion 30-1. The above method makes it possible to form a doped region 30 with a double thickness.

[0070] Reference Figure 2J One or more transistors are formed on a first surface (e.g., front surface) A. A trench isolation member 26 is formed in a trench 50. The trench isolation member 26 can be formed by filling the trench 50 with an insulating and / or conductive material and removing portions of the insulating material outside the trench 50. A thinning process, such as a chemical polishing process, can be performed from a second surface (e.g., rear surface or back surface) B to reduce the thickness of the semiconductor substrate 12 (e.g., semiconductor layer 14) so ​​that the photodiode region can have the desired thickness (e.g., a second depth Dp2). In some embodiments, the structural depth of the trench isolation member 26 may be substantially the same as the thickness of the semiconductor layer 14 after the thinning process. In alternative embodiments where the semiconductor substrate 12 further includes other layers besides the semiconductor layer 14 and these layers are not removed during the thinning process, the structural depth of the trench isolation member 26 may be substantially the same as the combined thickness of the remaining semiconductor substrate 12 and the semiconductor layer 14 above it after the thinning process.

[0071] Figure 3 This is a cross-sectional view of a pixel structure according to some embodiments of the present invention. Figure 3 pixel structure and Figure 1A Their pixel structures are similar, therefore Figure 3Components (e.g., floating diffusion region 20, transfer gate 24, well isolation 22, semiconductor layer 14, trench isolation 26, etc.) may include those with... Figure 1A The components have similar characteristics (such as composition, shape, structure, arrangement, distribution, and combination thereof), and details may be omitted. The differences between the two will be described below. In some embodiments, at least one additional portion is disposed between a first portion 30-1 and a second portion 30-2 included in the doped region 30 of pixel 10A, and the doped region 30 includes a plurality of widths. For example, as Figure 3 As shown, the third portion 30-3 is disposed between the first portion 30-1 and the second portion 30-2, and the doped region 30 may include three different widths between the first surface A and the second surface B. In some embodiments, the first portion 30-1 (e.g., the upper portion) is disposed or formed to extend from the first surface A to a first depth Dp1 toward the second surface B. The third portion 30-3 (e.g., the middle portion) may be disposed or formed to extend from the first depth Dp1 toward the second surface B to a third depth Dp3. The second portion 30-2 (e.g., the bottom portion) may be disposed or formed to extend from the third depth Dp3 to the second surface B (e.g., a second depth Dp2). In some embodiments, the third portion 30-3 is disposed between and in direct contact with the first portion 30-1 and the second portion 30-2. For example, the first portion 30-1, the third portion 30-3, and the second portion 30-2 are disposed continuously from the first surface A to the second surface B.

[0072] In some embodiments, the first, second, and third portions 30-1, 30-2, and 30-3 have first, second, and third widths W1, W2, and W3, respectively, along the second direction D2, where the first width W1 is smaller than the second width W2, and the third width W3 is between the first width W1 and the second width W2. In other words, the widths W1, W2, and W3 of the doped region 30 decrease as the doped region 30 gets closer to the first surface A. In some embodiments, the first portion 30-1 of the doped region 30 has a substantially uniform width (e.g., width W1) between the first surface A and the first depth Dp1. The third portion 30-3 of the doped region 30 may have a substantially uniform width (e.g., width W3) between the first depth Dp1 and the third depth Dp3. The second portion 30-2 of the doped region 30 may have a substantially uniform width (e.g., width W2) between the third depth Dp3 and the second surface B (e.g., the second depth Dp2).

[0073] In some embodiments, the first to third portions 30-1, 30-2, and 30-3 each have first, second, and third impurity concentrations of a second conductivity type (e.g., p-type impurity concentration), each of which is greater than the second conductivity type impurity concentration (e.g., p-type impurity concentration) of the semiconductor layer 14. In some embodiments, the first impurity concentration of the first portion 30-1 is less than the second impurity concentration of the second portion 30-2, and the third impurity concentration of the third portion 30-3 is between the first and second impurity concentrations. That is, the impurity concentration of the doped region 30 decreases as the doped region 30 gets closer to the first surface A. However, the invention is not limited thereto. In alternative embodiments, the impurity concentrations of the doped regions 30 from the first surface A to the second surface B are substantially the same, that is, the first, second, and third impurity concentrations of the first to third portions 30-1, 30-2, and 30-3 are substantially equal.

[0074] In the illustrated embodiment, semiconductor layer 14 includes a first region 14-1 (e.g., an upper region) surrounded by a first portion 30-1, a third region 14-3 (e.g., an intermediate layer portion) surrounded by a third portion 30-3, and a second region 14-2 (e.g., a lower or bottom layer portion) surrounded by a second portion 30-2. The first region 14-1 (e.g., the upper layer portion) is configured or formed to extend from a first surface A toward a second surface B to a first depth Dp1. The third region 14-3 (e.g., the intermediate layer portion) is configured or formed to extend from the first depth Dp1 toward the second surface B to a third depth Dp3. The third region 14-3 (e.g., the intermediate layer portion) may couple the first region 14-1 to the second region 14-2. The second region 14-2 (e.g., the lower or bottom layer portion) is configured or formed to extend from the third depth Dp3 to the second surface B (e.g., a second depth Dp2). In some embodiments, the third region 14-3 is disposed between and in direct contact with the first region 14-1 and the second region 14-2. For example, a first region 14-1, a third region 14-3, and a second region 14-2 are continuously disposed from a first surface A to a second surface B. The first region 14-1 of the semiconductor layer 14 may be disposed at substantially the same depth as the first portion 30-1 of the doped region 30, the third region 14-3 of the semiconductor layer 14 may be disposed at substantially the same depth as the third portion 30-3 of the doped region 30, and the second region 14-2 of the semiconductor layer 14 may be disposed at substantially the same depth as the second portion 30-2 of the doped region 30. In the second direction D2, the first width W1' of the first region 14-1 is greater than the second width W2' of the second region 14-2, and the third width W3' of the third region 14-3 is between the first width W1' and the second width W2'. In some embodiments, the combined lateral width of the first portion 30-1 of the doped region and the first region 14-1 is substantially equal to the combined lateral width of the second portion 30-2 of the doped region and the second region 14-2 of the semiconductor layer 14, and the combined width of the third portion 30-3 of the doped region 30 and the third region 14-3 of the semiconductor layer 14, that is, W1 + W1' = W2 + W2' = W3 + W3'. The first region 14-1 may have a constant or uniform width, that is, the first width W1' of the first region 14-1 is substantially constant from the first surface A to the first depth Dp1. Similarly, the third region 14-3 may have a constant or uniform width, that is, the third width W3' of the third region 14-3 is substantially constant from the first depth Dp1 to the third depth Dp3. The second region 14-2 may have a constant or uniform width, that is, the second width W2' of the second region 14-2 is substantially constant from the third depth Dp3 to the second surface B (e.g., the second depth Dp2).

[0075] In some embodiments, due to the width differences between the first to third portions 30-1, 30-2, and 30-3 of the doped region 30, the inner boundary of the doped region 30 has a transition point TN between adjacent pairs in the first to third portions 30-1, 30-2, and 30-3. Similarly, the boundary of the semiconductor layer 14 facing the doped region 30 also has a transition point TN between adjacent pairs in the first to third regions 14-1, 14-2, and 14-3. In such embodiments, the inner boundary of the doped region 30 and the boundary of the semiconductor layer 14 may also be referred to as a stepped boundary or a staircase-like boundary.

[0076] In some embodiments, the configuration of the doped regions 30 makes the first conductivity type (e.g., n-type) impurity concentration gradient of the semiconductor layer 14 smoother and facilitates the movement of charge (e.g., electrons). In particular, in some embodiments where the photodiode has a long depth in the depth direction, it is preferable to have doped regions with multiple widths. Furthermore, in alternative embodiments, the doped regions may have more than three portions / widths, thus the semiconductor layer 14 may have more than three portions / widths. In such embodiments, the first conductivity type (e.g., n-type) impurity concentration gradient can be further smoothed.

[0077] Figure 4 This is a cross-sectional view of a pixel structure according to some embodiments of the present invention. Figure 4 pixel structure and Figure 1A Their pixel structures are similar, therefore Figure 4 Components (e.g., floating diffusion region 20, transfer gate 24, well isolation 22, semiconductor layer 14, trench isolation 26, etc.) may include those with... Figure 1A The components have similar characteristics (such as composition, shape, structure, arrangement, distribution, and combination thereof), and details may be omitted. The differences between the two will be described below. In some embodiments, pixel 10B further includes a shallow trench separator 34 disposed on one side of the front surface region 18 (e.g., the front surface p-type region 18). For example, the shallow trench separator 34 is disposed on the trench separator 26 and surrounds the front surface region 18. In some embodiments where the trench separator 26 is a deep trench separator (DTI), the shallow trench separator 34 and / or the front surface region 18 may be used as a surface portion (e.g., an extension) of the trench separator 26.

[0078] In some embodiments, pixel isolation may be more reliably achieved by providing shallow trench isolation members 34 on the surface side (e.g., the front surface side) of the trench isolation member 26. Furthermore, as Figure 4As shown, the lateral width of the shallow trench isolation member 34 can be configured to be greater than the lateral width of the trench isolation member 26 below it, or the shallow trench isolation member 34 can be formed by using a material of a different mass than the trench isolation member 26. Therefore, the desired insulation performance can be achieved at the first surface (e.g., the front surface) A. Furthermore, forming the shallow trench isolation member 34 at the first surface (e.g., the front surface) A may also enable the mitigation / reduction of the electric field at the PN junction between the first portion 30-1 (e.g., the p-doped region) of the doped region 30 and the floating diffusion region 20 (e.g., the n-doped region).

[0079] Figure 5 This is a cross-sectional view of an image sensor according to some embodiments of the present invention.

[0080] Reference Figure 5 In some embodiments, the image sensor includes a pixel array containing multiple pixels 10, an anti-reflective layer AF, a color filter layer CFL, and a microlens layer ML. The image sensor may be a back-illuminated (BSI) sensor and / or a solid-state image sensor. The pixel array includes... Figure 1A A plurality of pixels 10 are arranged in a plurality of columns and a plurality of rows to form an array. Pixels 10 may have a size smaller than a micrometer, such as less than 0.8 μm or 0.7 μm. In an alternative embodiment, the pixel may be... Figure 3 , Figure 4 Pixels 10A and 10B are provided. A color filter layer CFL is disposed on the surface of the pixel array (e.g., the second surface B of pixel 10) and includes, for example, a plurality of color filters CF and a separation pattern SP between the color filters CF. Each color filter CF may have one of blue, green, and red, and the separation pattern SP may be a low-refractive-index pattern. The color filters CF are disposed corresponding to each pixel 10, and the separation pattern SP is disposed corresponding to the trench isolator 26. For example, the color filters CF overlap with the pixel 10 below them, and the separation pattern SP overlaps with the trench isolator 26 below them. An anti-reflective layer AF is disposed between the pixel array and the color filter layer CFL and is formed of, for example, silicon oxide or includes silicon oxide. A microlens layer ML is disposed on the color filter layer CFL and directs incident light to the photodiodes of each pixel 10. The microlens layer ML may include a microlens array and includes convex lens portions that overlap with each pixel 10 of the pixel array.

[0081] In some embodiments, based on the above, the pixel allows the photodiode to have a potential gradient, which can facilitate the movement of charge (e.g., electrons) in the photodiode. That is, by configuring doped regions 30 with different widths and concentrations (e.g., p-type doped regions), it is possible to modulate the potential of the photodiode and set the full-well capacity (FWC) and the degree of charge (e.g., electron) movement.

[0082] In some embodiments, a doped region (e.g., a p-type doped region) 30 is formed on the sidewalls adjacent to the deep trench isolator, making it possible to passivate the silicon interface of the trench sidewalls. This reduces the occurrence of white pixels. In some embodiments, the photodiode is allowed to have a potential gradient, thus allowing for further increases in the depth of the semiconductor layer. Therefore, the photodiode can be used to detect light with long wavelengths, making it suitable for applications such as security sensors using long-wavelength light. In some embodiments, a photodiode with a gradient doping profile for generating a target potential can be achieved without using multiple high-energy implantation depths to implant n-type impurities such as arsenic or phosphorus, promoting the movement of charge (e.g., electrons) from the photodiode to the floating diffusion region. This effectively reduces semiconductor substrate damage caused by ion implantation and shortens processing time (e.g., reducing loading time).

[0083] The description of the above-described examples of the invention, including those described in the abstract, is not intended to be exhaustive or to limit the invention to its precise form. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as will be recognized by those skilled in the art.

[0084] These modifications can be made to the invention based on the detailed description above. The terminology used in the following claims should not be construed as limiting the invention to the specific examples described in the specification. Rather, the scope of the invention is defined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

Claims

1. A pixel structure, characterized in that, include: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A trench isolation element is disposed in the semiconductor substrate; A semiconductor layer disposed in the semiconductor substrate and surrounded by the trench isolation member, wherein the semiconductor layer has a first conductivity type and a photodiode is formed in the semiconductor layer; as well as A doped region is disposed between the trench isolator and the semiconductor layer, the doped region having a second conductivity type opposite to the first conductivity type, wherein the doped region extends between the first surface and the second surface, and the width of the doped region decreases as the doped region gets closer to the first surface.

2. The pixel structure according to claim 1, characterized in that, The doped region includes: A first portion extends along a first direction from the first surface to a first depth relative to the first surface, and the first portion has a first width in a second direction perpendicular to the first direction; and The second portion is disposed between the first portion and the second surface, and the second portion has a second width in the second direction. The first width is smaller than the second width.

3. The pixel structure according to claim 2, characterized in that, The first portion has a first width that is constant from the first surface to the first depth, and the second portion has a second width that is constant from the first depth to the second surface.

4. The pixel structure according to claim 2, characterized in that, The semiconductor layer includes: A first region, surrounded by the first portion of the doped region, and the first region of the semiconductor layer having a first region impurity concentration of the first conductivity type; and A second region, surrounded by the second portion of the doped region, and the second region of the semiconductor layer having a second region impurity concentration of the first conductivity type, wherein the second region impurity concentration of the second region is lower than the first region impurity concentration of the first region.

5. The pixel structure according to claim 4, characterized in that, The first portion of the doped region has a first impurity concentration of the second conductivity type, the second portion of the doped region has a second impurity concentration of the second conductivity type, and the first impurity concentration of the first portion is less than the second impurity concentration of the second portion.

6. The pixel structure according to claim 4, characterized in that, The second portion of the doped region is in direct contact with the first portion of the doped region, and the second region of the semiconductor layer is in direct contact with the first region of the semiconductor layer.

7. The pixel structure according to claim 4, characterized in that, The doped region further includes: At least one third portion is located between the first portion and the second portion of the doped region, the at least one third portion of the doped region having a third width in the second direction, and the third width being between the first width and the second width.

8. The pixel structure according to claim 7, characterized in that, The first portion of the doped region has a first impurity concentration of the second conductivity type, the second portion of the doped region has a second impurity concentration of the second conductivity type, and the third portion of the doped region has a third impurity concentration of the second conductivity type, wherein each of the first impurity concentration, the second impurity concentration, and the third impurity concentration is greater than the impurity concentration of the semiconductor layer.

9. The pixel structure according to claim 8, characterized in that, The first impurity concentration in the first part is less than the second impurity concentration in the second part, and the third impurity concentration in the third part is between the first impurity concentration in the first part and the second impurity concentration in the second part.

10. The pixel structure according to claim 7, characterized in that, The semiconductor layer further includes: At least one third region is located between the first region and the second region of the semiconductor layer, the at least one third region of the semiconductor layer having a third width in the second direction, and the third width being between the first width of the first region of the semiconductor layer and the second width of the second region of the semiconductor layer.

11. The pixel structure according to claim 1, characterized in that, The doped region has a width inflection point at a first depth in the semiconductor layer.

12. The pixel structure according to claim 1, characterized in that, The semiconductor layer has a stepped boundary at the interface with the doped region.

13. The pixel structure according to claim 1, characterized in that, The surfaces of the doped region, the trench isolation element, and the semiconductor layer are coplanar.

14. The pixel structure according to claim 1, characterized in that, The doped region is in direct contact with the trench isolation element and the semiconductor layer.

15. The pixel structure according to claim 1, characterized in that, Further includes: A transmission gate is disposed on the first surface; as well as A floating diffusion region is disposed in the semiconductor substrate and adjacent to the first surface, wherein the transmission gate is configured to selectively couple the photodiode to the floating diffusion region.

16. The pixel structure according to claim 1, characterized in that, The doped region has a vertical thickness that is the same as the trench depth of the trench separator relative to the first surface.

17. A method for forming a pixel structure, characterized in that, include: A trench and a semiconductor layer of a first conductivity type are formed in a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to the first surface, and the semiconductor layer is surrounded by the trench; A doped region adjacent to the trench is formed in the semiconductor layer, wherein the doped region is a second conductivity type opposite to the first conductivity type and is configured to extend from a first depth to the second surface; The first impurity of the second conductivity type is diffused into the semiconductor layer between the trench and the first surface to form a first doped portion of the doped region between the first surface and the first depth, and a second doped portion between the first depth and the second surface; as well as A ditch isolation component is formed in the ditch.

18. The method according to claim 17, characterized in that, The formation of the doped region in the semiconductor layer includes: A barrier layer is formed, the barrier layer lining only a first channel portion of the trench between the first surface and the first depth, while a second channel portion of the trench between the first depth and the second surface does not have the barrier layer; and The second impurity of the second conductivity type is diffused into the semiconductor layer through the second trench portion of the trench.

19. The method according to claim 18, characterized in that, The diffusion of the second impurity of the second conductivity type into the semiconductor layer includes: The second impurity of the second conductivity type is formed via a plasma doping process through the second trench portion of the trench; and The second impurity of the second conductivity type is diffused into the semiconductor layer through an annealing process.

20. The method according to claim 18, characterized in that, The diffusion of the second impurity of the second conductivity type into the semiconductor layer includes: The deposition includes a layer of the second impurity of the second conductivity type, the layer being adjacent to the first trench portion and the second trench portion of the trench; and The second impurity of the second conductivity type is diffused into the semiconductor layer through an annealing process.

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