image sensor

Abstract

An image sensor includes: a stacked structure including a first substrate having a first surface and a second surface, and the first substrate including a photoelectric conversion region for each of a plurality of pixels; a first interconnect structure including a first interconnect and an insulating layer between the first interconnects on the second surface; a second substrate including logic elements for driving the plurality of pixels on the first interconnect structure of the first substrate; a second interconnect structure disposed between the second substrate and the first interconnect structure, and including an insulating layer between the second interconnect and the second interconnect; a transparent planarization layer including an inorganic material on the first surface; and a super-optical structure including a plurality of dielectric layers on the transparent planarization layer, and a nanoprism pattern disposed in at least one of the plurality of dielectric layers.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0189963, filed with the Korean Intellectual Property Office on December 18, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to an image sensor. Background Technology

[0003] An image sensor can be a semiconductor-based sensor that receives light based on the position and color corresponding to an image formed by an optical structure, and generates an electrical signal accordingly. The optical structure of an image sensor can primarily employ microlenses and color filters for each pixel. However, with the increasing demand for high-resolution cameras and as pixels become increasingly ultra-fine, the size of the optical structure is trending towards reduction.

[0004] However, the optical efficiency of image sensors decreases due to the miniaturization of optical structures. As an alternative to optical structures in related technologies, a method for introducing structures based on a novel optical technology known as "super-optics" is being actively researched. Summary of the Invention

[0005] One aspect of one or more exemplary embodiments of this disclosure provides an image sensor with improved reliability.

[0006] According to one aspect of an exemplary embodiment of the present disclosure, an image sensor includes: a stacked structure including an active pixel region defining a plurality of pixels, and a connection region and a pad region located outside the active pixel region, wherein the stacked structure includes: a first substrate having a first surface and a second surface opposite to the first surface, and including a photoelectric conversion region for each of the plurality of pixels; a first interconnect structure disposed on the second surface of the first substrate, and including a first interconnect and an insulating layer between the first interconnects; a second substrate disposed on the first interconnect structure, and including logic elements for driving the plurality of pixels; a second interconnect structure disposed between the second substrate and the first interconnect structure, and including an insulating layer between the second interconnect and the second interconnect; a transparent planarization layer disposed on the first surface of the first substrate, and including an inorganic material; and a super-optical structure disposed on the transparent planarization layer, and including a plurality of dielectric layers, and a nanoprism pattern disposed in at least one of the plurality of dielectric layers in the active pixel region.

[0007] According to one aspect of this disclosure, an image sensor includes: a stacked structure, the stacked structure including an active pixel region defining a plurality of pixels, and a connection region and a pad region located outside the active pixel region, wherein the stacked structure includes: a first substrate having a first surface and a second surface opposite to the first surface, and including a photoelectric conversion region for each of the plurality of pixels; a first interconnect structure disposed on the second surface of the first substrate, and including a first interconnect and an insulating layer between the first interconnects; a second substrate disposed on the first interconnect structure, and including logic elements for driving the plurality of pixels; a second interconnect structure disposed between the second substrate and the first interconnect structure, and including an insulating layer between the second interconnect and the second interconnect; and a transparent planarization layer disposed on the first substrate. The substrate has a first surface and includes an inorganic material; a super-optical structure disposed on a transparent planarization layer and including a plurality of dielectric layers and a nanoprism pattern disposed in at least one of the dielectric layers in an active pixel region; a first interconnect structure having a first conductor pattern extending through the first substrate and the first interconnect structure to a second interconnect structure in the interconnect region, the first conductor pattern electrically connecting the first interconnect and the second interconnect; and an external bonding pad in the pad region on the first surface of the first substrate; and a second interconnect structure having a second conductor pattern extending through the first substrate and the first interconnect structure to the second interconnect structure on one side of the external bonding pad, the second conductor pattern electrically connecting the external bonding pad and the second interconnect.

[0008] According to one aspect of this disclosure, an image sensor includes: a stacked structure, the stacked structure including an active pixel region defining a plurality of pixels, and a connection region and a pad region located outside the active pixel region, wherein the stacked structure includes: a first substrate having a first surface and a second surface opposite to the first surface, and including a photoelectric conversion region for each of the plurality of pixels; a first interconnect structure disposed on the second surface of the first substrate, and including a first interconnect and an insulating layer between the first interconnects; a second substrate disposed on the first interconnect structure, and including logic elements for driving the plurality of pixels; a second interconnect structure disposed between the second substrate and the first interconnect structure, and including an insulating layer between the second interconnect and the second interconnect; a first bonding structure disposed between the first interconnect structure and the second interconnect structure, and The device includes a first bonding insulating layer and a first bonding pad connected to a first interconnect in the first bonding insulating layer; a second bonding structure disposed between the first bonding structure and the second interconnect structure, and including a second bonding insulating layer bonded to the first bonding insulating layer, and a second bonding pad connected to the second interconnect in the second bonding insulating layer and bonded to the first bonding pad respectively; a transparent planarization layer disposed on a first surface of a first substrate, and comprising an inorganic material; a super-optical structure disposed on the transparent planarization layer, and comprising a plurality of dielectric layers, and a nanoprism pattern disposed in at least one of the plurality of dielectric layers in an active pixel region; and an external bonding pad disposed on a region of the second interconnect structure exposed by a pad opening, the pad opening passing through the first substrate in the pad region to reach the second interconnect structure. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is an exploded perspective view of an image sensor according to an embodiment.

[0011] Figure 2 yes Figure 1 A plan view of part "A" in the image sensor, and Figure 3 yes Figure 2 A side view of the section taken along line I-I'.

[0012] Figure 4 This is a cross-sectional side view of an image sensor according to an embodiment.

[0013] Figure 5 and Figure 6 These are cross-sectional side views of image sensors according to various embodiments.

[0014] Figure 7This is a cross-sectional side view of an image sensor according to an embodiment.

[0015] Figure 8 and Figure 9 This is a cross-sectional side view of an image sensor according to various embodiments. Detailed Implementation

[0016] One or more exemplary embodiments of this disclosure will now be described with reference to the accompanying drawings. Those skilled in the art will understand that aspects of some embodiments can be combined together or implemented individually.

[0017] In this specification, the description of a first component (or region, layer, part, section, etc.) as "located on a second component", "connected to a second component" or "coupled to a second component" means that the first component is directly located on and / or directly connected to and / or directly coupled to the second component, or that a third component is located between the two.

[0018] The same reference numerals may refer to the same parts. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of components may be exaggerated for the purpose of effectively describing the technical content. As used herein, the phrase "at least one of..." following the list of elements modifies the entire list of elements, rather than a single element in the list. For example, the phrase "at least one of a, b, and c" (or "at least one of a, b, or c") should be understood to include: only a; only b; only c; both a and b; both a and c; both b and c; or all of a, b, and c.

[0019] Although the terms “first,” “second,” etc., may be used to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless explicitly stated in the context, singular expressions include plural expressions.

[0020] Furthermore, the terms "below," "under," "above," and "over" are used to describe the relationships between the components shown in the accompanying drawings. These terms, which are relative concepts, are based on the directions shown in the accompanying drawings.

[0021] It should be understood that the terms “comprising,” “including,” “having,” etc., specify the presence of the features, quantities, steps, operations, elements, components, or combinations thereof described in the specification, without precluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0022] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be construed as having an overly idealized or formal meaning unless expressly defined herein.

[0023] Figure 1 This is an exploded perspective view of an image sensor according to an embodiment. Figure 2 yes Figure 1 A plan view of part "A" in the image sensor, and Figure 3 yes Figure 2 A side view of the section taken along line I-I'.

[0024] Reference Figures 1 to 3 The image sensor 10 according to the embodiment may include a stacked structure ST, wherein a first substrate structure 100 and a second substrate structure 200 are stacked and electrically connected to each other. The stacked structure ST used in this embodiment may include: an active pixel region APR, in which a plurality of pixels PX are arranged; a pad region PDR, disposed on at least one side of the active pixel region APR; and an optical black region OB and a connection region CR, located between the active pixel region APR and the pad region PDR.

[0025] like Figure 1 As shown, the active pixel region APR can be disposed in the inner region of the stacked structure ST. Multiple pixels PX can be disposed in the active pixel region APR. In the active pixel region APR, multiple pixels PX can be disposed in a matrix on the first substrate 110 in rows and columns along a first direction D1 and a second direction D2 perpendicular to the first direction D1.

[0026] Each of the plurality of pixels PX may include at least one photoelectric conversion region PD formed in the first substrate 110. The plurality of pixels PX may be regions that receive light from an external source from the stacked structure ST and convert it into an electrical signal. For example, the plurality of pixels PX may include: a photoelectric conversion region PD that receives light from an external source; and a transistor forming a pixel circuit that converts photocharge accumulated in the photoelectric conversion region PD into an electrical signal.

[0027] The pad area PDR can be set on at least one side of the active pixel area APR, for example, on three sides of the active pixel area APR, such as... Figure 1 As shown. Multiple external bonding pads 390 can be disposed on the pad area PDR and configured to send or receive electrical signals with external devices, etc.

[0028] The optical black area OB and the connection area CR can be sequentially arranged around the source pixel area APR between the active pixel area APR and the pad area PDR. The optical black area OB can be a light-blocking area and can include an optical black pixel PX' that generates a dark signal to serve as a reference pixel for the active pixel area APR, and a dummy pixel DX can be further disposed around the optical black pixel PX' (see [reference]). Figure 2 The connection region CR can be located on one side of the optical black region OB, but this is only exemplary. The connection region CR can be configured to transmit electrical signals of the photoelectric conversion region PD to the circuitry of the second substrate 210 and / or receive electrical signals of the photoelectric conversion region PD from the circuitry of the second substrate 210 by connecting the first interconnect 125 and the second interconnect 225 using the first connection structure 362.

[0029] As mentioned above, refer to Figure 3 The image sensor 10 according to this embodiment may include a stacked structure ST having a first substrate structure 100 and a second substrate structure 200.

[0030] The first substrate structure 100 may include a first substrate 110 having a first surface 110a and a second surface 110b opposite to each other, and a front optical structure 300 located on the first surface 110a of the first substrate 110 (see [link]). Figure 7 The first substrate 100 includes a first interconnect structure 120 on a second surface 110b of the first substrate 110. The second substrate structure 200 may include a second substrate 210 on which logic elements 215 are disposed, and a second interconnect structure 220 on the second substrate 210 and in contact with the first interconnect structure 120. The first substrate structure 100 may also be referred to as a "sensor chip," and the second substrate structure 200 may also be referred to as a "logic chip." The image sensor according to this embodiment is shown as a stacked structure having two substrates, but is not limited thereto, and in some embodiments, it may include a stacked structure having at least three substrates. For example, at least some transistors for pixel circuitry may be implemented on separate substrates, rather than on the first substrate 110.

[0031] The image sensor 10 according to this embodiment may include a super-optical structure 400 instead of an optical lens. In this case, the super-optical structure 400 may refer to an optical structure based on super-optics, and may also be referred to as a metasurface or a superlens.

[0032] In this embodiment, the super-optical structure 400 can be disposed on the first surface 110a (which can be used as the incident surface) of the first substrate 110, and can be configured to disperse the incident light according to the wavelength (e.g., color) and focus the dispersed light onto the photoelectric conversion region PD of different pixels PX.

[0033] Reference Figure 3 The super-optical structure 400 may be a multilayer structure comprising multiple dielectric layers 410, 421, 422, and 423, and may include nanoprism patterns NP1, NP2, and NP3. The nanoprism patterns NP1, NP2, and NP3 may be nanoscale structures (e.g., pillar structures) disposed in at least one of the dielectric layers 410, 421, 422, and 423 (e.g., at least one of 421, 422, and 423). In this embodiment, a transparent planarization layer 350 comprising inorganic material may be disposed on the first surface 110a of the first substrate 110, and the super-optical structure 400 may be disposed on the transparent planarization layer 350.

[0034] Nanoprism patterns NP1, NP2, and NP3 can be disposed in the overlapping region of the active pixel region APR. Multiple dielectric layers 410, 421, 422, and 423 can extend through the active pixel region APR, as well as the optical black region OB and the connection region CR, to the pad region PDR.

[0035] The first substrate 110 of the first substrate structure 100 may be a semiconductor substrate. For example, the first substrate 110 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.

[0036] The first substrate 110 may include a photodiode (PD) isolation pattern 150 defining photodiode regions of a plurality of pixels PX. The PD isolation pattern 150 may surround the photoelectric conversion region PD. For each of the plurality of pixels PX, at least one photoelectric conversion region PD may be formed in the first substrate 110. The photoelectric conversion region PD may generate charge proportional to the amount of light incident from an external source. For example, the photoelectric conversion region PD may be a photodiode, phototransistor, photogate, pinned photodiode, or organic photodiode. The photoelectric conversion region PD may be disposed in an active pixel region APR.

[0037] Furthermore, as described above, in the optical black region adjacent to the active pixel region APR, a reference photoelectric conversion region PD' may be included in a reference pixel RX, which generates a dark signal for referencing the active pixel region APR. Additionally, a dummy photoelectric conversion region NPD may be configured as a dummy pixel DX that is not used as a photoelectric conversion element. The reference photoelectric conversion region PD' and the dummy photoelectric conversion region NPD may also be separated by a PD isolation pattern 150.

[0038] In a planar view, the PD isolation pattern 150 may have a lattice shape (or approximately a lattice shape) that isolates multiple pixel PX or photodiode (PD) regions. For example, the PD isolation pattern 150 may extend through at least a portion of the first substrate 110. In this embodiment, the PD isolation pattern 150 may include a deep trench extending from the second surface 110b to the first surface 110a. The PD isolation pattern 150 may include an insulating pad (not shown) on the sidewalls of the deep trench, and a filler portion filled in the insulating pad. For example, the insulating pad may include silicon oxide, silicon nitride, and / or silicon oxynitride, and the filler portion may include an insulating material, a semiconductor material, or a conductive material. For example, the filler portion may include polycrystalline silicon doped with impurities.

[0039] A component isolation pattern 112 defining an active region can be formed on a second surface 110b of the first substrate 110. A floating diffusion region FD and components for pixel circuitry can be formed in the active region. The components for pixel circuitry may include circuit elements (e.g., various transistors such as transmission gates TG). A PD isolation pattern 150 can be connected to the component isolation pattern 112, which can be a shallow trench structure. In this embodiment, the component isolation pattern 112 can be disposed on the PD isolation pattern 150. For example, the component isolation pattern 112 may include silicon oxide.

[0040] The first interconnect structure 120 may include a first interconnect insulating layer 121 and a plurality of first interconnects 125 within the first interconnect insulating layer 121. The number of layers and arrangement of the first interconnects included in the first interconnect structure 120 shown in the figures are merely illustrative examples. For example, the first interconnect insulating layer 121 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-κ material having a dielectric constant lower than that of silicon oxide. For example, the first interconnects 125 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or alloys thereof.

[0041] Similar to the first substrate 110, the second substrate 210 can be a bulk silicon substrate or an SOI substrate. Logic elements 215 can be disposed on the second substrate 210. Logic elements 215 can form circuitry that provides specific signals to each pixel PX of the active pixel region APR and / or controls output signals from each pixel PX. For example, logic elements 215 may include various transistors that form control register blocks, timing generators, ramp signal generators, row drivers, readout circuitry, and / or input / output buffer (I / O) circuitry.

[0042] The second interconnect structure 220 may be disposed between the first interconnect structure 120 and the second substrate 210 of the first substrate structure 100. The second interconnect structure 220 may include a second interconnect insulating layer 221 and a plurality of second interconnects 225 on the second interconnect insulating layer 221. The number of layers and arrangement of the second interconnects included in the second interconnect structure 220 shown in the figures are merely illustrative examples. The plurality of second interconnects 225 may include vias electrically connecting logic elements 215. For example, the second interconnect insulating layer 221 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-κ material having a dielectric constant lower than that of silicon oxide. The second interconnects 225 may include at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or alloys thereof.

[0043] In this embodiment, the first interconnect structure 120 can be bonded to the second interconnect structure 220. In some embodiments, the first interconnect structure 120 and the second interconnect structure 220 may include a bonding insulating layer (not shown) disposed on the surfaces to be bonded. Furthermore, the first substrate structure 100 and the second substrate structure 200 can be electrically connected to each other via a first connection structure 362 and a second connection structure 372 passing through the first substrate structure 100. The first connection structure 362 and the second connection structure 372 can be disposed in the pad region PDR and the connection region CR, respectively, and can electrically connect the first interconnect 125 to the second interconnect 225.

[0044] refer to Figure 3 The first substrate structure 100 may include a surface insulating layer 310 and a transparent planarization layer 350 sequentially disposed on a first surface 110a of the first substrate 110.

[0045] A surface insulating layer 310 may be disposed on a first surface 110a of the first substrate 110. The surface insulating layer 310 may extend through the peripheral area (OB / CR) and the active pixel area (APR) to the pad area (PDR). The surface insulating layer 310 may include an insulating material. For example, the surface insulating layer 310 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or any combination thereof, but is not limited thereto. Furthermore, the surface insulating layer 310 may be multilayered. For example, the surface insulating layer 310 may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, or a hafnium oxide film sequentially stacked on the first surface 110a of the first substrate 110, but is not limited thereto. The surface insulating layer 310 may serve as an anti-reflective film to prevent light incident on the first substrate 110 from being reflected, thereby improving the light reception rate of the photoelectric conversion region (PD).

[0046] In this embodiment, the color filter and its associated configuration (e.g., grid pattern) on the surface insulating layer 310 can be omitted. Since the super-optical structure 400 can be configured to have excellent regional wavelength selectivity, the color filter provided in each pixel PX can be omitted.

[0047] In this way, by omitting the color filter and its associated configuration, the manufacturing process can be simplified, allowing for thinner thicknesses and overcoming temperature limitations imposed by the organic materials constituting the color filter. For example, after the color filter is formed, it is difficult to introduce high-temperature processes (e.g., 200°C or higher), and there is a risk of delamination and / or cracking within the color filter due to differences in the coefficients of thermal expansion of other components in contact with it. By omitting the color filter, which can be made of organic materials, these limitations can be fundamentally addressed.

[0048] Reference Figure 3 In the peripheral region (OB / CR), the first conductive layer 361 and the light-blocking filter layer 340L can be sequentially disposed on the surface insulating layer 310. In some embodiments, the light-blocking filter layer 340L can form an optical black region OB, and can be configured together with the first conductive layer 361 as a light-blocking structure. In this embodiment, similar to the transparent planarization layer 350, the light-blocking filter layer 340L may include inorganic materials. For example, the light-blocking filter layer 340L may include TiO2, ZnO, or Al2O3. In some embodiments, the light-blocking filter layer 340L may include organic materials.

[0049] Reference Figure 3 The bias contact plug 380 and the first conductive layer 361 can be disposed in the optical black region OB. The first conductive layer 361 can cover the surface insulating layer 310 on the first surface 110a of the first substrate 110. Furthermore, the first conductive layer 361 can conformally cover the inner wall of the first trench TR1 and can be connected to the PD isolation pattern 150. The bias contact plug 380 can fill the first trench TR1. The bias contact plug 380 can include a metallic material (e.g., aluminum). The bias contact plug 380 can be connected to the PD isolation pattern 150 through the first conductive layer 361. A bias voltage can be applied to the PD isolation pattern 150 through the bias contact plug 380.

[0050] A first connection structure 362 may be disposed in the connection region CR. The first connection structure 362 may include a first conductor pattern formed along the inner sidewall of a first via TH1, which extends through the first substrate 110 and the first interconnect structure 120 to the second interconnect structure 220. The first conductor pattern can electrically connect the first interconnect 125 to the second interconnect 225. In this way, the first connection structure 362 can electrically connect the first substrate structure 100 to the second substrate structure 200 (specifically, by electrically connecting the first interconnect 125 to the second interconnect 225 through the first interconnect structure 120 and a portion of the second interconnect structure 220). The first connection structure 362 may be formed together with a first conductive layer 361. For example, the first connection structure 362 may include a metallic material (e.g., tungsten).

[0051] The second connection structure 372 and the external bonding pad 390 may be disposed in the pad region PDR. The second connection structure 372 may include a second conductor pattern formed along the inner sidewall of the second via TH2, which passes through the first substrate 110 and the first interconnect structure 120 to extend to the second interconnect structure 220. The second conductor pattern may electrically connect the external bonding pad 390 to the second interconnect 225.

[0052] Similar to the first connection structure 362, the second connection structure 372 can connect the first substrate structure 100 and the second substrate structure 200 to each other (specifically, by connecting the first interconnect 125 to the second interconnect 225 through the first interconnect structure 120 and a portion of the second interconnect structure 220). A second conductive layer 371 can be disposed on the first surface 110a of the first substrate 110 on the surface insulating layer 310. The second conductive layer 371 can conformally cover the inner wall of the second trench TR2. Similarly, a second conductor pattern extending from the second conductive layer 371 can be conformally formed to extend into the second via TH2 and can be configured as the second connection structure 372. The second conductive layer 371 and the second connection structure 372 can comprise the same metallic material (e.g., tungsten).

[0053] In this embodiment, the external bonding pad 390 can be formed by filling the second trench TR2. The external bonding pad 390 may include a metallic material (e.g., aluminum). The external bonding pad 390 can connect the second conductive layer 371 and the second connection structure 372 to the second interconnect 225, and can also connect to the logic element 215 of the second substrate 210 through the second interconnect 225. The external bonding pad 390 can serve as an electrical connection path between the image sensor 10 and external components. For example, in the multiple pixels PX of the active pixel region APR, the electrical signal generated by the photoelectric conversion region PD can be processed by the pixel circuit of the first substrate 110 and the logic circuit of the second substrate 210, and can be sent to the external component through the external bonding pad 390.

[0054] Reference Figure 3 The transparent planarization layer 350 can be formed not only in the active pixel region (APR), but also in the optical black region (OB) and the connection region (CR), which serve as the surrounding region, as well as the pad region (PDR). The transparent planarization layer 350 can cover the light-blocking filter layer 340L, the first connection structure 362, and the second connection structure 372 on the first surface 110a of the first substrate 110, and can have a flat upper surface.

[0055] The transparent planarization layer 350 may include a light-transmitting inorganic material. In some embodiments, the transparent planarization layer 350 may include an oxide such as tetraethyl orthosilicate (TEOS). However, the transparent planarization layer 350 is not limited to this, and may include, for example, a spin-coated hard mask (SOH), a flowable oxide (FOX), a Tonen silazane (TOSZ), undoped silicon glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicone glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable chemical vapor deposition (CVD) (FCVD) oxide, or any combination thereof. By using chemical vapor deposition, flowable CVD processes, or spin-coating processes, the transparent planarization layer 350 can have a flat upper surface. During the formation of the transparent planarization layer 350, the voids V1 in the first connection structure 362 and the voids V2 in the second connection structure 372 may be partially filled.

[0056] like Figure 3As shown, the first connection structure 362 may include a gap V1 surrounded by a first conductor pattern, and the transparent planarization layer 350 may have a first extension 350E1 extending into the gap V1 of the first connection structure 362. The first extension 350E1 may fill the upper region of the gap V1. Similarly, the second connection structure 372 may include a gap V2 surrounded by a second conductor pattern, and the transparent planarization layer 350 may have a second extension 350E2 extending into the gap V2 of the second connection structure 372. The second extension 350E2 may fill the upper region of the gap V2.

[0057] In this embodiment, the super-optical structure 400 can be disposed on the transparent planarization layer 350. As described above, the super-optical structure 400 may include: dielectric layers 410, 421, 422 and 423; and nanoprism patterns NP1, NP2 and NP3 disposed in at least one of the plurality of dielectric layers 410, 421, 422 and 423 (e.g., at least one of 421, 422 and 423).

[0058] Thus, in this embodiment, similar to the super-optical structure 400, the transparent planarization layer 350 may include inorganic materials to effectively prevent deformation (e.g., peeling, cracking, etc.) caused by the thermal expansion coefficient of the super-optical structure 400.

[0059] The super-optical structure 400 used in this embodiment may include three nanoprism structure layers on the substrate dielectric layer 410. Specifically, these three nanoprism structure layers may include a first molding layer 421 having a first nanoprism pattern NP1, a second molding layer 422 disposed on the first molding layer 421 and having a second nanoprism pattern NP2, and a third molding layer 423 disposed on the second molding layer 422 and having a third nanoprism pattern NP3.

[0060] The first to third nanoprism patterns NP1, NP2, and NP3 can be appropriately designed in terms of refractive index, shape, and / or height according to the wavelength. To obtain the height necessary to ensure the desired phase difference, the nanoprism patterns used in this embodiment can be disposed in three molding layers 421, 422, and 423. The first to third nanoprism patterns NP1, NP2, and NP3 can be configured such that some of the nanoprism patterns overlap each other. The super-optical structure 400 that can be used in this embodiment is not limited to this arrangement, and the nanoprism patterns can be disposed in various forms (shape, height, overlap, etc.) on one molding layer or three or more molding layers.

[0061] For example, the first to third molding layers 421, 422, and 423 may comprise transparent inorganic materials, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbonate, or silicon carbonitride. The substrate dielectric layer 410 may comprise the same or similar materials as the first to third molding layers 421, 422, and 423. The first to third nanoprism patterns NP1, NP2, and NP3 may be selected from materials with appropriate refractive indices based on the wavelength of the incident light. For example, the first to third nanoprism patterns NP1, NP2, and NP3 may comprise transparent inorganic materials, such as titanium oxide, silicon nitride, niobium oxide, tantalum oxide, aluminum oxide, or hafnium oxide.

[0062] In some embodiments, such as Figure 3 As shown, in the super-optical structure 400, the first to third etch stop films 431, 432, and 433 can be respectively disposed between the substrate dielectric layer 410 and corresponding layers in the first to third molding layers 421, 422, and 423. The first etch stop film 431 can be used to form a hole for the first nanoprism pattern NP1 in the first molding layer 421. Similarly, the second etch stop film 432 and the third etch stop film 433 can be used to form holes for the second nanoprism pattern NP2 and the third nanoprism pattern NP3 in the second molding layer 422 and the third molding layer 423, respectively. For example, the first etch stop film 431 and the second etch stop film 432 can include, for example, aluminum oxide.

[0063] The super-optical structure 400 used in this embodiment may include an anti-reflection layer 450 on the third molding layer 423. The anti-reflection layer 450 prevents reflection of light incident on the super-optical structure 400, thereby improving light reception efficiency. The anti-reflection layer 450 may include a material with a different refractive index than the material of the third molding layer 423. For example, the anti-reflection layer 450 may include silicon nitride, aluminum oxide, or hafnium oxide. In this embodiment, the anti-reflection layer 450 may include a plurality of apertures h (see...). Figure 2 Apertures h can be provided in the antireflective layer 450, which can not only prevent light interference but also improve light absorption, thereby improving the antireflective function. In some embodiments, a fourth etch stop film 434 can be disposed between the antireflective layer 450 and the third molding layer 423 to form a plurality of apertures h.

[0064] As described above, the first to third nanoprism patterns NP1, NP2 and NP3 can be disposed only in the active pixel region APR, but the substrate dielectric layer 410 and the first to third molding layers 421, 422 and 423 can extend to the peripheral region (OB / CR) and the pad region PDR.

[0065] By extending through the super-optical structure 400, the transparent planarization layer 350, and the surface insulating layer 310 in the pad region PDR, a pad opening OP that exposes the external bonding pad 390 can be formed. The external bonding pad 390 can be exposed through the pad opening OP in the pad region PDR for connection to external devices.

[0066] In this embodiment, multiple interfaces on the multilayer can be exposed on the inner sidewalls of the pad openings OP. However, it is not limited to this, but the transparent planarization layer 350 can have sides 350S that are relatively recessed compared to the individual layers (e.g., 410, 421, 422, and 433) of the super-optical structure 400. As described above, the recess depth can be understood as a difference in film material density due to different formation processes (rather than differences in constituent materials). For example, since the super-optical structure 400 can be formed by chemical vapor deposition, physical vapor deposition, sputtering, or atomic layer deposition, the super-optical structure 400 can have a film material that is relatively denser than the transparent planarization layer 350.

[0067] Figure 4 This is a cross-sectional side view of an image sensor according to an embodiment.

[0068] Reference Figure 4 The image sensor 10A according to this embodiment can have the same characteristics as... Figures 1 to 3 (in particular Figure 3 The image sensor 10 shown has a similar structure, except that the super-optical structure 400A includes two nanoprism structure layers. Specifically, the first organic material filling portion 365 and the second organic material filling portion 375 can be respectively disposed in the gap between the first connecting structure 362 and the second connecting structure 372, and the light-blocking filter layer can be omitted in the optical black region OB. Furthermore, unless otherwise specifically stated, the components of this embodiment can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the image sensor 10 shown is used for understanding.

[0069] The super-optical structure 400A used in this embodiment may include and Figures 1 to 3This is a different nanoprism structure layer from previous embodiments. The super-optical structure 400A may include a first molding layer 421 having a first nanoprism pattern NP1 on a substrate dielectric layer 410, and a second molding layer 422 including a second nanoprism pattern NP2 on the first molding layer 421. The nanoprism patterns NP1 and NP2 may be disposed in an overlapping region within the active pixel region APR. To obtain the height required to ensure the desired phase difference, the first nanoprism pattern NP1 and the second nanoprism pattern NP2 may be disposed in the two molding layers 421 and 422, respectively. In this embodiment, the first nanoprism pattern NP1 and the second nanoprism pattern NP2 may be configured to partially overlap each other.

[0070] The first organic material filling portion 365 and the second organic material filling portion 375 can be respectively disposed in the gaps between the first connecting structure 362 and the second connecting structure 362. For example... Figure 4 As shown, a first organic material filling portion 365 filled with organic material can be disposed in the gap surrounded by the first connecting structure 362. Similarly, a second organic material filling portion 375 filled with organic material can be disposed in the gap surrounded by the second connecting structure 372.

[0071] In this embodiment, unlike previous embodiments, the light-blocking filter layer can be omitted in the optical black area OB. Typically, the light-blocking filter layer can be provided together with the color filter of the active pixel area APR, but it can also be provided separately. In this embodiment, the anti-reflection layer 450 can have an extension 450E in the peripheral area (e.g., the optical black area OB and the connecting area CR). The extension 450E may not include any holes and substantially completely covers the peripheral area, and can partially function as a light-blocking filter layer.

[0072] Figure 5 This is a cross-sectional side view of an image sensor according to an embodiment.

[0073] Reference Figure 5 The image sensor 10B according to this embodiment has a similar Figures 1 to 3 (in particular Figure 3 The image sensor 10 shown in the diagram has a similar structure, except that the first substrate structure 100 and the second substrate structure 200 are connected by a metal-dielectric hybrid bonding. Unless otherwise specifically stated, the components of this embodiment can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the image sensor 10 shown is used for understanding.

[0074] Unlike previous embodiments, the image sensor 10B according to this embodiment can connect the first substrate structure 100 and the second substrate structure 200 in a different manner without using the first connection structure and / or the second connection structure. Specifically, the first substrate structure 100 and the second substrate structure 200 can be connected by a metal-dielectric hybrid bonding.

[0075] like Figure 5 As shown, the first bonding structure 190 and the second bonding structure 290 can be respectively disposed on the opposing surfaces of the first interconnection structure 120 and the second interconnection structure 220, and the first bonding structure 190 and the second bonding structure 290 can be electrically coupled and mechanically coupled.

[0076] The first bonding structure 190 may include a first bonding insulating layer 191 disposed on the first interconnect structure 120, and a first bonding pad 195 electrically connected to the first interconnect 125 on the bonding surface of the first bonding insulating layer 191. The surface of the first bonding pad 195 may be substantially coplanar with the bonding surface of the first bonding insulating layer 191.

[0077] Similarly, the second bonding structure 290 may include a second bonding insulating layer 291 disposed on the second interconnect structure 220, and a second bonding pad 295 electrically connected to the second interconnect 225 on the bonding surface of the second bonding insulating layer 291. The surface of the second bonding pad 295 may be substantially coplanar with the bonding surface of the second bonding insulating layer 291.

[0078] The first bonding structure 190 and the second bonding structure 290 can be hybrid bonded by a high-temperature annealing process while still bonded to each other. The hybrid bonding can include metal-to-metal bonding of the first bonding pad 195 and the second bonding pad 295, and dielectric bonding of the first bonding insulating layer 191 and the second bonding insulating layer 291. Through this hybrid bonding, the first substrate structure 100 and the second substrate structure 200 can not only be firmly bonded to each other, but the first interconnect 125 and the second interconnect 225 can also be electrically connected via metal-to-metal bonding. Therefore, the first bonding pad 195 and the second bonding pad 295 can replace the first connection structure 362 and the second connection structure 372 used to connect the first interconnect 125 and the second interconnect 225 in the previous embodiment (see...). Figure 3 and Figure 4 ).

[0079] The external bonding pad 390 can be disposed on the first substrate 110 in a manner similar to that of the previous embodiment (see [reference]). Figure 3 and Figure 4 And it can be exposed through the pad openings OP that pass through the super-optical structure 400 and the transparent planarization layer 350. (See reference...) Figure 5The stacked structure may include a via TH2 extending through the first substrate 110 to the first interconnect structure 120 on one side of the external bonding pad 390. The pad connection structure 372 may extend into the via TH2 and may include a conductor pattern electrically connecting the external bonding pad 390 to the first interconnect 125. The transparent planarization layer 350 may include an extension 350E2 filling the void V2 surrounded by the pad connection structure 372. The second extension 350E2 may fill the upper region of the void V2.

[0080] Figure 6 This is a cross-sectional side view of an image sensor according to an embodiment.

[0081] Reference Figure 6 The image sensor 10C according to this embodiment has a similar Figures 1 to 3 (in particular Figure 3 The image sensor 10 shown in the diagram has a similar structure, except that the first substrate structure 100 and the second substrate structure 200 are connected by a metal-dielectric hybrid bonding, and the organic material filling portion 375 is disposed in the pad connection structure 372. Unless otherwise specifically stated, the components of this embodiment can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the image sensor 10 shown is used for understanding.

[0082] In this embodiment, with Figure 5 Similarly, in the embodiments described above, the first substrate structure 100 and the second substrate structure 200 can be connected by a metal-dielectric hybrid bonding.

[0083] The first bonding structure 190 and the second bonding structure 290 may be respectively disposed on the opposing surfaces of the first interconnection structure 120 and the second interconnection structure 220, and the first bonding structure 190 and the second bonding structure 290 may be electrically coupled and mechanically coupled.

[0084] The first bonding structure 190 may include a first bonding insulating layer 191 disposed on the first interconnect structure 120, and a first bonding pad 195 electrically connected to the first interconnect 125 on the bonding surface of the first bonding insulating layer 191. Similarly, the second bonding structure 290 may include a second bonding insulating layer 291 disposed on the second interconnect structure 220, and a second bonding pad 295 electrically connected to the second interconnect 225 on the bonding surface of the second bonding insulating layer 291.

[0085] Through the intermetallic bonding of the first bonding pad 195 and the second bonding pad 295 and the dielectric bonding of the first bonding insulating layer 191 and the second bonding insulating layer 291, the first substrate structure 100 and the second substrate structure 200 can not only be firmly bonded to each other, but the first interconnect 125 and the second interconnect 225 can also be electrically connected through intermetallic bonding.

[0086] Similar to the previous embodiments (see...) Figure 5 The external bonding pad 390 may be disposed on the first substrate 110 and may be exposed through the pad opening OP passing through the super-optical structure 400 and the transparent planarization layer 350. The image sensor 10C according to this embodiment may include an organic material filling portion 375 that fills the void V2 surrounded by the pad connection structure 372.

[0087] Figure 7 This is a cross-sectional side view of an image sensor according to an embodiment.

[0088] Reference Figure 7 The image sensor 10D according to this embodiment has the same characteristics as... Figure 6 The image sensor 10C shown has a similar structure, except that the external bonding pad 390 is disposed on the second interconnect structure 220, the pad opening OP passes through the first substrate structure 100, and a ground connection structure 382 is also used in the connection region CR. Unless otherwise specifically stated, the components of this embodiment can be referred to... Figures 1 to 3 The image sensor 10 shown and Figure 6 The description of the same or similar components of the image sensor 10C shown is used for understanding.

[0089] In this embodiment, the external bonding pad 390 can be disposed on the second substrate structure 200, particularly on the second interconnect structure 220. The pad opening OP can pass through the first substrate structure 100, and the external bonding pad 390 can be exposed through the pad opening OP. The first substrate structure 100 and the second substrate structure 200 can be electrically and mechanically connected through the first bonding structure 190 and the second bonding structure 290.

[0090] The image sensor 10D according to this embodiment may include a third via TH3 extending through the first substrate 110 into the first interconnect structure 120 in the connection region CR. The ground connection structure 382 may include a conductor pattern extending into the third via TH3 and connected to the first interconnect 125. The transparent planarization layer 350 may include an extension 350E that partially fills the void V3 surrounded by the ground connection structure 382.

[0091] Figure 8 This is a cross-sectional side view of an image sensor according to an embodiment.

[0092] Reference Figure 8 The image sensor 10E according to this embodiment has the same characteristics as... Figures 1 to 3 (in particular Figure 3 The image sensor 10 shown in the diagram has a similar structure, except that the super-optical structure 400A includes two nanoprism structure layers and also includes a color filter 340 and its associated configuration. Unless otherwise specifically stated, the components of this embodiment can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the image sensor 10 shown is used for understanding.

[0093] The super-optical structure 400A used in this embodiment may include the same as in previous embodiments (see...). Figures 1 to 3 Different nanoprism structure layers. The super-optical structure 400A may include a first molding layer 421 having a first nanoprism pattern NP1 on a substrate dielectric layer 410, and a second molding layer 422 having a second nanoprism pattern NP2 on the first molding layer 421. The nanoprism patterns NP1 and NP2 may be disposed in an overlapping region in the active pixel region APR. In this embodiment, the first nanoprism pattern NP1 and the second nanoprism pattern NP2 may be configured to partially overlap each other.

[0094] In this embodiment, the first substrate structure 100 may include a front optical structure 300 disposed on a first surface 110a of the first substrate 110. The front optical structure 300 may include a surface insulating layer 310, a grid pattern 320, a protective film 330, a color filter 340, and a transparent planarization layer 350.

[0095] A surface insulating layer 310 may be disposed on the first surface 110a of the first substrate 110. The surface insulating layer 310 may extend to the peripheral area (OB / CR), the pad area PDR, and the active pixel area APR. The surface insulating layer 310 may include an insulating material. For example, the surface insulating layer 310 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or any combination thereof, but is not limited thereto. Furthermore, the surface insulating layer 310 may be multilayered. For example, the surface insulating layer 310 may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film that may be sequentially stacked on the first surface 110a of the first substrate 110, but is not limited thereto. The surface insulating layer 310 may function as an anti-reflective film to prevent light incident on the first substrate 110 from being reflected, thereby improving the light reception rate of the photoelectric conversion area PD.

[0096] In the active pixel region APR, a grid pattern 320 between color filters 340 can be disposed on the surface insulating layer 310. Color filters 340 can be disposed on the surface insulating layer 310. Color filters 340 can be configured to correspond to each pixel PX of the active pixel region APR. Color filters 340 can have various color filters depending on each pixel. For example, color filters 340 can include red, green, and blue color filters. In some embodiments, color filters 340 can be configured in a Bayer pattern. However, this is merely illustrative and not limiting. For example, color filters 340 can include yellow, magenta, and cyan color filters, and may also include a white color filter.

[0097] In the planar view, the grid pattern 320 may have a grid shape. In some embodiments, the grid pattern 320 may be configured to overlap with the PD isolation pattern 150 in the vertical direction (e.g., D3). In some embodiments, the grid pattern 320 may include a conductive pattern and a low-refractive-index pattern. The conductive pattern can effectively prevent ESD failures by preventing the accumulation of charges generated by electrostatic discharge (ESD) or the like on the surface of the first substrate 110. The low-refractive-index pattern can improve light collection efficiency by refracting or reflecting obliquely incident light, thereby improving the quality of the image sensor. For example, the conductive pattern may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), or copper (Cu). Furthermore, the low-refractive-index pattern may include a low-refractive-index material with a refractive index lower than that of silicon (Si). For example, the low-refractive-index pattern may include at least one of silicon oxide, aluminum oxide, tantalum oxide, or any combination thereof.

[0098] Reference Figure 8 In the peripheral region (OB / CR), the first conductive layer 361 and the light-blocking filter layer 340L can be sequentially disposed on the surface insulating layer 310. The light-blocking filter layer 340L can be disposed in the optical black region OB and can be configured together with the first conductive layer 361 as a light-blocking structure. In this embodiment, the light-blocking filter layer 340L can be disposed together with a portion of the color filter 340. The light-blocking filter layer 340L can have a thickness substantially the same as that of the color filter 340, but is not limited thereto. The light-blocking filter layer 340L can include a blue color filter or a black color filter.

[0099] In this embodiment, the transparent planarization layer 350 can be disposed in the active pixel region APR and its surrounding regions (e.g., the optical black region OB and the connection region CR) and the pad region PDR in a manner similar to that in previous embodiments. The transparent planarization layer 350 can cover the color filter 340, the light-blocking filter layer 340L, the first connection structure 362, and the second connection structure 372 on the first surface 110a of the first substrate 110, and can have a flat upper surface. The transparent planarization layer 350 may include a light-transmitting inorganic material. For example, the transparent planarization layer 350 may include an oxide such as tetraethyl orthosilicate (TEOS). In this embodiment, similar to the super-optical structure 400A, the transparent planarization layer 350 may include an inorganic material to effectively prevent deformation (e.g., peeling, cracking, etc.) caused by the thermal expansion coefficient of the super-optical structure 400A.

[0100] Figure 9 This is a cross-sectional side view of an image sensor according to an embodiment.

[0101] Reference Figure 9 The image sensor 10F according to this embodiment has the same characteristics as... Figure 8 The image sensor 10E shown has a similar structure, except that the super-optical structure 400B includes a single-layer nanoprism structure layer. The first substrate structure 100 and the second substrate structure 200 are connected by a metal-dielectric hybrid bonding. An external bonding pad 390 is disposed on the second interconnect structure 220, the pad opening OP passes through the first substrate structure 100, and an organic material filling portion 385 is disposed in the ground connection structure 382. Unless otherwise specifically stated, the components of this embodiment can be understood by referring to... Figures 1 to 3 The image sensor 10 shown and Figure 8 The description of the same or similar components of the image sensor 10E shown is used for understanding.

[0102] Unlike previous embodiments, the super-optical structure 400B used in this embodiment may include a single-layer nanoprism structure layer. Specifically, the super-optical structure 400B may include a substrate dielectric layer 410, a nanoprism pattern NP' on the substrate dielectric layer 410, and a molding layer 421 covering the nanoprism pattern NP' on the substrate dielectric layer 410. Furthermore, in this embodiment, the anti-reflective layer 450L may be formed to the active pixel region (APR), the peripheral region (OB / CR), and the pad region (PDR) without any holes.

[0103] In this embodiment, with Figure 5 Similarly, in the embodiments described above, the first substrate structure 100 and the second substrate structure 200 can be connected by a metal-dielectric hybrid bonding.

[0104] Specifically, such as Figure 9As shown, the first bonding structure 190 and the second bonding structure 290 can be respectively disposed on the opposing surfaces of the first interconnect structure 120 and the second interconnect structure 220, and the first bonding structure 190 and the second bonding structure 290 can be electrically coupled and mechanically coupled. The first bonding structure 190 may include a first bonding insulating layer 191 disposed on the first interconnect structure 120, and a first bonding pad 195 electrically connected to the first interconnect 125 on the bonding surface of the first bonding insulating layer 191. Similarly, the second bonding structure 290 may include a second bonding insulating layer 291 disposed on the second interconnect structure 220, and a second bonding pad 295 electrically connected to the second interconnect 225 on the bonding surface of the second bonding insulating layer 291.

[0105] Through the intermetallic bonding of the first bonding pad 195 and the second bonding pad 295 and the dielectric bonding of the first bonding insulating layer 191 and the second bonding insulating layer 291, the first substrate structure 100 and the second substrate structure 200 can not only be firmly bonded to each other, but the first interconnect 125 and the second interconnect 225 can also be electrically connected through intermetallic bonding.

[0106] In this embodiment, the external bonding pad 390 may be disposed on the second substrate structure 200, particularly on the second interconnect structure 220. The pad opening OP may pass through the first substrate structure 100, and the external bonding pad 390 may be exposed through the pad opening OP.

[0107] The image sensor 10F according to this embodiment may include a third via TH3 extending through the first substrate 110 into the first interconnect structure 120 in the connection region CR. A ground connection structure 382 may extend into the third via TH3 and may include a conductor pattern connected to the first interconnect 125. An organic material filling portion 385 filled with organic material may be formed in the void V3 surrounded by the ground connection structure 382.

[0108] In this embodiment, the transparent planarization layer 350 may include a light-transmitting inorganic material similar to that in previous embodiments. The transparent planarization layer 350 may cover the ground connection structure 382 in the connection region CR and may contact the organic material filling portion 385. In this embodiment, the transparent planarization layer 350 may also include an inorganic material similar to the super-optical structure 400B to effectively prevent deformation (e.g., peeling, cracking, etc.) caused by the thermal expansion coefficient of the super-optical structure 400B.

[0109] According to an embodiment, similar to the super-optical structure, the transparent planarization layer beneath the super-optical structure may include inorganic materials to prevent deformation (e.g., peeling, cracking, etc.) caused by the coefficient of thermal expansion, thereby improving the reliability of the image sensor.

[0110] The various advantages and effects of this disclosure are not limited to those described above, and will be readily understood from the description of exemplary embodiments.

[0111] Although exemplary embodiments have been described and illustrated above, it will be apparent to those skilled in the art that modifications and alterations can be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. An image sensor, comprising: The stacked structure includes an active pixel region in which multiple pixels are arranged, and a connection region and a pad region located outside the active pixel region. The stacked structure further includes: A first substrate has a first surface and a second surface opposite to the first surface, the first substrate including a photoelectric conversion region for each of the plurality of pixels; A first interconnect structure is disposed on the second surface of the first substrate and includes a first interconnect and an insulating layer between the first interconnects; A second substrate is disposed on the first interconnect structure and includes logic elements for driving the plurality of pixels; A second interconnect structure is disposed between the second substrate and the first interconnect structure, and includes an insulating layer between the second interconnect and the second interconnect; A transparent planarization layer is disposed on the first surface of the first substrate and comprises an inorganic material; and A super-optical structure is disposed on the transparent planarization layer and includes multiple dielectric layers and a nanoprism pattern disposed in at least one of the multiple dielectric layers in the active pixel region.

2. The image sensor according to claim 1, wherein, The stacked structure further includes a first connection structure having a first conductor pattern extending through the first substrate and the first interconnect structure to the second interconnect structure in the connection region. The first conductor pattern electrically connects the first interconnect to the second interconnect. The first connection structure includes a gap surrounded by the first conductor pattern.

3. The image sensor according to claim 2, wherein, The transparent planarization layer includes a first extension that extends into and partially fills the gap in the first connection structure.

4. The image sensor according to claim 2, wherein, The first connecting structure further includes a first organic material filling portion, which fills the void.

5. The image sensor according to claim 2, wherein, The stacked structure further includes: External bonding pads, in the pad region on the first surface of the first substrate, and The second connection structure includes a second conductor pattern that extends through the first substrate and the first interconnect structure to the second interconnect structure on one side of the external bonding pad. The second conductor pattern electrically connects the external bonding pad to the second interconnect. The second connection structure includes a gap surrounded by the second conductor pattern.

6. The image sensor according to claim 5, wherein, The transparent planarization layer includes a second extension that extends into and partially fills the gap in the second connection structure.

7. The image sensor according to claim 5, wherein, The second connection structure further includes a second organic material filling portion, which fills the void.

8. The image sensor according to claim 1, wherein, The stacked structure further includes a first bonding structure and a second bonding structure, which are disposed between the first interconnect structure and the second interconnect structure and are bonded to each other. The first bonding structure includes a first bonding insulating layer on the first interconnect structure and a first bonding pad in the first bonding insulating layer, the first bonding pad being connected to the first interconnect. The second bonding structure includes a second bonding insulating layer on the second interconnect structure and bonded to the first bonding insulating layer, and a second bonding pad in the second bonding insulating layer, wherein the second bonding pad is connected to the second interconnect and bonded to the first bonding pad respectively.

9. The image sensor according to claim 8, wherein, The stacked structure further includes: External bonding pads, in the pad region on the first surface of the first substrate, and A pad connection structure has a conductor pattern that extends through the first substrate to the first interconnect structure on one side of the external bonding pad, the conductor pattern electrically connecting the external bonding pad and the first interconnect. The pad connection structure includes a gap surrounded by the conductor pattern.

10. The image sensor according to claim 9, wherein, The transparent planarization layer includes an extension that extends into and partially fills the gap.

11. The image sensor according to claim 9, wherein, The pad connection structure also includes an organic material filling portion, which fills the gap.

12. The image sensor according to claim 8, wherein, The stacked structure further includes: External bonding pads are disposed on the area of ​​the second interconnect structure exposed by pad openings, the pad openings extending through the first substrate to the second interconnect structure in the pad area. A ground connection structure having a conductor pattern extending through the first substrate to the first interconnect structure in the connection region, the conductor pattern being electrically connected to the first interconnect, and... The grounding connection structure also includes a gap surrounded by the conductor pattern.

13. The image sensor according to claim 1, further comprising a color filter disposed on the first substrate in the active pixel region.

14. The image sensor according to claim 1, wherein, The plurality of dielectric layers include a base dielectric layer located on the transparent planarization layer, and at least one molded layer having a nanoprism pattern on the base dielectric layer.

15. The image sensor according to claim 14, wherein, The at least one molding layer further includes: The first molding layer has a first nano-prism pattern; A second molding layer is disposed on the first molding layer and has a second nanoprism pattern; and A third molding layer is disposed on the second molding layer and has a third nanoprism pattern.

16. The image sensor according to claim 14, wherein, The super-optical structure also includes an anti-reflective layer on the at least one molded layer.

17. An image sensor, comprising: The stacked structure includes an active pixel region in which multiple pixels are arranged, and a connection region and a pad region located outside the active pixel region. The stacked structure further includes: A first substrate has a first surface and a second surface opposite to the first surface, the first substrate including a photoelectric conversion region for each of the plurality of pixels; A first interconnect structure is disposed on the second surface of the first substrate and includes a first interconnect and an insulating layer between the first interconnects; A second substrate is disposed on the first interconnect structure and includes logic elements for driving the plurality of pixels; A second interconnect structure is disposed between the second substrate and the first interconnect structure, and includes an insulating layer between the second interconnect and the second interconnect; A transparent planarization layer is disposed on the first surface of the first substrate and comprises an inorganic material; A super-optical structure is disposed on the transparent planarization layer and includes multiple dielectric layers and a nanoprism pattern disposed in at least one of the multiple dielectric layers in the active pixel region. A first connection structure having a first conductor pattern extending through the first substrate and the first interconnect structure to a second interconnect structure in the connection region, the first conductor pattern electrically connecting the first interconnect to the second interconnect. External bonding pads, located on the first surface of the first substrate in the pad region; and The second connection structure has a second conductor pattern that extends through the first substrate and the first interconnect structure to the second interconnect structure on one side of the external bonding pad, and the second conductor pattern electrically connects the external bonding pad to the second interconnect.

18. The image sensor according to claim 17, wherein, The transparent planarization layer includes a first extension and a second extension, the first extension partially filling a first gap in the first connection structure surrounded by the first conductor pattern, and the second extension partially filling a second gap in the second connection structure surrounded by the second conductor pattern.

19. An image sensor, comprising: The stacked structure includes an active pixel region defining a plurality of pixels, and a connection region and a pad region located outside the active pixel region. The stacking structure includes: A first substrate has a first surface and a second surface opposite to the first surface, the first substrate including a photoelectric conversion region for each of the plurality of pixels; A first interconnect structure is disposed on the second surface of the first substrate and includes a first interconnect and an insulating layer between the first interconnects; A second substrate is disposed on the first interconnect structure and includes logic elements for driving the plurality of pixels; A second interconnect structure is disposed between the second substrate and the first interconnect structure, and includes an insulating layer between the second interconnect and the second interconnect; A first bonding structure is disposed between the first interconnect structure and the second interconnect structure, and includes a first bonding insulating layer and a first bonding pad connected to the first interconnect in the first bonding insulating layer; The second bonding structure is disposed between the first bonding structure and the second interconnect structure, and includes a second bonding insulating layer bonded to the first bonding insulating layer, and a second bonding pad connected to the second interconnect in the second bonding insulating layer and bonded to the first bonding pad respectively. A transparent planarization layer is disposed on the first surface of the first substrate and comprises an inorganic material; A super-optical structure is disposed on the transparent planarization layer and includes multiple dielectric layers and a nanoprism pattern disposed in at least one of the multiple dielectric layers in the active pixel region; and An external bonding pad is disposed on the area of ​​the second interconnect structure exposed by a pad opening, the pad opening passing through the first substrate to reach the second interconnect structure in the pad area.

20. The image sensor according to claim 19, wherein, The stacked structure further includes a ground connection structure having a conductor pattern extending through the first substrate to the first interconnect structure in the connection region, the conductor pattern being electrically connected to the first interconnect. The transparent planarization layer includes an extension that partially fills the gaps surrounded by the conductor pattern of the ground connection structure.

Images