Image sensor and manufacturing method

Abstract

This invention relates to an image sensor and a manufacturing method thereof, and more particularly to an image sensor and a manufacturing method thereof that prevents damage that may occur on a semiconductor layer on the side where the floating diode is formed by forming a plug structure between a floating diode and a metal contact electrically connected to the floating diode.

Description

Technical Field

[0001] This invention relates to an image sensor and a manufacturing method thereof, and more particularly to an image sensor and a manufacturing method thereof that prevents damage that may occur on a semiconductor layer on the side where the floating diode is formed by forming a plug structure between a floating diode and a metal contact electrically connected to the floating diode. Background Technology

[0002] Image sensors, as imaging devices that generate images in devices such as mobile phone cameras, can be classified into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors based on their manufacturing process and application. Among these, CMOS image sensors are widely used in general semiconductor chip manufacturing processes due to their excellent integration competitiveness, cost-effectiveness, and ease of connection with peripheral chips.

[0003] Figure 1 This is a cross-sectional view of a conventional image sensor according to the present invention. Next, we will refer to... Figure 1 The structure of the existing image sensor 9 and its problems are explained in detail.

[0004] See Figure 1 The existing image sensor 9 may include a photodiode 920 within a semiconductor layer 910 and a floating diode 930 on a side spaced apart from the photodiode 920. Furthermore, an insulating film layer 940 is formed on the semiconductor layer 910, and a metal contact 950 may be formed in a shape that extends through the insulating film layer 940. The metal contact 950, as described above, is made of, for example, tungsten (W), extends vertically within the insulating film layer 940, and its bottom surface is connected to the floating diode 930, while its upper surface may be connected to a metal wiring (not shown).

[0005] During the reactive ion etching process performed to form the metal contact 950 connected to the floating diode 930 as described above, damage may occur on the semiconductor layer 910 on the side where the floating diode 930 is formed. Furthermore, during the metal layer gap filling within the insulating film layer 940 to form the metal contact 950, contamination may occur due to the metal layer penetrating into the floating diode 930. In such cases, dark current may be generated in the pixel area, which could lead to a decrease in device reliability.

[0006] To address the problems described above, the inventors of this invention provide a novel image sensor and its manufacturing method, the details of which will be explained later.

[0007] Prior technology documents

[0008] Patent documents

[0009] US Patent 9,054,106 B2, "Semiconductor Structure and Method for Manufacturing the Semiconductor" Summary of the Invention

[0010] Technical issues

[0011] The present invention aims to solve the problems existing in the prior art as described above.

[0012] The purpose of this invention is to provide an image sensor and a manufacturing method thereof that can prevent damage that may occur on the semiconductor layer on the side where the floating diode is formed by forming a plug structure between the floating diode and the metal contacts electrically connected to the floating diode.

[0013] Furthermore, the present invention aims to provide an image sensor and a manufacturing method thereof that can prevent the floating diode from being contaminated by metallic substances during the formation of metal contacts by forming a plug structure on the floating diode in advance.

[0014] Furthermore, the present invention aims to provide an image sensor and a manufacturing method thereof that can suppress leakage current generated from the surface of a semiconductor layer in the pixel region by forming a pinning layer on one side of the surface of a floating diode.

[0015] Furthermore, the present invention aims to provide an image sensor and a manufacturing method thereof that can ensure the connection between the floating diode and the plug structure by forming a pinning layer only in a portion of the surface of the floating diode.

[0016] Furthermore, the present invention aims to provide an image sensor and manufacturing method that achieve engineering convenience by directly connecting the plug structure and the drive gate via a polycrystalline silicon film.

[0017] Furthermore, the present invention aims to provide an image sensor and a manufacturing method thereof that can prevent damage that may occur on the semiconductor layer on the side where the floating diode is formed by means of a wet etching process to remove the first insulating film on the floating diode.

[0018] Technical solution

[0019] To achieve the objectives described above, the present invention can be implemented through embodiments configured as follows.

[0020] In one embodiment of the present invention, the image sensor according to the present invention is characterized by comprising: a semiconductor layer; a photodiode located within the semiconductor layer; a floating diode located within the semiconductor layer; a plug structure having a side on the semiconductor layer connected to the floating diode; and a metal contact connected to the plug structure.

[0021] In another embodiment of the present invention, the image sensor according to the present invention is characterized by further comprising a first pinning layer, wherein the first pinning layer is a first conductive impurity doped region on one side of the surface of the photodiode.

[0022] In another embodiment of the present invention, the image sensor according to the present invention is characterized by further comprising a second pinning layer, the second pinning layer being a first conductive impurity doped region on one side of the surface of the floating diode.

[0023] In another embodiment of the invention, the image sensor according to the invention is characterized in that the second pinning layer has a smaller horizontal width compared to the floating diode.

[0024] In yet another embodiment of the present invention, the image sensor according to the present invention is characterized in that the plug structure is a polycrystalline silicon film.

[0025] In another embodiment of the invention, the image sensor according to the invention is characterized in that the bottom surface of the plug structure is in contact with the floating diode.

[0026] In another embodiment of the present invention, the image sensor according to the present invention is characterized in that it further includes a plug insulating film, the plug insulating film being located between the plug structure and the floating diode, the plug insulating film being located on the bottom surface of the plug structure adjacent to one or both sides of the plug structure.

[0027] In another embodiment of the invention, the image sensor according to the invention is characterized in that the plug structure has a stepped portion on the bottom surface.

[0028] In another embodiment of the invention, the image sensor according to the invention is characterized in that it further includes a plug spacer located on the sidewall of the plug structure.

[0029] In another embodiment of the present invention, the image sensor according to the present invention is characterized in that it further includes a drive gate located on the semiconductor layer, the drive gate being physically connected to the plug structure.

[0030] In another embodiment of the invention, the image sensor according to the invention is characterized in that it further includes an element separation film located within the semiconductor layer, and the drive gate is connected to the plug structure by means of a polycrystalline silicon film that is in contact with and extends on the element separation film.

[0031] In another embodiment of the present invention, the image sensor according to the present invention is characterized by comprising: a pixel region, which receives incident light; a logic region located at the periphery of the pixel region; a semiconductor layer; a photodiode located within the semiconductor layer in the pixel region; a floating diode located within the semiconductor layer in the pixel region; a plug structure having a side on the semiconductor layer connected to the floating diode; a metal contact connected to the plug structure; and a logic gate comprising a first gate and a second gate on the semiconductor layer in the logic region.

[0032] In another embodiment of the invention, the image sensor according to the invention is characterized in that the plug structure is formed together with the logic gate in the same engineering process.

[0033] In another embodiment of the invention, the image sensor according to the invention is characterized by further comprising: a drive gate located on the semiconductor layer; and a polycrystalline silicon film located on the semiconductor layer, which connects the drive gate and the plug structure between the drive gate and the plug structure.

[0034] In another embodiment of the present invention, the image sensor according to the present invention is characterized in that it further includes: a first gate insulating film located between the first gate and the semiconductor layer; a second gate insulating film located between the second gate and the semiconductor layer; and a plug insulating film located between the plug structure and the semiconductor layer, wherein the first gate insulating film has a thicker upper and lower thickness compared to the second gate insulating film.

[0035] In another embodiment of the invention, the image sensor according to the invention is characterized in that the plug insulating film has a thicker upper and lower thickness compared to the second door insulating film.

[0036] In another embodiment of the invention, the image sensor according to the invention is characterized in that at least one side of the floating diode is surrounded by the photodiode.

[0037] In one embodiment of the present invention, the image sensor manufacturing method according to the present invention is characterized by comprising: a step of forming a first insulating film having a first thickness on a semiconductor layer; a step of forming a first opening on a floating diode by etching one side of the first insulating film; a step of forming a polycrystalline silicon film on the first insulating film and filling the first opening; a step of forming a plug structure having a side connected to the floating diode on a logic gate and the floating diode by etching the polycrystalline silicon film; a step of forming an insulating film layer on the semiconductor layer in a manner covering the logic gate and the plug structure; and a step of forming a metal contact in a shape penetrating the insulating film layer in a manner connected to the plug structure.

[0038] In another embodiment of the invention, the image sensor manufacturing method according to the invention is characterized by comprising: a step of forming a second opening by etching the other side of the first insulating film; and a step of forming a second insulating film having a second thickness on the semiconductor layer opened by means of the second opening, wherein the first thickness has a larger value than the second thickness.

[0039] In another embodiment of the present invention, the image sensor manufacturing method according to the present invention is characterized by further comprising the step of forming spacers on the sidewalls of the logic gate and the plug structure.

[0040] Invention Effects

[0041] The present invention can achieve the effects described below through the configuration described above.

[0042] The present invention can prevent damage that may occur on the semiconductor layer on the side where the floating diode is formed by forming a plug structure between the floating diode and the metal contacts electrically connected to the floating diode.

[0043] Furthermore, the present invention can prevent the floating diode from being contaminated by metallic substances during the formation of metal contacts by forming a plug structure on the floating diode in advance.

[0044] Furthermore, the present invention can suppress leakage current generated from the surface of the semiconductor layer in the pixel region by forming a pinning layer on one side of the surface of the floating diode.

[0045] Furthermore, the present invention can ensure that the floating diode is connected to the plug structure by forming a pinning layer only in a portion of the surface of the floating diode.

[0046] Furthermore, the present invention achieves engineering convenience by allowing the plug structure and the drive gate to be directly connected by means of a polycrystalline silicon film.

[0047] Furthermore, the present invention can prevent damage that may occur on the semiconductor layer on the side where the floating diode is formed by removing the first insulating film on the floating diode in advance by means of a wet etching process.

[0048] Furthermore, it should be noted that even effects not explicitly mentioned herein, the effects and potential effects described in the following description that can be achieved according to the technical features of the present invention should be understood as described in the description of the present invention. Attached Figure Description

[0049] Figure 1 This is a cross-sectional view of an existing image sensor.

[0050] Figure 2 This is a plan view of an image sensor according to one embodiment of the present invention.

[0051] Figure 3 This is a plan view of an image sensor according to a first embodiment of the present invention.

[0052] Figure 4 It is based on Figure 3 A cross-sectional view of the image sensor.

[0053] Figure 5 This is a plan view of an image sensor according to a second embodiment of the present invention.

[0054] Figure 6 It is based on Figure 5 A cross-sectional view of the image sensor.

[0055] Figure 7 It is based on Figure 5 A cross-sectional view of the image sensor at the CC' position.

[0056] Figure 8 This is a plan view of an image sensor according to a third embodiment of the present invention.

[0057] Figure 9 It is based on Figure 8 A cross-sectional view of the DD' section of the image sensor.

[0058] Figure 10 It is based on Figure 8 A cross-sectional view of the image sensor EE'.

[0059] Figures 11 to 17 This is a cross-sectional view used to illustrate an image sensor manufacturing method according to one embodiment of the present invention.

[0060] Symbol Explanation

[0061] 1: Image sensor according to the first embodiment, 110: semiconductor layer, 111: element separation film, 121: photodiode, 121a: first impurity region, 121b: second impurity region / first pinning layer, 123: floating diode, 123a: third impurity region, 123b: fourth impurity region / second pinning layer, 125, 125a, 125b: source / drain, 127: well region, 127a: first well region, 127b: second well region, 141: transmission gate, 143: reset gate, 145: drive gate, 147: selection gate, 149: logic gate, 149a: first gate, 149b: second gate, 1 51: Gate insulating film, 151a: First gate insulating film, 151b: Second gate insulating film, 153: Gate spacer, 160: Plug structure, 160a: Step section, 161: Plug insulating film, 163: Plug spacer, 170: Insulating film layer, 180: Metal contact, 190: Silicate film, P: Pixel area, P1: Unit pixel area, L: Logic area, Tx: Transmission transistor, Rx: Reset transistor, Dx: Drive transistor, Sx: Select transistor, PS: Polysilicon film, I1: First insulating film, I2: Second insulating film, T1: First thickness, T2: Second thickness, O1: First opening, O2: Second opening. Detailed Implementation

[0062] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The embodiments of the present invention can be modified in many different ways and should not be construed as limiting the scope of the invention to the following embodiments, but should be interpreted based on the matters set forth in the claims. Furthermore, the following embodiments are provided for reference only to illustrate the invention more completely to those skilled in the art.

[0063] It is important to note that in the following text, when a component (or layer) is described as being positioned on top of other components (or layers), the component can be positioned directly above other components, or other components or layers can exist between the corresponding components. Furthermore, when a component is described as being positioned directly on or above other components, no other components will exist between the corresponding components. Additionally, the terms "above," "upper part," "lower part," "upper side," "lower side," or "one side" used to describe a component represent relative positional relationships.

[0064] In addition, terms such as first and second may be used to describe various items such as multiple elements, regions and / or parts, but the items are not limited by these terms.

[0065] Furthermore, it should be noted that when a particular embodiment can be implemented in different ways, the specific engineering sequence may be executed in a manner different from that described below. For example, two engineering steps described consecutively may actually be executed simultaneously or in reverse order.

[0066] In addition, the conductivity type or doped region of the constituent elements may be specified as "P-type" or "N-type" according to their main charge carrier characteristics, but this is only for the convenience of explanation, and the technical concept of the present invention is not limited by the illustrative content. For example, "P-type" or "N-type" in the following content may also be represented by the more general terms "first conductivity type" or "second conductivity type", wherein the first conductivity type represents the P-type and the second conductivity type represents the N-type.

[0067] Furthermore, the terms "high concentration" and "low concentration" used to indicate the doping concentration of impurity regions should be understood as representing the relative doping concentration of one constituent element to another.

[0068] Furthermore, it should be noted that the image sensor according to the present invention is applicable not only to front-illuminated image sensors but also to back-illuminated image sensors.

[0069] Next, on the illustrated plan view, the x-axis direction is set as the "first direction" and the y-axis direction is set as the "second direction".

[0070] Figure 2 This is a plan view of an image sensor according to one embodiment of the present invention.

[0071] See Figure 2 A pixel region P and a logic region L can be formed on the image sensor according to the present invention. The pixel region P is a region that absorbs light incident from the outside, while the logic region L is a region that constitutes the periphery of the pixel region. The pixel region P may include a plurality of unit pixel regions P1. Furthermore, pads (PADs) (not shown) for electrical connection with external terminals can be formed on the logic region L.

[0072] Figure 3 This is a plan view of an image sensor according to a first embodiment of the present invention, and Figure 4 It is based on Figure 3 A cross-sectional view of the image sensor.

[0073] Next, the image sensor 1 according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings. The image sensor described below, as an example, may be a complementary metal-oxide-semiconductor (CMOS) image sensor.

[0074] See Figure 3 as well as Figure 4 The present invention relates to an image sensor 1, and more particularly to an image sensor and a method thereof that can prevent damage that may occur on the semiconductor layer on the side where the floating diode is formed by forming a plug structure between a floating diode and a metal contact electrically connected to the floating diode, thereby blocking the generation of dark current in the pixel region P.

[0075] Therefore, the image sensor 1 according to the first embodiment may firstly include a semiconductor layer 110. The semiconductor layer 110 is, for example, configured to include an epitaxial layer and be formed together in the pixel region P and the logic region L. Furthermore, the semiconductor layer 110 may, as an example, be a low-concentration first conductivity type impurity doped region. In addition, a plurality of element separation films 111 may be formed at intervals from the surface of the semiconductor layer 110 to a certain depth. The element separation films 111, as described above, define active regions and can be formed by performing a shallow trench isolation (STI) process.

[0076] Furthermore, within a unit pixel region P1, photodiodes 121 and floating diodes 123 can be formed spaced apart from each other within the semiconductor layer 110. As an example, photodiodes 121 and floating diodes 123 can be formed on one side of the surface of the semiconductor layer 110. Photodiode 121 is the region that generates charge in response to incident light, while floating diode 123 is the region that sequentially reads out the charge stored in photodiode 121 according to a readout timing sequence. As described above, both photodiode 121 and floating diode 123 can be second-conductivity impurity-doped regions.

[0077] The photodiode 121 is preferably a pinned photodiode. As described above, the photodiode 121 can be manufactured by performing ion implantation on the semiconductor layer 110 to form a first impurity region 121a and a second impurity region 121b of the second conductivity type. In this case, the second impurity region 121b is formed above the first impurity region 121a. The first impurity region 121a is a low-concentration doped region of the second conductivity type, while the second impurity region 121b is preferably a high-concentration doped region of the first conductivity type compared to the epitaxial layer of the semiconductor layer 110. The first impurity region 121a is the region that functions as a photodiode, while the second impurity region 121b is equivalent to a pinned layer.

[0078] Furthermore, the floating diode 123 is also preferably a pinned floating diode. As described above, the floating diode 123, like the photodiode 121, can also include a third impurity region 123a of the second conductivity type and a fourth impurity region 123b of the first conductivity type. In this case, the fourth impurity region 123b is formed on one side of the surface of the semiconductor layer 110, and it is preferably formed only in a portion of the area, connected to the plug structure 160 (which will be described later) and one side of the floating diode 123. For example, it is preferable that the fourth impurity region 123b is not formed on the central side of the floating diode 123, but rather on the edge or corner side of the floating diode 123. By adopting the configuration described above, leakage current generated from the surface of the semiconductor layer 110 can be suppressed. The third impurity region 123a is the region that functions as a floating diode, while the fourth impurity region 123b is the region equivalent to a pinned layer. Hereinafter, the pinned layer 121b of the photodiode 121 will be referred to as the "first pinned layer," and the pinned layer 123b of the floating diode 123 will be referred to as the "second pinned layer."

[0079] Furthermore, multiple source / drain regions 125 can be formed between each other within the unit pixel region P1 and the logic region L.

[0080] Furthermore, a transmission gate 141, a reset gate 143, a drive gate 145, and a selection gate 147 may be formed on the semiconductor layer 110 of the unit pixel region P1, spaced apart from each other.

[0081] The source / drain regions 125 described above can be formed within the semiconductor layer 110 in such a manner that each gate 143 is interposed. Thereby, a transmission transistor Tx can be formed on the side of transmission gate 141, a reset transistor Rx can be formed on the side of reset gate 143, a drive transistor Dx can be formed on the side of drive gate 145, and a select transistor Sx can be formed on the side of select gate 147.

[0082] For example, the transmission transistor Tx is configured to connect or disconnect between the photodiode 121 and the floating diode 123, and can be formed between the photodiode 121 and the floating diode 123. Furthermore, the reset transistor Rx is formed between the transmission transistor Tx and the drive transistor Dx, and can reset the stored charge of the floating diode 123 by resetting the voltage of the floating diode 123 to the power supply voltage.

[0083] Furthermore, the selection transistor Sx amplifies the voltage of the floating diode 123, while the drive transistor Dx selectively outputs the amplified voltage according to the selection signal. As an example, the drive transistor Dx can be formed between the reset transistor Rx and the selection transistor Sx.

[0084] Furthermore, a pair of logic gates 149 can be formed on the semiconductor layer 110 of the logic region L. Hereinafter, the pair of logic gates 149 will be referred to as "first gate 149a" and "second gate 149b," respectively. As an example, one of the first gate 149a and the second gate 149b can be a gate of a P-type metal-oxide-semiconductor (PMOS) transistor, while the other can be a gate of an N-type metal-oxide-semiconductor (NMOS) transistor. Furthermore, one of the first gate 149a and the second gate 149b can be loaded with a high voltage (HV), while the other can be loaded with a low voltage (LV). Hereinafter, for ease of explanation, the gate loaded with a high voltage (HV) will be referred to as the first gate 149a. Source / drain regions 125 can be formed within the semiconductor layer 110 on both sides of the first gate 149a and the second gate 149b.

[0085] For example, a first conductivity type high-concentration doped region, i.e., a source / drain region 125a, can be formed on both sides of the first gate 149a, and a second conductivity type high-concentration doped region, i.e., a source / drain region 125b, can be formed on both sides of the second gate 149b. Furthermore, within the semiconductor layer 110, a second conductivity type doped region, i.e., a first well region 127a, can be formed around the source / drain region 125a, and a first conductivity type doped region, i.e., a second well region 127b, can be formed around the source / drain region 125b. Hereinafter, the first well region 127a and the second well region 127b will be collectively referred to as well region 127.

[0086] The gates 141 to 149 described above may include a polycrystalline silicon film. Furthermore, a gate insulating film 151 may be formed between each gate 141 to 149 and the semiconductor layer 110. The gate insulating film 151, as an example, may include a silicon oxide film, a high-dielectric-constant film, or a combination thereof. Furthermore, the gate insulating film 151 may be formed by processes such as atomic layer deposition (ALD), chemical vapor deposition (CVP), or physical vapor deposition (PVD). Furthermore, the first thickness T1 of the first gate insulating film 151a under the first gate 149a when a high voltage (HV) is applied may have a larger value than the second thickness T2 of the second gate insulating film 151b under the second gate 149b when a low voltage (LV) is applied (T1>T2). Furthermore, gate spacers 153 may be formed on the sidewalls of each gate 141 to 149. The gate spacer 153 described above may, as an example, include an oxide film or a nitride film, but the scope of the invention is not limited thereto.

[0087] Furthermore, a plug structure 160 can be formed on the semiconductor layer 110 on the side where the floating diode 123 is formed. The plug structure 160 is formed together with the gates 141 to 149, and may include, for example, a polysilicon film. Furthermore, a gate insulating film 151 may not be formed between the plug structure 160 and the floating diode 123. That is, because the floating diode 123 needs to be electrically connected to the metal contacts 180 described later, a gate insulating film 151 may not be formed between the plug structure 160 and the floating diode 123.

[0088] Alternatively, a plug insulating film 161, identical to the gate insulating film 151, can be formed only in a portion of the area between the plug structure 160 and the floating diode 123. That is, the plug insulating film 161 can be formed only on the underside of the plug structure 160, and only in a portion of the area to allow the floating diode 123 and the metal contacts 180 connected to the floating diode 123 to be electrically connected to each other, thereby giving the floating diode 123 a side that connects to the plug structure 160.

[0089] Therefore, at least one side of the bottom surface of the plug structure 160 can be connected to the upper side of the floating diode 123. For this purpose, the plug insulating film 161 can be formed on the bottom surface of the plug structure 160 at one side or at both sides spaced apart. When the plug insulating film 161 is formed as described above, a step portion 160a can be formed on the bottom surface of the plug structure 160. The step portion 160a is formed on the bottom surface of the plug structure 160 in a stepped shape corresponding to the plug insulating film 161. In this case, the plug insulating film 161 can have a value substantially the same as the first thickness T1.

[0090] Furthermore, plug spacers 163 may be formed on both side walls of the plug structure 160. The plug spacers 163 are configurations corresponding to the door spacers 153 and can be formed together with the door spacers 153 in the same process.

[0091] Furthermore, an insulating film layer 170 may be formed on the semiconductor layer 110 in such a way that it covers the various gates 141 to 149 and the plug structure 160. The insulating film layer 170 may, as an example, comprise a nitride film or an oxynitride film, but the scope of the invention is not limited by the specific examples.

[0092] Furthermore, as a structure penetrating the insulating film layer 170, a plurality of metal contacts 180 can be formed along the vertical direction, thereby electrically connecting to each source / drain region 125, each gate 141 to 149, and the plug structure 160. In addition, the metal contacts 180 connected to the drive gate 145 and the metal contacts 180 connected to the plug structure 160 can be electrically connected to each other by means of metal wiring (not shown).

[0093] At this time, a silicide film 190 can be formed on the source / drain region 125 on the side connected to the metal contact 180 and on each of the gates 141 to 149. The silicide film 190 can be formed using a metal film such as cobalt (Co), nickel (Ni), or titanium (Ti) through self-aligned silicide (Salicide) engineering to improve contact resistance and ensure thermal stability. Furthermore, it is preferable not to form the silicide film 190 on the plug structure 160.

[0094] According to a first embodiment of the present invention, the metal contact 180 is not directly physically connected to the floating diode 123, but is connected to the plug structure 160. Therefore, when performing an etching process (e.g., reactive ion etching) to form the metal contact 180, damage to the semiconductor layer 110 on the side of the floating diode 123 can be prevented. Furthermore, contamination of the floating diode 123 by the metal material used to form the metal contact 180 can be prevented. In this way, the phenomenon of dark current generation in the pixel region P can be suppressed by means of the plug structure 160. This has a more significant effect when applied to image sensors using a global shutter method where the time electrons remain in the floating diode 123 is shorter than that of a rolling shutter method. However, it should be noted that the image sensor 1 according to the present invention is not limited to a global shutter method.

[0095] Figure 5 This is a plan view of an image sensor according to a second embodiment of the present invention. Figure 6 It is based on Figure 5 The BB' cross-sectional view of the image sensor, and Figure 7 It is based on Figure 5 A cross-sectional view of the image sensor at the CC' position.

[0096] Next, the image sensor 2 according to the second embodiment of the present invention will be described in detail with reference to the accompanying drawings. The only difference between the image sensor 2 according to the second embodiment and the image sensor 1 according to the first embodiment is the plug structure 260, therefore, only the plug structure 260 will be described in detail below. In addition, for the configuration corresponding to the image sensor 1 according to the first embodiment, the first digit of the drawing number is changed from "1" to "2".

[0097] See Figures 5 to 7The image sensor 2 according to the second embodiment has a plug structure 260. The plug structure 260 can be connected to the drive gate 245. As an example, a single polysilicon film PS can extend on the semiconductor layer 110 from the region where the drive transistor Dx is formed to the region where the floating diode 223 is formed. In this case, the polysilicon film PS can be formed across the element separation film 221 from the region where the drive transistor Dx is formed to the region where the floating diode 223 is formed.

[0098] Furthermore, a gate insulating film 251 and a plug insulating film 261 can be formed between the polysilicon film PS and the semiconductor layer 210. The gate insulating film 251 and the plug insulating film 261, as described above, can have sides that are physically connected to each other. As an example, the gate insulating film 251 and the plug insulating film 261 can be constructed as a single structure. In this case, it is preferable that the plug insulating film 261 is formed in a manner that covers a portion of the upper side of the floating diode 223. Alternatively, as another example, the plug insulating film 261 may not be formed to cover at least a portion of the upper side of the floating diode 223. That is, between the polysilicon film PS and the semiconductor layer 210, the gate insulating film 251 can be formed in a manner that extends across the element separation film 211 to the side adjacent to the floating diode 233 but does not cover the side of the floating diode 233.

[0099] Figure 8 This is a plan view of an image sensor according to a third embodiment of the present invention. Figure 9 It is based on Figure 8 The image sensor's DD' cross-sectional view, and Figure 10 It is based on Figure 8 A cross-sectional view of the image sensor EE'.

[0100] Next, the image sensor 3 according to the third embodiment of the present invention will be described in detail with reference to the accompanying drawings. The image sensor 3 according to the third embodiment may be, for example, an X-ray sensor, and may not have a transmission transistor. Furthermore, for the configuration corresponding to the image sensor 1 according to the first embodiment, the first digit of the drawing number is changed from "1" to "3".

[0101] See Figures 8 to 10 The image sensor 3 according to the third embodiment may include a floating diode 323 located within the photodiode 321 in the semiconductor layer 310. Furthermore, a plug structure 360 ​​is formed on the photodiode 321, and the plug structure 360 ​​may be substantially the same as the plug structure 160 according to the first embodiment or the plug structure 260 according to the second embodiment.

[0102] Figures 11 to 17This is a cross-sectional view used to illustrate a method for manufacturing an image sensor according to one embodiment of the present invention. It should be noted that... Figures 11 to 17 The peripheral structures of the floating diode (such as the transfer transistor and photodiode) have been omitted above.

[0103] Next, a method for manufacturing an image sensor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. For ease of explanation, only the formation process of the plug structure 160 on the semiconductor layer 110 will be described below.

[0104] See Figure 11 First, a first insulating film I1 can be formed on the semiconductor layer 110. The first insulating film I1 may include a silicon oxide film, a high dielectric constant film, or a combination thereof. As an example, the first insulating film I1 may be a silicon oxide film formed by performing a thermal oxidation process. In this case, the first insulating film I1 may have a first thickness T1 along the vertical direction.

[0105] See Figure 12 Next, the first insulating film I1 on the side forming the second gate 149b can be removed. For example, the first insulating film I1 on the side forming the second gate 149b can be removed by performing an etching process after forming a mask pattern (not shown) on the first insulating film I1. Through this process, a first opening O1 can be formed on the first insulating film I1 on the side forming the second gate 149b, thereby exposing the upper side surface of the semiconductor layer 110.

[0106] See Figure 13 A second insulating film I2 can be formed on the semiconductor layer 110 on the side of the first opening O1 through subsequent processes. The second insulating film I2 may include a silicon oxide film, a high dielectric constant film, or a combination thereof. As an example, the second insulating film I2 may be a silicon oxide film formed by performing a thermal oxidation process. Furthermore, the second insulating film I2 has a second thickness T2 along the vertical direction, and the second thickness T2 may have a smaller value (T2) compared to the first thickness T1. <T1)。

[0107] See Figure 14Next, the first insulating film I1 on the upper side of the semiconductor layer 110 forming the floating diode 123 can be removed, thereby opening at least one side of the floating diode 123. This can be done by performing an etching process such as a wet etching process using a mask pattern (not shown) on the first insulating film I1. This allows a second opening O2 to be formed on the upper side of the floating diode 123. By performing a wet etching process as described above, damage to the semiconductor layer 110 can be prevented. In the above example, the case where the second opening O2 is formed after the first opening O1 is described, but in some cases, the second opening O2 can be formed first, or a pair of openings O1 and O2 can be formed simultaneously in the same process, without particular limitation.

[0108] See Figure 15 Next, a polycrystalline silicon film PS can be deposited on the first insulating film I1, the second insulating film I2, and in a manner that fills the opening O.

[0109] See Figure 16 Next, the polycrystalline silicon film PS and, in some cases, the first insulating film I1 beneath the polycrystalline silicon film PS can be etched to form the gates 141 to 149 and the plug structure 160. Furthermore, a gate insulating film 151 is formed beneath each of the gates 141 to 149, while a plug insulating film 161 may or may not be formed beneath the plug structure 160. Additionally, the first gate insulating film 151a beneath the first gate 149a may have a first thickness T1, and the second gate insulating film 151b beneath the second gate 149b may have a second thickness T2.

[0110] Next, gate spacers 153 can be formed on the sidewalls of each of the gates 141 to 149, and plug spacers 163 can be formed on the sidewalls of the plug structure 160. This process can be performed by etching after depositing a third insulating film (not shown) to cover the gates 141 to 149 and the plug structure 160. Next, source / drain regions 125 can be formed by performing ion implantation within the semiconductor layer 110.

[0111] Next, a self-aligned silicide process can be performed to form a silicide film 190 on the upper side of the source / drain regions 125 and each of the gates 141 to 149.

[0112] See Figure 17 Next, an insulating film layer 170 covering each gate 141 to 149 and the plug structure 160 can be formed on the semiconductor layer 110. Then, the insulating film layer 170 can be etched using a mask pattern (not shown) and metal contacts 180 can be formed by filling the gaps in the metal layer.

[0113] The detailed description above is merely illustrative of the invention. Furthermore, the foregoing description is only a preferred embodiment of the invention, and the invention can be used in many different combinations, modifications, and environments. That is, changes or modifications can be made within the scope of the concept of the invention disclosed in this specification and / or within the technical or knowledge scope of the industry. The embodiments described above are merely illustrative of the best state for implementing the technical idea of ​​the invention, but various modifications can be made according to the specific application field and usage requirements of the invention. Therefore, the invention is not limited to the embodiments disclosed in the detailed description of the invention above.

Claims

1. An image sensor, characterized in that, include: Semiconductor layer; A photodiode, located within the semiconductor layer; A floating diode, located within the semiconductor layer; A plug structure having one side on the semiconductor layer that is connected to the floating diode; as well as Metal contacts that are connected to the plug structure.

2. The image sensor according to claim 1, characterized in that, It also includes a first pinning layer, which is a first conductive impurity doped region on one side of the surface of the photodiode.

3. The image sensor according to claim 1, characterized in that, It also includes a second pinning layer, which is a first conductive impurity doped region on one side of the surface of the floating diode.

4. The image sensor according to claim 3, characterized in that, The second pinning layer has a smaller horizontal width compared to the floating diode.

5. The image sensor according to claim 1, characterized in that, The plug structure is a polycrystalline silicon film.

6. The image sensor according to claim 1, characterized in that, The bottom surface of the plug structure is in contact with the floating diode.

7. The image sensor according to claim 1, characterized in that, It also includes a plug insulating film, which is located between the plug structure and the floating diode. The plug insulating film is located on the bottom surface of the plug structure, adjacent to one or both sides of the plug structure.

8. The image sensor according to claim 7, characterized in that, The plug structure has a stepped section on the bottom surface.

9. The image sensor according to claim 1, characterized in that, It also includes a plug spacer located on the sidewall of the plug structure.

10. The image sensor according to claim 1, characterized in that, It also includes a drive gate, which is located on the semiconductor layer. The drive door is physically connected to the plug structure.

11. The image sensor according to claim 10, characterized in that, It also includes a component separation membrane, which is located within the semiconductor layer. The drive gate is connected to the plug structure by means of a polycrystalline silicon film that is in contact with and extends on the element separation membrane.

12. An image sensor, characterized in that, include: A pixel region is the area that receives incident light. A logical region located at the periphery of the pixel region; Semiconductor layer; A photodiode located within the semiconductor layer in the pixel region; A floating diode located within the semiconductor layer in the pixel region; A plug structure having one side on the semiconductor layer that is connected to the floating diode; Metal contacts that are connected to the plug structure; as well as A logic gate, comprising a first gate and a second gate on the semiconductor layer within the logic region.

13. The image sensor according to claim 12, characterized in that, The plug structure is formed together with the logic gate in the same process.

14. The image sensor according to claim 12, characterized in that, Also includes: A drive gate, located on the semiconductor layer; as well as A polycrystalline silicon film, which connects the drive gate and the plug structure between the drive gate and the plug structure and is located on the semiconductor layer.

15. The image sensor according to claim 12, characterized in that, Also includes: A first insulating film is located between the first gate and the semiconductor layer; A second insulating film is located between the second gate and the semiconductor layer; as well as A plug insulating film is located between the plug structure and the semiconductor layer. The first door insulating film has a thicker upper and lower thickness compared to the second door insulating film.

16. The image sensor according to claim 15, characterized in that, The plug insulating film has a thicker upper and lower section compared to the second door insulating film.

17. The image sensor according to claim 12, characterized in that, At least one side of the floating diode is surrounded by the photodiode.

18. A method for manufacturing an image sensor, characterized in that, include: The step of forming a first insulating film having a first thickness on a semiconductor layer; The step of forming the first opening on the floating diode by etching one side of the first insulating film; The step of forming a polycrystalline silicon film on the first insulating film and filling the first opening; The step of forming a plug structure having a side connected to the floating diode on the logic gate and the floating diode by etching the polycrystalline silicon film. The step of forming an insulating film layer on the semiconductor layer in a manner that covers the logic gate and the plug structure; as well as The step of forming a metal contact in a shape that penetrates the insulating film layer in a manner that connects to the plug structure.

19. The image sensor manufacturing method according to claim 18, characterized in that, include: The second opening is formed by etching the other side of the first insulating film; as well as The step of forming a second insulating film having a second thickness on the semiconductor layer opened by means of the second opening, The first thickness has a larger value compared to the second thickness.

20. The image sensor manufacturing method according to claim 18, characterized in that, It also includes the step of forming spacers on the sidewalls of the logic gate and the plug structure.

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