Solar cell surface patterning method and solar cell

Abstract

This disclosure provides a method for patterning the surface of a solar cell and a solar cell. The method includes: forming a dielectric layer on a substrate; using a steel plate as a printing mask to form a photoresist layer with a preset pattern on the dielectric layer; removing the printing mask; using the photoresist layer as an etching mask to perform a wet etching process on the dielectric layer to obtain a patterned dielectric layer; and removing the photoresist layer. This disclosure uses a steel plate as a printing mask, eliminating the need for polyimide (PI) screen printing film, saving costs, and improving edge neatness, which is beneficial for forming high-precision structures.

Description

Technical Field

[0001] This disclosure relates to the field of solar cells, and particularly to a method for patterning the surface of a solar cell and a solar cell. Background Technology

[0002] The trend towards higher efficiency in solar cells requires the formation of dielectric layer patterns with high spatial resolution on the silicon wafer surface for various advanced processes such as selective diffusion, localized passivation contacts, selective deposition, and surface structure manipulation. For example, in cell structures such as Passivated Emitter and Back Contact Cell (PERC), Passivated Emitter and Fully Diffused Back Field Cell (PERT), Tunneling Oxide Passivated Contact Cell (TOPCon), Tunneling Oxide Passivated Contact Back Contact Cell (TBC), and Interdigitated Back Contact Cell (IBC), window regions can be formed on dielectric layers such as phosphosilicate glass (PSG), borosilicate glass (BSG), silicon oxide (SiOx), or silicon nitride (SiNx) to achieve localized doping, localized polycrystalline silicon deposition, or localized opening metallization. This reduces interfacial recombination, lowers contact resistance, and improves cell efficiency.

[0003] In industrial mass production, PSG and BSG are typically formed after the thermal diffusion process, serving as the natural dielectric layer between the diffusion region and the substrate silicon. For SiOx / SiNx structures formed by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), patterning of the dielectric layer is also required to achieve local passivation or selective deposition functionality. The development trends of high-efficiency solar cell structures, such as the localized polycrystalline silicon contacts of TOPCon, the bipolar cross structure of TBC, and the selective emitter (SE) of PERC, all place higher demands on the fineness, uniformity, low damage, and low cost of dielectric layer patterning.

[0004] Therefore, how to achieve stable, controllable, and residue-free patterns on the dielectric layer using a low-cost, high-precision, and high-capacity method is one of the key issues in modern crystalline silicon solar cell technology. Summary of the Invention

[0005] Embodiments of this disclosure provide a method for patterning the surface of a solar cell, comprising: forming a dielectric layer on a substrate; using a steel plate as a printing mask to form a photoresist layer with a preset pattern on the dielectric layer; removing the printing mask; using the photoresist layer as an etching mask to perform a patterning process on the dielectric layer by a wet etching process to obtain a patterned dielectric layer; and removing the photoresist layer.

[0006] In some embodiments, the substrate includes a silicon wafer, and the dielectric layer includes at least one of phosphosilicate glass, borosilicate glass, silicon oxide, and silicon nitride.

[0007] In some embodiments, forming a photoresist layer with a preset pattern on a dielectric layer includes: printing curable photoresist on the dielectric layer and curing the curable photoresist to form a photoresist layer with a preset pattern.

[0008] In some embodiments, the curing process includes UV curing, thermal curing, or a combination thereof.

[0009] In some embodiments, prior to the curing process, the curable photoresist comprises a photosensitive resin matrix, a photoinitiator, a crosslinking agent, a rheology modifier, and a solvent, and has a viscosity at room temperature of 2000 mPa·s to 20000 mPa·s.

[0010] In some embodiments, the method further includes pre-baking the photoresist layer prior to the curing process, the pre-baking process comprising processing at 80°C to 120°C for 1 min to 5 min.

[0011] In some embodiments, the wet etching solution used in the wet etching process includes HF, KOH, or a mixture of HF and ammonium fluoride, and magnetic stirring or ultrasonic assistance is used during the wet etching process.

[0012] In some embodiments, the thickness of the photoresist layer is 2 μm to 30 μm.

[0013] In some embodiments, the linewidth of the patterned dielectric layer is from 10 μm to 1500 μm.

[0014] Another embodiment of this disclosure provides a solar cell, which is a solar cell obtained according to any of the above-described solar cell surface patterning methods.

[0015] This disclosure utilizes a steel plate as a printing mask, eliminating the need for polyimide (PI) screen printing film, saving costs, and improving edge neatness, which is beneficial for forming high-precision structures. Attached Figure Description

[0016] Figure 1 A schematic flowchart of a method for patterning the surface of a solar cell according to some embodiments is shown.

[0017] Figure 2 A cross-sectional view of a portion of a solar cell according to some embodiments is shown.

[0018] Figure 3 A cross-sectional view of a portion of a solar cell according to some embodiments is shown.

[0019] Figure 4 A cross-sectional view of a portion of a solar cell according to some embodiments is shown.

[0020] Figure 5A cross-sectional view of a portion of a solar cell according to some embodiments is shown.

[0021] Explanation of reference numerals in the attached figures: 101. Substrate; 102. Dielectric layer; 103. Photoresist layer. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described in detail below with reference to the accompanying drawings.

[0023] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0024] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0025] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0028] Currently, the main methods for patterning dielectric layers include photolithography, mesh-mask paste printing, and laser ablation. Photolithography is extremely expensive, costing over 1-2 yuan per silicon wafer, and has low production capacity, making it unsuitable for large-size (M10 / G12) mass production. Therefore, almost no mass production lines use photolithography for patterning the dielectric layers of solar cells. Mesh-mask paste printing uses non-curable screen printing paste, and the core raw material, the screen, is mostly imported. Its HF resistance is limited (generally <1-2 min), making it difficult to guarantee deep etching, resulting in poor resolution (>80-120μm), rough edges, and unsuitability for high-precision structures (such as polysilicon patterning for TOPCon). It also leaves significant residue and is difficult to clean. Laser ablation damages the silicon wafer surface, easily introducing interface recombination. The heat-affected zone for fine patterns is large, and linewidths are difficult to achieve below 40-50μm, posing an even greater risk for thin M10 / G12 wafers (≤120μm). Currently, no method in the industry can simultaneously meet the following requirements: resolution less than 50μm, HF resistance greater than 5–10 minutes, no damage to silicon wafers, cost less than 0.1–0.2 yuan per wafer, and compatibility with existing screen printing production lines (3600 wafers / hour). Therefore, further improvements in this area are expected.

[0029] like Figure 1 and Figure 2As shown, embodiments of this disclosure provide a method for patterning the surface of a solar cell, including step S101: forming a dielectric layer 102 on a substrate 101. In some embodiments, the substrate 101 may include a monocrystalline or polycrystalline silicon wafer, for example, a p-type or n-type crystalline silicon wafer. In some embodiments, the thickness of the silicon wafer may be 70 μm to 180 μm, for example, 130 μm to 160 μm, and the resistivity may be 0.5 Ω·cm to 5 Ω·cm. In some embodiments, the dielectric layer 102 may include at least one of phosphosilicate glass (PSG), borosilicate glass (BSG), silicon oxide, and silicon nitride. In some embodiments, the dielectric layer 102 may be formed by a thermal diffusion process, for example, by introducing a phosphorus- or boron-containing source gas (e.g., POCl3 / BBr3, etc.) into a tube diffusion furnace, the temperature of the thermal diffusion process may be 750°C to 900°C, for example, 800°C to 870°C, and the time of the thermal diffusion process may be 10 min to 60 min. In some embodiments, after the thermal diffusion process, a dielectric layer 102 (e.g., a PSG layer or BSG layer) with a thickness of 50 nm to 200 nm is formed on the silicon wafer surface. In some embodiments, the dielectric layer 102 is formed on the silicon wafer by forming silicon oxide and / or silicon nitride via PECVD or LPCVD, for example, by depositing SiOx or SiNx in a PECVD apparatus as a passivation layer, a barrier layer, or a mask for subsequent poly-Si selective deposition. The deposition process temperature can be from 150°C to 450°C, for example, from 200°C to 380°C. In some embodiments, the thickness of the dielectric layer 102 formed by the deposition process can be from 20 nm to 200 nm, for example, from 50 nm to 100 nm. In some embodiments, a denser SiOx layer can also be formed using LPCVD, with the LPCVD temperature ranging from 500°C to 800°C.

[0030] like Figure 3As shown, in some embodiments, the method of this disclosure further includes step S102, using a steel plate as a printing mask to form a photoresist layer 103 with a preset pattern on the dielectric layer 102. In some embodiments, the steel plate may include an electroformed nickel steel plate, and the screen opening or preset pattern is designed according to the required pattern linewidth (e.g., 10μm to 100μm, 20μm to 60μm). During printing, the photoresist is aligned with the silicon wafer gate lines or the pre-designed battery structure area and printed onto the surface of the dielectric layer 102 according to the preset pattern. In some embodiments, the printing pressure may be 15N / cm to 40N / cm, the squeegee angle may be 45° to 75°, and the printing speed may be 100mm / s to 400mm / s. In some embodiments, the pattern linewidth and edge steepness are controlled by adjusting the photoresist viscosity, steel plate screen tension, squeegee pressure, and steel plate opening size. By using steel plates as printing masks, the need for polyimide (PI) screen printing films is eliminated, saving costs and improving edge neatness, which is conducive to forming high-precision structures and achieving high-resolution mask patterning.

[0031] In some embodiments, the method disclosed herein further includes step S103, removing the printing mask, i.e., the steel plate.

[0032] like Figure 4As shown, in some embodiments, the method of this disclosure further includes step S104, using the photoresist layer 103 as an etching mask, and performing a wet etching process to pattern the dielectric layer 102 to obtain a patterned dielectric layer 102. In the wet etching process, the dielectric layer 102 not covered by the photoresist layer 103 will be etched, thereby forming openings in the dielectric layer 102. In some embodiments, the temperature of the wet etching process is 20°C to 40°C, for example, 20°C to 30°C, and the etching time can be 0.5 min to 10 min, which is adjusted according to the thickness of the dielectric layer 102 and the etching rate. In some embodiments, taking the SiO2 material dielectric layer 102 as an example, HF undergoes a typical etching reaction with SiO2; the P or B doped in PSG / BSG exists in the form of oxides and also dissolves in HF. Since the photoresist mask does not react with HF after curing and has a dense surface, HF has difficulty penetrating, forming etching selectivity between the dielectric layer 102 and the photoresist layer 103. In some embodiments, the etching rate of the dielectric layer 102 can be from 10 nm / min to 200 nm / min. The photoresist mask has an extremely low etching or swelling rate, remaining intact throughout the etching time, thereby achieving precise control over the opening morphology. In some embodiments, the dielectric layer 102 includes PSG and / or BSG, and etching continues until the surface PSG / BSG not covered by the photoresist layer 103 is completely removed, and the surface diffusion layer is moderately thinned or the depth is limited; in some embodiments, the dielectric layer 102 includes SiOx, and etching continues to the silicon surface or stops at a preset residual thickness. In some embodiments, calibration can be performed by online monitoring time, thickness measurement (ellipsoid, reflectivity), or sample testing. The wet etching process causes almost no damage to the silicon wafer itself, does not introduce thermal damage or lattice dislocations, and is beneficial for suppressing recombination in high-efficiency battery structures.

[0033] In some embodiments, after etching is complete, the sample can be rinsed with deionized water for 1 to 5 minutes to remove any residual etching solution. Afterward, drying can be performed, either by spin drying or hot air drying, to avoid water stains.

[0034] like Figure 4As shown, in some embodiments, the method of this disclosure further includes step S105, removing the photoresist layer 103 to avoid affecting subsequent processes and electrical performance. In some embodiments, the photoresist layer can be removed by solvent method, plasma ashing, or wet stripping. Solvent method can use N-methyl-2-pyrrolidone (NMP), organic stripping solution, or alkaline stripping solution, etc., with a removal temperature of 60°C to 120°C and a removal time of 5 min to 30 min, and can be combined with ultrasonic assistance to accelerate the removal. In plasma ashing, the photoresist layer 103 on the silicon wafer surface is oxidized and decomposed in an O2 plasma reaction chamber. The plasma ashing power can be 200W to 1000W, and the plasma ashing time can be 5 min to 20 min. In some embodiments, plasma ashing can be used in combination with solvent method, first softening most of the photoresist mask with solvent, and then removing the residual thin layer with O2 plasma.

[0035] In some embodiments, after removing the photoresist layer 103, residual organic matter and metal ions are removed by rinsing with deionized (DI) water, cleaning with dilute HCl, etc., to ensure that there is no photoresist residue on the surface, the interface is clean, and it is beneficial for subsequent deposition or diffusion.

[0036] In some embodiments, forming a photoresist layer 103 with a predetermined pattern on the dielectric layer 102 includes: printing a curable photoresist on the dielectric layer 102, and curing the curable photoresist to form the photoresist layer 103 with the predetermined pattern. In some embodiments, the curing process includes UV curing, thermal curing, or a combination thereof. In some embodiments, in UV curing, irradiation is performed under a UV light source in the 200nm to 400nm wavelength band, with an irradiation energy of 500mJ / cm² to 3000mJ / cm², initiating resin crosslinking through a photoinitiator to form a three-dimensional network structure, thereby improving chemical corrosion resistance and mechanical strength. In some embodiments, thermal curing is performed at a temperature of 150°C to 250°C for 5 min to 30 min, promoting further crosslinking of the resin through high temperature, thereby enhancing the HF resistance of the photoresist mask. In some embodiments, UV curing and thermal curing can be used in combination to obtain the best overall performance. In some embodiments, after the photoresist layer 103 has cured, its corrosion resistance time in HF or buffered oxide etchant (BOE) solution is greater than or equal to 5 minutes, and in some embodiments greater than or equal to 10 minutes. Furthermore, it exhibits good adhesion to the dielectric layer 102, with no large-area peeling or detachment during etching. Additionally, the surface of the cured photoresist layer 103 is free of obvious pinholes and cracks, thus preventing pattern distortion caused by the etchant penetrating through defects. This disclosure, using a wet etching process and employing the photoresist mask of this disclosure, solves the problems of mask durability and inaccurate patterns in conventional wet etching. Moreover, the improved performance of the cured photoresist layer makes it possible to achieve high-precision, non-destructive wet patterning under low-cost, high-volume conditions.

[0037] In some embodiments, prior to the curing process, the curable photoresist comprises a photosensitive resin matrix, a photoinitiator, a crosslinking agent, a rheology modifier, and a solvent, and has a viscosity at room temperature of 2000 mPa·s to 20000 mPa·s. In some embodiments, the photosensitive resin matrix may include acrylates and / or epoxy resins, etc. In some embodiments, the photoinitiator may include iodonium salts, N-hydroxynaphthalimide trifluoromethanesulfonate, etc. In some embodiments, the crosslinking agent may include one or more of hexamethoxymethyl melamine, 6-hexanediol diacrylate, and trimethylolpropane triacrylate. In some embodiments, the rheology modifier may include polyacrylates, etc. In some embodiments, the solvent may include ethylene glycol monobutyl ether, cyclohexanone, etc. In some embodiments, the photoresist has a viscosity at room temperature of 5000 mPa·s to 15000 mPa·s to better suit screen printing at 325 mesh to 600 mesh.

[0038] In some embodiments, the method disclosed herein further includes pre-baking the photoresist layer before curing, the pre-baking process comprising processing at 80°C to 120°C for 1 min to 5 min. Pre-baking can evaporate some of the solvent, improve pattern stability, and prevent mask flow or collapse during subsequent curing and etching processes.

[0039] In some embodiments, the wet etching process uses a wet etching solution comprising HF, KOH, or a mixture of HF and ammonium fluoride (i.e., BOE), and magnetic stirring or ultrasonic assistance is employed during the wet etching process. In some embodiments, for PSG or BSG, the concentration of the HF solution can be 2 wt% to 10 wt%, with HF:NH4F in the BOE ratio of 1:6–1:10; for silicon oxide, BOE or a 1 wt% to 5 wt% HF solution is used. In some embodiments, employing magnetic stirring or ultrasonic assistance can better ensure etching uniformity.

[0040] In some embodiments, the thickness of the photoresist layer is 2 μm to 30 μm. In some embodiments, the thickness of the photoresist layer is 5 μm to 10 μm to ensure sufficient shielding capability and corrosion resistance.

[0041] In some embodiments, the linewidth of the patterned dielectric layer is from 10 μm to 1500 μm. In other embodiments, the linewidth of the patterned dielectric layer is 10 μm, 20 μm, 30 μm, 50 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, or any suitable value between them. This ensures both resolution and printing stability and throughput, and results in a finer finish and cleaner edges than traditional screen printing masks.

[0042] The method disclosed herein is applicable to the formation of structures such as selective diffusion windows, localized dielectric layer openings, localized polycrystalline silicon deposition regions, and TBC / TOPCon overlapping regions in solar cells. In some embodiments, through the above steps, this disclosure forms openings or window regions with precise patterns on the dielectric layer 102. Subsequently, different follow-up processes can be implemented depending on the different cell structures. For example, wet removal of the silicon thin film can be performed. For n+poly, p+poly, or diffusion regions formed by thermal diffusion, the method disclosed herein can be used to remove PSG / BSG in localized areas before wet etching to achieve a selective emitter or back surface field structure. For example, selective thermal diffusion windows can be formed. For PSG / BSG layers formed by thermal diffusion, the method disclosed herein can be used to remove PSG / BSG in localized areas before a second diffusion or other treatment to achieve a selective emitter or back surface field structure; for example, localized re-diffusion can be performed in the back surface field (BSF) or selective emitter (SE) regions to increase the local doping concentration. For example, in the localized polysilicon contacts of the TOPCon / TBC structure, in the regions where SiOx is patterned and removed, n-type or p-type polysilicon is deposited via LPCVD or PECVD to form localized passivated contacts; the corresponding non-opening regions are still passivated by SiOx / SiNx, thus achieving a structure with both localized contacts and global passivation. For TBC, the polysilicon in the N-region and P-region can be deposited in different patterned regions, and the patterned SiOx formed by this disclosure can be used to achieve P / N region isolation and overlapping design. In addition, by forming gate lines or solder ribbon openings on the dielectric layer, and then performing metallization processes such as screen printing silver paste and Ni / Cu plating, metal / silicon contacts with low contact resistance can be achieved.

[0043] This disclosed method successfully balances pattern precision and production cost. By employing photoresist materials that can be printed using high-mesh-count screen printing, it achieves fine linewidths of 10-1500μm, meeting the requirements of advanced battery structures such as TOPCon. Simultaneously, by retaining the screen printing process, its equipment and per-wafer processing costs are significantly lower than photolithography, with a production capacity of 3000-5000 wafers / hour, enabling low-cost, large-scale manufacturing of high-precision patterns. Furthermore, this disclosed method achieves a breakthrough in mask corrosion resistance, ensuring pattern quality. Due to UV / thermal cross-linking treatment of the screen-printed photoresist, its HF / BOE resistance time is increased from less than 2 minutes for traditional screen-printed photoresists to over 5 minutes. This allows the mask to remain intact and dimensionally stable during deep etching, resulting in steep-edge, burr-free, and dimensionally accurate dielectric layer windows, significantly improving pattern fidelity. Furthermore, the method disclosed herein achieves efficient patterning without causing damage. Since this method ultimately relies on gentle wet chemical etching to remove the dielectric layer, it completely avoids the lattice thermal and physical damage caused by laser or dry etching, thus helping to maintain the low recombination characteristics of the silicon wafer surface. All of this is predicated on the excellent corrosion resistance of the cured photoresist mask provided in this disclosure, enabling reliable, long-term, and controllable wet etching. Moreover, the method disclosed herein is perfectly compatible with existing production lines and easy to promote. The main processes of this disclosure, such as screen printing, curing, wet etching, and photoresist removal, can all find corresponding or similar equipment modules in existing battery production lines, requiring no huge additional investment and having a low technology adoption threshold.

[0044] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for patterning the surface of a solar cell, characterized in that, include: A dielectric layer is formed on the substrate; A photoresist layer with a preset pattern is formed on the dielectric layer using a steel plate as a printing mask. Remove the printed mask; Using the photoresist layer as an etching mask, the dielectric layer is patterned by a wet etching process to obtain a patterned dielectric layer; Remove the photoresist layer.

2. The solar cell surface patterning method according to claim 1, characterized in that, The substrate includes a silicon wafer, and the dielectric layer includes at least one of phosphosilicate glass, borosilicate glass, silicon oxide, and silicon nitride.

3. The solar cell surface patterning method according to claim 1, characterized in that, Forming a photoresist layer with a preset pattern on the dielectric layer includes: printing curable photoresist on the dielectric layer, and curing the curable photoresist to form a photoresist layer with a preset pattern.

4. The solar cell surface patterning method according to claim 3, characterized in that, The curing process includes UV curing, thermal curing, or a combination thereof.

5. The solar cell surface patterning method according to claim 3, characterized in that, The curable photoresist comprises a photosensitive resin matrix, a photoinitiator, a crosslinking agent, a rheology modifier, and a solvent, and has a viscosity of 2000 mPa·s to 20000 mPa·s at room temperature.

6. The solar cell surface patterning method according to claim 3, characterized in that, Also includes: Prior to the curing process, the photoresist layer is pre-baked, which includes processing at 80°C to 120°C for 1 to 5 minutes.

7. The solar cell surface patterning method according to claim 1, characterized in that, The wet etching process uses a wet etching solution including HF, KOH, or a mixture of HF and ammonium fluoride. During the wet etching process, magnetic stirring or ultrasonic assistance is employed.

8. The solar cell surface patterning method according to claim 1, characterized in that, The thickness of the photoresist layer is 2 μm to 30 μm.

9. The solar cell surface patterning method according to claim 1, characterized in that, The linewidth of the patterned dielectric layer is 10 μm to 1500 μm.

10. A solar cell, characterized in that, The solar cell is a solar cell obtained by the solar cell surface patterning method according to any one of claims 1 to 9.

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