Three-dimensional multi-core particle optoelectronic integrated structure of laser top layer stack and preparation method thereof

Abstract

This invention discloses a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking and its fabrication method. The method includes: S1: providing a silicon optoelectronic conversion substrate, which integrates a silicon optical waveguide and has a first interconnect pad array formed on its upper surface; S2: aligning and bonding at least one electrical functional core and at least one silicon optical core to the upper surface of the silicon optoelectronic conversion substrate with their active surfaces facing down through a first bonding layer to form a first core layer; the optical ports of the silicon optical core are optically coupled to the silicon optical waveguide in the silicon optoelectronic conversion substrate; S3: forming a dielectric layer on top of the first core layer and fabricating vertical interconnect vias in the dielectric layer. This invention achieves ultra-high density integration, excellent thermal management, and efficient optoelectronic coupling through an innovative three-dimensional stacking architecture and in-situ self-grown interconnect process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic integration and advanced packaging technology, specifically to a three-dimensional heterogeneous integrated structure for optoelectronic co-packaging (CPO) and its manufacturing method, particularly a multi-layer three-dimensional optoelectronic integration scheme that independently stacks laser chips on the top layer and adopts in-situ self-grown microbump interconnect technology. Background Technology

[0002] With the rapid development of artificial intelligence, cloud computing, and high-speed data communication, the requirements for data transmission bandwidth and energy efficiency are increasing. Optoelectronic co-packaging technology tightly integrates optoelectronic devices with integrated circuits, becoming a key to overcoming the bottleneck of electrical interconnection. In existing technologies, a 2.5D integration method is typically used to place electrical functional chips, silicon photonic chips, and laser chips side by side on a silicon interposer.

[0003] However, this planar integration method has the following drawbacks: 1) As the main heat source, the heat from the laser can easily affect nearby temperature-sensitive devices (such as modulators and detectors); 2) The planar layout limits the integration density; 3) The coupling between the laser and the silicon waveguide usually requires a complex optical alignment structure; 4) The electrical interconnection paths between the individual chips are relatively long, which affects signal integrity.

[0004] Therefore, there is an urgent need for a three-dimensional optoelectronic integration solution that can achieve higher integration density, better thermal management, shorter interconnect paths, and more efficient optical coupling. Summary of the Invention

[0005] This invention aims to overcome the shortcomings of existing technologies and provide a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking and its fabrication method. This approach achieves ultra-high density integration, excellent thermal management, and efficient optoelectronic coupling through an innovative three-dimensional stacking architecture and in-situ self-growing interconnect process.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A method for fabricating a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking, comprising the following steps: S1: Provides a silicon photoelectric conversion substrate, which integrates a silicon optical waveguide and has a first interconnect pad array formed on its upper surface; S2: At least one electrical functional chip and at least one silicon photonic chip are aligned and bonded to the upper surface of the silicon photoelectric conversion substrate with their active surfaces facing down through a first bonding layer to form a first chip layer; the optical port of the silicon photonic chip is optically coupled to the silicon photonic waveguide in the silicon photoelectric conversion substrate; S3: A dielectric layer is formed on top of the first core layer, and a vertical interconnect via is fabricated in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to the electrode of a specific core in the first core layer or the first interconnect pad of the silicon photoelectric conversion substrate. S4: A second interconnect pad array is formed on the upper surface of the dielectric layer, and the second interconnect pads are electrically connected to the lower structure through the vertical interconnect vias; S5: At least one laser chip is aligned and bonded to the upper surface of the dielectric layer with its active surface facing down through the second bonding layer to form a second chip layer at the top layer, so that a gap is formed between the electrode of the laser chip and the corresponding pad, and metal is selectively grown in the gap to form micro metal bumps to achieve electrical connection; wherein, the light outlet of the laser chip is coupled to the silicon optical waveguide or the silicon optical chip in the silicon photoelectric conversion substrate in a vertical or deflected manner.

[0007] Optionally, the laser core is a VCSEL core, and the laser core further includes a back reflector electrode. The process also includes forming a dielectric layer on the first core layer and fabricating vertical interconnect vias in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to an electrode of a specific core in the first core layer, and a gap is formed between the top of the vertical interconnect via and the back reflector electrode. Metal is selectively grown in the gap to form micro-metal bumps, thereby achieving electrical connection.

[0008] Optionally, in step S5, the selective growth of metal in the gap is an in-situ self-grown metal interconnect process, which is chemical plating or electroplating. The selective growth of metal in the gap is achieved by using a mask or the bonding layer as an insulating mask. The self-grown metals include copper, aluminum, tungsten, titanium, cobalt, molybdenum and their alloys, and the process is carried out at a solution temperature of 40°C to 80°C.

[0009] Optionally, in step S3, the material of the dielectric layer is silicon nitride, silicon oxide, aluminum nitride, or a photosensitive polymer, and its thickness is 5 μm to 50 μm.

[0010] Optionally, in step S3, the method for preparing the vertical interconnect via includes: The dielectric layer is deposited or coated on the surface of the first core layer; Through-holes are formed in the dielectric layer using photolithography and etching processes; A diffusion barrier layer and a seed layer are deposited on the inner wall of the through-hole; Metal pillars are formed by filling metal through an electroplating process, wherein the material of the metal pillars is copper, tungsten, or their alloys.

[0011] Optionally, in step S5, the laser chip is a VCSEL chip, and its light output port is vertically coupled downward to the silicon waveguide in the silicon photoelectric conversion substrate through a vertical grating coupler disposed in the corresponding area on the silicon photoelectric conversion substrate.

[0012] Optionally, in step S5, the laser core is a side-emitting laser core, and a 45° reflecting mirror or microprism is integrated in front of the light outlet of the laser core, inside the dielectric layer or inside the silicon photoelectric conversion substrate, for redirecting the horizontally emitted beam by 90° and coupling it vertically downward.

[0013] Optionally, in steps S2 and S5, the first bonding layer and the second bonding layer are non-conductive polymers, silicon dioxide, or aluminum nitride, and the bonding process is hot-press bonding, anodic bonding, or low-temperature plasma activation bonding, with a bonding temperature below 300°C.

[0014] Optionally, step S2 may be followed by: A first aluminum nitride insulating encapsulation material is filled in the gaps between the core particles of the first core layer and between the core particles and the silicon photoelectric conversion substrate.

[0015] Step S5 is followed by: A second aluminum nitride insulating encapsulation material is filled around the laser core of the second core layer.

[0016] Optionally, step S6 is also included: bonding or depositing a heat dissipation cover plate on the upper surface of the second core layer, wherein the heat dissipation cover plate is made of silicon, diamond, aluminum nitride or metal composite material.

[0017] Optionally, the silicon photoelectric conversion substrate is a silicon interposer or a silicon adapter plate, which also integrates through-silicon vias for transmitting electrical signals from the upper surface to system-level interconnect solder balls on the lower surface.

[0018] A three-dimensional multi-core optoelectronic integrated structure prepared according to the above-described method comprises: A silicon photoelectric conversion substrate, which integrates a silicon optical waveguide inside and has a first interconnect pad array on its upper surface; The first core layer, located on the silicon photoelectric conversion substrate, includes at least one flip-bonded electrical functional core and at least one flip-bonded silicon photonic core; the silicon photonic core is optically coupled to the silicon photonic waveguide. A dielectric layer covers the first core layer and has embedded a plurality of vertically interconnected metal pillars therein; The second interconnect pad array is located on the upper surface of the dielectric layer and is electrically connected to the first core layer or silicon photoelectric conversion substrate through the vertical interconnect metal pillars. The second core layer, located above the dielectric layer, includes at least one flip-chip bonded laser core. The active surface electrode of the laser core is electrically connected to the second interconnect pad array via in-situ grown micro-metal bumps, and its light outlet is optically coupled to the underlying optical waveguide structure.

[0019] Optionally, the laser chip is a VCSEL chip, and a vertical grating coupler is provided at the corresponding position of the silicon photoelectric conversion substrate. The light emitted by the VCSEL chip passes vertically through the corresponding light-transmitting area in the dielectric layer and is then guided into the silicon optical waveguide by the vertical grating coupler.

[0020] Optionally, the laser chip is a VCSEL chip and also includes a back reflector electrode. The top of the vertical interconnect metal pillar is electrically connected to the back reflector electrode via micro-metal bumps grown in situ.

[0021] Optionally, the dielectric layer may have a light-transmitting window in the region corresponding to the light exit port of the laser chip, or may have an integrated beam steering element.

[0022] Optionally, the electrical functional chip is a CMOS main control chip, and the silicon photonics chip integrates a Ge detector array.

[0023] Optionally, it also includes a heat dissipation cover plate bonded to the upper surface of the second core layer.

[0024] Optionally, the gaps between the cores of the first core layer and between the cores and the silicon photoelectric conversion substrate are filled with a first aluminum nitride insulating encapsulation material, and the laser cores of the second core layer are filled with a second aluminum nitride insulating encapsulation material.

[0025] Optionally, the silicon photoelectric conversion substrate is a silicon interposer or a silicon adapter plate, which also integrates through-silicon vias and has system-level interconnect solder balls on its lower surface.

[0026] The beneficial effects of this invention are as follows: 1. Three-dimensional stacking enables ultra-high density integration, freeing up layout space for silicon photoelectric conversion substrates; 2. The laser is placed independently on the top layer, optimizing the thermal management path and reducing thermal crosstalk; 3. In-situ self-grown microbump technology enables low-temperature, high-precision, and high-reliability vertical interconnection; 4. The vertical optical coupling path is shortened, improving coupling efficiency and reducing alignment difficulty; 5. End-to-end low-temperature process, compatible with integration of various heterogeneous materials; 6. The application of materials such as aluminum nitride takes into account the requirements of electrical insulation, optical transmission and thermal conduction; 7. By flexibly defining the function of the silicon photoelectric conversion substrate, the architecture of this invention can be applied to various technical paths from passive adapter boards to active interposers, and has strong scalability and compatibility.

[0027] Icon labels: 10-Silicon photoelectric conversion substrate; 11-First interconnect pad array; 12-Through silicon via; 21-Vertical interconnect metal pillar; 22-Second interconnect pad array; 30-Laser chip; 31-Micro metal bump. Attached Figure Description

[0028] Figure 1 This is a flowchart of the preparation method of the present invention; Figure 2 This is a cross-sectional schematic diagram of the first embodiment of the three-dimensional structure of the present invention; Figure 3 This is a cross-sectional schematic diagram of the second embodiment of the three-dimensional structure of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described below in conjunction with the accompanying drawings.

[0031] Example 1

[0032] like Figure 2 As shown, this embodiment illustrates a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking, comprising: A silicon photoelectric conversion substrate 10 has a silicon optical waveguide integrated inside, and a first interconnect pad array 11 on its upper surface; The first core layer, located on the silicon photoelectric conversion substrate 10, includes at least one flip-bonded electrical functional core and at least one flip-bonded silicon photonic core. In this embodiment, the electrical functional core includes an EIC-CMOS (Electronic Integrated Circuit-Complementary Metal-Oxide-Semiconductor) controller, and the silicon photonic core includes a PIC (Photonic Integrated Circuit) which integrates a Ge (germanium) detector array. The silicon photonic core is optically coupled to the silicon optical waveguide. A dielectric layer covers the first core layer and has embedded a plurality of vertically interconnected metal pillars 21 therein; The second interconnect pad array 22 is located on the upper surface of the dielectric layer and is electrically connected to the first core layer or silicon photoelectric conversion substrate through the vertical interconnect metal pillars 21. The second core layer, located above the dielectric layer, includes at least one flip-bonded laser core 30. The active surface electrode of the laser core 30 is electrically connected to the second interconnect pad array 22 through in-situ grown micro-metal bumps 31, and its light outlet is optically coupled to the underlying optical waveguide structure.

[0033] Specifically, in this embodiment, the silicon photoelectric conversion substrate 10 is an SOI (silicon insulated) substrate, and integrates a silicon waveguide, a vertical grating coupler, a silicon via 21, and horizontal interconnects. A first interconnect pad array 11 is formed on the upper surface of the silicon photoelectric conversion substrate 10, and system-level interconnect solder balls are formed on the lower surface.

[0034] A dielectric layer, approximately 20 μm thick, is placed over the first core layer and is made of aluminum nitride. Copper vertical interconnect pillars are embedded in the dielectric layer.

[0035] The second core layer is an InP / GaAs VCSEL (Indium Phosphide / Gallium Arsenide Vertical Cavity Surface Emitting Laser) core, flip-chip bonded to the upper surface of the dielectric layer. The front electrode of the VCSEL is connected to the second interconnect pad on the upper surface of the dielectric layer through in-situ grown copper microbumps, and the back electrode is connected through additional vertical interconnect pillars.

[0036] Aluminum nitride filler layers surround each core particle, providing mechanical support, thermal conductivity, and electrical insulation.

[0037] Preferred options also include a heat dissipation cover: made of aluminum nitride, bonded to the top of the structure.

[0038] In this embodiment, the laser chip 30 is a VCSEL chip, and a vertical grating coupler is provided at the corresponding position of the silicon photoelectric conversion substrate. The light emitted by the VCSEL chip passes perpendicularly through the corresponding light-transmitting area in the dielectric layer and is then guided into the silicon optical waveguide by the vertical grating coupler. The laser chip 30, being a VCSEL chip, also includes a back reflection electrode. The top of the vertical interconnect metal pillar 21 is electrically connected to the back reflection electrode via an in-situ grown micro-metal bump 31. The dielectric layer has a light-transmitting window in the area corresponding to the light exit port of the laser chip, or integrates a beam steering element. The electrical functional chip is a CMOS main control chip, and the silicon photoelectric chip integrates a Ge detector array.

[0039] refer to Figure 1The flowchart of the first embodiment of the present invention describes a method for fabricating a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking, comprising the following steps: S1: A silicon photoelectric conversion substrate 10 is provided, which integrates a silicon optical waveguide and has a first interconnect pad array 11 formed on its upper surface; Specifically, it provides 8-inch SOI wafers (220nm top silicon layer, 2μm buried oxide layer). It employs standard CMOS and silicon photonics processes: silicon waveguide structures are defined in the top silicon layer using electron beam lithography and reactive ion etching; PN junctions are formed through ion implantation and thermal annealing to construct silicon-based modulators. Ge photodetectors are formed by selectively epitaxially growing Ge layers; vertical grating couplers are formed by etching and deposition; in non-optical paths, through-silicon vias (TSVs) are formed by deep silicon etching, SiO2 (silicon dioxide) insulating layers are deposited, and then copper is filled to form TSVs; aluminum nitride interlayer dielectric is deposited, through-holes are formed by photolithography, and copper is deposited to form the first redistribution layer; dielectric and metal layers are repeatedly deposited to finally form the first interconnect pad array; the back side of the wafer is thinned to expose the TSVs and form the bottom solder ball array.

[0040] Step S2: At least one electrical functional chip and at least one silicon photonic chip are aligned and bonded to the upper surface of the silicon photoelectric conversion substrate with their active surfaces facing down through the first bonding layer to form a first chip layer; the optical port of the silicon photonic chip is optically coupled to the silicon photonic waveguide in the silicon photoelectric conversion substrate.

[0041] Specifically, both the electrical functional chips (such as CMOS main control chips) and the silicon photonics chips employ flip-chip technology, bonding them with their active surfaces (i.e., the side with transistors, optoelectronic devices, and electrodes) facing the silicon photoelectric conversion substrate 10. This bonding method minimizes the interconnect path: the chip electrodes are directly face-to-face connected to the first interconnect pad array 11 on the substrate, eliminating the need for wire bonding, significantly reducing parasitic inductance and resistance, and improving signal transmission speed and quality; it also facilitates heat dissipation: heat generated on the active surface can be directly conducted to the substrate through metal bumps, and then discharged through through-silicon vias 12 (TSVs) or heat dissipation structures within the substrate, forming an efficient thermal management path.

[0042] Step S3: A dielectric layer is formed on the first core layer, and a vertical interconnect via is fabricated in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to the electrode of a specific core in the first core layer or the first interconnect pad of the silicon photoelectric conversion substrate.

[0043] Specifically, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a 5μm thick aluminum nitride layer on the first core layer; photoresist is spin-coated and exposed and developed to create via patterns; reactive ion etching (RIE) is used to etch through the aluminum nitride to the lower electrode; the photoresist is removed and the vias are cleaned; a 10nm TaN / 50nm Cu (10nm tantalum nitride / 50nm copper) diffusion barrier layer and seed layer are deposited; copper is electroplated to fill the vias, forming copper pillars with a diameter of 3μm; chemical mechanical polishing is used to remove excess copper from the surface, making the surface flat.

[0044] Step S4: A second interconnect pad array is formed on the upper surface of the dielectric layer, and the second interconnect pads are electrically connected to the lower structure through the vertical interconnect vias.

[0045] Specifically, 300 nm of aluminum nitride is deposited on the planarized dielectric layer surface; the second interconnect pad pattern is defined by photolithography; aluminum nitride is etched to open the pad windows; a Ti / Cu (titanium / copper) adhesion layer and a seed layer are deposited; copper is electroplated to thicken to 2 μm to form the second interconnect pad array 22.

[0046] Step S5: At least one laser chip 30, with its active surface facing down, is aligned and bonded to the upper surface of the dielectric layer through the second bonding layer to form a second chip layer at the top layer, so that a gap is formed between the electrode of the laser chip and the corresponding pad. Metal is selectively grown in the gap to form micro-metal bumps 31 to achieve electrical connection; wherein, the light outlet of the laser chip 30 is coupled to the silicon optical waveguide or the silicon optical chip in the silicon photoelectric conversion substrate 10 in a vertical or deflected manner.

[0047] Specifically, in this embodiment, the VCSEL wafer is prepared as follows: InGaAs (indium gallium arsenide) multi-quantum-well active regions are epitaxially grown on a GaAs (gallium arsenide) substrate, a ring-shaped p-type electrode (10 μm inner diameter) is fabricated on the front side, and an n-type electrode is fabricated on the back side; the wafer is thinned to 80 μm and diced to obtain VCSEL chips; an 800 nm thick aluminum nitride bonding layer is spin-coated on the dielectric layer surface; the VCSEL chips are precisely aligned using an infrared-aligned flip-chip bonder (the VCSEL light output port is aligned with the substrate vertical grating coupler); bonding is performed at 200°C and 3000 N pressure for 30 minutes; chemical copper plating is used to form microbumps between the VCSEL front electrode and the second interconnect pad; for the VCSEL back reflective electrode connection: an additional via is fabricated in the dielectric layer to the driving circuit pad of the lower CMOS chip, and a microbump connecting the back electrode is formed by chemical copper plating; aluminum nitride encapsulation material is then filled.

[0048] In one embodiment, the laser chip 30 is a VCSEL chip, and the laser chip 30 further includes a back reflector electrode. The embodiment also includes the steps of forming a dielectric layer on the first chip layer and preparing vertical interconnect vias in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to the electrode of a specific chip in the first chip layer, and a gap is formed between the top of the vertical interconnect via and the back reflector electrode. Metal is selectively grown in the gap to form micro-metal bumps 31 to achieve electrical connection.

[0049] In one embodiment, the selective growth of metal in the gap is an in-situ self-grown metal interconnect process, which is chemical plating or electroplating. The selective growth of metal in the gap is achieved by using a mask or the bonding layer as an insulating mask. The self-grown metal includes copper, aluminum, tungsten, titanium, cobalt, molybdenum and their alloys, and the process is carried out at a solution temperature of 40°C to 80°C.

[0050] In one embodiment, the dielectric layer is made of silicon nitride, silicon oxide, aluminum nitride, or a photosensitive polymer, and has a thickness of 5 μm to 50 μm.

[0051] In one embodiment, a heat dissipation cover plate is bonded or deposited on the upper surface of the second core layer. The heat dissipation cover plate is made of silicon, diamond, aluminum nitride, or a metal composite material. Specifically, for heat dissipation, a 200 μm thick aluminum nitride heat dissipation cover plate is bonded to the top of the structure using silver sintering paste at 250°C.

[0052] In one embodiment, step S3, the method for preparing the vertical interconnect via includes: The dielectric layer is deposited or coated on the surface of the first core layer; Through-holes are formed in the dielectric layer using photolithography and etching processes; A diffusion barrier layer and a seed layer are deposited on the inner wall of the through-hole; Metal pillars are formed by filling metal through an electroplating process, wherein the material of the metal pillars is copper, tungsten, or their alloys.

[0053] In one embodiment, in step S5, the laser chip is a VCSEL chip, and its light output port is vertically coupled downward to the silicon waveguide in the silicon photoelectric conversion substrate through a vertical grating coupler disposed in the corresponding area on the silicon photoelectric conversion substrate.

[0054] In one embodiment, in steps S2 and S5, the first bonding layer and the second bonding layer are non-conductive polymers, silicon dioxide, or aluminum nitride, and the bonding process is hot-press bonding, anodic bonding, or low-temperature plasma activation bonding, with a bonding temperature below 300°C.

[0055] In one embodiment, step S2 is followed by: A first aluminum nitride insulating encapsulation material is filled in the gaps between the core particles of the first core layer and between the core particles and the silicon photoelectric conversion substrate.

[0056] Step S5 is followed by: A second aluminum nitride insulating encapsulation material is filled around the laser core of the second core layer.

[0057] In one embodiment, the silicon photoelectric conversion substrate is a silicon interposer or a silicon adapter plate, and it also integrates through-silicon vias for transmitting electrical signals from the upper surface to system-level interconnect solder balls on the lower surface.

[0058] Working mechanism: Driven by a CMOS chip, the VCSEL emits a 980nm laser beam that travels vertically downwards through the transparent region of the dielectric layer. The beam is captured by a vertical grating coupler in the substrate and coupled into a horizontal silicon waveguide. The optical signal propagates within the waveguide, is modulated by a silicon-based modulator, and then output, or is received by a Ge detector and converted into an electrical signal. All electrical signals propagate in three-dimensional space via microbumps and vertical interconnect pillars, resulting in extremely short paths.

[0059] Example 2: like Figure 3 As shown, the main difference between this embodiment and Embodiment 1 is that the silicon photonics functional part is directly integrated into the silicon photoelectric conversion substrate, rather than as an independent chip.

[0060] The silicon photoelectric conversion substrate not only includes interconnect functions, but also directly integrates a complete silicon photonic chip, including: silicon photonic waveguide, Mach-Zehnder modulator, microring resonator, grating coupler and germanium photodetector group.

[0061] The first core layer contains only the EIC-CMOS main control chip, simplifying the structure.

[0062] The top-level VCSEL laser has the same structure.

[0063] The preparation methods differ as follows: In step S1, a more complex silicon photonics process is used to directly fabricate complete photonic integrated circuits on the SOI wafer. This requires: multi-step photolithography and etching to define various photonic devices; selective epitaxial growth and doping of germanium to form detectors; formation and insulating isolation of metal electrodes; and performance testing and calibration of waveguides, modulators, and detectors.

[0064] The advantages of this approach are: 1) it reduces the number of core particles and improves reliability; 2) the optical path is entirely within the substrate, resulting in lower coupling loss; 3) the heat source is more dispersed; and 4) the fabrication process may be simpler.

[0065] Example 3

[0066] This embodiment further expands the IC integration location based on embodiment 1 or 2: On the back (bottom) side of the silicon photoelectric conversion substrate 10, a back logic chip layer is integrated through wafer thinning, back photolithography, and interconnection processes. This back layer can be electrically connected to the upper structure through through-silicon vias 12; the back logic chip can be a power management chip, a control chip, or a memory chip, etc.

[0067] This embodiment achieves double-sided IC integration, that is, different types or functions of ICs are integrated on the top and bottom of the adapter board, which greatly improves the functional density and system integration.

[0068] Example 4

[0069] This embodiment is a combination and extension of the foregoing embodiments, demonstrating the implementation method with the highest integration: The adapter board integrates active logic circuits (such as CMOS driver and control circuits); the upper surface of the adapter board integrates silicon photonics chips and / or dedicated logic chips via flip-chip; the lower surface of the adapter board integrates power management or memory chips; the top layer is still the laser chip, interconnected with the lower structure through a dielectric layer.

[0070] This embodiment achieves heterogeneous IC integration with multiple locations, multiple layers, and multiple functions, giving full play to the advantages of three-dimensional stacking, and is suitable for cutting-edge applications such as high-performance computing and photonic AI accelerators in the future.

[0071] Example 5: For the case where an edge-emitting laser (such as a DFB laser) is used as the top-level laser, the fabrication method differs in that: Integrating a 45° mirror within a dielectric layer or silicon photoelectric conversion substrate: forming a 45° bevel through anisotropic etching or grayscale lithography, and depositing highly reflective metal; The VCSEL vertical grating coupler can be replaced with an end-face coupler or a tilted grating; The laser emitter is placed horizontally with its emitting surface facing the reflector. The mirror deflects the horizontal light 90° downwards and couples it into the waveguide.

[0072] Bonding layer materials: In addition to aluminum nitride, benzocyclobutene (BCB), polyimide (PI), silsesquioxane (HSQ), etc. can also be used, depending on the requirements of dielectric constant, thermal conductivity and light transmittance.

[0073] Microbump growth technology: In addition to chemical copper plating, electroplating copper can also be used: Requires the pre-formation of a continuous seed layer; Electroless nickel-gold plating: suitable for gold electrode systems; Selective atomic layer deposition: enables bumps with sub-100nm dimensions.

[0074] Vertical interconnect technology: In addition to electroplated copper pillars, the following can also be used: Tungsten chemical vapor deposition filling; Copper-copper direct bonding; Conductive adhesive filling.

[0075] Heat dissipation solutions: In addition to aluminum nitride cover plates, the following can also be used: embedded microchannel cooling; thermoelectric cooler integration; phase change material heat dissipation.

[0076] In one embodiment, the laser chip is a side-emitting laser chip, and a 45° reflecting mirror or microprism is integrated in front of the laser chip's output port, inside the dielectric layer, or inside the silicon photoelectric conversion substrate to redirect the horizontally emitted beam by 90° and couple it vertically downward.

[0077] The significant advancements of this invention compared to existing technologies are as follows: Integration density: Through three-dimensional stacking, the density of functional devices per unit area is increased by 2-3 times; Thermal performance: Independent heat dissipation on the top layer of the laser reduces the chip junction temperature by 15-20°C; Electrical performance: The resistance of micro-bump interconnects is reduced by 50% and the inductance by 70% compared to traditional solder balls; Optical performance: The coupling efficiency of vertical optical coupling can reach over 70%, which is 20% higher than edge coupling; Reliability: Low-temperature process throughout the entire process results in low thermal stress and an expected lifespan increase of 30%; Cost: Wafer-level processing is possible, and mass production has a significant cost advantage.

[0078] The three-dimensional optoelectronic integrated structure provided by this invention can be widely used in: Data center optical interconnect modules (400G / 800G / 1.6T optical modules); optoelectronic co-packaging for high-performance computing systems; photonics processing for 5G / 6G communication front-ends; optical computing and artificial intelligence accelerators; LiDAR and 3D sensing systems.

[0079] Benefiting from the teachings presented in the foregoing description and the accompanying drawings, those skilled in the art will conceive of many modifications and other embodiments of the invention set forth herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and is not intended to be limiting.

Claims

1. A method for fabricating a three-dimensional multi-core optoelectronic integrated structure with laser top-layer stacking, characterized in that, Including the following steps: S1: Provides a silicon photoelectric conversion substrate, which integrates a silicon optical waveguide and has a first interconnect pad array formed on its upper surface; S2: At least one electrical functional chip and at least one silicon photonic chip are aligned and bonded to the upper surface of the silicon photoelectric conversion substrate with their active surfaces facing down through a first bonding layer to form a first chip layer; the optical port of the silicon photonic chip is optically coupled to the silicon photonic waveguide in the silicon photoelectric conversion substrate; S3: A dielectric layer is formed on top of the first core layer, and a vertical interconnect via is fabricated in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to the electrode of a specific core in the first core layer or the first interconnect pad of the silicon photoelectric conversion substrate. S4: A second interconnect pad array is formed on the upper surface of the dielectric layer, and the second interconnect pads are electrically connected to the lower structure through the vertical interconnect vias; S5: At least one laser chip is aligned and bonded to the upper surface of the dielectric layer with its active surface facing down through the second bonding layer to form a second chip layer at the top layer, so that a gap is formed between the electrode of the laser chip and the corresponding pad, and metal is selectively grown in the gap to form micro metal bumps to achieve electrical connection; wherein, the light outlet of the laser chip is coupled to the silicon optical waveguide or the silicon optical chip in the silicon photoelectric conversion substrate in a vertical or deflected manner.

2. The preparation method according to claim 1, characterized in that, The laser core is a VCSEL core, which also includes a back reflector electrode. The process further includes forming a dielectric layer on the first core layer and fabricating vertical interconnect vias in the dielectric layer. The lower end of the vertical interconnect via is electrically connected to an electrode of a specific core in the first core layer. A gap is formed between the top of the vertical interconnect via and the back reflector electrode. Metal is selectively grown in the gap to form micro-metal bumps, thereby achieving electrical connection.

3. The preparation method according to claim 2, characterized in that, In step S5, the selective growth of metal in the gap is an in-situ self-grown metal interconnect process, which is chemical plating or electroplating. The selective growth of metal in the gap is achieved by using a mask or the bonding layer as an insulating mask. The self-grown metals include copper, aluminum, tungsten, titanium, cobalt, molybdenum and their alloys. The process is carried out at a solution temperature of 40°C to 80°C.

4. The preparation method according to claim 1, characterized in that, In step S3, the material of the dielectric layer is silicon nitride, silicon oxide, aluminum nitride, or a photosensitive polymer, and its thickness is 5 μm to 50 μm.

5. The preparation method according to claim 1, characterized in that, In step S3, the method for preparing the vertical interconnect via includes: The dielectric layer is deposited or coated on the surface of the first core layer; Through-holes are formed in the dielectric layer using photolithography and etching processes; A diffusion barrier layer and a seed layer are deposited on the inner wall of the through-hole; Metal pillars are formed by filling metal through an electroplating process, wherein the material of the metal pillars is copper, tungsten, or their alloys.

6. The preparation method according to claim 1, characterized in that, In step S5, the laser chip is a VCSEL chip, and its light output port is vertically coupled downward to the silicon waveguide in the silicon photoelectric conversion substrate through a vertical grating coupler disposed in the corresponding area on the silicon photoelectric conversion substrate.

7. The preparation method according to claim 1, characterized in that, In step S5, the laser core is a side-emitting laser core. A 45° reflecting mirror or microprism is integrated in front of the light outlet of the laser core, inside the dielectric layer, or inside the silicon photoelectric conversion substrate to redirect the horizontally emitted beam by 90° and then couple it vertically downward.

8. The preparation method according to claim 1, characterized in that, In steps S2 and S5, the first bonding layer and the second bonding layer are non-conductive polymers, silicon dioxide, or aluminum nitride, and the bonding process is hot-press bonding, anodic bonding, or low-temperature plasma activation bonding, with a bonding temperature below 300°C.

9. The preparation method according to claim 1, characterized in that, Step S2 is followed by: A first aluminum nitride insulating encapsulation material is filled in the gaps between the core particles of the first core layer and between the core particles and the silicon photoelectric conversion substrate. Step S5 is followed by: A second aluminum nitride insulating encapsulation material is filled around the laser core of the second core layer.

10. The preparation method according to claim 1, characterized in that, It also includes step S6: bonding or depositing a heat dissipation cover plate on the upper surface of the second core layer, wherein the heat dissipation cover plate is made of silicon, diamond, aluminum nitride or metal composite material.

11. The preparation method according to claim 1, characterized in that, The silicon photoelectric conversion substrate is a silicon interposer or a silicon adapter plate, and it also integrates silicon vias to transmit electrical signals from the upper surface to the system-level interconnect solder balls on the lower surface.

12. A three-dimensional multi-core optoelectronic integrated structure prepared by the method according to any one of claims 1-11, characterized in that, include: A silicon photoelectric conversion substrate, which integrates a silicon optical waveguide inside and has a first interconnect pad array on its upper surface; The first core layer, located on the silicon photoelectric conversion substrate, includes at least one flip-bonded electrical functional core and at least one flip-bonded silicon photonic core; the silicon photonic core is optically coupled to the silicon photonic waveguide. A dielectric layer covers the first core layer and has embedded a plurality of vertically interconnected metal pillars therein; The second interconnect pad array is located on the upper surface of the dielectric layer and is electrically connected to the first core layer or silicon photoelectric conversion substrate through the vertical interconnect metal pillars. The second core layer, located above the dielectric layer, includes at least one flip-chip bonded laser core. The active surface electrode of the laser core is electrically connected to the second interconnect pad array via in-situ grown micro-metal bumps, and its light outlet is optically coupled to the underlying optical waveguide structure.

13. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The laser chip is a VCSEL chip, and a vertical grating coupler is provided at the corresponding position of the silicon photoelectric conversion substrate. The light emitted by the VCSEL chip passes vertically through the corresponding light-transmitting area in the dielectric layer and is then guided into the silicon optical waveguide by the vertical grating coupler.

14. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The laser chip is a VCSEL chip and also includes a back reflector electrode. The top of the vertical interconnect metal pillar is electrically connected to the back reflector electrode through micro-metal bumps grown in situ.

15. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The dielectric layer has a light-transmitting window in the region corresponding to the light outlet of the laser chip, or it integrates a beam steering element.

16. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The electrical functional chip is a CMOS main control chip, and the silicon photonics chip integrates a Ge detector group.

17. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, It also includes a heat dissipation cover plate bonded to the upper surface of the second core layer.

18. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The gaps between the cores of the first core layer and between the cores and the silicon photoelectric conversion substrate are filled with a first aluminum nitride insulating encapsulation material, and the laser cores of the second core layer are filled with a second aluminum nitride insulating encapsulation material.

19. The three-dimensional multi-core optoelectronic integrated structure according to claim 11, characterized in that, The silicon photoelectric conversion substrate is a silicon interposer or a silicon adapter plate, which also integrates silicon vias and has system-level interconnect solder balls on its lower surface.

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