Method for manufacturing solar cell and solar cell
By setting a dielectric layer and optimizing the etching process during the fabrication of solar cells, the leakage risk in BC cells was solved, resulting in higher cell efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TRINA SOLAR CO LTD
- Filing Date
- 2026-05-20
- Publication Date
- 2026-06-19
AI Technical Summary
During the fabrication of BC cells, heterojunctions with a high risk of leakage are easily formed, which in turn reduces the output efficiency of the solar cell.
In the fabrication process of solar cells, a high-quality dense film is formed by setting a dielectric layer between the first doped layer and the second doped layer, which improves the insulation performance. The dielectric layer and the doped layer are protected by etching and cleaning processes to avoid the formation of heterojunctions and reduce the generation of leakage current.
This effectively avoids the formation of heterojunctions, reduces leakage current, and improves the discharge efficiency of solar cells.
Smart Images
Figure CN122248832A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cell technology, and in particular to a method for preparing a solar cell and the solar cell itself. Background Technology
[0002] With the development of solar energy technology, more and more types of solar cells have been developed. Currently, back contact (BC) cell technology is considered the future direction of crystalline silicon cell technology. BC cell technologies mainly include TBC (Tunnel Back Contact), HPBC (Hybrid Passivated Back Contact), and HBC (Heterojunction Back Contact), which move the PN junction and metal contact to the back of the cell. This eliminates electrode obstruction on the front, allowing for a larger area of sunlight absorption, thus improving conversion efficiency and generating more electricity.
[0003] During the fabrication of BC cells, heterojunctions with a high risk of leakage are easily formed, which in turn reduces the output efficiency of solar cells. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for preparing a solar cell and a solar cell to address the problem of leakage current easily generated in the existing technology, which affects the power generation efficiency of solar cells.
[0005] In a first aspect, this application provides a method for preparing a solar cell, comprising:
[0006] A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed in the first region of the back surface of the substrate.
[0007] A first passivation layer and a second doped layer are formed sequentially; the first passivation layer covers the side of the silicon thin film layer away from the substrate and a second region of the backlight surface, and the second doped layer is disposed on the side of the first passivation layer away from the substrate; the second region is disposed adjacent to the first region;
[0008] Etching the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region forms a first opening; the first opening exposes a portion of the surface of the first doped layer away from the substrate;
[0009] A first electrode is formed; the first electrode is electrically connected to the first doped layer exposed by the first opening.
[0010] In one embodiment, the first etch selectivity ratio of the silicon thin film layer and the dielectric layer is greater than the second etch selectivity ratio of the silicon thin film layer and the first doped layer.
[0011] In one embodiment, the etching of the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region forms a first opening, including:
[0012] Laser etching is performed on the second doped layer, the first passivation layer, and the silicon thin film layer located in the first region to expose a portion of the surface of the dielectric layer away from the substrate;
[0013] Wet etching is used to expose the dielectric layer to the surface of the first doped layer on the side away from the substrate, forming a first opening;
[0014] The dielectric layer has a thickness greater than 5 nm.
[0015] In one embodiment, the wet etching exposes the dielectric layer to the surface of the first doped layer on the side away from the substrate, including:
[0016] Acid etching exposes the dielectric layer to the surface of the first doped layer on the side away from the substrate.
[0017] In one embodiment, before the etching of the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region forms the first opening, the method further includes:
[0018] A transparent conductive layer is formed on the side of the second doped layer away from the substrate;
[0019] Etching the transparent conductive layer in the first region forms a second opening, the second opening exposing the surface of the second doped layer away from the substrate, the second opening coinciding with the orthographic projection of the first opening onto the substrate surface; or,
[0020] After etching the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region to form the first opening, the process further includes:
[0021] A transparent conductive layer is formed on the side of the second doped layer away from the substrate and in contact with the first doped layer exposed by the first opening.
[0022] In one embodiment, after forming the transparent conductive layer, the method further includes:
[0023] An isolation groove is formed, which is located on the side of the first opening near the second region, and the isolation groove at least penetrates the transparent conductive layer to isolate the transparent conductive layer of the first region and the second region.
[0024] In one embodiment, the isolation groove penetrates the transparent conductive layer and is located at the edge region of the first region and the second region; or,
[0025] The isolation groove is located in the first region and penetrates the transparent conductive layer; or...
[0026] The isolation trench is located in the first region and extends through the transparent conductive layer, the second doped layer, the first passivation layer, the silicon thin film layer, and a portion of the dielectric layer.
[0027] In one embodiment, the material of the first doped layer includes doped polycrystalline silicon;
[0028] The dielectric layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, and silicon phosphide.
[0029] In one embodiment, the silicon thin film layer includes a first intrinsic layer;
[0030] The material of the first intrinsic layer includes any one of intrinsic polycrystalline silicon, intrinsic microcrystalline silicon, and intrinsic amorphous silicon.
[0031] In one embodiment, the temperature of the fabrication process for the first passivation layer is lower than the temperature of the fabrication process for the first intrinsic layer; or...
[0032] The density of the first intrinsic layer is higher than that of the first passivation layer.
[0033] In one embodiment, a tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed in a first region of the backlight surface of the substrate, including:
[0034] A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed on the back surface of the substrate.
[0035] Etching removes the tunneling layer, the first doped layer, the dielectric layer, and the silicon thin film layer located in the second region;
[0036] The etched solar cell was cleaned with a cleaning solution;
[0037] The etching rate of the cleaning solution on the silicon thin film layer is lower than that on the dielectric layer.
[0038] In one embodiment, cleaning the etched solar cell with a cleaning solution includes:
[0039] The etched solar cell was cleaned using a water-based cleaning solution.
[0040] The hydrophobicity of the silicon thin film layer is better than that of the dielectric layer.
[0041] Secondly, this application provides a solar cell prepared using the above-described preparation method, the solar cell comprising:
[0042] Substrate;
[0043] A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially stacked in the first region of the backlight surface of the substrate.
[0044] A first passivation layer is disposed on the side of the silicon thin film layer away from the substrate and in a second region of the backlight surface; the second region is disposed adjacent to the first region.
[0045] The second doped layer is disposed on the side of the first passivation layer away from the substrate;
[0046] The first doped layer is disposed within the first opening and is electrically connected to the first doped layer exposed by the first opening; the first opening is disposed in the first region, the first opening penetrates the silicon thin film layer, the second doped layer, the first passivation layer and the dielectric layer, and exposes a portion of the surface of the first doped layer away from the substrate.
[0047] In one embodiment, the solar cell further includes:
[0048] A transparent conductive layer is disposed on the side of the second doped layer away from the substrate; or,
[0049] A transparent conductive layer is disposed on the side of the second doped layer away from the substrate and is in contact with the first doped layer exposed by the first opening.
[0050] In one embodiment, the solar cell further includes:
[0051] An isolation groove is provided on the side of the first opening near the second region, and the isolation groove at least penetrates the transparent conductive layer to isolate the transparent conductive layer between the first region and the second region.
[0052] The aforementioned method for fabricating solar cells and the solar cells themselves, by setting a silicon thin film layer, can protect the dielectric layer and the first doped layer during the fabrication process, and can also improve the insulation performance of the film layer between the first and second doped layers. By setting a dielectric layer between the first and second doped layers, the insulation performance can be further improved, ensuring physical and electrical dual isolation between the first and second doped layers, thereby avoiding the formation of heterojunctions, reducing leakage current, and improving discharge efficiency. Attached Figure Description
[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0054] Figure 1 This is a flowchart of a method for fabricating a solar cell provided in one embodiment;
[0055] Figure 2 A flowchart illustrating a method for fabricating a solar cell as provided in another embodiment;
[0056] Figure 3 This is a flowchart of forming a first opening provided in one embodiment;
[0057] Figure 4 A flowchart illustrating a method for fabricating a solar cell as provided in another embodiment;
[0058] Figure 5 A flowchart illustrating a method for fabricating a solar cell as provided in another embodiment;
[0059] Figure 6 A flowchart illustrating a method for fabricating a solar cell as provided in another embodiment;
[0060] Figure 7 This is a flowchart illustrating the fabrication of a substrate backlight film layer structure in one embodiment;
[0061] Figure 8 A flowchart illustrating a method for fabricating a solar cell as provided in another embodiment;
[0062] Figure 9 This is a schematic diagram of the structure of a solar cell provided in one embodiment;
[0063] Figure 10 This is a schematic diagram of the structure of a solar cell provided in another embodiment;
[0064] Figure 11 This is a schematic diagram of the structure of a solar cell provided in another embodiment;
[0065] Figure 12 This is a schematic diagram of the structure of a solar cell provided in another embodiment;
[0066] Figure 13 This is a partial top view of a solar cell provided in one embodiment.
[0067] Figure label:
[0068] Substrate: 300; Tunneling layer: 301; First doped layer: 302; Dielectric layer: 303; Silicon thin film layer: 304; First passivation layer: 305; Second doped layer: 306; First electrode: 307; Second passivation layer: 308; Anti-reflection layer: 309; Transparent conductive layer: 310; Isolation trench: 311; Second electrode: 312; First diffusion layer: 313; Second diffusion layer: 314; Void region: 315. Detailed Implementation
[0069] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0071] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0073] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0074] Please see Figure 1 and Figure 9 This application provides a method for preparing a solar cell, comprising the following steps:
[0075] Step 102: A tunneling layer 301, a first doped layer 302, a dielectric layer 303 and a silicon thin film layer 304 are sequentially formed in the first region of the back surface of the substrate 300.
[0076] The substrate 300 includes, but is not limited to, a doped semiconductor substrate 300 made of silicon or germanium, or a doped compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Exemplarily, in this embodiment, the substrate 300 may be made of doped single-crystal silicon. Further, the doping element type of the substrate 300 may be N-type, and the N-type element may be, for example, any one of phosphorus, arsenic, or antimony. The doping element type of the substrate 300 may also be P-type, and the P-type element may be, for example, boron or gallium.
[0077] The tunneling layer 301 is used to achieve interface passivation of the substrate 300, achieving a chemical passivation effect. Specifically, by saturating the dangling bonds on the surface of the substrate 300, the interface defect state density of the substrate 300 is reduced, thereby reducing the recombination centers on the surface of the substrate 300 and lowering the carrier recombination rate. The thickness of the tunneling layer 301 is less than or equal to 3 nanometers. Exemplarily, it can be 1 nanometer, 2 nanometers, 3 nanometers, or any value less than or equal to 3 nanometers. The material of the tunneling layer 301 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. The material of the tunneling layer 301 may contain dopants of the same type as the dopant elements in the substrate 300.
[0078] The thickness of the first doped layer 302 is greater than or equal to 10 nanometers and not greater than 600 nanometers. For example, it can be 10 nanometers, 50 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, or any value within the range of 10 nanometers to 600 nanometers. The material of the first doped layer 302 can be doped polycrystalline silicon, or doped polycrystalline silicon containing at least one of oxygen, carbon, and nitrogen. The doping type of the first doped layer 302 can be the same as or opposite to the doping type of the substrate 300.
[0079] The thickness of dielectric layer 303 is greater than or equal to 5 nanometers. For example, it can be 5 nanometers, 6 nanometers, 7 nanometers, etc., and there is no limitation here. Dielectric layer 303 is made of insulating material.
[0080] The thickness of the silicon thin film layer 304 is greater than or equal to 2 nanometers and less than or equal to 100 nanometers. For example, it can be 2 nanometers, 10 nanometers, 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, or any value within the range of 2 nanometers to 100 nanometers. The material of the silicon thin film layer 304 can be intrinsic amorphous silicon, intrinsic polycrystalline silicon, or polycrystalline silicon or amorphous silicon containing at least one of oxygen, carbon, and nitrogen elements. By setting the silicon thin film layer 304, the dielectric layer 303 and the first doped layer 302 can be protected, reducing optical losses during the fabrication process and improving battery efficiency.
[0081] Among them, the tunneling layer 301, the first doped layer 302, the dielectric layer 303, and the silicon thin film layer 304 can all be prepared by plasma-enhanced chemical vapor deposition (PECVD). Alternatively, different films can be prepared by PECVD, plasma-enhanced atomic layer deposition (PEALD), or atomic layer deposition (ALD), etc., without any restrictions.
[0082] Step 104: Sequentially form the first passivation layer 305 and the second doped layer 306.
[0083] The first passivation layer 305 covers the side of the silicon thin film layer 304 away from the substrate 300 and the second region of the backlight surface. The second doped layer 306 is disposed on the side of the first passivation layer 305 away from the substrate 300. The second region is disposed adjacent to the first region.
[0084] The thickness of the first passivation layer 305 is greater than or equal to 3 nanometers and less than or equal to 15 nanometers. For example, it can be 3 nanometers, 6 nanometers, 9 nanometers, 12 nanometers, 15 nanometers, or any value within the range of 3 nanometers to 15 nanometers. The material of the first passivation layer 305 may include intrinsic amorphous silicon, or the material of the first passivation layer 305 may be doped with at least one element selected from oxygen, carbon, and nitrogen, for example, amorphous silicon containing at least one element selected from oxygen, carbon, and nitrogen.
[0085] The material of the second doped layer 306 may include doped amorphous silicon or microcrystalline silicon, or doped amorphous silicon or microcrystalline silicon containing at least one of oxygen, carbon, and nitrogen. The doping type of the second doped layer 306 is opposite to that of the first doped layer 302. In this embodiment, the thickness of the second doped layer 306 ranges from 3 to 60 nanometers. Exemplarily, it can be any value within the range of 3 nanometers, 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, or 3 to 60 nanometers. In this embodiment, the first passivation layer 305 and the second doped layer 306 extend from the space containing the first region to the space containing the second region, respectively. It can be understood that the first passivation layer 305 covers the second region of the silicon thin film layer 304 and the substrate 300, and the second doped layer 306 covers the side of the first passivation layer 305 away from the substrate 300.
[0086] Understandably, when the first passivation layer 305 is made of intrinsic amorphous silicon, due to its thin film structure, it may not be able to effectively insulate the first doped layer 302 and the second doped layer 306. This would lead to the formation of a heterojunction between the first doped layer 302, the first passivation layer 305, and the second doped layer 306. The built-in electric field of this heterojunction would drive the movement of charge carriers, and this movement would be opposite to the direction of current movement in the solar cell, thus generating leakage current. By providing a dielectric layer 303 between the first doped layer 302 and the second doped layer 306, a high-quality, dense film can be formed, increasing the insulation performance of the film structure between the first doped layer 302 and the second doped layer 306, ensuring electrical isolation between the first doped layer 302 and the second doped layer 306, thereby avoiding the formation of a heterojunction and reducing leakage current.
[0087] In this embodiment, the first region and the second region may be flush or not. Optionally, there is a step between the substrate 300 containing the first region and the substrate 300 containing the second region, see reference. Figure 13 The thickness of the substrate 300 containing the first region is greater than or equal to the thickness of the substrate 300 containing the second region.
[0088] Step 106: Etch the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304 and the dielectric layer 303 located in the first region to form a first opening, the first opening exposing a portion of the surface of the first doped layer 302 away from the substrate 300.
[0089] The first opening exposes a portion of the surface of the first doped layer 302 on the side away from the substrate 300, providing a basis for setting the electrodes.
[0090] Step 108: Form a first electrode 307, which is electrically connected to the first doped layer 302 exposed by the first opening.
[0091] The material of the first electrode 307 includes, but is not limited to, one or more of aluminum (Al), titanium (Ti), nickel (Ni), cobalt (Co), silver (Ag), copper (Cu), and tin (Sn). The first electrode 307 can be formed by screen printing, laser transfer, or electroplating. In the embodiments of this application, the first electrode 307 can be understood as a metal grid line, and the width and thickness of the metal grid line are not limited.
[0092] The above-described method for fabricating solar cells, by setting a silicon thin film layer 304, can protect the dielectric layer 303 and the first doped layer 302 during the fabrication process, and can also improve the insulation performance of the film layer between the first doped layer 302 and the second doped layer 306. By setting a dielectric layer 303 between the first doped layer 302 and the second doped layer 306, the insulation performance can be further improved, ensuring physical and electrical dual isolation between the first doped layer 302 and the second doped layer 306, thereby avoiding the formation of heterojunctions, reducing leakage current, and improving discharge efficiency.
[0093] In one embodiment, see [reference] Figure 2 and Figure 9 The preparation method also includes:
[0094] Step 110: A second passivation layer 308 and an antireflection layer 309 are sequentially formed on the light-receiving surface of the substrate 300.
[0095] The material of the second passivation layer 308 can be at least one of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the material of the second passivation layer 308 can also be intrinsic amorphous silicon, or amorphous silicon containing at least one of oxygen, carbon, and nitrogen. The thickness of the second passivation layer 308 can be greater than or equal to 1.5 nanometers; for example, it can be 1.5 nanometers, 2 nanometers, 3 nanometers, 4 nanometers, etc., without limitation. In addition, the second passivation layer 308 can be formed by chemical deposition. The second passivation layer 308 plays a surface passivation role in the solar cell, and can effectively chemically passivate the dangling bonds on the surface of the substrate 300.
[0096] The antireflection layer 309 can be a single-layer or multi-layer structure. In a multi-layer antireflection layer 309, each layer can be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the antireflection layer 309 can be greater than or equal to 40 nanometers. For example, it can be 40 nanometers, 45 nanometers, 50 nanometers, etc., and there is no limitation here.
[0097] Optionally, a portion of the light-receiving surface of the substrate 300 may be texturized. For example, a doped single-crystal silicon substrate will be used as an example. The anisotropic etching properties of the silicon substrate reacting in a low-concentration alkaline solution create a pyramidal textured surface. Furthermore, surface contaminants and cutting damage layers on the silicon substrate can be removed, thereby reducing reflectivity and increasing the absorption of sunlight by the silicon substrate.
[0098] In one embodiment, the first etch selectivity ratio of the silicon thin film layer 304 and the dielectric layer 303 is greater than the second etch selectivity ratio of the silicon thin film layer 304 and the first doped layer 302.
[0099] Etching selectivity refers to the ratio of the etching rates of different materials. A higher etching selectivity indicates that the etching process has a much higher etching rate for one material than for another. In this embodiment, the first etching selectivity of the silicon thin film layer 304 and the dielectric layer 303 is greater than the second etching selectivity of the silicon thin film layer 304 and the first doped layer 302. This means that the etching rate of the dielectric layer 303 is less than the etching rate of the first doped layer 302, i.e., the dielectric layer 303 is more difficult to etch than the first doped layer 302. By limiting the etching rate of the dielectric layer 303 to be more difficult than the first doped layer 302, etching can be stopped at the dielectric layer 303, thereby reducing damage to the dielectric layer 303 during laser etching.
[0100] In one embodiment, see [reference] Figure 3 The etching of the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304, and the dielectric layer 303 located in the first region forms the first opening, including:
[0101] Step 1061: Laser etching of the second doped layer 306, the first passivation layer 305 and the silicon thin film layer 304 located in the first region to expose a portion of the surface of the dielectric layer 303 away from the substrate 300.
[0102] Step 1062: Wet etching is used to etch the exposed dielectric layer 303 to the surface of the first doped layer 302 away from the substrate 300 to form a first opening.
[0103] The dielectric layer 303 has a thickness greater than 5 nm. For example, the thickness of the dielectric layer 303 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.
[0104] By etching to form the first opening, a portion of the first doped layer 302 can be exposed, providing a basis for the electrical connection between the first electrode 307 and the first doped layer 302. Laser etching of the second doped layer 306, the first passivation layer 305, and the silicon thin film layer 304, which are located away from the first doped layer 302, allows for high-speed and efficient formation of the first opening. Furthermore, laser etching is a non-contact process, reducing the risk of cracking in the substrate 300. If the dielectric layer 303 is too thin, the laser energy may break it down, damaging the first doped layer 302 and the tunneling layer 301. By limiting the thickness of the dielectric layer 303 to greater than 5 nanometers, the risk of breakdown can be reduced, thus protecting the first doped layer 302 and the tunneling layer 301. Since the dielectric layer 303 is adjacent to the first doped layer 302, laser etching of the dielectric layer 303 may damage the first doped layer 302. By wet etching the dielectric layer 303, the dielectric layer 303 can be etched relatively gently to expose part of the first doped layer 302, reducing damage to the first doped layer 302.
[0105] In one embodiment, the surface of the dielectric layer 303 to the first doped layer 302 exposed by wet etching on the side away from the substrate 300 includes:
[0106] Acid etching exposes the dielectric layer 303 to the surface of the first doped layer 302 on the side away from the substrate 300.
[0107] Acid etching can be performed using hydrofluoric acid, hot phosphoric acid, etc. Acid etching has a higher selectivity for the dielectric layer 303 than for the first doped layer 302, which can remove the dielectric layer 303 more efficiently and reduce damage to the first doped layer 302.
[0108] Understandably, after laser etching, residues will form within the etched opening. Without the dielectric layer 303, these residues would form on the surface of the first doped layer 302, affecting the electrical contact between the first doped layer 302 and the transparent conductive layer 310 or the first electrode 307, introducing high contact resistance. By providing the dielectric layer 303 and using acid etching, the dielectric layer 303 can be dissolved, preventing residues from adhering to it and thus removing them. Simultaneously, wet acid etching can also remove residues from the sidewalls of the laser-etched opening, thereby preventing leakage current, reducing carrier recombination, and improving discharge efficiency.
[0109] In one embodiment, see [reference] Figure 4 and Figure 9 Before etching the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304, and the dielectric layer 303 located in the first region to form the first opening, the method further includes:
[0110] Step 202: Form a transparent conductive layer 310, which is disposed on the side of the second doped layer 306 away from the substrate 300.
[0111] The transparent conductive layer 310 can be made of one or more of zinc oxide (ZnO), indium oxide (InO), and tin oxide (SnO). The transparent conductive material can be doped with one or more of gallium (Ga), tin (Sn), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al).
[0112] Step 204: Etch the transparent conductive layer 310 disposed in the first region to form a second opening. The second opening exposes the surface of the second doped layer 306 away from the substrate 300, and the second opening coincides with the orthographic projection of the first opening on the surface of the substrate 300.
[0113] The method of etching the transparent conductive layer 310 is the same as the method of etching the second doped layer 306. Steps 204 and 1061 can be performed sequentially. That is, after laser etching penetrates the transparent conductive layer 310, the second doped layer 306, the first passivation layer 305 and the silicon thin film layer 304 are etched sequentially by laser.
[0114] After the transparent conductive layer 310 is formed, the second opening is etched by laser. The first opening formed subsequently does not contain the transparent conductive layer 310, which can reduce the material of the transparent conductive layer 310 and reduce costs.
[0115] In this embodiment, the first electrode 307 can be directly electrically connected to the first doped layer 302 in the first opening.
[0116] In another embodiment, see Figure 5 and Figure 10After etching the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304, and the dielectric layer 303 located in the first region to form the first opening, the fabrication method further includes:
[0117] Step 206: Form a transparent conductive layer 310. The transparent conductive layer 310 is disposed on the side of the second doped layer 306 away from the substrate 300 and is in contact with the first doped layer 302 exposed by the first opening.
[0118] The transparent conductive layer 310 has been described in detail in the foregoing embodiments and will not be repeated here. After etching to form the first opening, the transparent conductive layer 310 is formed inside the first opening. The transparent conductive layer 310 inside the first opening can act as a barrier layer to protect the first doped layer 302.
[0119] In one embodiment, see [reference] Figure 6 After forming the transparent conductive layer 310, the preparation method further includes:
[0120] Step 208: Form an isolation trench 311. The isolation trench 311 is located on the side of the first opening near the second region, and the isolation trench 311 at least penetrates the transparent conductive layer 310 to isolate the transparent conductive layer 310 of the first region and the second region.
[0121] It is understandable that the first and second regions have different electrical characteristics. If the functional layers of the first and second regions are continuous, a lateral parasitic channel will be formed, resulting in lateral leakage current. To reduce leakage current and increase open-circuit voltage, the transparent conductive layer 310 of the first and second regions is isolated by an isolation trench 311. The isolation trench 311 can be formed by etching, and step 208 can be performed simultaneously with step 204 to shorten the fabrication time and simplify the fabrication steps.
[0122] Since the first opening is used to set the first electrode 307, the isolation groove 311 is set on the side of the first opening close to the second region, that is, the isolation groove 311 is set between the first electrode 307 and the second electrode 312 in the second region, which can be used to achieve insulation between the first electrode 307 and the second electrode 312.
[0123] In one embodiment, see [reference] Figure 9 and Figure 10 The isolation groove 311 penetrates the transparent conductive layer 310 and is located at the edge of the first and second regions. Through the aforementioned restriction, the transparent conductive layer 310 of the first and second regions can be isolated, reducing leakage current.
[0124] In another embodiment, see Figure 11The isolation trench 311 is located in the first region and penetrates the transparent conductive layer 310. Through the aforementioned limitations, the requirements for the etching process are reduced, and the fabrication time is shortened.
[0125] In another embodiment, see Figure 12 The isolation trench 311 is disposed in the first region and penetrates the transparent conductive layer 310, the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304, and part of the dielectric layer 303. Through the aforementioned limitation, deep electrical isolation can be achieved, reducing parasitic channels.
[0126] In one embodiment, the first doped layer 302 is made of doped polycrystalline silicon. The dielectric layer 303 is made of at least one of silicon oxide, silicon nitride, silicon carbide, and silicon phosphide. All of the aforementioned dielectric materials are high-resistivity materials with good insulating properties, enabling electrical isolation between the first doped layer 302 and the second doped layer 306, thus preventing short circuits.
[0127] In one embodiment, the silicon thin film layer 304 includes a first intrinsic layer, the material of which includes any one of intrinsic polycrystalline silicon, intrinsic microcrystalline silicon, and intrinsic amorphous silicon.
[0128] It is understandable that the dielectric layer 303 is relatively thinner than the first intrinsic layer and is more susceptible to damage, thus failing to effectively protect the first doped layer 302. To improve the protection of the dielectric layer 303, the embodiments of this application provide a first intrinsic layer. By providing the first intrinsic layer, the dielectric layer 303 can be effectively protected from damage caused by other film layer fabrication processes.
[0129] In one embodiment, the temperature of the fabrication process of the first passivation layer 305 is lower than the temperature of the fabrication process of the first intrinsic layer.
[0130] By limiting the fabrication temperature of the first passivation layer 305 to be lower than that of the fabrication temperature of the first intrinsic layer, a first intrinsic layer with higher density can be obtained, thereby better protecting the dielectric layer 303.
[0131] In another embodiment, the density of the first intrinsic layer is higher than the density of the first passivation layer 305.
[0132] Higher density means that the atoms or molecules are arranged more tightly and there are fewer internal gaps. Using a first intrinsic layer with higher density to protect the dielectric layer 303 can effectively block the penetration and corrosion of chemical substances and inhibit the diffusion of impurity ions.
[0133] In one embodiment, see [reference] Figure 7A tunneling layer 301, a first doped layer 302, a dielectric layer 303, and a silicon thin film layer 304 are sequentially formed in a first region of the backlight surface of the substrate 300, including:
[0134] Step 1021: A tunneling layer 301, a first doped layer 302, a dielectric layer 303 and a silicon thin film layer 304 are sequentially formed on the back surface of the substrate 300.
[0135] The formation method can be plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or atomic layer deposition (ALD), etc., and there are no restrictions here.
[0136] Step 1022: Etch away the tunneling layer 301, the first doped layer 302, the dielectric layer 303 and the silicon thin film layer 304 located in the second region.
[0137] Laser etching can be used for etching.
[0138] Step 1023: Clean the etched solar cells with a cleaning solution.
[0139] The etching rate of the cleaning solution on the silicon thin film layer 304 is lower than that on the dielectric layer 303.
[0140] Understandably, without the dielectric layer 303, dopants or metal ions on the surface of the first doped layer 302 might migrate to other areas via the cleaning solution, affecting not only the cleaning effect but also the passivation level of subsequent film layers, especially the passivation level of the film structure in the second region. Cleaning the solar cell with the dielectric layer 303 effectively prevents dopants and metal ions on the surface of the first doped layer 302 from escaping into the cleaning solution. By limiting the etching rate of the cleaning solution on the silicon thin film to be lower than the etching rate on the dielectric layer 303, the dielectric layer 303 can be effectively protected from damage, thereby better confining the dopants and metal ions in the first doped layer 302.
[0141] Cleaning the etched solar cells can remove residues generated during the etching process and reduce surface contamination.
[0142] In one embodiment, cleaning the etched solar cell with a cleaning solution includes:
[0143] Water-based cleaning solution was used to clean the etched solar cells.
[0144] Among them, the hydrophobicity of silicon thin film layer 304 is better than that of dielectric layer 303.
[0145] Understandably, dielectric layer 303 is more hydrophilic than silicon thin film layer 304. Without silicon thin film layer 304, residues would easily remain on the surface of dielectric layer 303 after cleaning with water-based cleaning solution, affecting the preparation of subsequent film layers. By setting silicon thin film layer 304 outside dielectric layer 303 and limiting its hydrophobicity, the residue of water-based cleaning solution on the solar cell can be reduced, ensuring the cleanliness of the outermost layer of the solar cell—silicon thin film layer 304—in the current step.
[0146] In another embodiment, see Figure 11 The dielectric layer 303 has a void region 315 near the edge of the first passivation layer 305. That is, no dielectric material is provided in the edge region of the dielectric layer 303 near the first passivation layer 305.
[0147] The width of the void region 315 is greater than 20 nanometers. For example, it can be 20 nanometers, 2 nanometers, or 30 nanometers, and there is no limitation here. Note that when the isolation trench 311 penetrates part of the dielectric layer 303, the orthographic projections of the isolation trench 311 and the void region 315 on the substrate 300 do not coincide.
[0148] By setting the void region 315, the first doped layer 302 can be prevented from collecting carriers at the interface, thereby reducing short circuits.
[0149] In one embodiment, see [reference] Figures 8 to 12 After forming the transparent conductive layer 310, the preparation method further includes:
[0150] Step 210: Form a second electrode 312. The second electrode 312 is disposed in the second region and is electrically connected to the second doped layer 306 through the transparent conductive layer 310.
[0151] The material and arrangement of the second electrode 312 are the same as those of the first electrode 307, and will not be described again here.
[0152] In one embodiment, the fabrication method further includes, prior to forming the tunneling layer 301 and the first doped layer 302:
[0153] See Figures 9 to 12 A first diffusion layer 313 is formed on the back surface of the substrate 300. The first diffusion layer 313 can be formed by depositing relevant diffusion materials on the back surface of the substrate 300 using methods such as plasma-enhanced chemical vapor deposition (PECVD).
[0154] The first diffusion layer 313 has the same doping type as the first doped layer 302, and the doping concentration of the first diffusion layer 313 is less than or equal to the doping concentration of the first doped layer 302. The diffusion depth of the dopant element in the first diffusion layer 313 is greater than or equal to 10 nanometers and less than or equal to 1500 nanometers. For example, the diffusion depth can be any depth among 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, 1000 nanometers, 1100 nanometers, 1200 nanometers, 1300 nanometers, 1400 nanometers, and 1500 nanometers. The first diffusion layer 313 can improve the diffusion of dopant elements in the substrate 300 and the first doped layer 302.
[0155] In one embodiment, the preparation method further includes, prior to the formation of the second passivation layer 308 and the antireflection layer 309:
[0156] See Figures 9 to 12 A second diffusion layer 314 is formed on the light-receiving surface of the substrate 300. The formation method of the second diffusion layer 314 is the same as that of the first diffusion layer 313, and will not be described in detail here.
[0157] The second diffusion layer 314 has the same or opposite doping type as the substrate 300, and the doping concentration of the second diffusion layer 314 is greater than or equal to the doping concentration of the substrate 300. Here, the substrate 300 refers to the portion excluding the first diffusion layer 313 and the second diffusion layer 314. The diffusion depth of the doped element in the second diffusion layer 314 is greater than or equal to 10 nanometers and less than or equal to 1500 nanometers. For example, the diffusion depth can be any depth among 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, 1000 nanometers, 1100 nanometers, 1200 nanometers, 1300 nanometers, 1400 nanometers, and 1500 nanometers. By forming the second diffusion layer 314, the fill factor of the solar cell can be improved.
[0158] It should be understood that while the steps in the flowchart are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Furthermore, at least some steps in certain figures may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is also not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages within other steps.
[0159] In one embodiment, this application provides a solar cell prepared using the above-described solar cell preparation method, see reference. Figures 9 to 12 The solar cell includes a substrate 300, a tunneling layer 301, a first doped layer 302, a dielectric layer 303, a silicon thin film layer 304, a first passivation layer 305, a second doped layer 306, and a first electrode 307.
[0160] The substrate 300 includes, but is not limited to, a doped semiconductor substrate made of silicon or germanium, or a doped compound semiconductor substrate 300 made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The tunneling layer 301, the first doped layer 302, the dielectric layer 303, and the silicon thin film layer 304 are sequentially stacked on the first region of the backlight surface of the substrate 300.
[0161] The thickness of the tunneling layer 301 is less than or equal to 3 nanometers. For example, it can be 1 nanometer, 2 nanometers, 3 nanometers, or any value less than or equal to 3 nanometers. The material of the tunneling layer 301 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. The material of the tunneling layer 301 may contain dopant elements of the same type as those in the substrate 300. The tunneling layer 301 is used to achieve interface passivation of the substrate 300, providing a chemical passivation effect.
[0162] The thickness of the first doped layer 302 is greater than or equal to 10 nanometers and not greater than 600 nanometers. For example, it can be 10 nanometers, 50 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, or any value within the range of 10 nanometers to 600 nanometers. The material of the first doped layer 302 can be doped polycrystalline silicon, or doped polycrystalline silicon containing at least one of oxygen, carbon, and nitrogen. The doping type of the first doped layer 302 can be the same as or opposite to the doping type of the substrate 300.
[0163] The thickness of the dielectric layer 303 is greater than or equal to 5 nanometers; for example, it can be 5 nanometers, 6 nanometers, 7 nanometers, etc., and is not limited here. The dielectric layer 303 is made of an insulating material. By limiting the thickness of the dielectric layer 303 to greater than 5 nanometers, the first doped layer 302 can be protected from laser damage during the subsequent fabrication of the first opening.
[0164] The thickness of the silicon thin film layer 304 is greater than or equal to 2 nanometers and less than or equal to 100 nanometers. For example, it can be 2 nanometers, 10 nanometers, 25 nanometers, 50 nanometers, 75 nanometers, 100 nanometers, or any value within the range of 2 nanometers to 100 nanometers. The material of the silicon thin film layer 304 can be intrinsic amorphous silicon, intrinsic polycrystalline silicon, or polycrystalline silicon or amorphous silicon containing at least one of the elements oxygen, carbon, and nitrogen.
[0165] The first passivation layer 305 is disposed on the side of the silicon thin film layer 304 away from the substrate 300 and in the second region of the backlight surface, and the second region is disposed adjacent to the first region.
[0166] The thickness of the first passivation layer 305 is greater than or equal to 3 nanometers and less than or equal to 15 nanometers. For example, it can be 3 nanometers, 6 nanometers, 9 nanometers, 12 nanometers, 15 nanometers, or any value within the range of 3 nanometers to 15 nanometers. The material of the first passivation layer 305 may include intrinsic amorphous silicon, or the material of the first passivation layer 305 may be doped with at least one element selected from oxygen, carbon, and nitrogen, for example, amorphous silicon containing at least one element selected from oxygen, carbon, and nitrogen.
[0167] In this embodiment, the first region and the second region may be flush or not. Optionally, there is a step between the substrate 300 containing the first region and the substrate 300 containing the second region, see reference. Figure 13 The thickness of the substrate 300 containing the first region is greater than or equal to the thickness of the substrate 300 containing the second region.
[0168] The second doped layer 306 is disposed on the side of the first passivation layer 305 away from the substrate 300. The material of the second doped layer 306 may include doped amorphous silicon or microcrystalline silicon, or doped amorphous silicon or microcrystalline silicon containing at least one of oxygen, carbon, and nitrogen. The doping type of the second doped layer 306 is opposite to that of the first doped layer 302. In this embodiment, the thickness of the second doped layer 306 ranges from 3 to 60 nanometers. Exemplarily, it can be any value within the range of 3 nanometers, 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, 50 nanometers, 60 nanometers, or any value within the range of 3 to 60 nanometers.
[0169] The first electrode 307 is disposed in the first opening and is electrically connected to the first doped layer 302 exposed by the first opening. The first opening is disposed in the first region and penetrates the silicon thin film layer 304, the second doped layer 306, the first passivation layer 305 and the dielectric layer 303, and exposes a portion of the surface of the first doped layer 302 away from the substrate 300.
[0170] The material of the first electrode 307 includes, but is not limited to, one or more of aluminum (Al), titanium (Ti), nickel (Ni), cobalt (Co), silver (Ag), copper (Cu), and tin (Sn). The first electrode 307 can be formed by screen printing, laser transfer, or electroplating. In the embodiments of this application, the first electrode 307 can be understood as a metal grid line, and the width and thickness of the metal grid line are not limited.
[0171] The first opening can be formed by a combination of laser etching and wet etching. For example, laser etching is performed on the second doped layer 306, the first passivation layer 305, and the silicon thin film layer 304 located in the first region to expose a portion of the surface of the dielectric layer 303 away from the substrate 300. Wet etching is then performed on the exposed surface of the dielectric layer 303 to the surface of the first doped layer 302 away from the substrate 300 to form the first opening.
[0172] The aforementioned solar cell, by providing a silicon thin film layer 304, can protect the dielectric layer 303 and the first doped layer 302, and also improve the insulation performance of the film layer between the first doped layer 302 and the second doped layer 306. By providing a dielectric layer 303 between the first doped layer 302 and the second doped layer 306, the insulation performance can be further improved, ensuring physical and electrical dual isolation between the first doped layer 302 and the second doped layer 306, thereby avoiding the formation of a heterojunction, reducing leakage current, and improving discharge efficiency.
[0173] In one embodiment, see [reference] Figures 9 to 12 The solar cell also includes a second passivation layer 308 and an antireflection layer 309.
[0174] The material of the second passivation layer 308 can be at least one of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the material of the second passivation layer 308 can also be intrinsic amorphous silicon, or amorphous silicon containing at least one of oxygen, carbon, and nitrogen. The thickness of the second passivation layer 308 can be greater than or equal to 1.5 nanometers, and for example, it can be 1.5 nanometers, 2 nanometers, 3 nanometers, 4 nanometers, etc., without limitation.
[0175] The antireflection layer 309 can be a single-layer or multi-layer structure. In a multi-layer antireflection layer 309, each layer can be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the antireflection layer 309 can be greater than or equal to 40 nanometers. For example, it can be 40 nanometers, 45 nanometers, 50 nanometers, etc., and there is no limitation here.
[0176] In one embodiment, see [reference] Figure 9 The solar cell also includes a transparent conductive layer 310.
[0177] The transparent conductive layer 310 is disposed on the side of the second doped layer 306 away from the substrate 300.
[0178] Since the second doped layer 306 in the first opening has been removed by laser etching, and there is no second doped layer 306 in the first opening, the transparent conductive layer 310 disposed on the side of the second doped layer 306 away from the substrate 300 is also not disposed in the first opening.
[0179] In another embodiment, see Figure 10The solar cell also includes a transparent conductive layer 310.
[0180] The transparent conductive layer 310 is disposed on the side of the second doped layer 306 away from the substrate 300 and is in contact with the first doped layer 302 exposed by the first opening.
[0181] The transparent conductive layer 310 can be made of one or more of zinc oxide (ZnO), indium oxide (InO), and tin oxide (SnO). The transparent conductive material can be doped with one or more of gallium (Ga), tin (Sn), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al).
[0182] In one embodiment, see [reference] Figures 9 to 12 The solar cell also includes an isolation trench 311.
[0183] An isolation groove 311 is provided on the side of the first opening near the second region, and the isolation groove 311 penetrates at least through the transparent conductive layer 310 to isolate the transparent conductive layer 310 of the first region and the second region.
[0184] It is understandable that the first region and the second region have different electrical characteristics. If the functional layers of the first region and the second region are continuous, a lateral parasitic channel will be formed, which will then generate lateral leakage current. In order to reduce leakage current and increase open-circuit voltage, the transparent conductive layer 310 of the first region and the second region is isolated by the isolation groove 311.
[0185] In one embodiment, see [reference] Figure 9 and Figure 10 The isolation groove 311 penetrates the transparent conductive layer 310 and is located at the edge of the first region and the second region.
[0186] In another embodiment, see Figure 11 The isolation groove 311 is located in the first region and penetrates the transparent conductive layer 310.
[0187] In another embodiment, see Figure 12 The isolation trench 311 is located in the first region and penetrates the transparent conductive layer 310, the second doped layer 306, the first passivation layer 305, the silicon thin film layer 304, and part of the dielectric layer 303.
[0188] In one embodiment, the first doped layer 302 is made of doped polysilicon. The dielectric layer 303 is made of at least one of silicon oxide, silicon nitride, silicon carbide, and silicon phosphide.
[0189] In one embodiment, the silicon thin film layer 304 includes a first intrinsic layer, the material of which includes intrinsic polycrystalline silicon, intrinsic microcrystalline silicon, and intrinsic amorphous silicon. By providing the first intrinsic layer, the dielectric layer 303 can be effectively protected from damage caused by other film layer fabrication processes.
[0190] In one embodiment, the density of the first intrinsic layer is higher than that of the first passivation layer 305. Using a first intrinsic layer with higher density to protect the dielectric layer 303 can effectively block the penetration and corrosion of chemical substances and inhibit the diffusion of impurity ions.
[0191] In one embodiment, the silicon thin film layer 304 is more hydrophobic than the dielectric layer 303. By limiting the hydrophobicity of the silicon thin film layer 304, the residue of water-based cleaning solution on the solar cell after cleaning can be reduced.
[0192] In one embodiment, see [reference] Figure 11 The dielectric layer 303 has a void region 315 near the edge of the first passivation layer 305. That is, no dielectric material is provided in the edge region of the dielectric layer 303 near the first passivation layer 305.
[0193] The width of the void region 315 is greater than 20 nanometers. For example, it can be 20 nanometers, 2 nanometers, or 30 nanometers, and there is no limitation here. Note that when the isolation trench 311 penetrates part of the dielectric layer 303, the orthographic projections of the isolation trench 311 and the void region 315 on the substrate 300 do not coincide.
[0194] In one embodiment, see [reference] Figures 9 to 12 The solar cell also includes a second electrode 312, which is disposed in the second region and electrically connected to the second doped layer 306 through a transparent conductive layer 310. The material of the second electrode 312 is the same as that of the first electrode 307, and will not be described in detail here.
[0195] In one embodiment, see [reference] Figures 9 to 12 The solar cell also includes a first diffusion layer 313 and a second diffusion layer 314.
[0196] The first diffusion layer 313 is located between the substrate 300 and the tunneling layer 301. The doping type of the first diffusion layer 313 is the same as that of the first doped layer 302, and the doping concentration of the first diffusion layer 313 is less than or equal to the doping concentration of the first doped layer 302. The diffusion depth of the doped element in the first diffusion layer 313 is greater than or equal to 10 nanometers and less than or equal to 1500 nanometers. For example, the diffusion depth can be any depth among 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, 1000 nanometers, 1100 nanometers, 1200 nanometers, 1300 nanometers, 1400 nanometers, and 1500 nanometers.
[0197] The second diffusion layer 314 is located between the substrate 300 and the second passivation layer 308. The doping type of the second diffusion layer 314 is the same as or opposite to the doping type of the substrate 300, and the doping concentration of the second diffusion layer 314 is greater than or equal to the doping concentration of the substrate 300. In this embodiment, the substrate 300 refers to the portion excluding the first diffusion layer 313 and the second diffusion layer 314. The diffusion depth of the doped element in the second diffusion layer 314 is greater than or equal to 10 nanometers and less than or equal to 1500 nanometers. For example, the diffusion depth can be any depth among 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, 800 nanometers, 900 nanometers, 1000 nanometers, 1100 nanometers, 1200 nanometers, 1300 nanometers, 1400 nanometers, and 1500 nanometers.
[0198] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0199] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0200] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a solar cell, characterized in that, include: A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed in the first region of the back surface of the substrate. The first passivation layer and the second doped layer are formed sequentially; The first passivation layer covers the side of the silicon thin film layer away from the substrate and the second region of the backlight surface; the second doped layer is disposed on the side of the first passivation layer away from the substrate; the second region is disposed adjacent to the first region. The second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region are etched to form a first opening; The first opening exposes a portion of the surface of the first doped layer on the side away from the substrate; Form the first electrode; The first electrode is electrically connected to the first doped layer exposed by the first opening.
2. The method for preparing a solar cell according to claim 1, characterized in that, The first etching selectivity ratio of the silicon thin film layer and the dielectric layer is greater than the second etching selectivity ratio of the silicon thin film layer and the first doped layer.
3. The method for preparing a solar cell according to claim 2, characterized in that, The etching of the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region forms a first opening, including: Laser etching is performed on the second doped layer, the first passivation layer, and the silicon thin film layer located in the first region to expose a portion of the surface of the dielectric layer away from the substrate; Wet etching is used to expose the dielectric layer to the surface of the first doped layer on the side away from the substrate, forming a first opening; The dielectric layer has a thickness greater than 5 nm.
4. The method for preparing a solar cell according to claim 3, characterized in that, The wet etching exposes the dielectric layer to the surface of the first doped layer on the side away from the substrate, including: Acid etching exposes the dielectric layer to the surface of the first doped layer on the side away from the substrate.
5. The method for preparing a solar cell according to any one of claims 1 to 3, characterized in that, Before the etching of the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region to form the first opening, the method further includes: A transparent conductive layer is formed on the side of the second doped layer away from the substrate; Etching the transparent conductive layer in the first region forms a second opening, the second opening exposing the surface of the second doped layer away from the substrate, the second opening coinciding with the orthographic projection of the first opening onto the substrate surface; or, After etching the second doped layer, the first passivation layer, the silicon thin film layer, and the dielectric layer located in the first region to form the first opening, the process further includes: A transparent conductive layer is formed on the side of the second doped layer away from the substrate and in contact with the first doped layer exposed by the first opening.
6. The method for preparing a solar cell according to claim 5, characterized in that, After forming the transparent conductive layer, the method further includes: An isolation groove is formed, which is located on the side of the first opening near the second region, and the isolation groove at least penetrates the transparent conductive layer to isolate the transparent conductive layer of the first region and the second region.
7. The method for preparing a solar cell according to claim 6, characterized in that, The isolation groove penetrates the transparent conductive layer and is located at the edge region of the first region and the second region; or... The isolation groove is located in the first region and penetrates the transparent conductive layer; or... The isolation trench is located in the first region and extends through the transparent conductive layer, the second doped layer, the first passivation layer, the silicon thin film layer, and a portion of the dielectric layer.
8. The method for preparing a solar cell according to claim 2, characterized in that, The material of the first doped layer includes doped polycrystalline silicon; The dielectric layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, and silicon phosphide.
9. The method for preparing a solar cell according to claim 1, characterized in that, The silicon thin film layer includes a first intrinsic layer; The material of the first intrinsic layer includes any one of intrinsic polycrystalline silicon, intrinsic microcrystalline silicon, and intrinsic amorphous silicon.
10. The method for preparing a solar cell according to claim 9, characterized in that, The temperature of the first passivation layer preparation process is lower than the temperature of the first intrinsic layer preparation process. or, The density of the first passivation layer and the first intrinsic layer is higher than the density of the first passivation layer.
11. The method for preparing a solar cell according to claim 1, characterized in that, A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed in a first region on the back surface of the substrate, including: A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially formed on the back surface of the substrate. The tunneling layer, the first doped layer, the dielectric layer, and the silicon thin film layer located in the second region are removed by etching. The etched solar cell was cleaned with a cleaning solution; The etching rate of the cleaning solution on the silicon thin film layer is lower than that on the dielectric layer.
12. The method for preparing a solar cell according to claim 11, characterized in that, The process of cleaning the etched solar cell with a cleaning solution includes: The etched solar cell was cleaned using a water-based cleaning solution. The hydrophobicity of the silicon thin film layer is better than that of the dielectric layer.
13. A solar cell, characterized in that, The solar cell is prepared by the preparation method according to any one of claims 1-12, comprising: Substrate; A tunneling layer, a first doped layer, a dielectric layer, and a silicon thin film layer are sequentially stacked in the first region of the backlight surface of the substrate. A first passivation layer is disposed on the side of the silicon thin film layer away from the substrate and in a second region of the backlight surface; the second region is disposed adjacent to the first region. The second doped layer is disposed on the side of the first passivation layer away from the substrate; A first electrode is disposed within a first opening and electrically connected to the first doped layer exposed by the first opening; the first opening is disposed in the first region, the first opening penetrates the silicon thin film layer, the second doped layer, the first passivation layer and the dielectric layer, and exposes a portion of the surface of the first doped layer away from the substrate.
14. The solar cell according to claim 13, characterized in that, The solar cell also includes: A transparent conductive layer is disposed on the side of the second doped layer away from the substrate; or, A transparent conductive layer is disposed on the side of the second doped layer away from the substrate and is in contact with the first doped layer exposed by the first opening.
15. The solar cell according to claim 14, characterized in that, The solar cell also includes: An isolation groove is provided on the side of the first opening near the second region, and the isolation groove at least penetrates the transparent conductive layer to isolate the transparent conductive layer between the first region and the second region.