Photovoltaic cell, photovoltaic module and method for manufacturing a photovoltaic cell

Abstract

This application relates to photovoltaic cells, photovoltaic modules, and methods for manufacturing photovoltaic cells. A photovoltaic cell includes: a substrate having a first surface and a second surface disposed opposite to each other; a tunneling passivation structure disposed on the second surface; and an emitter layer disposed on the first surface and doped with p-type elements. The first surface includes a metal electrode region and a non-metal electrode region, and the portion of the emitter layer corresponding to the non-metal electrode region is doped with carbon elements. The above-described photovoltaic cell, photovoltaic module, and method for manufacturing photovoltaic cells can solve the problems of severe carrier recombination and insufficient surface passivation performance caused by high concentrations of B vacancies in the boron-diffused emitter on the front surface of existing TOPCon cells.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell technology, and in particular to photovoltaic cells, photovoltaic modules, and methods for manufacturing photovoltaic cells. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells significantly reduce back surface recombination due to their passivated contact structure with a tunneling oxide layer and a doped polycrystalline silicon layer on the back side, and have achieved mass production efficiencies of over 25%. However, their front surface still generally uses a traditional boron-diffused emitter. This structure is prone to generating a high concentration of B vacancies during boron diffusion, which become carrier recombination centers, resulting in an extremely high front surface recombination current density (J0), which severely restricts further improvements in open-circuit voltage and conversion efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for manufacturing photovoltaic cells, photovoltaic modules, and photovoltaic cells to solve the problems of severe carrier recombination and insufficient surface passivation performance caused by high concentration of B vacancies in the boron diffusion emitter on the front surface of existing TOPCon cells.

[0004] A photovoltaic cell, the photovoltaic cell comprising:

[0005] The substrate has a first surface and a second surface that are arranged opposite to each other.

[0006] A tunneling passivation structure is disposed on the second surface; and

[0007] An emitter layer is disposed on the first surface and doped with p-type elements. The first surface includes a metal electrode region and a non-metal electrode region. In the emitter layer, the portion corresponding to the non-metal electrode region is doped with carbon elements.

[0008] In some embodiments, the tunneling passivation structure includes a tunneling layer and a doped conductive layer stacked on the second surface in a direction away from the substrate;

[0009] The photovoltaic cell further includes a second passivation layer and a second antireflection layer stacked on the doped conductive layer along a direction away from the substrate;

[0010] The photovoltaic cell further includes a first passivation layer and a first antireflection layer stacked on the emitter layer in a direction away from the substrate.

[0011] A photovoltaic module, the photovoltaic module comprising the photovoltaic cells described above.

[0012] A method for manufacturing a photovoltaic cell, the method comprising:

[0013] A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other;

[0014] A p-type doped emitter material layer is formed on the first surface;

[0015] A carbon source layer structure is deposited on the side of the emitter material layer opposite to the substrate, and carbon elements in the carbon source layer structure are diffused to at least a portion of the emitter material layer along the first surface to form an emitter layer.

[0016] In some embodiments, depositing a carbon source layer structure on the side of the emitter material layer opposite to the substrate and diffusing carbon elements in the carbon source layer structure to at least a portion of the emitter material layer along the first surface to form an emitter layer includes:

[0017] A mask layer is deposited on the side of the emitter material layer opposite to the substrate;

[0018] A first carbon source layer is deposited on the side of the mask layer opposite to the emitter material layer;

[0019] Carbon elements in the first carbon source layer are diffused through the mask layer to at least a portion of the emitter material layer along the first surface to form an emitter layer.

[0020] In some embodiments, the first carbon source layer includes an intrinsic semiconductor layer containing carbon, and the mask layer includes a silicon oxide layer.

[0021] In some embodiments, after depositing a first carbon source layer on the side of the mask layer opposite to the emitter material layer, the method further includes:

[0022] The first carbon source layer is patterned to remove the portion of the first carbon source layer corresponding to the metal electrode region.

[0023] Carbon elements in the first carbon source layer diffuse to the portion of the emitter material layer corresponding to the non-metallic electrode region to form an emitter layer.

[0024] In some embodiments, depositing a carbon source layer structure on the side of the emitter material layer opposite to the substrate and diffusing carbon elements in the carbon source layer structure to at least a portion of the emitter material layer along the first surface to form an emitter layer includes:

[0025] A second carbon source layer is deposited on the side of the emitter material layer opposite to the substrate;

[0026] Carbon elements in the second carbon source layer diffuse into at least a portion of the emitter material layer along the first surface to form an emitter layer.

[0027] In some embodiments, the second carbon source layer comprises a carbon-doped silicon oxide layer.

[0028] In some embodiments, after depositing a second carbon source layer on the side of the emitter material layer opposite to the substrate, the method further includes:

[0029] The second carbon source layer is patterned so that it only covers the portion of the emitter material layer corresponding to the non-metallic electrode region.

[0030] Carbon elements in the second carbon source layer diffuse into the portion of the emitter material layer corresponding to the non-metallic electrode region to form an emitter layer.

[0031] The aforementioned manufacturing methods for photovoltaic cells, photovoltaic modules, and photovoltaic cells introduce carbon elements into the emitter layer of the first surface (front surface) of the photovoltaic cell. By utilizing the high concentration of vacancies generated during the diffusion of carbon atoms with p-type elements (e.g., forming CB pairs), dangling bonds are effectively saturated and carrier recombination centers are suppressed, thereby significantly reducing the front surface recombination current density (J0). This structural improvement directly enhances the passivation quality of the emitter layer, resulting in a lower open-circuit voltage (V). OC This improved efficiency and ultimately broke through the efficiency bottleneck caused by the inherent defects of p-type element (such as boron) diffusion on the front surface of traditional TOPCon cells, providing a reliable way to prepare higher-efficiency solar cells. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a photovoltaic cell in one embodiment of this application.

[0033] Figure 2 This is a schematic diagram of a photovoltaic cell in another embodiment of this application.

[0034] Figure 3 for Figure 1 This is a schematic diagram of the substrate after polishing in one embodiment of the photovoltaic cell manufacturing process.

[0035] Figure 4 for Figure 1 The diagram shows a sample of the substrate after texturing, one embodiment of the photovoltaic cell manufacturing process.

[0036] Figure 5 for Figure 1 This is a schematic diagram of the photovoltaic cell manufacturing process after the deposition of the emitter material layer, as shown in one embodiment.

[0037] Figure 6 for Figure 1 This is a schematic diagram of a photovoltaic cell manufacturing process after the front borosilicate glass layer has been removed.

[0038] Figure 7 for Figure 1 This is a schematic diagram of the photovoltaic cell manufacturing process after the deposition of the mask layer, as shown in one embodiment.

[0039] Figure 8 for Figure 1 This is a schematic diagram of the photovoltaic cell manufacturing process after the deposition of the first carbon source layer, as shown in one embodiment.

[0040] Figure 9 for Figure 1 This diagram illustrates a photovoltaic cell manufacturing process where carbon elements in the first carbon source layer diffuse to the emitter material layer.

[0041] Figure 10 for Figure 1 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after the front oxide layer and the back borosilicate glass layer have been removed.

[0042] Figure 11 for Figure 1 This is a schematic diagram of one embodiment of the photovoltaic cell manufacturing process, after the first carbon source layer and the back emitter layer have been removed.

[0043] Figure 12 for Figure 1 This is a schematic diagram after removing the mask in one embodiment of the photovoltaic cell manufacturing process.

[0044] Figure 13 for Figure 1 This is a schematic diagram of one embodiment of the photovoltaic cell fabrication process, showing the deposition of a tunneling layer and a layer of doped conductive material.

[0045] Figure 14 for Figure 1 The diagram illustrates a photovoltaic cell manufacturing process where the doped conductive material layer is transformed into a doped conductive layer.

[0046] Figure 15 for Figure 1 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after the front phosphosilicate glass layer has been removed.

[0047] Figure 16 for Figure 1 This is a schematic diagram of a photovoltaic cell manufacturing process after the front doped conductive layer has been removed.

[0048] Figure 17 for Figure 1 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after removing the front tunneling layer and the back phosphosilicate glass layer.

[0049] Figure 18 for Figure 1 This is a schematic diagram of one embodiment of the photovoltaic cell manufacturing process, showing the front and back passivation layers and the antireflection layer after deposition.

[0050] Figure 19 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process, showing the deposition of the second carbon source layer.

[0051] Figure 20 for Figure 1 The diagram shows a photovoltaic cell manufacturing process in another embodiment, after the carbon element in the second carbon source layer diffuses to the emitter material layer.

[0052] Figure 21 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process shown, after the back borosilicate glass layer has been removed.

[0053] Figure 22 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process, after the back emitter layer has been removed.

[0054] Figure 23 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process, showing the deposition of a tunneling layer and a layer of doped conductive material.

[0055] Figure 24 for Figure 1 The diagram shows a different embodiment of the photovoltaic cell manufacturing process, illustrating the transformation of the doped conductive material layer into a doped conductive layer.

[0056] Figure 25 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process shown, after the front phosphosilicate glass layer has been removed.

[0057] Figure 26 for Figure 1 This is a schematic diagram of another embodiment of the photovoltaic cell manufacturing process, showing the process after removing the front-side doped conductive layer.

[0058] Figure 27 for Figure 1 The schematic diagram shown is an example of a photovoltaic cell manufacturing process after removing the front tunneling layer, the second carbon source layer, and the back phosphosilicate glass layer.

[0059] Figure 28 for Figure 2 This is a schematic diagram of the patterned second carbon source layer in one embodiment of the photovoltaic cell manufacturing process.

[0060] Figure 29 for Figure 2 This diagram illustrates a photovoltaic cell manufacturing process where carbon elements from the second carbon source layer diffuse to the emitter material layer.

[0061] Figure 30 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after a protective layer has been deposited on the second carbon source layer.

[0062] Figure 31 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after the back borosilicate glass layer has been removed.

[0063] Figure 32 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process after the back emitter layer has been removed.

[0064] Figure 33 for Figure 2 This is a schematic diagram of one embodiment of the photovoltaic cell fabrication process, showing the deposition of a tunneling layer and a layer of doped conductive material.

[0065] Figure 34 for Figure 2 The diagram illustrates a photovoltaic cell manufacturing process where the doped conductive material layer is transformed into a doped conductive layer.

[0066] Figure 35 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after the front phosphosilicate glass layer has been removed.

[0067] Figure 36 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process after the front doped conductive layer has been removed.

[0068] Figure 37 for Figure 2 This is a schematic diagram of a photovoltaic cell manufacturing process shown in one embodiment, after removing the front tunneling layer, protective layer, and second carbon source layer, as well as the back phosphosilicate glass layer.

[0069] Figure 38 for Figure 2 This is a schematic diagram of one embodiment of the photovoltaic cell manufacturing process, showing the front and back passivation layers and the antireflection layer after deposition.

[0070] Figure 39 This is a flowchart of a method for manufacturing a photovoltaic cell according to one embodiment of this application.

[0071] Figure label:

[0072] 100, Substrate; 110, First surface; 111, Metal electrode region; 112, Non-metal electrode region; 120, Second surface; 200, Emitter layer; 200a, Emitter material layer; 300, Tunneling passivation structure; 310, Tunneling layer; 320, Doped conductive layer; 320a, Doped conductive material layer; 411, First passivation layer; 412, First antireflection layer; 421, Second passivation layer; 422, Second antireflection layer; 510. Mask layer; 521, First carbon source layer; 522, Second carbon source layer; 5221, Notch; 610, Back emitter layer; 620, Borosilicate glass layer; 630, Front tunneling layer; 640, Front doped conductive layer; 640a, Front doped conductive material layer; 650, Phosphosilicate glass layer; 660, Oxide layer; 670, Protective layer; 681, First inner expansion layer; 682, Second inner expansion layer; 710, First electrode; 720, Second electrode. Detailed Implementation

[0073] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0074] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0075] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0076] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0077] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0078] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0079] See Figure 1 and Figure 2 An embodiment of this application provides a photovoltaic cell comprising a substrate 100, an emitter layer 200, and a tunneling passivation structure 300. The substrate 100 has a first surface 110 and a second surface 120 disposed opposite to each other; the tunneling passivation structure 300 is disposed on the second surface 120; the emitter layer 200 is disposed on the first surface 110 and is doped with a p-type element (e.g., boron, gallium, with boron being the primary example discussed later); at least a portion of the emitter layer 200 along the first surface 110 is doped with carbon.

[0080] The first surface 110 is the front surface, also known as the light-facing surface, and the second surface 120 is the back surface, also known as the backlight surface. The substrate 100 is an n-type silicon wafer.

[0081] The photovoltaic cell in the above embodiment introduces carbon elements into the emitter layer 200 of the first surface 110 (front surface) of the photovoltaic cell. By utilizing the high concentration of vacancies generated during the diffusion of carbon atoms with p-type elements (e.g., forming CB pairs), dangling bonds are effectively saturated and carrier recombination centers are suppressed, thereby significantly reducing the front surface recombination current density (J0). This structural improvement directly enhances the passivation quality of the emitter layer 200, resulting in a lower open-circuit voltage (V). OC This improved efficiency and ultimately broke through the efficiency bottleneck caused by the inherent defects of p-type element (such as boron and gallium) diffusion on the front surface of traditional TOPCon cells, providing a reliable way to prepare higher-efficiency solar cells.

[0082] See Figure 2 In some embodiments, the first surface 110 includes a metal electrode region 111 and a non-metal electrode region 112, and the portion of the emitter layer 200 corresponding to the non-metal electrode region 112 is doped with carbon.

[0083] Specifically, the photovoltaic cell includes a first electrode 710 located on the front side and a second electrode 720 located on the back side, with opposite polarities. The metal electrode region 111 is the projection area of ​​the first electrode 710 onto the first surface 110 along the cell stacking direction, and the non-metallic electrode region 112 is the area on the first surface 110 other than the metal electrode region 111.

[0084] In the above embodiment, by precisely defining the carbon doping region in the emitter layer 200 corresponding to the non-metallic electrode region 112, the carbon passivation effect is effectively utilized to suppress B vacancies in this region and reduce surface recombination, while ensuring that the position in the emitter layer 200 corresponding to the metal electrode region 111 still maintains the original high concentration boron doping characteristics. This partitioned structure design enables the metal electrode region 111 to maintain excellent ohmic contact and low contact resistance, while the non-metallic electrode region 112 obtains a significantly enhanced passivation effect. Thus, high open-circuit voltage and low series resistance are achieved simultaneously as a whole, solving the core contradiction in traditional processes where surface passivation and metal contact are difficult to achieve simultaneously.

[0085] Or, in Figure 1 In the embodiment shown, the entire surface of the emitter layer 200 is doped with carbon, that is, the portions of the emitter layer 200 corresponding to the metal electrode region 111 and the non-metal electrode region 112 are all doped with carbon.

[0086] See Figure 1 and Figure 2In some embodiments, the tunneling passivation structure 300 includes a tunneling layer 310 and a doped conductive layer 320 stacked on the second surface 120 along a direction away from the substrate 100. The photovoltaic cell also includes a second passivation layer 421 and a second antireflection layer 422 stacked on the doped conductive layer 320 along a direction away from the substrate 100. The photovoltaic cell also includes a first passivation layer 411 and a first antireflection layer 412 stacked on the emitter layer 200 along a direction away from the substrate 100.

[0087] Specifically, the tunneling layer 310 is an ultrathin silicon oxide layer, and the doped conductive layer 320 is an n-type doped polysilicon layer. The first passivation layer 411 and the second passivation layer 421 are aluminum oxide thin films. The first antireflection layer 412 and the second antireflection layer 422 are silicon nitride thin films. In addition, inside the substrate 100, there is a first inner expansion layer 681 extending inward from the first surface 110, and a second inner expansion layer 682 extending inward from the second surface 120. The first inner expansion layer 681 is a film layer formed by diffusion inside the substrate 100 during the formation of the emitter layer 200, and the second inner expansion layer 682 is a film layer formed inside the substrate 100 during the formation of the tunneling passivation structure 300.

[0088] See Figure 1 and Figure 2 The photovoltaic module provided in one embodiment of this application includes the photovoltaic cell in any of the foregoing embodiments.

[0089] See Figure 1 and Figure 2 ,as well as Figure 39 One embodiment of this application provides a method for manufacturing a photovoltaic cell, including:

[0090] S100, a substrate 100 is provided, the substrate 100 including a first surface 110 and a second surface 120 disposed opposite to each other;

[0091] S200, a p-type doped emitter material layer 200a is formed on the first surface 110;

[0092] S300, A carbon source layer structure is deposited on the side of the emitter material layer 200a away from the substrate 100;

[0093] S400, the carbon element in the carbon source layer structure is diffused to at least a portion of the emitter material layer 200a along the first surface 110 to form the emitter layer 200.

[0094] The photovoltaic cell manufacturing method in the above embodiments involves depositing a carbon source layer structure on the side of the emitter material layer 200a away from the substrate 100 after forming the emitter material layer 200a, and then introducing carbon elements into the emitter layer 200 using a subsequent diffusion process, thereby achieving carbon doping modification of the traditional boron emitter. This process route cleverly utilizes the solid-state diffusion principle to ensure that p-type elements can effectively penetrate into the emitter layer 200 and combine with vacancies (e.g., forming CB pairs), thereby significantly reducing the carrier recombination center density, enhancing the passivation effect of the front surface, and ultimately providing a reliable manufacturing solution that can be integrated into existing production lines to improve the open-circuit voltage and conversion efficiency of the cell.

[0095] Furthermore, the manufacturing method of photovoltaic cells also includes: S500, depositing a tunneling passivation structure 300 on the second surface 120.

[0096] It should be noted that step S500 can be performed after steps S200 to S400 or before steps S200 to S400. That is, the front structure can be deposited first or the back structure can be deposited first, and the order is not limited.

[0097] See Figures 3 to 4 In some embodiments, step S100 includes:

[0098] S110, Provides a mechanically polished n-type silicon wafer as substrate 100;

[0099] S120, perform secondary polishing on substrate 100 ( Figure 3 );

[0100] S130, Texturing the base 100 ( Figure 4 );

[0101] S140, Perform RCA cleaning on substrate 100.

[0102] The polishing, texturing, and RCA cleaning steps mentioned above are existing technologies, and their specific processes will not be described in detail here.

[0103] See Figures 5 to 6 In some embodiments, step S200 includes:

[0104] S210, Boron diffusion junction (emitter material layer 200a) is grown on the first surface 110 using a boron diffusion furnace. Figure 5 );

[0105] During this step, a back-side emitter layer 610 is also formed around the second surface 120. Additionally, a borosilicate glass layer 620 is formed on the side of the emitter material layer 200a and the back-side emitter layer 610 facing away from the substrate 100. In other embodiments, other elements, such as gallium, can be selected as the p-type element.

[0106] S220, Remove the front borosilicate glass layer 620 to expose the emitter material layer 200a. Figure 6 );

[0107] For example, chain-linked hydrofluoric acid can be used to remove the front borosilicate glass layer 620.

[0108] See Figures 7 to 8 In some embodiments, step S300 includes:

[0109] S310a, A mask layer 510 is deposited on the side of the emitter material layer 200a facing away from the substrate 100. Figure 7 );

[0110] S320a, A first carbon source layer 521 is deposited on the side of the mask layer 510 opposite to the emitter material layer 200a. Figure 8 );

[0111] Specifically, in some embodiments, the mask layer 510 includes a silicon oxide layer, and the first carbon source layer 521 includes an intrinsic semiconductor layer containing carbon elements.

[0112] Furthermore, a silicon oxide layer with a thickness of 2 to 5 nanometers is deposited on the side of the emitter material layer 200a facing away from the substrate 100 using PECVD as a mask layer 510.

[0113] An intrinsic semiconductor layer (specifically an intrinsic polysilicon layer) containing carbon is deposited on the side of the mask layer 510 opposite to the emitter material layer 200a using PECVD, serving as the first carbon source layer 521. Specifically, methane gas is introduced during the deposition of the intrinsic polysilicon layer to provide carbon.

[0114] In the above embodiments, the mask layer 510 is provided between the emitter material layer 200a and the first carbon source layer 521 (an intrinsic semiconductor layer containing carbon elements) to protect the formed emitter layer 200 from being etched and damaged when the first carbon source layer 521 (an intrinsic semiconductor layer containing carbon elements) is removed after the carbon elements diffuse to the emitter material layer 200a.

[0115] See Figures 8 to 9 In some embodiments, step S400 includes:

[0116] S410a, the carbon element in the first carbon source layer 521 is diffused through the mask layer 510 to at least a portion of the emitter material layer 200a along the first surface 110 to form the emitter layer 200.

[0117] Specifically, under high temperature conditions, carbon elements in the first carbon source layer 521 are diffused through the mask layer 510 to at least a portion of the emitter material layer 200a along the first surface 110 to form the emitter layer 200 (a carbon-doped boron emitter). For example, the temperature can be set to 945°C.

[0118] exist Figures 8 to 9 In the illustrated embodiment, carbon elements in the first carbon source layer 521 diffuse through the mask layer 510 to the entire area of ​​the emitter material layer 200a along the first surface 110. In other embodiments, the first carbon source layer 521 can also be patterned to remove the portion corresponding to the metal electrode region 111. Thus, during high-temperature diffusion, only the portion of the emitter material layer 200a corresponding to the non-metallic electrode region 112 will be doped with carbon elements. That is, in the formed emitter layer 200, only the portion corresponding to the non-metallic electrode region 112 is doped with carbon elements.

[0119] See Figures 9 to 10 In some embodiments, step S400 further includes:

[0120] S420a, the oxide layer 660 formed during the removal of S410a, and the borosilicate glass layer 620 previously formed by back-side plating.

[0121] Specifically, hydrofluoric acid cleaning is used to remove the oxide layer 660 and the borosilicate glass layer 620 on the back side.

[0122] See Figures 10 to 12 In some embodiments, step S400 further includes:

[0123] S430a, Remove the previously back-side emitter layer 610 formed by back-side plating, and the first carbon source layer 521 ( Figure 11 );

[0124] S440a, Remove mask layer 510 ( Figure 12 ).

[0125] Specifically, in step S430a, the first carbon source layer 521 and the back-side emitter layer 610 are etched away using a mixture of alkaline solution (e.g., TMAH, KOH, NaOH, etc.) and additives, wherein the volume ratio of the additives is 0.5-1.5%. As mentioned earlier, the mask layer 510 can protect the inner emitter layer 200 in this step (S430a) from etching damage. In step S440a, the mask layer 510 (silicon oxide) is removed by hydrofluoric acid cleaning. After etching, RCA cleaning is performed to remove residual reagents.

[0126] See Figure 6 and Figure 19 In other embodiments, step S300 includes:

[0127] S310b, Deposit a second carbon source layer 522 on the side of the emitter material layer 200a away from the substrate 100.

[0128] Specifically, in some embodiments, the second carbon source layer 522 includes a carbon-doped silicon oxide layer.

[0129] Furthermore, a silicon oxide layer with a thickness of 40 to 60 nanometers and doped with carbon is deposited on the side of the emitter material layer 200a facing away from the substrate 100 using PECVD, serving as a second carbon source layer 522. Specifically, methane gas is introduced during the deposition of the silicon oxide layer to provide carbon.

[0130] In the above embodiments, the silicon oxide layer doped with carbon is directly used as the second carbon source layer 522 (carbon source layer structure). When the second carbon source layer 522 is removed in the future, since acid solutions such as hydrofluoric acid are usually used for cleaning, the inner emitter layer 200 will not be damaged. Therefore, there is no need to set a mask between the second carbon source layer 522 and the emitter material layer 200a, which can simplify the process steps and improve production efficiency.

[0131] See Figures 19 to 20 In some embodiments, step S400 includes:

[0132] S410b, the carbon element in the second carbon source layer 522 is diffused to at least a portion of the emitter material layer 200a along the first surface 110 to form the emitter layer 200.

[0133] Specifically, under high temperature conditions, carbon elements in the second carbon source layer 522 diffuse into at least a portion of the emitter material layer 200a along the first surface 110 to form the emitter layer 200 (a carbon-doped boron emitter). For example, the temperature can be set to 945°C.

[0134] exist Figures 19 to 20 In the illustrated embodiment, step S410b includes:

[0135] S411b: The carbon element in the second carbon source layer 522 is diffused to the entire region along the first surface 110 of the emitter material layer 200a to form the emitter layer 200. In other embodiments (corresponding to the subsequent step S412b), the carbon element may be doped to a portion of the emitter material layer 200a along the first surface 110, which will be described in detail later.

[0136] Preferably, after step S411b, the second carbon source layer 522 (carbon-doped silicon oxide) can be temporarily left unremoved. After the tunneling passivation structure 300 is deposited, the second carbon source layer 522 (carbon-doped silicon oxide) and the part of the wrap-around structure formed during the formation of the tunneling passivation structure 300 (e.g., the front tunneling layer 630 formed during the deposition of the tunneling layer 310) can be removed together. This simplifies the process and improves production efficiency.

[0137] See Figures 20 to 22 In some embodiments, step S400 further includes:

[0138] S420b, Remove the borosilicate glass layer 620 previously formed on the back side ( ) Figure 21 );

[0139] S430b, Remove the previously formed back-side emitter layer 610 ( ) Figure 22 ).

[0140] Specifically, in step S420b, hydrofluoric acid is used for cleaning to remove the borosilicate glass layer 620 previously formed by back-side plating. In step S430b, the back-side emitter layer 610 is etched away using a mixture of alkaline solution (e.g., TMAH, KOH, NaOH, etc.) and additives, and the second surface 120 is polished. After polishing, the size of the tower base is 10 to 15 micrometers.

[0141] See Figure 19 and Figure 28 In some other embodiments, step S300 further includes actions performed after step S310b:

[0142] S320b: The second carbon source layer 522 is patterned so that the second carbon source layer 522 only covers the portion of the emitter material layer 200a corresponding to the non-metallic electrode region 112.

[0143] Specifically, a laser-assisted delamination technique is used to form a notch 5221 in the portion of the second carbon source layer 522 corresponding to the metal electrode region 111, effectively removing the portion of the second carbon source layer 522 corresponding to the metal electrode region 111. The width of the notch 5221 ranges from 30 micrometers to 120 micrometers. Thus, during the subsequent high-temperature diffusion process, only the portion of the emitter material layer 200a corresponding to the non-metallic electrode region 112 will be doped with carbon, meaning that only the portion of the formed emitter layer 200 corresponding to the non-metallic electrode region 112 will be doped with carbon.

[0144] See Figures 28 to 29 In some embodiments, step S410b includes actions performed after step S320b:

[0145] S412b, the carbon element in the second carbon source layer 522 diffuses into the portion of the emitter material layer 200a corresponding to the non-metallic electrode region 112 to form the emitter layer 200.

[0146] Specifically, under high temperature conditions, carbon elements in the second carbon source layer 522 diffuse into the portion of the emitter material layer 200a corresponding to the non-metallic electrode region 112 to form the emitter layer 200 (a carbon-doped boron emitter). For example, the temperature can be set to 945°C.

[0147] See Figures 29 to 30 In some embodiments, step S410b further includes actions performed after step S412b:

[0148] S413b, a protective layer 670 is deposited on the side of the second carbon source layer 522 away from the substrate 100, the protective layer 670 covering the area of ​​the second carbon source layer 522 and the emitter layer 200 exposed through the notch 5221.

[0149] Specifically, the protective layer 670 is a silicon oxide layer, which is deposited by PECVD with a thickness of 50 nanometers to 100 nanometers. By setting the protective layer 670, the area of ​​the emitter layer 200 exposed at the notch 5221 can be protected to prevent damage to the area of ​​the emitter layer 200 exposed at the notch 5221 during subsequent etching.

[0150] Preferably, after step S413b, the protective layer 670 (silicon oxide layer) is not removed temporarily. After the tunneling passivation structure 300 is deposited, the protective layer 670, the second carbon source layer 522 (carbon-doped silicon oxide) inside it, and the front tunneling layer 630 are removed together to simplify the process flow.

[0151] After that, Figures 31 to 32 The corresponding steps are the same as those in the aforementioned embodiments. Figures 21 to 22 The corresponding steps are the same, so they will not be repeated here.

[0152] See Figures 12 to 14 In some embodiments, step S500 includes:

[0153] S510, depositing a tunneling layer 310 and a doped conductive material layer 320a on the second surface 120. Figure 13 );

[0154] S520, transforming the doped conductive material layer 320a into a doped conductive layer 320 ( Figure 14 ).

[0155] Specifically, in step S510, an ultrathin silicon oxide is deposited on the second surface 120 by LPCVD to serve as a tunneling layer 310; intrinsic polycrystalline silicon is deposited on the tunneling layer 310 by LPCVD to serve as a doped conductive material layer 320a. In step S520, the doped conductive material layer 320a is transformed into n-type doped polycrystalline silicon by high-temperature phosphorus diffusion to serve as the doped conductive layer 320, with a thickness of approximately 120 nm to 140 nm.

[0156] See Figures 14 to 17 In some embodiments, step S500 further includes:

[0157] S530, Remove the phosphorosilicate glass layer 650 formed in step S520 by the front side winding plating. Figure 15 );

[0158] S540, Remove the front-side doped conductive layer 640 formed by front-side plating (in step S510, a front-side doped conductive material layer 640a is formed by front-side plating; in step S520, the front-side doped conductive material layer 640a is transformed into the front-side doped conductive layer 640) Figure 16 );

[0159] S550, removing the front tunneling layer 630 formed by the front side winding plating, and the back phosphorus glass layer 650 ( Figure 17 ).

[0160] Specifically, in step S530, a chain-type hydrofluoric acid cleaning process is used to remove the front-side phosphosilicate glass layer 650 formed by the surrounding plating. In step S540, the front-side doped conductive layer 640 is etched away using a mixture of alkaline solution (TMAH, KOH, NaOH, etc.) and additives, wherein the volume ratio of the additives is 0.5-1.5%. In step S550, hydrofluoric acid cleaning is used to remove the front-side tunneling layer 630 and the back-side phosphosilicate glass layer 650. Afterwards, RCA cleaning is performed to remove residual chemicals.

[0161] Figures 23 to 27 The corresponding steps are the same as those in the aforementioned embodiments. Figures 13 to 17 The corresponding steps are basically the same. Figures 33 to 37The corresponding steps are the same as those in the aforementioned embodiments. Figures 13 to 17 The corresponding steps are basically the same. The only difference is that... Figure 17 In the corresponding step S550, the front tunneling layer 630 formed by front-side winding plating and the back phosphorus glass layer 650 are removed. Figure 27 In the corresponding step S550, the front tunneling layer 630, the second carbon source layer 522, and the back phosphorus glass layer 650 are removed. Figure 37 In the corresponding step S550, the front tunneling layer 630, the protective layer 670, the second carbon source layer 522, and the back phosphorus silicate glass layer 650 are removed. After step S550 is completed, residual chemicals are removed by RCA cleaning.

[0162] See Figure 18 and Figure 1 In some embodiments, step S500 is followed by:

[0163] S600, deposited to form a passivation layer and an antireflection layer on the front and back sides;

[0164] S700, fabrication of metal electrodes.

[0165] Specifically, in step S600, a first passivation layer 411 is deposited on the front side, and a second passivation layer 421 is deposited on the back side. Further, an aluminum oxide film with a thickness of 10 nanometers is deposited using ALD as the first passivation layer 411 / second passivation layer 421, with a deposition temperature of 290°C. Then, a first antireflection layer 412 is deposited on the front side, and a second antireflection layer 422 is deposited on the back side. Further, silicon nitride with a thickness of 70 nanometers is deposited using PECVD as the first antireflection layer 412, and silicon nitride with a thickness of 80 nanometers is deposited as the second antireflection layer 422, with a deposition temperature of 580°C.

[0166] In step S700, a first electrode 710 is formed on the front side and a second electrode 720 is formed on the back side. Further, a paste is first screen-printed, then placed in a chain sintering furnace for sintering, and finally laser-assisted sintering (LECO) is used to achieve better metal contact.

[0167] Figure 27 The steps that follow are the same as those in the previous embodiment (S600 and S700). Figure 37 The steps that follow are the same as those in the previous embodiment (S600 and S700).

[0168] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0169] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A photovoltaic cell, characterized in that, The photovoltaic cell includes: The substrate has a first surface and a second surface that are arranged opposite to each other. A tunneling passivation structure is disposed on the second surface; and An emitter layer is disposed on the first surface and doped with p-type elements. The first surface includes a metal electrode region and a non-metal electrode region. In the emitter layer, the portion corresponding to the non-metal electrode region is doped with carbon elements.

2. The photovoltaic cell according to claim 1, characterized in that, The tunneling passivation structure includes a tunneling layer and a doped conductive layer stacked on the second surface in a direction away from the substrate; The photovoltaic cell further includes a second passivation layer and a second antireflection layer stacked on the doped conductive layer along a direction away from the substrate; The photovoltaic cell further includes a first passivation layer and a first antireflection layer stacked on the emitter layer in a direction away from the substrate.

3. A photovoltaic module, characterized in that, The photovoltaic module includes the photovoltaic cell according to any one of claims 1 to 2.

4. A method for manufacturing a photovoltaic cell, characterized in that, The method for manufacturing the photovoltaic cell includes: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A p-type doped emitter material layer is formed on the first surface; A carbon source layer structure is deposited on the side of the emitter material layer opposite to the substrate, and carbon elements in the carbon source layer structure are diffused to at least a portion of the emitter material layer along the first surface to form an emitter layer.

5. The method for manufacturing a photovoltaic cell according to claim 4, characterized in that, The step of depositing a carbon source layer structure on the side of the emitter material layer opposite to the substrate, and diffusing carbon elements in the carbon source layer structure to at least a portion of the emitter material layer along the first surface to form an emitter layer includes: A mask layer is deposited on the side of the emitter material layer opposite to the substrate; A first carbon source layer is deposited on the side of the mask layer opposite to the emitter material layer; Carbon elements in the first carbon source layer are diffused through the mask layer to at least a portion of the emitter material layer along the first surface to form an emitter layer.

6. The method for manufacturing a photovoltaic cell according to claim 5, characterized in that, The first carbon source layer includes an intrinsic semiconductor layer containing carbon elements, and the mask layer includes a silicon oxide layer.

7. The method for manufacturing a photovoltaic cell according to claim 5, characterized in that, After depositing a first carbon source layer on the side of the mask layer opposite to the emitter material layer, the process further includes: The first carbon source layer is patterned to remove the portion of the first carbon source layer corresponding to the metal electrode region. Carbon elements in the first carbon source layer diffuse to the portion of the emitter material layer corresponding to the non-metallic electrode region to form an emitter layer.

8. The method for manufacturing a photovoltaic cell according to claim 4, characterized in that, The step of depositing a carbon source layer structure on the side of the emitter material layer opposite to the substrate, and diffusing carbon elements in the carbon source layer structure to at least a portion of the emitter material layer along the first surface to form an emitter layer includes: A second carbon source layer is deposited on the side of the emitter material layer opposite to the substrate; Carbon elements in the second carbon source layer diffuse into at least a portion of the emitter material layer along the first surface to form an emitter layer.

9. The method for manufacturing a photovoltaic cell according to claim 8, characterized in that, The second carbon source layer includes a carbon-doped silicon oxide layer.

10. The method for manufacturing a photovoltaic cell according to claim 8, characterized in that, After depositing a second carbon source layer on the side of the emitter material layer opposite to the substrate, the method further includes: The second carbon source layer is patterned so that it only covers the portion of the emitter material layer corresponding to the non-metallic electrode region. Carbon elements in the second carbon source layer diffuse into the portion of the emitter material layer corresponding to the non-metallic electrode region to form an emitter layer.

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