Solar cell and preparation method thereof, photovoltaic module

Abstract

This application provides a solar cell and its fabrication method, as well as a photovoltaic module. A contact layer is disposed on one side of a supporting substrate, and a doped region is disposed on the side of the contact layer opposite to the supporting substrate. The doped region includes intersecting current-collecting regions and multiple active regions disposed on both sides thereof. An electrode layer is disposed on the surface of the contact layer, comprising a fine grid structure in the active region, a current-collecting structure in the current-collecting region, and a connecting structure. The fine grid connects to the current-collecting structure, and the connecting structure consists of at least two connecting grid lines, with each end of the connecting grid line connected to an adjacent current-collecting structure. The dual connecting grid lines can disperse carrier transport pressure, reduce series resistance and recombination loss, and improve carrier transport efficiency. Simultaneously, they can form multi-point contact welding with the solder strip, expanding the contact area, enhancing welding bonding force, reducing the risk of desoldering and poor soldering during long-term use, and improving the solder strip alignment tolerance, significantly improving the welding yield, batch consistency, and long-term operational stability of the solar cell mass production.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a solar cell and its preparation method, and a photovoltaic module. Background Technology

[0002] With the rapid development of the photovoltaic industry, tunneling oxide passivated contact (TBC) cells have become the mainstream technology route for next-generation crystalline silicon cells due to their core advantages of high conversion efficiency and low degradation. Zero busbar (OBB) technology can effectively reduce cell shading loss and silver paste consumption, and is highly compatible with TBC cells, making it the mainstream solution for mass production in the industry.

[0003] In solar cells of related technologies, adjacent welding joints are connected by a single thickened single wire, which makes it difficult to balance conductivity and shading loss. It also has problems such as small welding contact area, weak bonding force, and poor tolerance for welding strip misalignment. Mass production welding yield is low, and long-term outdoor use is prone to desoldering and incomplete welding, which seriously affects the operational stability and power generation performance of cells and modules. Summary of the Invention

[0004] The purpose of this application is to provide a solar cell and its preparation method, as well as a photovoltaic module, to solve the technical problems of technical defects in solar cells in related technologies.

[0005] In a first aspect, this application provides a solar cell, comprising: Supporting substrate; A contact layer is disposed on one side of the supporting substrate. The side of the contact layer opposite to the supporting substrate includes multiple doped regions. Each doped region includes a current-carrying region and multiple active regions. The multiple active regions are respectively disposed on both sides of the current-carrying region. The current-carrying region extends along a first direction, and the active regions extend along a second direction, where the first direction and the second direction intersect. An electrode layer is disposed on the side of the contact layer away from the supporting substrate. The electrode layer includes multiple fine gate structures, multiple bus structures, and multiple connection structures. The fine gate structures are disposed in the active region of the doped region, and the bus structures and connection structures are disposed in the bus region of the doped region. The fine gate structures connect to the bus structures, and the connection structures respectively connect two adjacent bus structures in the same bus region. The connection structure includes at least two connection gate lines extending along the first direction, and the two ends of the connection gate lines are respectively connected to the two bus structures.

[0006] In the solar cell approved in this application, a contact layer is disposed on one side of a supporting substrate. The side of the contact layer away from the supporting substrate includes multiple doped regions, each doped region including a current-carrying region and multiple active regions. The multiple active regions are respectively disposed on both sides of the current-carrying region. The current-carrying region extends along a first direction, and the active regions extend along a second direction, with the first and second directions intersecting. An electrode layer is disposed on the side of the contact layer away from the supporting substrate. The electrode layer includes multiple fine grid structures, multiple current-carrying structures, and multiple connection structures. The fine grid structures are disposed in the active regions of the doped regions, and the current-carrying structures and connection structures are disposed in the current-carrying regions of the doped regions. The fine grid structures connect to the current-carrying structures, and the connection structures respectively connect two adjacent current-carrying structures within the same current-carrying region. The connection structure includes at least two connection grid lines extending along the first direction, with each end of the connection grid line connected to one of the two current-carrying structures. The shunt design with dual connection grid lines can effectively disperse carrier transport pressure, significantly reduce the local series resistance of the current-carrying path, reduce recombination losses during carrier transport, and significantly improve carrier transport efficiency. The limiting adapter structure formed by the dual connecting grid lines can form stable multi-point contact welding with the solder ribbon, significantly increasing the effective welding contact area between the solder ribbon and the connecting grid lines, and significantly enhancing the welding bonding force. This fundamentally reduces the risk of desoldering and cold solder joints caused by thermal cycling and environmental aging during long-term outdoor use of solar cells, greatly improving the long-term operational stability of solar cells and modules. Simultaneously, this dual connecting grid line structure provides ample alignment tolerance for solder ribbon laying, effectively adapting to common alignment deviations caused by equipment and processes during industrial mass production. This significantly reduces welding failures caused by solder ribbon misalignment, and significantly improves the welding yield and batch consistency of mass-produced solar cells.

[0007] The solar cell further includes a plurality of solder strips arranged along the first direction, the solder strips being disposed on a plurality of the current-collecting structures in the current-collecting region; The connection structure includes two connection grid lines, with a receiving groove formed between the two connection grid lines, and the solder strip covers at least one of the connection grid lines and is at least partially disposed within the receiving groove.

[0008] The ratio of the linewidth of the connecting grid line to the width of the bus region is α, and α satisfies: 0.1≤α≤0.4; the width of the connecting grid line ranges from 60μm to 100μm.

[0009] The width of the solder strip ranges from 200μm to 400μm, and the spacing between two adjacent connecting grid lines within the same connection structure ranges from 120μm to 280μm.

[0010] The solar cell includes a central region and two end regions located at both ends of the central region. The end regions and the central region are arranged along a first direction. The connecting structure is located within the end regions. The dimension of the end regions along the first direction is L1, and the dimension of the solar cell along the first direction is L2. The ratio of L1 to L2 is β, and β satisfies: 0.03≤β≤0.15.

[0011] The doped region includes an N-type doped region, and the linewidth of the connecting gate line is negatively correlated with the doping concentration of the N-type doped region; when the doping concentration of the N-type doped region is 3 × 10⁻⁶, the linewidth of the connecting gate line is negatively correlated with the doping concentration of the N-type doped region. 19 cm -3 -6×10 19 cm -3 When the linewidth of the connecting gate line is in the range of 80μm-100μm; when the doping concentration of the N-type doped region is in the range of 6×10 19 cm -3 -9×10 19 cm -3 At that time, the linewidth of the connecting gate line ranges from 60μm to 80μm; Or, the doped region includes a P-type doped region, and the linewidth of the connecting gate line is negatively correlated with the doping concentration of the P-type doped region; when the doping concentration of the P-type doped region is 1×10 20 cm -3 -3×10 20 cm -3 When the linewidth of the connecting gate line is in the range of 80μm-100μm; when the doping concentration of the P-type doped region is in the range of 3×10 20 cm -3 -5×10 20 cm -3 At that time, the linewidth of the connecting gate line ranges from 60μm to 80μm.

[0012] Secondly, this application provides a method for preparing a solar cell, the method comprising: A support substrate is provided, and the contact layer is deposited on the support substrate; A doped region is formed on the contact layer, wherein the doped region includes a current-collecting region and a plurality of active regions, the plurality of active regions being respectively disposed on both sides of the current-collecting region, the current-collecting region extending along a first direction, and the active regions extending along a second direction, the first direction and the second direction intersecting; The electrode layer is printed on the contact layer, wherein the electrode layer includes a plurality of fine gate structures, a plurality of bus structures, and a plurality of connection structures. The fine gate structures are disposed in the active region of the doped region, and the bus structures and the connection structures are disposed in the bus region of the doped region. The fine gate structures connect the bus structures, and the connection structures respectively connect two adjacent bus structures in the same bus region. The connection structure includes at least two connection gate lines extending along the first direction, and the two ends of the connection gate lines are respectively connected to the two bus structures. The electrode layer is sintered; Solder strips are welded onto the electrode layer for encapsulation to form the solar cell.

[0013] The electrode layer is printed on the contact layer, including: Highly conductive silver paste is used for screen printing, wherein the silver content of the silver paste is ≥92.5%, the printing pressure range is 40N-50N, and the printing speed is 400mm / s-500mm / s; Sintering the electrode layer includes: The electrode layer is sintered according to preset parameters, wherein the preset parameters include heating rate, peak temperature, peak holding time and cooling rate, the heating rate ranges from 10℃ / s to 20℃ / s, the peak temperature ranges from 680℃ to 720℃, the peak holding time ranges from 3s to 8s, and the cooling rate ranges from 3℃ / s to 6℃ / s.

[0014] The process of welding solder strips onto the electrode layer includes: Welding strips are performed on the electrode layer by infrared cryogenic welding, wherein the welding temperature ranges from 160℃ to 200℃, the holding time ranges from 10s to 14s, and the welding strip tension ranges from 0.3N to 0.7N.

[0015] Thirdly, this application provides a photovoltaic module comprising at least one of the aforementioned solar cells. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 1 ; Figure 2This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 2 ; Figure 3 This is a connection diagram of a busbar structure and connection structure provided in an embodiment of this application; Figure 4 This is a partial cross-sectional structural diagram of a welding strip and connection structure provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 3 ; Figure 6 This is a schematic diagram of the cross-sectional structure of a solar cell provided in an embodiment of this application; Figure 7 This is a flowchart of a method for preparing a solar cell according to an embodiment of this application; Figure 8 This is a flowchart of step S310 in a method for preparing a solar cell provided in this application; Figure 9 This is a flowchart of step S410 in a method for preparing a solar cell provided in this application; Figure 10 This is a flowchart of step S510 in a method for preparing a solar cell provided in this application.

[0018] Label Explanation: Solar cell 100, middle region 101, end region 102, supporting substrate 10, contact layer 20, doped region 21, busbar region 211, doped polycrystalline silicon layer 22, tunneling oxide layer 23, electrode layer 30, busbar structure 31, connection structure 32, connecting grid line 321, solder ribbon 40, first direction D1, second direction D2. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0021] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0022] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" shall be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0023] With the rapid development of the photovoltaic industry, tunneling oxide passivated contact (TBC) cells have become the mainstream technology route for next-generation crystalline silicon cells due to their core advantages of high conversion efficiency and low degradation. Zero busbar (OBB) technology can effectively reduce cell shading loss and silver paste consumption, and is highly compatible with TBC cells, making it the mainstream solution for mass production in the industry.

[0024] In solar cells of related technologies, adjacent welding joints are connected by a single thickened single wire, which makes it difficult to balance conductivity and shading loss. It also has problems such as small welding contact area, weak bonding force, and poor tolerance for welding strip misalignment. Mass production welding yield is low, and long-term outdoor use is prone to desoldering and incomplete welding, which seriously affects the operational stability and power generation performance of cells and modules.

[0025] Please refer to Figures 1 to 6 , Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 1 , Figure 2 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 2 , Figure 3 This is a connection diagram of a busbar structure and connection structure provided in an embodiment of this application. Figure 4 This is a partial cross-sectional structural diagram of a welding strip and connection structure provided in an embodiment of this application. Figure 5 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application. Figure 3 , Figure 6 This is a schematic diagram of the cross-sectional structure of a solar cell provided in an embodiment of this application.

[0026] It should be noted that the bus structures, solder strips, and other structures shown in the accompanying drawings of this application are portions of a type of doped region. In other words, for example, the bus structures and solder strips in the drawings are portions of the structures corresponding to the P-type doped region. The structures of the N-type doped region are not shown and should not be construed as limiting this application.

[0027] This application provides a solar cell 100 to solve the technical problem of technical defects in solar cells in related technologies.

[0028] The solar cell 100 includes a supporting substrate 10, a contact layer 20, and an electrode layer 30. The contact layer 20 is disposed on one side of the supporting substrate 10. The side of the contact layer 20 away from the supporting substrate 10 includes multiple doped regions 21. Each doped region 21 includes a current-collecting region 211 and multiple active regions. The multiple active regions are respectively disposed on both sides of the current-collecting region 211. The current-collecting region 211 extends along a first direction D1, and the active regions extend along a second direction D2. The first direction D1 and the second direction D2 intersect. The electrode layer 30 is disposed on the side of the contact layer 20 away from the support substrate 10. The electrode layer 30 includes a plurality of fine gate structures, a plurality of bus structures 31 and a plurality of connection structures 32. The fine gate structures are disposed in the active region of the doped region 21, and the bus structures 31 and the connection structures 32 are disposed in the bus region 211 of the doped region 21. The fine gate structures connect the bus structures 31, and the connection structures 32 respectively connect two adjacent bus structures 31 within the same bus region 211. The connection structure 32 includes at least two connecting gate lines 321 extending along the first direction D1, and the two ends of the connecting gate lines 321 are respectively connected to the two bus structures 31.

[0029] It should be noted that in the embodiments of this application, the solar cell 100 is a back contact cell (BC cell). In other embodiments, the solar cell 100 may also be a tunnel oxide passivated contact cell (TOPCon), a heterojunction cell (HJT), etc., and this application does not limit it.

[0030] The solar cell 100 includes a support substrate 10, a contact layer 20, and an electrode layer 30. The support substrate 10 generates photogenerated carriers, the contact layer 20 separates and directionally transports carriers, and the electrode layer 30 completes the efficient collection and external export of carriers, thereby realizing the basic functions of the solar cell 100.

[0031] The supporting substrate 10 is the core support and carrier generation unit of the solar cell 100. Specifically, the supporting substrate 10 serves as the generation region for photogenerated carriers (electron-hole pairs), providing the foundation for the photoelectric conversion of the cell. At the same time, the supporting substrate 10 provides physical support for the contact layer 20 and the electrode layer 30 of the entire solar cell 100, and is the basic substrate of the solar cell 100.

[0032] The electrical properties of the silicon material in the supporting substrate 10 directly determine the generation efficiency, lifetime, and transport capacity of photogenerated carriers. Optionally, in this embodiment, the supporting substrate 10 is an n-type single-crystal silicon wafer, and the thickness of the supporting substrate 10 is 135 μm and the resistivity is 5 Ω. cm, carrier lifetime ≥2.05ms.

[0033] The contact layer 20 is the core functional layer of the solar cell 100. The contact layer 20 is disposed on the back side of the supporting substrate 10. In this embodiment, the contact layer 20 is prepared by low-pressure chemical vapor deposition (LPCVD).

[0034] The contact layer 20 includes a tunneling oxide layer 23 and a doped polysilicon layer 22. The tunneling oxide layer 23 is disposed between the doped polysilicon layer 22 and the carrier substrate 10. The tunneling oxide layer 23 and the doped polysilicon layer 22 form a passivation stack, which can effectively passivate the dangling bonds on the back of the silicon wafer, reduce the carrier recombination rate on the surface of the carrier substrate 10, and significantly improve the effective lifetime of the carriers.

[0035] The doped polycrystalline silicon layer 22 has a doped region 21 on the side opposite to the supporting substrate 10. Specifically, in this embodiment, the doped region 21 includes an N-type doped region and a P-type doped region. The P-type doped region and the N-type doped region are arranged in an interdigitated staggered pattern. This arrangement can maximize the contact area between the P-type doped region and the N-type doped region, improve the separation efficiency of charge carriers, and shorten the transport path of charge carriers.

[0036] The P-type doped region can capture and transport photogenerated holes, and directionally conduct the holes to the electrode layer 30; the N-type doped region can capture and transport photogenerated electrons, and directionally conduct the electrons to the electrode layer 30.

[0037] The doped region 21 includes a bus region 211 and an active region. That is, both the P-type doped region and the N-type doped region include the bus region 211 and the active region. This application only uses the bus region 211 and the active region of one of the doped regions 21 as an example for illustration, and should not be construed as a limitation of this application.

[0038] Understandably, the busbar region 211 is a main strip-shaped region that extends continuously along the first direction D1. The busbar region 211 can receive all photogenerated carriers collected by the active regions on both sides and transmit them laterally to the busbar structure 31 with low loss along the first direction D1, realizing the transition of carriers from dispersed collection to centralized aggregation. The busbar region 211 provides a stable, highly doped conductive substrate for the busbar structure 31 and the connection structure 32, significantly reducing the contact resistance between the metal electrode and the semiconductor. At the same time, it provides a continuous doped connection substrate for the active regions on both sides, ensuring the conductivity continuity of the entire doped region 21 and avoiding the problem of carrier transmission interruption.

[0039] Furthermore, the continuous strip-shaped busbar region 211, through a highly doped design, significantly reduces the series resistance of carrier lateral transport, minimizes carrier recombination losses during the busbar process, and significantly improves the battery's fill factor. The busbar region 211 serves as a dedicated area for soldering the solder ribbon 40 during encapsulation, physically isolating the soldering process from the active carrier collection region. This separation of the soldering functional area from the active collection region avoids damage to the passivation structure of the active region caused by high temperatures and pressures during the soldering process, reducing the risk of performance degradation during long-term battery use.

[0040] Understandably, the active region is a plurality of long branch regions extending from the main trunk of the confluence region 211 to both sides, extending along the second direction D2. The first direction D1 and the second direction D2 intersect each other. In this embodiment, the first direction D1 and the second direction D2 are orthogonal at 90°, that is, the active region and the confluence region 211 are perpendicular to each other.

[0041] The active region is multiple, and through the multi-branch full-coverage design, the photogenerated carriers generated by the entire light-absorbing surface of the solar cell 100 are collected nearby and efficiently, avoiding recombination losses caused by long-distance carrier transmission.

[0042] The active region collects the carriers and transmits them quickly to the main trunk's convergence region 211 via the shortest path, forming a complete carrier transmission link: active region collection - convergence region 211 aggregation - output from electrode layer 30.

[0043] The multiple active regions are respectively located on both sides of the current collection region 211. The design of the multiple active regions being symmetrically distributed on both sides of the current collection region 211 ensures the uniformity of carrier collection and current distribution inside the solar cell 100, avoids overheating and electromigration failure caused by excessively high local current density, and improves the stability of the battery during long-term use.

[0044] The electrode layer 30 includes a plurality of fine gate structures, which are micron-sized metal fine gate lines printed on the active region of the doped region 21. The extension direction is consistent with the second direction D2 of the active region, and the ends are directly electrically connected to the bus structure 31, serving as the first step for charge carriers to enter the metal electrode from the semiconductor. The fine gate structures, through metal-semiconductor ohmic contacts, extract photogenerated charge carriers from the active region nearby and directionally transmit all collected current to the bus structure 31.

[0045] The electrode layer 30 includes a plurality of bus structures 31, which are metallized pads printed on the bus region 211 of the doped region 21. The plurality of bus structures 31 are arranged at intervals along the first direction D1 of the bus region 211.

[0046] The busbar structure 31 receives all the charge carriers transmitted from the fine grid structure, collects and aggregates them, and then connects them through the solder ribbon 40. The busbar structure 31 provides a stable and highly adhesive welding platform for the solder ribbon 40, ensuring the continuity of current transmission throughout the electrode layer 30. In other words, the busbar structure 31 serves as a positioning reference for the solder ribbon 40, providing a core welding contact surface for the solder ribbon 40, and together with the connecting structure 32, forms a continuous welding interface, ensuring stable welding and adhesion between the solder ribbon 40 and the battery.

[0047] The electrode layer 30 includes a plurality of connection structures 32, each connection structure 32 connecting two adjacent busbar structures 31 within the same busbar region 211. Each connection structure 32 includes at least two connection gate lines 321 extending along the first direction D1, with each end of the connection gate line 321 connecting two busbar structures 31.

[0048] This application uses two connecting gate lines 321 as an example for illustration, and should not be construed as a limitation of this application. In this embodiment, the two connecting gate lines 321 are parallel. In other embodiments, the extending directions of the two connecting gate lines 321 may also be at an angle, and this application does not limit this.

[0049] The solar cell 100 further includes a plurality of solder ribbons 40 disposed along the first direction D1, the solder ribbons 40 being disposed on a plurality of the current-collecting structures 31 of the current-collecting region 211. A receiving groove is formed between two of the connecting grid lines 321, and the solder ribbons 40 cover at least one of the connecting grid lines 321 and are at least partially disposed within the receiving groove. The solder ribbons 40 conduct all the cell current collected by the current-collecting structures 31 and the connecting structures 32 to an external circuit with low loss, connecting adjacent cells in series to form a complete power generation circuit.

[0050] The welding strip 40 is disposed on multiple busbar structures 31 in the busbar region 211. This means that the welding strip 40 is continuously and fully laid along the first direction D1 in the entire busbar region 211 with the busbar structure 31 as the positioning anchor point. It does not only make single-point contact with discrete busbar structures 31, but simultaneously and continuously covers all busbar structures 31 and the connecting structures 32 between the busbar structures 31, forming welding contact with both at the same time.

[0051] The connecting gate line 321 is a highly conductive silver paste gate line extending along the first direction D1, protruding from the surface of the contact layer 20, and its two ends are electrically connected to the two adjacent bus structures 31 respectively. It also undertakes the dual core functions of carrier busing and welding of the solder strip 40.

[0052] The two connecting grid lines 321, which are at least partially spaced apart, together with the middle confluence region 211, form a strip-shaped groove space that extends continuously along the first direction D1. This groove is the receiving groove.

[0053] The diameter of the welding strip 40 is larger than the width of the receiving groove. After the welding strip 40 is placed, its bottom arc-shaped structure will naturally embed into the receiving groove, achieving a slot-type fit that is at least partially located in the receiving groove. At the same time, the bottom sides of the welding strip 40 will respectively overlap the upper surfaces of the two connecting grid lines 321, achieving full coverage of the two connecting grid lines 321 in the optimal state. Even if there is a mass production alignment deviation, at least one of the connecting grid lines 321 will be covered to ensure effective welding contact.

[0054] When the solder ribbon 40 is subjected to high-temperature welding, the tin plating layer on the surface of the solder ribbon 40 melts and simultaneously forms a stable ohmic contact with the two connecting grid lines 321 and the contact area in the receiving groove, realizing double-contact welding. Compared with the traditional single thickened single wire, the welding contact area is increased, which improves the welding bonding force from the source.

[0055] Understandably, the receiving groove provides a natural physical constraint on the solder strip 40. Once embedded, the solder strip 40 will not slide freely. Even if a normal alignment deviation of ±30μm occurs during mass production, the solder strip 40 can still be confined within the receiving groove and effectively welded to at least one of the connecting grid lines 321, thus avoiding the problems of desoldering and incomplete soldering that are prone to occur in traditional single-line structures.

[0056] Furthermore, the welding strip 40 and the two connecting grid lines 321 simultaneously form surface contact, increasing the welding contact area compared to the traditional single-line structure, and significantly improving the welding bonding force and tensile strength. This solves the common industry problem of weak bonding force and easy desoldering during long-term outdoor hot and cold cycles in traditional single-contact point welding.

[0057] Furthermore, during the process of embedding the welding strip 40 into the receiving groove, it will automatically find and center its position, realize the self-calibration of the welding surface, avoid the problems of misalignment and incomplete welding of the welding strip 40 in the traditional single-line structure, and greatly improve the welding consistency and yield of mass production.

[0058] Furthermore, the two connecting gate lines 321 simultaneously serve the dual functions of carrier convergence and soldering of the solder strip 40. The dual-path current carrying reduces series resistance and carrier recombination loss, thereby improving carrier transport efficiency. At the same time, by coordinating the matching of linewidth and doping concentration, the total width of the two lines is controlled, which can minimize additional light-shielding loss and achieve a net efficiency improvement in electrical gain that far exceeds optical loss.

[0059] In the solar cell 100 of this application, the contact layer 20 is disposed on one side of the supporting substrate 10. The side of the contact layer 20 away from the supporting substrate 10 includes a plurality of doped regions 21. The doped regions 21 include a busbar region 211 and a plurality of active regions. The plurality of active regions are respectively disposed on both sides of the busbar region 211. The busbar region 211 extends along a first direction D1, and the active regions extend along a second direction D2. The first direction D1 and the second direction D2 intersect. The electrode layer 30 is disposed on the side of the contact layer 20 opposite to the supporting substrate 10. The electrode layer 30 includes multiple fine gate structures, multiple bus structures 31, and multiple connection structures 32. The fine gate structures are disposed in the active region of the doped region 21, and the bus structures 31 and the connection structures 32 are disposed in the bus region 211 of the doped region 21. The fine gate structures connect to the bus structures 31, and the connection structures 32 respectively connect two adjacent bus structures 31 within the same bus region 211. The connection structure 32 includes at least two connecting gate lines 321 extending along the first direction D1, and the two ends of the connecting gate lines 321 are respectively connected to the two bus structures 31. The shunt design of the dual connecting gate lines 321 can effectively disperse the carrier transport pressure, significantly reduce the local series resistance of the bus path, reduce recombination losses during carrier transport, and significantly improve carrier transport efficiency. The limiting adapter structure formed by the dual connecting grid lines 321 can form a stable multi-point contact welding with the solder ribbon 40, significantly increasing the effective welding contact area between the solder ribbon 40 and the connecting grid lines 321, and significantly enhancing the welding bonding force. This fundamentally reduces the risk of desoldering and poor soldering caused by thermal cycling and environmental aging during long-term outdoor use of the solar cell 100, greatly improving the long-term operational stability of the solar cell 100 and the module. Simultaneously, this dual connecting grid line 321 structure provides ample alignment tolerance space for the solder ribbon 40, effectively adapting to common alignment deviations caused by equipment and processes during industrial mass production. This significantly reduces welding failures caused by solder ribbon 40 misalignment, and significantly improves the welding yield and batch consistency of the mass production of the solar cell 100.

[0060] Please refer to Figures 1 to 6 In one embodiment, the solar cell 100 includes a central region 101 and two end regions 102 disposed at both ends of the central region 101. The end regions 102 and the central region 101 are arranged along a first direction D1. The connecting structure 32 is disposed within the end regions 102. The dimension of the end regions 102 along the first direction D1 is L1, and the dimension of the solar cell 100 along the first direction D1 is L2. The ratio of L1 to L2 is β, and β satisfies: 0.03≤β≤0.15.

[0061] It should be noted that during the string welding, lamination, and long-term outdoor operation of photovoltaic cells, more than 90% of the problems of solder strip 40 desoldering, grid line breakage, and busbar failure occur in the two end regions 102 of the cell. This region is the core stress point of the solder strip 40 clamping welding and the stress concentration area of ​​the lamination process. At the same time, the temperature change at the edge is greater during outdoor use, and the fatigue damage caused by thermal expansion and contraction is much higher than that in the middle region 101 of the cell. In contrast, the welding stress in the middle region 101 of the cell is uniform and the failure risk is extremely low.

[0062] This application addresses the core challenge of welding reliability of the solar cell 100 by setting the dual-line connection structure 32 only in the high-failure-risk end region 102 and adopting a conventional busbar design in the middle region 101. This approach not only precisely solves the problem of increased silver paste consumption, increased shading loss, and increased production costs caused by laying a dual-line structure across the entire cell, but also avoids these issues.

[0063] The end region 102 has a dimension L1 along the first direction D1, and the solar cell 100 has a dimension L2 along the first direction D1. The ratio β of L1 and L2 satisfies: 0.03 ≤ β ≤ 0.15. If β < 0.03, the length of the end region 102 is too short to completely cover the high-stress area, the string welding clamping area, and the edge thermal stress concentration area of ​​the welding strip 40. The connection structure 32 of the double line cannot effectively reinforce the welding segment most prone to failure, and cannot play the core role of improving welding reliability and reducing the risk of desoldering and grid breakage. At the same time, the excessively short region will greatly increase the difficulty of screen printing pattern switching, exceeding the conventional process accuracy of mass production lines, and making it impossible to achieve large-scale stable production. If β > 0.15, the length of the end region 102 is too large, the coverage of the double-line connection structure 32 is too large, the silver paste consumption increases significantly, directly increasing the mass production cost of the solar cell 100. Furthermore, the additional shading loss caused by the double-line structure increases significantly, offsetting the electrical gain of the dual-path current carrying, resulting in a decrease in the conversion efficiency of the solar cell 100.

[0064] The solar cell 100 described in this application has a double-line connection structure 32 only in the end region 102 where the welding failure risk is highest. This specifically improves the welding bonding strength, fatigue resistance, and redundancy backup capability of the high-risk section, and completely solves the problem of grid breakage at the edge of the cell. The middle region 101 adopts a conventional design without adding extra silver paste cost or shading loss. Compared with the full-cell double-line solution, it can reduce the grid line silver paste consumption by 10%-15% while ensuring welding reliability, and significantly improves the economics of mass production.

[0065] Optionally, the ratio β of L1 and L2 can be 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, or other values ​​within the range of 0.03-0.15. This application does not impose any restrictions on this.

[0066] Please refer to Figures 1 to 6 In one embodiment, the ratio of the linewidth of the connecting gate line 321 to the width of the bus region 211 is α, wherein α satisfies: 0.1≤α≤0.4; and the width of the connecting gate line 321 is in the range of 60μm-100μm.

[0067] The ratio α of the linewidth of the connecting grid line 321 to the width of the current-collecting region 211 satisfies: 0.1 ≤ α ≤ 0.4. If α < 0.1, the linewidth of a single connecting grid line 321 is too narrow. On the one hand, this will lead to insufficient grid line conductivity, a sharp increase in series resistance, and a significant increase in carrier current-collecting losses, completely offsetting the electrical gain of dual-path current carrying. On the other hand, the excessively narrow linewidth exceeds the stable process range of photovoltaic mass production screen printing, which is prone to defects such as printing defects and sintering grid breaks, resulting in current-collecting interruption and partial cell failure, making it unsuitable for large-scale mass production. If α > 0.4, the linewidth of a single connecting grid line 321 is too wide, and the total width of the two lines will significantly exceed the width of a traditional single line. The light-shielding loss of the metal grid line will increase sharply, and eventually the optical loss will exceed the electrical gain, making it impossible to achieve a positive improvement in battery efficiency. At the same time, the excessively wide grid line will encroach on the space for laying the solder ribbon 40 in the current-collecting region 211, and may even extend beyond the boundary of the current-collecting region 211 into the active region, causing problems such as leakage and increased carrier recombination.

[0068] In summary, the ratio α of the linewidth of the connecting grid line 321 to the width of the bus region 211 satisfies: 0.1 ≤ α ≤ 0.4. This range is the optimal range that balances battery performance, welding compatibility, and mass production feasibility. Optionally, α can be 0.1, 0.15, 0.2, 0.22, 0.25, 0.3, 0.35, 0.37, 0.4, or other values ​​within the range of 0.1-0.4. This application does not impose any restrictions on this value.

[0069] Further optionally, the width of the connecting gate line 321 is in the range of 60μm-100μm. For example, the width of the connecting gate line 321 can be 60μm, or 62μm, or 63μm, or 65μm, or 67μm, or 70μm, or 73μm, or 75μm, or 80μm, or 82μm, or 85μm, or 88μm, or 90μm, or 91μm, or 95μm, or 99μm, or 100μm, or other values ​​within the range of 60μm-100μm. This application does not limit this value.

[0070] The ratio α of the linewidth of the connecting grid line 321 to the width of the current-carrying region 211 satisfies: 0.1≤α≤0.4. The width range of the connecting grid line 321 is 60μm-100μm. Through the dual limitation of relative ratio and absolute value, the conductivity of the connecting grid line 321 and the electrical gain of dual-path current carrying are guaranteed, while the light-shielding loss of the connecting grid line 321 is strictly controlled, providing stable parameter support for the positive improvement of battery conversion efficiency.

[0071] Please refer to Figures 1 to 6 In one embodiment, the doped region 21 includes an N-type doped region, and the linewidth of the connecting gate line 321 is negatively correlated with the doping concentration of the N-type doped region; when the doping concentration of the N-type doped region is in the range of 3 × 10⁻⁶. 19 cm -3 -6×10 19 cm -3 When the linewidth of the connecting gate line 321 is in the range of 80μm-100μm; when the doping concentration of the N-type doped region is in the range of 6×10 19 cm -3 -9×10 19 cm -3 At that time, the linewidth of the connecting gate line 321 ranges from 60μm to 80μm.

[0072] Specifically, as the doping concentration of the N-type doped region increases, the concentration of free electrons inside the semiconductor also increases, significantly enhancing lateral conductivity and drastically reducing sheet resistance. This results in a significant reduction in lateral transport and recombination losses of photogenerated electrons within the semiconductor. When the conductivity of the N-type doped region itself is sufficiently strong, the requirement for the current-carrying capacity of the metal connecting gate 321 decreases accordingly. There is no need to widen the connecting gate 321 to reduce series resistance; instead, the connecting gate 321 can be made narrower to reduce light-shielding losses and silver paste consumption while maintaining current-carrying capacity. Conversely, when the doping concentration of the N-type doped region is low, the semiconductor's conductivity is weak, and lateral carrier transport losses are high. In this case, a wider connecting gate 321 must be used to increase the conductive cross-sectional area of ​​the connecting gate 321, reducing series resistance and compensating for the insufficient conductivity of the semiconductor, thus preventing carrier accumulation and increased recombination losses.

[0073] The linewidth of the connecting gate line 321 is negatively correlated with the doping concentration of the N-type doped region. By matching the optimal linewidth to the N-type doped region with different doping concentrations, low-loss current collection of charge carriers is ensured, while the light-shielding loss of the connecting gate line 321 is minimized, thereby achieving a stable positive improvement in battery conversion efficiency.

[0074] Optionally, the doping concentration of the N-type doped region can be 3 × 10⁻⁶. 19 cm -3 or 4×10 19 cm -3 or 5×10 19 cm -3 or 6×10 19 cm -3 or 7×10 19 cm -3 or 8×10 19 cm -3 or 9×10 19 cm -3 or in 3×10 19 cm -3 -6×10 19 cm -3 Other values ​​within this range are not limited in this application.

[0075] In one embodiment, the doped region 21 includes a P-type doped region, and the linewidth of the connecting gate line 321 is negatively correlated with the doping concentration of the P-type doped region; when the doping concentration of the P-type doped region is in the range of 1×10 20 cm -3 -3×10 20 cm -3When the linewidth of the connecting gate line 321 is in the range of 80μm-100μm; when the doping concentration of the P-type doped region is in the range of 3×10 20 cm -3 -5×10 20 cm -3 At that time, the linewidth of the connecting gate line 321 ranges from 60μm to 80μm.

[0076] Specifically, as the doping concentration of the P-type doped region increases, the free hole concentration inside the semiconductor also increases simultaneously, significantly enhancing lateral conductivity and drastically reducing sheet resistance. This results in a significant reduction in lateral transport and recombination losses of photogenerated holes within the semiconductor. When the conductivity of the P-type doped region itself is sufficiently strong, the current-carrying capacity requirement of the metal connecting gate 321 decreases accordingly. There is no need to widen the connecting gate 321 to reduce series resistance; instead, the connecting gate 321 can be made narrower to reduce light-shielding losses and silver paste consumption while maintaining current-carrying capacity. Conversely, when the doping concentration of the P-type doped region is low, the semiconductor's conductivity is weak, and lateral carrier transport losses are high. In this case, a wider connecting gate 321 must be used to increase the conductive cross-sectional area of ​​the connecting gate, reducing series resistance, compensating for the insufficient conductivity of the semiconductor, and preventing carrier accumulation and increased recombination losses.

[0077] The linewidth of the connecting gate line 321 is negatively correlated with the doping concentration of the P-type doped region. By matching the optimal linewidth to the P-type doped region with different doping concentrations, low-loss hole collection is ensured, while the light-blocking loss of the connecting gate line 321 is minimized, thereby achieving a stable positive improvement in battery conversion efficiency.

[0078] Optionally, the doping concentration of the P-type doped region can be 1×10⁻⁶. 20 cm -3 or 1.2×10 20 cm -3 or 1.5×10 20 cm -3 or 1.8×10 20 cm -3 or 2×10 20 cm -3 or 2.1×10 20 cm -3 or 2.4×10 20 cm -3 or 2.5×10 20 cm -3 or 2.7×10 20 cm -3 or 2.9×10 20 cm-3 or 3×10 20 cm -3 or at 1×10 20 cm -3 -3×10 20 cm -3 Other values ​​within this range are not limited in this application.

[0079] Please refer to Figures 1 to 6 In one embodiment, within the same connection structure 32, the spacing between two adjacent connection grid lines 321 is 2 / 3 of the width of the solder strip 40.

[0080] In this embodiment, the cross-section of the welding strip 40 is circular. When the distance between the two connecting grid lines 321 is 2 / 3 of the width of the welding strip 40, after the welding strip 40 is placed, its bottom arc structure will naturally embed into the receiving groove formed by the two connecting grid lines 321, forming a physical limit. At the same time, the bottom arc surfaces on both sides of the welding strip 40 will completely overlap the upper surfaces of the two connecting grid lines 321, forming a stable double contact point surface welding, which is completely different from the traditional single contact point line welding of single line structure.

[0081] If the distance between two adjacent connecting grid lines 321 is less than 2 / 3 of the width of the welding strip 40, the width of the receiving groove is too narrow, and the welding strip 40 cannot be embedded in the groove. It can only overlap the connecting grid line 321, which cannot form a limiting effect. The alignment tolerance is greatly reduced, and the welding contact area is sharply reduced, resulting in insufficient welding pull and easy desoldering. If the distance between two adjacent connecting grid lines 321 is greater than 2 / 3 of the width of the welding strip 40, the width of the receiving groove is too wide, and the welding strip 40 is easy to sink completely into the groove. Only the bottom tip of the welding strip 40 forms point contact with the connecting grid line 321. The effective welding contact area is greatly reduced, the welding bonding force is insufficient, and physical limiting cannot be formed. The welding strip 40 is easy to deviate and slide out, resulting in poor welding or desoldering.

[0082] It should be noted that, in one embodiment, the spacing between two adjacent connecting grid lines 321 is based on 2 / 3 of the width of the solder strip 40, and the value of the spacing is allowed to fluctuate within ±15% of the base value. All of the above are embodiments of this application, and this application does not limit them.

[0083] In one embodiment, the width of the solder strip 40 ranges from 200μm to 400μm, and within the same connection structure 32, the spacing between two adjacent connection grid lines 321 ranges from 120μm to 280μm.

[0084] The width of the solder strip 40 ranges from 200μm to 400μm. If the width of the solder strip 40 is less than 200μm, its cross-sectional area is too small, resulting in insufficient conductivity. This leads to a sharp increase in the series resistance of the solar cells 100 after stringing, and a significant increase in current transmission loss. Simultaneously, an excessively thin solder strip 40 lacks mechanical strength, making it prone to breakage and tensile deformation during high-speed stringing, thus failing to adapt to mass production processes. If the width of the solder strip 40 is greater than 400μm, its light-shielding area increases significantly, reducing the effective light-absorbing area of ​​the solar cells 100 and significantly increasing optical losses, thus offsetting electrical gains. Furthermore, an excessively thick solder strip 40 results in excessive welding stress, easily causing fragmentation and microcracks in the solar cells 100 during stringing, significantly increasing the production scrap rate.

[0085] Therefore, the width of the welding strip 40 is in the range of 200μm-400μm, which ensures sufficient mechanical strength while avoiding excessive welding stress. Optionally, the width of the welding strip 40 can be 200μm, 210μm, 220μm, 230μm, 240μm, 250μm, 260μm, 270μm, 280μm, 290μm, 300μm, 310μm, 320μm, 330μm, 340μm, 350μm, 360μm, 370μm, 380μm, 390μm, or 400μm, or other values ​​within the range of 200μm-400μm. This application does not impose any limitations on this.

[0086] Within the same connection structure 32, the spacing between two adjacent connection grid lines 321 ranges from 120μm to 280μm. If the spacing is less than 120μm, it cannot meet the 2 / 3 ratio requirement of the minimum specification 200μm solder ribbon 40, making it impossible to form effective slot limiting and double contact welding. At the same time, the excessively narrow spacing exceeds the mass production process precision of screen printing, easily leading to defects such as grid line adhesion and pattern deformation. If the spacing is greater than 280μm, it exceeds the 2 / 3 ratio requirement of the maximum specification 400μm solder ribbon 40, making it impossible to form effective physical limiting and stable welding contact. At the same time, the excessively wide spacing will cause the grid lines to extend beyond the boundary of the current collection area 211, resulting in increased light-shielding loss and increased leakage risk.

[0087] Therefore, the spacing between two adjacent connecting grid lines 321 is 120μm-280μm, which covers 2 / 3 of the spacing of the 200μm-400μm solder strip 40, while reserving ±10% mass production process tolerance, which can realize the automatic centering limit of the solder strip 40. Optionally, the spacing between two adjacent connecting gate lines 321 can be 120μm, or 130μm, or 140μm, or 150μm, or 160μm, or 167μm, or 170μm, or 180μm, or 190μm, or 200μm, or 210μm, or 220μm, or 230μm, or 233μm, or 240μm, or 250μm, or 260μm, or 270μm, or 280μm, or other values ​​within the range of 120μm-280μm, and this application does not impose any restrictions on this.

[0088] Please refer to the above as well. Figure 7 , Figure 7 This is a flowchart of a method for preparing a solar cell according to an embodiment of this application.

[0089] This application also provides a method for preparing a solar cell 100. The method is used to prepare the solar cell 100 and includes steps S100, S200, S300, S400 and S500. The detailed description of steps S100, S200, S300, S400 and S500 is as follows.

[0090] S100: Provide a support substrate 10 and deposit the contact layer 20 on the support substrate 10.

[0091] After providing the support substrate 10, the surface of the support substrate 10 is treated. The side of the support substrate 10 facing the light is subjected to texturing and antireflection film preparation. Texturing forms a pyramid-shaped micro-nano structure, which increases the number of light reflections and improves light absorption efficiency. The antireflection film is generally made of materials such as SiNx and Al2O3 to reduce the surface reflectivity of light.

[0092] The contact layer 20 is deposited on the supporting substrate 10 in two steps: Step 1: A silicon dioxide tunneling oxide layer 23 is grown on the silicon wafer surface through a thermal oxidation process to achieve chemical passivation of the silicon wafer surface; Step 2: An intrinsic polycrystalline silicon layer is deposited on the surface of the tunneling oxide layer 23 using a low-pressure chemical vapor deposition (LPCVD) process, which serves as the substrate for the subsequent fabrication of the patterned doped region 21.

[0093] S200: A doped region 21 is formed on the contact layer 20, wherein the doped region 21 includes a bus region 211 and a plurality of active regions, the plurality of active regions are respectively disposed on both sides of the bus region 211, the bus region 211 extends along a first direction D1, the active regions extend along a second direction D2, and the first direction D1 and the second direction D2 intersect.

[0094] A mask layer is formed on the surface of the polycrystalline silicon layer, and a doped window is formed on the mask layer by laser grooving process according to the preset busbar region 211 and active region pattern.

[0095] Forming doped regions 21 on the contact layer 20 includes performing partitioned doping diffusion. Specifically, a two-step diffusion process is used to form the P-type doped region and the N-type doped region respectively. Step 1: The P-type doped region is formed within the P-type doped window using a boron diffusion process, thus completing the preparation of the hole-selective conduction region; Step 2: The N-type doped region is formed within the N-type doped window by phosphorus diffusion process, thus completing the preparation of the electron-selective conduction region; S300: The electrode layer 30 is printed on the contact layer 20, wherein the electrode layer 30 includes a plurality of fine gate structures, a plurality of bus structures 31 and a plurality of connection structures 32. The fine gate structures are disposed in the active region of the doped region 21, and the bus structures 31 and the connection structures 32 are disposed in the bus region 211 of the doped region 21. The fine gate structures connect the bus structures 31, and the connection structures 32 respectively connect two adjacent bus structures 31 within the same bus region 211. The connection structure 32 includes at least two connection gate lines 321 extending along the first direction D1, and the two ends of the connection gate lines 321 are respectively connected to two bus structures 31.

[0096] Please refer to Figure 8 , Figure 8 This is a flowchart of step S310 in a method for preparing a solar cell provided in this application.

[0097] In one embodiment, step S300, which involves printing the electrode layer 30 on the contact layer 20, includes step S310, which is described in detail below.

[0098] S310: Screen printing is performed using highly conductive silver paste, wherein the silver content of the paste is ≥92.5%, the printing pressure range is 40N-50N, and the printing speed is 400mm / s-500mm / s; The mesh count ranges from 600 to 800.

[0099] It should be noted that a pre-baking process is required after printing. The printed electrode layer 30 is pre-baked at a medium to low temperature to remove most of the organic carrier in the silver paste, fix the grid pattern, and prevent pattern deformation and smudging in subsequent processes.

[0100] S400: The electrode layer 30 is sintered.

[0101] Please refer to Figure 9 , Figure 9 This is a flowchart of step S410 in a method for preparing a solar cell provided in this application.

[0102] In one embodiment, step S400, which involves sintering the electrode layer 30, includes step S410, which is described in detail below.

[0103] S410: The electrode layer 30 is sintered according to preset parameters, wherein the preset parameters include heating rate, peak temperature, peak holding time and cooling rate, the heating rate is in the range of 10℃ / s-20℃ / s, the peak temperature is in the range of 680℃-720℃, the peak holding time is in the range of 3s-8s, and the cooling rate is in the range of 3℃ / s-6℃ / s.

[0104] This application does not limit the sintering method and equipment for the electrode layer 30. The sintering process curve is divided into three stages: heating, holding, and cooling. Heating stage: The temperature is rapidly increased from room temperature to the peak sintering temperature at a heating rate of 10℃ / s-20℃ / s; Peak holding stage: The peak temperature is controlled at 680℃-720℃, and the peak holding time is 3s-8s to complete the sintering of the silver paste and the formation of ohmic contact. Cooling phase: The temperature is gradually reduced to room temperature at a rate of 3℃ / s-6℃ / s to avoid rapid cooling that could cause gate line cracking or silicon wafer warping.

[0105] Sintering the electrode layer 30 allows the organic carrier in the silver paste to completely volatilize, the glass phase to melt and wet, and the silver particles to sinter and densify, forming highly conductive metal grid lines. This significantly reduces the series resistance of the electrodes and reduces Joule heat loss in current transmission.

[0106] S500: Weld solder strips 40 onto the electrode layer 30 for encapsulation to form the solar cell 100.

[0107] Please refer to Figure 10 , Figure 10 This is a flowchart of step S510 in a method for preparing a solar cell provided in this application.

[0108] In one embodiment, welding the solder strip 40 onto the electrode layer 30 includes step S510, which is described in detail below.

[0109] S510: Welding of the welding strip 40 on the electrode layer 30 by infrared low temperature, wherein the welding temperature range is 160℃-200℃, the holding time ranges from 10s to 14s, and the tension of the welding strip 40 ranges from 0.3N to 0.7N.

[0110] The connecting grid line 321 of the dual-line system forms a double contact point welding with the welding strip 40, which increases the welding contact area and welding pull force compared with the traditional single-line system. At the same time, the slot-type limiting structure greatly improves the alignment tolerance of the welding strip 40 and improves the batch welding yield.

[0111] This application also provides a photovoltaic module comprising at least one of the solar cells 100.

[0112] In the photovoltaic module approved in this application, the contact layer 20 is disposed on one side of the supporting substrate 10. The side of the contact layer 20 away from the supporting substrate 10 includes a plurality of doped regions 21. The doped region 21 includes a current-collecting region 211 and a plurality of active regions. The plurality of active regions are respectively disposed on both sides of the current-collecting region 211. The current-collecting region 211 extends along a first direction D1, and the active regions extend along a second direction D2. The first direction D1 and the second direction D2 intersect. The electrode layer 30 is disposed on the side of the contact layer 20 opposite to the supporting substrate 10. The electrode layer 30 includes multiple fine gate structures, multiple bus structures 31, and multiple connection structures 32. The fine gate structures are disposed in the active region of the doped region 21, and the bus structures 31 and the connection structures 32 are disposed in the bus region 211 of the doped region 21. The fine gate structures connect to the bus structures 31, and the connection structures 32 respectively connect two adjacent bus structures 31 within the same bus region 211. The connection structure 32 includes at least two connecting gate lines 321 extending along the first direction D1, and the two ends of the connecting gate lines 321 are respectively connected to the two bus structures 31. The shunt design of the dual connecting gate lines 321 can effectively disperse the carrier transport pressure, significantly reduce the local series resistance of the bus path, reduce recombination losses during carrier transport, and significantly improve carrier transport efficiency. The limiting adapter structure formed by the dual connecting grid lines 321 can form a stable multi-point contact welding with the solder ribbon 40, significantly increasing the effective welding contact area between the solder ribbon 40 and the connecting grid lines 321, and significantly enhancing the welding bonding force. This fundamentally reduces the risk of desoldering and cold solder joints caused by thermal cycling and environmental aging during long-term outdoor use of the photovoltaic module, and significantly improves the long-term operational stability of the photovoltaic module. At the same time, the dual connecting grid line 321 structure provides sufficient alignment tolerance space for the solder ribbon 40, which can effectively adapt to the common alignment deviations caused by equipment and processes in industrial mass production, significantly reducing welding failure problems caused by solder ribbon 40 misalignment, and significantly improving the welding yield and batch consistency of the photovoltaic module in mass production.

[0113] The following two embodiments are provided to illustrate the effect of the solar cell described in this application, and should not be construed as limiting the application.

[0114] Example 1: The effect of dual-line parameters on cell efficiency under the conditions of main grid reserved width (busbar region width) and doping concentration gradient.

[0115] Experimental Design Objective Investigate the main gate reserved width (bus region width, 450μm-500μm) and doping concentration (1×10⁻⁶). 19 cm -3 -2×10 20 cm-3 Under gradient conditions, the impact of different double-line widths on the balance between "shielding area (optical loss) and carrier transport (electrical gain)" is investigated, quantifying the actual benefits of short-circuit current density and conversion efficiency.

[0116] Experimental variables and control group Fixed variables: solder strip diameter 0.3mm (corresponding to double-line spacing = 0.3mm × 2 / 3 = 0.2mm), effective battery area 3764.8cm². 2 The number of coarse weld points is 720, and the spacing between adjacent coarse weld points is 5.79 mm. Variable gradient: Main gate reserved width (W): 450μm, 500μm; Doping concentration (N): 1×10 19 cm -3 5×10 19 cm -3 2×10 20 cm -3 ; Dual line width (w): corresponds to 1 / 5, 1 / 4, and 1 / 3 of the main gate width (i.e., 450μm main gate corresponds to 90μm, 112.5μm, and 150μm; 500μm main gate corresponds to 100μm, 125μm, and 167μm). Control group: Traditional thickened single-line structure (line width = 150μm, light-blocking area 0.65cm²) 2 (To ensure consistent conductivity benchmarks).

[0117] Preparation process details Printing process: Silver paste screen printing is used. The paste type is BC special high conductivity silver paste (silver content ≥92.5%), the printing pressure is 45N, the printing speed is 450m / s, and the screen mesh is 700 mesh. Sintering process: Sintering, heating rate 15℃ / s, peak temperature 700℃, holding time 5s, cooling rate 5℃ / s; Welding process: Infrared low temperature welding, welding temperature 180℃, holding time 12s, and welding strip tension controlled at 0.5N.

[0118] Optical loss analysis: Total width of the double line = 2 × single line width. When the single line width is 90μm, the total width is 180μm (slightly exceeding the 150μm of a single line), and the light-blocking area increases by approximately 1.2 times (double line: 0.78cm). 2 Single root: 0.65cm 2 Theoretically, this leads to a reduction of approximately 0.8% in incident luminous flux, corresponding to a decrease of approximately 0.05 mA / cm² in short-circuit current density (Jsc). 2 ; Electrical gain analysis: The dual-line design employs a dual-path current carrying capacity, which disperses the carrier transport pressure, and the linewidth matches the doping concentration (e.g., 5×10⁻⁶). 19 cm -3 At high concentrations, the narrow linewidth still ensures current-carrying capacity, and carrier recombination losses are reduced. Experimental data show that the carrier mobility of the double-line structure is increased by 8%-12% compared to the single-line structure, corresponding to an increase in Jsc of approximately 0.14-0.21 mA / cm². 2 ; Net profit logic: Electrical gain (0.14mA / cm) 2 -0.21mA / cm 2 Optical loss (0.05 mA / cm) > Optical loss 2 Ultimately, Jsc achieved a net improvement; Experimental data

[0119] Results Analysis The core logic behind the efficiency improvement is that the "electrical gain (carrier transport optimization)" of the dual-line structure offsets the "optical loss (slight increase in light blocking)" and the net benefit is positive. Among them, the dual-line width of "1 / 5 of the main grid width" (total width 180μm-200μm) is the optimal choice, with an efficiency improvement of 0.21%-0.26%, which is in line with the actual efficiency improvement range of TBC cells (in the industry, single-structure optimization usually improves efficiency by 0.1%-0.3%). Effect of doping concentration: The higher the doping concentration, the stronger the carrier mobility, and the more significant the electrical gain for the same doublet width (2×10). 20 cm -3 Concentration group better than 1×10 19 cm -3 The group verified the necessity of "linewidth matching with doping concentration"; Critical value of total line width: When the total line width is ≥300μm (150μm for a single line), the optical loss exceeds the electrical gain, and the efficiency improvement is negligible. Therefore, it is further clarified that "1 / 5 of the main gate width" is the optimal line width ratio.

[0120] Example 2: The effect of matching grid line spacing and solder strip width on welding performance.

[0121] Experimental Design Objective Based on the optimal parameters of Example 1 (main gate width 450 μm, doping concentration 5 × 10⁻⁶), 19 cm -3 The study investigated the quantitative effects of different solder strip widths (diameters) and corresponding double-line spacing (2 / 3 of the solder strip diameter) on welding tensile force, allowable offset, and welding yield.

[0122] Experimental variables and control group Fixed variables: gate width 450 μm, doping concentration 5 × 10⁻⁶ 19 cm -3 Dual-line width 90μm, effective battery area 3764.8cm² 2 ; Variable gradient: Weld strip width (diameter D): 0.25mm, 0.3mm, 0.35mm; Double line spacing (S): corresponds to 2 / 3 of the solder strip diameter (0.25mm×2 / 3≈0.167mm, 0.3mm×2 / 3=0.2mm, 0.35mm×2 / 3≈0.233mm); Control group: Traditional thickened single-line structure (line width 150μm, light-blocking area 0.65cm²) 2 (The welding parameters are consistent with those of the experimental group).

[0123] Preparation process details Printing process: Same as in Example 1 (silver paste screen printing, pressure 45N, speed 450mm / s). Sintering process: Same as in Example 1 (700℃×5s); Welding process: Infrared low-temperature welding, welding temperature 180℃, holding time 5s, welding strip tension 0.5N; Test method: Welding tensile test: A universal tensile testing machine was used to apply tensile force perpendicular to the length of the weld strip, and the maximum tensile force at break was recorded. Allowable offset: Gradually increase the solder strip alignment offset and test the maximum offset value without solder detachment after welding; Welding yield: The welding pass rate of 1000 batteries is statistically analyzed (no desoldering or poor welding is considered passable).

[0124] Welding tensile force theory: Tensile force is positively correlated with contact area. The double-line structure has two contact points, and the contact area is increased by about 60% compared with the single line (based on the contact geometry model of the weld strip and the grid line, the weld strip is embedded between the double lines to form contact on both sides). Offset tolerance theory: When the spacing between the two lines is 2 / 3 of the solder strip diameter, the solder strip can move within a small range within the "groove" formed by the two lines, and the allowable offset is about 10% of the solder strip diameter (based on mechanical interference model simulation). Experimental results and quantitative output (data within a reasonable range)

[0125] Experimental conclusions Welding tensile strength improvement: The tensile strength of each experimental group increased by 43.75%-62.5% compared with the control group. The core reason is that the double contact point increases the bonding area, which significantly enhances the welding stability and conforms to the actual welding mechanics law. Fault-tolerant and production-adaptable: Allows for an offset of 25μm-35μm, perfectly matching the ±30μm alignment accuracy requirements in industrial production, effectively avoiding desoldering problems caused by equipment errors and operational deviations. Significantly improved yield: The welding yield was ≥98.1%, which is more than 5.8 percentage points higher than the control group (92.3%). Among them, the matching degree of 0.3mm welding strip and 0.2mm spacing was the best, with a yield of 98.8%, which meets the stability requirements of mass production.

[0126] In summary, based on Embodiments 1 and 2, the beneficial effects of the technical solution of this application can be derived as follows.

[0127] 1. Optimized Efficiency: By using dual-wire narrow linewidth and parameter matching, and with a slight increase in light shading, the net increase in short-circuit current density is achieved by 0.09 mA / cm² due to improved carrier transport efficiency. 2 -0.16mA / cm 2 The battery conversion efficiency is improved by 0.12%-0.26%, which is in line with the actual technical improvement range of TBC batteries; 2. Significantly improved welding reliability: The dual-line dual-contact design increases welding tensile strength by 43.75%-62.5% (from 1.0N to 1.3N-1.45N), significantly reducing the risk of desoldering during long-term use; 3. Fault tolerance to meet production needs: Allows for solder strip offset of 25μm-35μm, matching industrial alignment precision, increasing welding yield from 92.3% to over 98.1%, and reducing production losses; 4. Strong production line adaptability: It only uses silver paste screen printing process, without the need to modify existing production equipment, and can be directly introduced into TBC battery production lines, reducing technical transformation costs; 5. Flexible parameter adaptation: The width and spacing of the dual lines can be flexibly adjusted according to the reserved width of the main grid, the doping concentration, and the width of the solder strip, adapting to different specifications of TBC-0BB cells and making it suitable for a wide range of applications.

[0128] In this application, the terms "embodiment" and "implementation" mean that a specific feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The appearance of these phrases in various locations throughout the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this application can be combined with other embodiments. Furthermore, it should be understood that the features, structures, or characteristics described in the various embodiments of this application can be arbitrarily combined to form another embodiment that does not depart from the spirit and scope of the technical solution of this application, provided there is no contradiction between them.

[0129] The above description represents some embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A solar cell, characterized in that, include: Supporting substrate; A contact layer is disposed on one side of the support substrate. The side of the contact layer opposite to the support substrate includes multiple doped regions. Each doped region includes a current-collecting region and multiple active regions. The multiple active regions are respectively disposed on both sides of the current-collecting region. The current-collecting region extends along a first direction, and the active regions extend along a second direction. The first direction and the second direction intersect. as well as An electrode layer is disposed on the side of the contact layer away from the carrier substrate. The electrode layer includes multiple fine gate structures, multiple bus structures, and multiple connection structures. The fine gate structures are disposed in the active region of the doped region, and the bus structures and the connection structures are disposed in the bus region of the doped region. The fine grid structure connects to the busbar structure, and the connecting structure connects two adjacent busbar structures within the same busbar region. The connecting structure includes at least two connecting grid lines extending along the first direction, and the two ends of the connecting grid lines are respectively connected to the two busbar structures.

2. The solar cell according to claim 1, characterized in that, The solar cell further includes a plurality of solder strips arranged along the first direction, the solder strips being disposed on a plurality of the current-collecting structures in the current-collecting region; The connection structure includes two connection grid lines, with a receiving groove formed between the two connection grid lines, and the solder strip covers at least one of the connection grid lines and is at least partially disposed within the receiving groove.

3. The solar cell according to claim 1, characterized in that, The ratio of the linewidth of the connecting grid line to the width of the bus region is α, where α satisfies: 0.1≤α≤0.4; the width of the connecting grid line ranges from 60μm to 100μm.

4. The solar cell according to claim 2, characterized in that, The width of the solder strip ranges from 200μm to 400μm, and the spacing between two adjacent connecting grid lines within the same connection structure ranges from 120μm to 280μm.

5. The solar cell according to claim 1, characterized in that, The solar cell includes a central region and two end regions located at both ends of the central region. The end regions and the central region are arranged along a first direction. The connecting structure is located within the end regions. The dimension of the end regions along the first direction is L1, and the dimension of the solar cell along the first direction is L2. The ratio of L1 to L2 is β, and β satisfies: 0.03≤β≤0.

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6. The solar cell according to claim 1, characterized in that, The doped region includes an N-type doped region, and the linewidth of the connecting gate line is negatively correlated with the doping concentration of the N-type doped region; when the doping concentration of the N-type doped region is 3 × 10⁻⁶... 19 cm -3 -6×10 19 cm -3 When the linewidth of the connecting gate line is in the range of 80μm-100μm; when the doping concentration of the N-type doped region is in the range of 6×10 19 cm -3 -9×10 19 cm -3 At that time, the linewidth of the connecting gate line ranges from 60μm to 80μm; Or, the doped region includes a P-type doped region, and the linewidth of the connecting gate line is negatively correlated with the doping concentration of the P-type doped region; when the doping concentration of the P-type doped region is 1×10 20 cm -3 -3×10 20 cm -3 When the linewidth of the connecting gate line is in the range of 80μm-100μm; when the doping concentration of the P-type doped region is in the range of 3×10 20 cm -3 -5×10 20 cm -3 At that time, the linewidth of the connecting gate line ranges from 60μm to 80μm.

7. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell according to any one of claims 1-6 comprises: A support substrate is provided, and the contact layer is deposited on the support substrate; A doped region is formed on the contact layer, wherein the doped region includes a current-collecting region and a plurality of active regions, the plurality of active regions being respectively disposed on both sides of the current-collecting region, the current-collecting region extending along a first direction, and the active regions extending along a second direction, the first direction and the second direction intersecting; The electrode layer is printed on the contact layer, wherein the electrode layer includes a plurality of fine gate structures, a plurality of bus structures, and a plurality of connection structures. The fine gate structures are disposed in the active region of the doped region, and the bus structures and the connection structures are disposed in the bus region of the doped region. The fine gate structures connect the bus structures, and the connection structures respectively connect two adjacent bus structures in the same bus region. The connection structure includes at least two connection gate lines extending along the first direction, and the two ends of the connection gate lines are respectively connected to the two bus structures. The electrode layer is sintered; Solder strips are welded onto the electrode layer for encapsulation to form the solar cell.

8. The preparation method according to claim 7, characterized in that, Printing the electrode layer on the contact layer includes: Highly conductive silver paste is used for screen printing, wherein the silver content of the silver paste is ≥92.5%, the printing pressure range is 40N-50N, and the printing speed is 400mm / s-500mm / s; Sintering the electrode layer includes: The electrode layer is sintered according to preset parameters, wherein the preset parameters include heating rate, peak temperature, peak holding time and cooling rate, the heating rate ranges from 10℃ / s to 20℃ / s, the peak temperature ranges from 680℃ to 720℃, the peak holding time ranges from 3s to 8s, and the cooling rate ranges from 3℃ / s to 6℃ / s.

9. The preparation method according to claim 7, characterized in that, Welding solder strips onto the electrode layer includes: Welding strips onto the electrode layer using infrared cryogenic welding, wherein the welding temperature ranges from 160℃ to 200℃, the holding time ranges from 10s to 14s, and the welding strip tension ranges from 0.3N to 0.7N.

10. A photovoltaic module, characterized in that, The photovoltaic module comprises at least one solar cell as described in any one of claims 1-6.

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