A low cost back contact cell and method of manufacturing the same

Abstract

This invention relates to a low-cost back-contact solar cell and its manufacturing method, belonging to the field of photovoltaic power generation technology. The low-cost back-contact solar cell includes: an N-type silicon wafer having a front and a back side; the N-type silicon wafer having a through-hole extending from the back side to the front side, with silver plugging material disposed within the through-hole; a portion of the front side of the N-type silicon wafer having a first tunnel oxide layer and a P-type silicon oxide layer sequentially stacked thereon. + -Poly layer; the P + - A front-side silver dot is provided above the Poly layer; a second tunnel oxide layer and an N-type silicon wafer are sequentially stacked on a portion of the back side. + -Poly layer; the N + - The surface of the Poly layer is covered with back silver; the areas of the N-type silicon wafer without front silver dots and back silver, and the surface of the through-holes are covered with a first passivation stack, which consists of an aluminum oxide film and a silicon nitride layer from the inside out; the surface of the front silicon nitride layer of the N-type silicon wafer is covered with a TCO layer. This invention replaces the traditional front silver gate lines and main gate with a TCO layer, optimizing the metal electrodes into a discrete silver dot structure, significantly reducing the cost of precious metal silver paste.

Description

Technical Field

[0001] This invention pertains to the field of photovoltaic power generation technology, and in particular relates to a low-cost back contact battery and its manufacturing method. Background Technology

[0002] Currently, the mainstream technology for crystalline silicon solar cells is Topcon cells. Although this technology has a mature and stable process, it still suffers from some light loss due to its front and back metal grid structure. Meanwhile, back-contact (BC) cell technology, with its advantages of no front shading and high conversion efficiency, has become an important direction for industry research and mass production.

[0003] However, in the industrialization process of existing back-contact batteries, the price of precious metal pastes for photovoltaics fluctuates wildly, and the silver paste consumption of traditional battery structures is relatively high, which greatly limits the cost advantage of batteries per kilowatt-hour. Summary of the Invention

[0004] The purpose of this invention is to provide a low-cost back-contact battery and its manufacturing method, thereby reducing the processing cost of solar cells.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] On the one hand, a low-cost back-contact battery is provided, the battery comprising:

[0007] An N-type silicon wafer has a front side and a back side. The N-type silicon wafer has a through hole that extends from the back side to the front side, and a silver plug is placed inside the through hole.

[0008] A portion of the front side of the N-type silicon wafer is sequentially stacked with a first tunnel oxide layer and a P-type silicon wafer. + -Poly layer; the P + -A silver dot is positioned above the Poly layer;

[0009] The back surface region of the N-type silicon wafer is sequentially stacked with a second tunnel oxide layer and an N-type silicon wafer. + -Poly layer;

[0010] The N + -The surface of the Poly layer is backed with silver;

[0011] The N-type silicon wafer has a first passivation layer on the surface of the area without front silver dots and back silver dots and the cover through-hole. The first passivation layer consists of an aluminum oxide film and a silicon nitride layer from the inside out.

[0012] The N-type silicon wafer has a TCO layer covering the surface of the silicon nitride layer on the front side, which connects the front silver dots to the via silver plugs.

[0013] Furthermore, the diameter of the through hole is 100um to 300um, and the hole spacing is 5 to 30mm.

[0014] Furthermore, the thickness of the alumina layer is 3nm to 20nm.

[0015] Furthermore, the thickness of silicon nitride on the back side of the N-type silicon wafer is 60–200 nm; the thickness of silicon nitride on the front side of the N-type silicon wafer is 10–30 nm.

[0016] Furthermore, the TCO layer has a sheet resistance of 20–120 Ω / □, a TCO refractive index of 1.9–2.1, and a thickness of 70–120 nm.

[0017] Furthermore, the N-type silicon wafer has a localized passivated region and a non-passivated region on its front side, the localized passivated region being a polished surface and having the P-type passivated region positioned above it. + -Poly layer, the non-passivated region has a velvety structure.

[0018] On the other hand, a low-cost method for manufacturing a back-contact battery is provided, comprising the following steps:

[0019] S1. Polish the N-type silicon wafer on both sides;

[0020] S2, Forming a first tunnel oxide layer on the front side of the N-type silicon wafer, P + - Poly layer and BSG layer, forming a second tunnel oxide layer and N on the back side. + - Poly layer and PSG layer;

[0021] S3. Use a laser to perform patterned micro-etching on the front and back poly layers, where the front side retains discretely distributed patterned areas.

[0022] S4. Use an infrared laser to drill holes in the silicon wafer to form through holes;

[0023] S5. By treating with an alkaline solution, a textured surface is formed on the front laser etching area, and the damaged layer and the surrounding coating are removed.

[0024] S6. Deposit a first passivation stack on the front and back sides of the battery, wherein the first passivation stack extends to the inner wall of the through hole;

[0025] S7, on the back N + -The poly area is printed with silver on the back, and on the front P + Discrete front-side silver dots are printed at the corresponding positions in the Poly region, and sintering allows the silver dots to penetrate the passivation layer and P. + -The poly layer forms an ohmic contact;

[0026] S8. Fill the through hole with silver plugging material;

[0027] S9. Deposit a TCO layer on the front side of the battery, wherein the TCO layer covers the front silver dots and is connected to the plugging silver.

[0028] Furthermore, in step S8, low-temperature silver paste is used to plug the holes, and the curing temperature of the low-temperature silver paste is lower than the sintering temperature in step S7.

[0029] Further, in step S9, a TCO layer is deposited using a PVD or RPD process, wherein the material of the TCO layer includes any one of ITO, AZO, or IWO.

[0030] On the other hand, a photovoltaic module is provided, comprising:

[0031] The cover plate, the back plate, and the battery string disposed between the cover plate and the back plate, the battery string being composed of multiple low-cost back-contact batteries electrically connected together.

[0032] Beneficial effects:

[0033] This disclosure replaces the traditional front-side silver gate line and main gate with a TCO layer, and optimizes the metal electrode into a discrete silver dot structure. This significantly reduces the cost of precious metal silver paste, while reducing front-side shading loss and effectively improving the short-circuit current (Isc).

[0034] This disclosure employs a localized SiO2 / Poly passivation structure on both the front and back sides, which can significantly improve the open-circuit voltage (Voc) of the battery. The aluminum oxide / silicon nitride layer retained on the front side ensures good interface passivation and hydrogen passivation effects when TCO cannot provide passivation.

[0035] This publicly disclosed solution can make full use of existing mature Topcon battery production lines for upgrading and transformation, reducing the entry barriers for new technologies and the risks of equipment investment.

[0036] This disclosure effectively circumvents existing patent restrictions on TBC batteries through a unique back contact structure design and process path.

[0037] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a battery structure diagram of an embodiment of the present disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] This invention provides a low-cost back-contact battery, the structural features of which are as follows:

[0042] N-type silicon wafers are used as the substrate.

[0043] The front side of an N-type silicon wafer has locally passivated and non-passivated regions. The locally passivated regions are polished, while the non-passivated regions are textured, with the textured structure improving light utilization. The polished front surface contains SiO2 / P... + - A poly stacked structure is used to replace the traditional PN junction to form good interface passivation, thereby improving the open-circuit voltage (Voc) of the battery.

[0044] The N-type silicon wafer is covered with an aluminum oxide / silicon nitride layer on its front side, with a total thickness ranging from 5nm to 30nm. This layer serves to passivate and provide a hydrogen source; at high temperatures, excess hydrogen from the silicon nitride will enter the battery, forming hydrogen passivation and ensuring a certain open-circuit voltage (Voc).

[0045] Silver paste electrodes are printed on the surface of the localized passivation region on the front side of the N-type silicon wafer. During sintering, the silver paste etches open the passivation layer, forming an ohmic contact with the underlying poly layer. By replacing traditional gate lines with a discrete silver dot layout, the silver paste consumption is significantly reduced, the light-shielding area is decreased, and the short-circuit current (Isc) is increased.

[0046] The outermost layer of the battery is covered with a TCO layer. The TCO layer is used for the lateral transport of charge carriers to replace part of the silver conductive path, and is connected with the plugging silver to connect the dispersed silver points on the front side into an electrical whole, ultimately guiding the positive electrode to the back side.

[0047] The back side of the N-type silicon wafer is polished, and localized SiO2 / N is formed on it. + - Poly passivation structure, with anti-reflective coating and metal electrode.

[0048] In some specific embodiments disclosed in this application, the battery structure is as follows: Figure 1 As shown, a low-cost back-contact battery has the following structure, wherein the battery uses an N-type silicon wafer 1 as a substrate.

[0049] The front side of the N-type silicon wafer 1 is the light-facing side, and the back side is the back-facing side. Both the front and back sides are polished or subjected to controlled texturing. The N-type silicon wafer 1 has a through hole that runs from the back side to the front side. A silver plug 18 is placed inside the through hole to allow the positive current to be led out from the back side.

[0050] The diameter of the through holes is 100µm to 300µm, and the spacing between the holes is 5 to 30mm.

[0051] A portion of the front side of the N-type silicon wafer 1 is sequentially stacked with a first tunnel oxide layer 13 and a P+-Poly layer 14; the first tunnel oxide layer 13 is a SiO2 layer.

[0052] A front silver dot 16 is provided above the P+-Poly layer 14. The front silver dot 16 serves as the positive electrode of the battery. The front silver dot 16 penetrates the thin passivation layer that may exist through sintering and forms a good ohmic contact with the P+-Poly layer 14.

[0053] The SiO2 thickness is 1-2 nm; P +- Poly thickness 100~300nm, sheet resistance 40~150Ω / □.

[0054] A second tunnel oxide layer 19 and an N+-Poly layer 20 are sequentially stacked on a portion of the back side of the N-type silicon wafer 1. The second tunnel oxide layer 19 is a SiO2 layer.

[0055] The surface of the N+-Poly layer 20 is provided with a back silver 21, which serves as a negative electrode for conducting negative electrode current.

[0056] The SiO2 thickness is 1-2 nm; N +- Polyester thickness is typically 100–300 nm, and sheet resistance is 10–100 Ω / □.

[0057] The N-type silicon wafer 1 has a first passivation layer on the surface of the area without front silver dots and back silver dots and the through-hole. The first passivation layer consists of an aluminum oxide film 11 and a silicon nitride layer 12 from the inside out. The first passivation layer covers the inner wall of the through-hole and is continuous with the first passivation layer on the surface of the N-type silicon wafer 1.

[0058] The thickness of the alumina layer is 3nm to 20nm.

[0059] The thickness of silicon nitride on the back side of the N-type silicon wafer is 60–200 nm; the thickness of silicon nitride on the front side of the N-type silicon wafer is 10–30 nm.

[0060] A TCO layer 17 covers the surface of the front silicon nitride layer 12 of the N-type silicon wafer 1. The TCO layer 17 not only covers the front silicon nitride layer 12 of the N-type silicon wafer 1, but also covers the front silver dots 16 and the via-plug silver 18. This facilitates lateral transmission, partially replacing expensive silver transmission, and connects with the via-plug silver, ultimately linking the scattered silver dots on the front into a whole, connecting the positive electrode to the back side.

[0061] The TCO layer has a sheet resistance of 20–120 Ω / □, a TCO refractive index of 1.9–2.1, and a thickness of 70–120 nm.

[0062] When Topcon is combined with MWT, the consumption of silver paste on the front side cannot be significantly reduced. Using TCO to replace the front conductive layer and silicon nitride antireflective layer, TCO has passivation issues. Current environments have increasingly higher requirements for battery efficiency, which facilitates further reduction of levelized cost of electricity (LCO). This patent mainly focuses on thinning the front silicon nitride, retaining only the passivation function and providing an H passivation source. A localized Poly / SiO2 passivation layer is added to the front side, which improves the passivation effect and reduces metal recombination. On the other hand, the localized Poly can avoid the absorption of light by the Poly layer, preventing a significant drop in Isc. Metal dots are printed on the localized Poly to replace metal grid lines, which greatly reduces costs. Finally, a layer of TCO is deposited on the front side to form an antireflective layer and a conductive layer, solving the lateral transport problem.

[0063] In some specific implementations, the battery thickness can be freely selected, and more specifically as follows:

[0064] Specific Implementation Scheme 1: An N-type silicon wafer is used, with laser-drilled holes of 100 μm in diameter and a hole spacing of 5 mm. The thickness of the tunnel oxide (SiO2) layers on both the front and back sides is controlled to 1 nm, while the thickness of both the P-Poly and N-Poly layers is 100 nm. In the front passivation stack, the aluminum oxide layer is 3 nm thick, and the silicon nitride layer on the back side is 60 nm thick, with a 10 nm silicon nitride layer to reduce absorption loss. The outermost layer is a TCO layer with a thickness of 95 nm, a sheet resistance of 120 Ω / □, and a refractive index of 1.9.

[0065] Specific Implementation Scheme 2: An N-type silicon wafer is used, with a laser-drilled hole diameter of 200 μm and a hole spacing of 15 mm. The thickness of the tunnel oxide (SiO2) layers on both the front and back sides is controlled at 1.5 nm, while the thickness of both the P-Poly and N-Poly layers is 200 nm. In the front passivation stack, the alumina layer is 10 nm thick, the front silicon nitride layer is 30 nm thick, and the back silicon nitride layer is 200 nm thick. The outermost layer is a TCO layer with a thickness of 95 nm, a sheet resistance of 70 Ω / □, and a refractive index of 2.0.

[0066] Specific implementation scheme 3: An N-type silicon wafer is used, with a laser-drilled hole diameter of 300μm and a hole spacing of 30mm. The tunnel oxide layer is 2nm thick, the poly layer is 300nm thick, the alumina layer is 120nm thick, and the back silicon nitride layer is 200nm thick. The TCO layer has a thickness of 120nm and a low sheet resistance of 20Ω / □.

[0067] Furthermore, this disclosure proposes a low-cost method for producing back-contact batteries. This method utilizes an upgraded existing Topcon production line, employing a synergistic design of a localized poly passivation structure and a TCO conductive layer to ensure high open-circuit voltage while significantly reducing silver paste consumption. The specific steps are as follows:

[0068] S1: Double-sided polishing of N-type silicon wafers: removing the surface damage layer to form a polished surface;

[0069] S2: Select one of the polished surfaces as the front side and perform LPCVDPoly-boron diffusion: forming SiO2 / P + -Poly / BSG sandwich structure; SiO2 thickness 1-2 nm; P + Poly thickness is typically 100–300 nm, with a sheet resistance of 40–150 Ω / □; BSG thickness is 30–80 nm.

[0070] S3: The back side is sequentially subjected to BSG removal, alkaline polishing, LPCVDPoly, and phosphorus diffusion; the back side is stripped of the wrap-around plating to form a clean polished surface, and SiO2 / N is formed on the polished back side surface. + -Poly / PSG sandwich structure; SiO2 thickness 1-2 nm; N + Poly thickness is typically 100–300 nm, with a sheet resistance of 10–100 Ω / □; PSG thickness is 50–100 nm.

[0071] S4: Patterning of the front and back sides using green or purple laser: The laser micro-etches the non-patterned areas on the front side to remove SiO2 / P. + -Poly / BSG, the graphic area cannot be discrete; it can be a circle, ellipse, square, polygon, or a combination thereof. Taking a circle as an example, the diameter of a discrete graphic is 100-1000 μm, and the closest distance between the edges of adjacent discrete graphics is 100-1000 μm. The laser performs micro-etching on the non-graphic area on the back side to remove PSG and some N. + -Poly, the remaining part N + - Poly and SiO2, the patterned area consists of fine grids and main grids; BSG is more difficult to remove, so the laser used will have a higher energy density per unit area;

[0072] S5: High-power infrared laser is used to drill holes in the silicon wafer, allowing light to enter from the back and exit from the front; a 1064nm infrared laser is used to form holes in the semi-finished product according to design requirements, with hole diameters ranging from 100um to 300um and hole spacing from 5 to 30mm.

[0073] S6: Post-texturing: Chain-type front-side PSG removal; semi-finished product then enters the main functional alkaline tank for texturing, forming a textured surface in the laser-treated area on the front side, and removing the N-plated coating in the non-laser-treated area. + -Poly, the back laser area removes the remaining N. + - Poly, the non-laser area is protected by SiO2, and the damage caused by the laser inside the hole is corroded away by the alkaline solution; then it enters the water tank for cleaning, etc., and then the hydrofluoric acid tank removes the BSG in the front non-laser area and the SiO2 tunneling layer in the back non-laser area.

[0074] S7: Alumina film coating: Double-sided alumina coating, thickness 3nm~20nm, preferably 5nm:

[0075] S8: Silicon nitride layer: 60-200 nm silicon nitride on the back side; 10-30 nm silicon nitride on the front side; aluminum oxide and silicon nitride films are also deposited inside the holes.

[0076] S9: Printing: Back side with N + -The poly area is printed with silver grid lines, using high-temperature silver paste; the front side has P... + - The wet weight of the printed silver dots in the poly zone is 4-10 mg, and the wet weight of the silver paste on the front side will be reduced by more than 80%; during sintering, the silver paste and the poly zone form an ohmic contact.

[0077] S10: Low-temperature silver paste is printed on the back hole plugging position. The advantage of using low-temperature silver paste instead of high-temperature silver paste is that it avoids the passivation layer inside the hole being burned through by high temperature and avoids leakage inside the hole.

[0078] S11: A TCO layer is deposited on the front side of the battery using PVD or RPD equipment. The sheet resistance of the TCO film is 20-120 Ω / □. The silver dots on the front side are connected to the silver plugs. The TCO has a refractive index of 1.9-2.1 and a thickness of 70-120 nm, which serves as an anti-reflection agent. The material can be ITO, AZO, IWO, etc.

[0079] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0080] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A low-cost back-contact battery, characterized in that, The battery includes: An N-type silicon wafer has a front side and a back side. The N-type silicon wafer has a through hole that extends from the back side to the front side, and a silver plug is placed inside the through hole. A portion of the front side of the N-type silicon wafer is sequentially stacked with a first tunnel oxide layer and a P-type silicon wafer. + -Poly layer; the P + -A silver dot is positioned above the Poly layer; The N-type silicon wafer back surface partial region is sequentially stacked with a second tunnel oxide layer and N + -Poly layer; The N + The surface of the Poly layer is provided with back silver; The N-type silicon wafer has a first passivation layer on the surface of the area without front silver dots and back silver dots and the cover through-hole. The first passivation layer consists of an aluminum oxide film and a silicon nitride layer from the inside out. The N-type silicon wafer has a TCO layer covering the surface of the silicon nitride layer on the front side, which connects the front silver dots to the via silver plugs.

2. The low-cost back-contact battery according to claim 1, characterized in that, The diameter of the through holes is 100um to 300um, and the spacing between the holes is 5 to 30mm.

3. The low-cost back-contact battery according to claim 1, characterized in that, The thickness of the alumina layer is 3nm to 20nm.

4. The low-cost back-contact battery according to claim 1, characterized in that, The thickness of silicon nitride on the back side of the N-type silicon wafer is 60–200 nm; the thickness of silicon nitride on the front side of the N-type silicon wafer is 10–30 nm.

5. The low-cost back-contact battery according to claim 1, characterized in that, The TCO layer has a sheet resistance of 20–120 Ω / □, a TCO refractive index of 1.9–2.1, and a thickness of 70–120 nm.

6. A low-cost back-contact battery according to claim 1, characterized in that, The N-type silicon wafer is provided with a local passivation region and a non-passivation region on the front surface, the local passivation region is a polished surface and is provided with the P + -Poly layer, and the non-passivation region is a textured surface.

7. A method for manufacturing a low-cost back-contact battery according to any one of claims 1-6, characterized in that, Includes the following steps: S1. Polish the N-type silicon wafer on both sides; S2, form a first tunnel oxide layer on the front surface of the N-type silicon wafer, P + -Poly layer and BSG layer, form a second tunnel oxide layer on the back surface, N + -Poly layer and PSG layer; S3. Use a laser to perform patterned micro-etching on the front and back poly layers, where the front side retains discretely distributed patterned areas. S4. Use an infrared laser to drill holes in the silicon wafer to form through holes; S5. By treating with an alkaline solution, a textured surface is formed on the front laser etching area, and the damaged layer and the surrounding coating are removed. S6. Deposit a first passivation stack on the front and back sides of the battery, wherein the first passivation stack extends to the inner wall of the through hole; S7, on the back N + -The poly area is printed with silver on the back, and on the front P + Discrete front-side silver dots are printed at the corresponding positions in the Poly region, and sintering allows the silver dots to penetrate the passivation layer and P. + -The poly layer forms an ohmic contact; S8. Fill the through hole with silver plugging material; S9. Deposit a TCO layer on the front side of the battery, wherein the TCO layer covers the front silver dots and is connected to the plugging silver.

8. A method for manufacturing a low-cost back-contact battery according to claim 7, characterized in that, In step S8, low-temperature silver paste is used to plug the holes, and the curing temperature of the low-temperature silver paste is lower than the sintering temperature in step S7.

9. The manufacturing method according to claim 7, characterized in that, Step S9 involves depositing a TCO layer using PVD or RPD processes. The material of the TCO layer includes any one of ITO, AZO, or IWO.

10. A photovoltaic module, characterized in that, include: A cover plate, a back plate, and a battery string disposed between the cover plate and the back plate, the battery string being composed of a plurality of low-cost back-contact battery electrical connections as described in any one of claims 1-6.

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