Solar cell and preparation method thereof, photovoltaic module

Abstract

This disclosure relates to the photovoltaic field, and particularly to a solar cell, a method for fabricating the same, and a photovoltaic module. The solar cell includes: a substrate, at least one side of which has a doped conductive region; an electrode electrically connected to the doped conductive region; wherein the electrode includes: a blocking portion electrically connected to the doped conductive region; an attachment portion located on the side of the blocking portion away from the substrate; a conductive portion located on the side of the attachment portion away from the substrate; and a main body portion located on the side of the conductive portion away from the substrate. This disclosure can at least improve the electrical performance and reliability of the solar cell.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a solar cell and its preparation method, and a photovoltaic module. Background Technology

[0002] With the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. Solar cells utilize the photovoltaic principle to generate photogenerated carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy. Electrodes typically include a main grid and a sub-grid. The sub-grid is primarily used to collect photogenerated carriers, while the main grid is mainly used to extract the photogenerated carriers collected by the sub-grid.

[0003] In the electrode fabrication process, it is necessary to control the formation of the electrode on a localized surface of the solar cell. The conventional method is to screen-print a silver-coated paste and then sinter it at high temperature to form the electrode. However, silver has a high unit price, and the resistivity of the electrode has a significant impact on the photoelectric conversion efficiency of the solar cell, resulting in a high amount of silver used in the electrode, which restricts further cost reduction. Summary of the Invention

[0004] This disclosure provides a solar cell and its preparation method, as well as a photovoltaic module, which can at least improve the electrical performance and reliability of the solar cell.

[0005] This disclosure provides a solar cell, comprising: a substrate having a doped conductive region on at least one side; an electrode electrically connected to the doped conductive region; wherein the electrode includes: a blocking portion electrically connected to the doped conductive region; an attachment portion located on the side of the blocking portion away from the substrate; a conductive portion located on the side of the attachment portion away from the substrate; and a main body portion located on the side of the conductive portion away from the substrate.

[0006] Optionally, the material of the blocking part is aluminum oxide or titanium nitride.

[0007] Optionally, the material of the attachment portion is nickel or a copper-nickel alloy.

[0008] Optionally, when the material of the attachment is a copper-nickel alloy, the mass percentage of nickel in the attachment is 5% to 20%.

[0009] Optionally, the thickness of the attachment portion is greater than the thickness of the blocking portion.

[0010] Optionally, the thickness of the blocking portion is 2nm to 5nm.

[0011] Optionally, the thickness of the attachment portion is 95nm~105nm.

[0012] Optionally, the conductive part is a network structure composed of conductive nanowires.

[0013] Optionally, the diameter of the conductive nanowire is 10 nm to 50 nm.

[0014] Optionally, the mesh porosity of the network structure is 60% to 90%.

[0015] Optionally, the thickness of the main body is 5μm to 10μm.

[0016] This disclosure also provides a method for fabricating a solar cell, comprising: providing a substrate having a doped conductive region on at least one side; forming an electrode on the surface of the doped conductive region, the electrode being electrically connected to the doped conductive region; wherein forming the electrode comprises: forming a blocking portion on the surface of the doped conductive region, the blocking portion being electrically connected to the doped conductive region; forming an attachment portion on the surface of the blocking portion; forming a conductive portion on the surface of the attachment portion; and forming a main body portion on the surface of the conductive portion.

[0017] Optionally, forming a barrier portion on the surface of the doped conductive region includes: performing image processing on the surface of the doped conductive region to obtain a groove region; and forming the barrier portion in the groove region using a first deposition process.

[0018] Optionally, the process parameters of the first deposition process include: a process temperature of 140°C to 160°C, and a precursor of trimethylaluminum and an aqueous solution.

[0019] Optionally, forming the main body on the surface of the conductive part includes: forming the main body on the surface of the conductive part using a pulse electroplating process, wherein the process parameters of the pulse electroplating process include: a current density of 1ASD to 10ASD and a current pulse duty cycle of 10% to 50%.

[0020] This disclosure also provides a photovoltaic module, comprising: a battery string, which is composed of a plurality of solar cells connected as described above, or a battery string composed of solar cells prepared by the method described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film away from the battery string.

[0021] The technical solution provided in this disclosure has at least the following advantages: The solar cell disclosed herein includes an electrode comprising a blocking portion, an attachment portion, a conductive portion, and a main body portion arranged sequentially along a direction away from the substrate. The blocking portion directly contacts the doped conductive region, effectively establishing a stable electrical connection. The attachment portion is located above the blocking portion, helping to enhance the bonding strength between the electrode as a whole and the substrate. The conductive portion is disposed on the side of the attachment portion away from the substrate, providing a path for current conduction between the main body portion and the blocking portion. This disclosure not only optimizes the interface characteristics between the electrode and the doped conductive region but also improves current conduction efficiency and structural stability, thereby improving the overall electrical performance and reliability of the solar cell. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figure 1 This is a partial structural schematic diagram of a solar cell provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another partial structure of a solar cell provided in an embodiment of this disclosure; Figure 3 This is a top view of the conductive part provided in an embodiment of the present disclosure; Figure 4 A schematic flowchart illustrating the method for fabricating a solar cell according to an embodiment of this disclosure; Figure 5 A schematic diagram of the substrate structure in the method for fabricating a solar cell provided in this disclosure embodiment; Figure 6 This is a schematic flowchart of step S2 in the method for preparing a solar cell provided in this embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure after image processing on the surface of the doped conductive region in the method for fabricating a solar cell provided in this embodiment of the present disclosure; Figure 8 In order to be in Figure 7 A schematic diagram of the structure after the blocking part is formed on the structure shown; Figure 9 In order to be in Figure 8 A schematic diagram of the structure after the attachment portion is formed on the structure shown; Figure 10 In order to be in Figure 9 A schematic diagram of the structure after the conductive part is formed on the structure shown; Figure 11 In order to be in Figure 10 A schematic diagram of the structure after the main body is formed on the shown structure; Figure 12 This is a partial three-dimensional structural diagram of a photovoltaic module provided in an embodiment of the present disclosure; Figure 13 for Figure 12 A schematic diagram of a cross-sectional structure along the cross-sectional direction NN1.

[0024] Explanation of reference numerals in the attached figures: Substrate 10, electrode 11, barrier portion 111, doped conductive region 101, first sub-doped conductive region 1011, second sub-doped conductive region 1012, tunneling layer 2, first passivation layer 4, first electrode 12, second electrode 13, second passivation layer 6, conductive portion 113, attachment portion 112, main body portion 114, groove region I, solar cell 100, encapsulating film 201, cover plate 202, conductive strip 203. Detailed Implementation

[0025] Currently, tunnel oxide passivated contact (TOPCon) solar cells have become the next-generation mainstream photovoltaic technology due to their high conversion efficiency and good compatibility with existing production lines. However, their metallization process heavily relies on expensive silver paste, which limits further cost reduction. Therefore, copper electroplating technology is considered a key path to replace silver paste. However, although copper is low in cost and has good conductivity, its atoms easily diffuse into the silicon substrate, forming recombination centers, leading to cell performance degradation. At the same time, the doped conductive region of TOPCon is usually a polycrystalline silicon thin film with a dense and hydrophobic surface. Directly depositing a metal layer on it easily leads to poor wetting and uneven nucleation, resulting in problems such as weak adhesion and interface porosity.

[0026] To address these issues, those skilled in the art have introduced a barrier material, such as nickel, between the doped conductive region and the copper layer to suppress copper diffusion and improve contact. However, direct electroplating or electroless plating on polycrystalline silicon results in poor wettability of the plating solution due to the hydrophobicity of the polycrystalline silicon surface, leading to porosity and weak adhesion. Furthermore, ensuring a strong bond between the seed layer and the silicon substrate, and between the seed layer and the subsequently electroplated copper layer, without sacrificing conductivity, remains a significant challenge.

[0027] To address the aforementioned issues, this disclosure creatively proposes a stacked electrode structure comprising a barrier portion, an attachment portion, a conductive portion, and a main body portion arranged sequentially along a direction away from the substrate. The barrier portion directly contacts the doped conductive region, effectively establishing a stable electrical connection. The attachment portion is located above the barrier portion, enhancing the bonding strength between the electrode as a whole and the substrate. The conductive portion is disposed on the side of the attachment portion away from the substrate, providing a pathway for current conduction between the main body portion and the barrier portion. This disclosure not only optimizes the interface characteristics between the electrode and the doped conductive region but also improves current conduction efficiency and structural stability, thereby enhancing the overall electrical performance and reliability of the solar cell.

[0028] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0031] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0032] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0033] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when describing a component on the surface of another component, or a component "directly" on another component, or a component surface on which another component is formed or disposed, it indicates that there is no intermediate component between the two components. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0034] In the description of the embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. The formation or placement of a second component above or on a first component, or on the surface of a first component, or on one side of a first component, may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be placed between the first and second components, thereby preventing direct contact between the first and second components. For simplicity and clarity, various components may be drawn at different scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, the formation or placement of a second component on the surface of a first component refers to direct contact between the first and second components. The term "component" can refer to a layer, film, region, portion, structure, etc.

[0035] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] Figure 1 This is a partial structural schematic diagram of a solar cell provided in an embodiment of this disclosure.

[0038] refer to Figure 1 This disclosure provides a solar cell, including a substrate 10 and an electrode 11.

[0039] At least one side of the substrate 10 has a doped conductive region 101; an electrode 11 is electrically connected to the doped conductive region 101; wherein the electrode 11 includes: a blocking portion 111, which is electrically connected to the doped conductive region 101; an attachment portion 112, which is located on the side of the blocking portion 111 away from the substrate 10; a conductive portion 113, which is located on the side of the attachment portion 112 away from the substrate 10; and a main body portion 114, which is located on the side of the conductive portion 113 away from the substrate 10.

[0040] The substrate 10 is used to receive light and generate photogenerated carriers. In some embodiments, the substrate 10 may be a semiconductor substrate.

[0041] In some embodiments, the material of the substrate 10 may be an elemental semiconductor material. The elemental semiconductor material may be composed of a single element, such as silicon or germanium. The elemental semiconductor material may be in a single-crystal state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state simultaneously possessing both single-crystal and amorphous states is called a microcrystalline state). For example, silicon may be at least one of single-crystal silicon, polycrystalline silicon, amorphous silicon, and microcrystalline silicon.

[0042] In some embodiments, the substrate 10 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc.

[0043] The substrate 10 can also be a sapphire substrate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0044] The substrate 10 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0045] The substrate 10 has a front side and a back side. In some embodiments, the solar cell is a single-sided cell, in which case the front side of the substrate can serve as the light-receiving surface for receiving incident light, and the back side serves as the back-lighting surface. In some embodiments, the solar cell is a bifacial cell, in which case both the front side and the back side of the substrate can serve as light-receiving surfaces and can both be used to receive incident light. It is understood that the back-lighting surface referred to in the embodiments of this disclosure can also receive incident light, but the degree of reception of incident light is weaker than that of the light-receiving surface, and therefore it is defined as a back-lighting surface.

[0046] In some embodiments, a texturing process can be performed on at least one of the front or back surfaces of the substrate 10 to form a textured surface on at least one of the front or back surfaces of the substrate 10. This can enhance the absorption and utilization efficiency of incident light on the front and back surfaces of the substrate 10. In some embodiments, the textured surface can be a pyramid textured surface. As a common textured surface, pyramid textured surface not only reduces the reflectivity of the substrate surface but also forms light traps, enhancing the absorption effect of the substrate on incident light and improving the photoelectric conversion efficiency of the solar cell.

[0047] Specifically, if the solar cell is a single-sided cell, a textured surface, such as a pyramidal textured surface, can be formed on the light-receiving surface of the substrate 10, while the back-lighting surface of the substrate can be a polished surface, meaning the back-lighting surface of the substrate is flatter than the light-receiving surface. It should be noted that for single-sided cells, a textured surface can also be formed on both the light-receiving and back-lighting surfaces of the substrate.

[0048] If the solar cell is a bifacial cell, a textured surface can be formed on both the light-receiving side and the back-lighting side of the substrate 10.

[0049] Solar cells can be one or any combination of BC (Back Contact) cells, PERC (Passivated Emitter Rear Cell) cells, TOPCON cells, heterojunction cells, thin-film solar cells, and tandem cells. Thin-film solar cells include, but are not limited to, perovskite thin-film solar cells, copper indium selenide (CIGS) thin-film solar cells, gallium arsenide (GaAs) thin-film solar cells, and cadmium sulfide (CdS) thin-film solar cells. Tandem cells include, but are not limited to, perovskite cells stacked with crystalline silicon cells, perovskite cells stacked with perovskite cells, and perovskite cells stacked with thin-film cells.

[0050] If the solar cell is a TOPCON cell, then both sides of the substrate have doped conductive regions; if the solar cell is a BC cell, then the back side of the substrate has doped conductive regions.

[0051] refer to Figure 2 The following explanation uses TOPCON solar cells as an example.

[0052] The doped conductive region 101 includes a first sub-doped conductive region 1011 and a second sub-doped conductive region 1012. The first sub-doped conductive region is located on the back side of the substrate 10, and the second sub-doped conductive region 1012 is located on the front side of the substrate 10.

[0053] In some embodiments, the solar cell includes a passivated contact structure located on the back side of the substrate 10. The passivated contact structure can form band bending on the back side of the substrate 10 to achieve selective transport of charge carriers.

[0054] The passivated contact structure includes a tunneling layer 2 and a first sub-doped conductive region 1011. The tunneling layer 2 is located on the back side of the substrate 10, and the first sub-doped conductive region 1011 is located on the surface of the tunneling layer 2.

[0055] The dopant concentration in the first sub-doped conductive region 1011 is higher than that in the substrate 10, creating a sufficiently high potential barrier on the back side of the substrate. This barrier induces band bending on the back side of the substrate, enabling the aggregation of majority carriers and the depletion of minority carriers, thus reducing carrier recombination. The tunneling layer 2 causes an asymmetric shift in the energy band on the back side of the substrate 10, making the barrier for majority carriers lower than that for minority carriers. Therefore, majority carriers can easily tunnel through the tunneling layer 2 to the first sub-doped conductive region 1011, while minority carriers have difficulty passing through the tunneling layer 2, achieving selective carrier transport. Furthermore, the tunneling layer 2 also provides chemical passivation. Specifically, due to the presence of interface state defects at the interface between the substrate 10 and the tunneling layer 2, the interface state density on the back side of the substrate 10 is relatively large. The increase in interface state density will promote the recombination of photogenerated carriers, reduce the fill factor, short-circuit current and open-circuit voltage of the solar cell, and thus result in a lower photoelectric conversion efficiency of the solar cell.

[0056] The tunneling layer 2 is located on the back side of the substrate 10, so that the tunneling layer 2 has a chemical passivation effect on the back side of the substrate 10. Specifically, by saturating the dangling bonds on the back side of the substrate 10, the defect state density on the back side of the substrate 10 is reduced, and the recombination centers on the surface of the substrate 10 are reduced, thereby reducing the carrier recombination rate.

[0057] In some embodiments, the material of the tunneling layer 2 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0058] The first sub-doped conductive region 1011 also serves as a field passivation effect. Specifically, the first sub-doped conductive region 1011 forms an electrostatic field pointing towards the interior of the substrate 10 on the back side of the substrate 10, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and decreasing the carrier recombination rate at the interface of the substrate 10. This, in turn, increases the open-circuit voltage, short-circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0059] The material of the first sub-doped conductive region 1011 may include at least one of amorphous silicon, polycrystalline silicon, or silicon carbide.

[0060] The first sub-doped conductive region 1011 may be doped with doping elements of the same type as the substrate 10. For example, if the doping element type of the substrate is P-type, then the doping element type in the first sub-doped conductive region 1011 may also be P-type; if the doping element type of the substrate is N-type, then the doping element type in the first sub-doped conductive region 1011 may also be N-type.

[0061] Therefore, the passivated contact structure provides good surface passivation for the back side of the substrate. The tunneling oxide layer allows majority carriers to tunnel into the first sub-doped conductive region 1011 while blocking minority carrier recombination. This allows majority carriers to be laterally transported in the first sub-doped conductive region 1011 and collected by the metal electrode, thereby greatly reducing the metal contact recombination current and improving the open-circuit voltage and short-circuit current of the solar cell.

[0062] The solar cell may also include a first passivation layer 4, which covers the surface of the first sub-doped conductive region 1011 away from the substrate 10. The first passivation layer 4 can provide good passivation for the back side of the substrate 10, for example, it can effectively chemically passivate the dangling bonds on the back side of the substrate 10, saturate the dangling bonds on the back side of the substrate, reduce the defect state density on the back side of the substrate 10, and suppress carrier recombination on the back side of the substrate 10.

[0063] The material of the first passivation layer 4 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0064] The first passivation layer can be a single-layer structure or a multi-layer structure. For a multi-layer structure, the materials of different layers can be different from each other, or some layers can be made of the same material but different from the materials of other layers. For example, the first passivation layer can be a multi-layer structure of silicon nitride and aluminum oxide layers.

[0065] Electrode 11 includes a first electrode 12 and a second electrode 13.

[0066] Multiple first electrodes 12 are arranged at intervals along the first direction X.

[0067] In some embodiments, a plurality of first electrodes 12 are located on the surface of the first passivation layer 4 and form an ohmic contact with the first sub-doped conductive region 1011.

[0068] In some embodiments, a plurality of first electrodes 12 are located on the surface of the first sub-doped conductive region 1011 and form an ohmic contact with the first sub-doped conductive region 1011.

[0069] The majority carriers in the substrate 10 tunnel through the tunneling layer 2 to the first sub-doped conductive region 1011. The majority carriers in the first sub-doped conductive region 1011 are then transported to the first electrode 12, which is in electrical contact with the first sub-doped conductive region 1011, and are collected by the first electrode 12.

[0070] The portion of the first sub-doped conductive region 1011 that is in contact with the metal electrode is typically defined as the electrode region, and the portion of the first sub-doped conductive region 1011 that is not in contact with the metal electrode is typically defined as the non-electrode region.

[0071] In some embodiments, the doping concentration in the electrode region is greater than that in the non-electrode region. This results in a lower sheet resistance in the electrode region compared to the non-electrode region. The first electrode makes electrical contact with the electrode region. Because the sheet resistance of the electrode region is lower, the contact resistance between the first electrode and the electrode region is also lower, enabling a better ohmic contact. This reduces metal-to-metal recombination between the first electrode and the electrode region, which is beneficial for improving the first electrode's ability to collect charge carriers.

[0072] The lower concentration of doped elements in the non-electrode region results in a weaker parasitic absorption capacity of the non-electrode region for incident light. This reduces the parasitic absorption of incident light by the doped conductive layer in the non-electrode region and improves the absorption and utilization rate of the substrate for incident light.

[0073] The second sub-doped conductive region 1012 is located within the substrate 10, and at least a portion of the surface of the substrate 10 serves as the top surface of the second sub-doped conductive region 1012.

[0074] In some embodiments, a portion of the substrate 10 surface serves as the top surface of the second sub-doped conductive region 1012 to form a selective emitter.

[0075] In some embodiments, the entire surface of the substrate 10 serves as the top surface of the second sub-doped conductive region 1012.

[0076] The doping element type of the second sub-doped conductive region 1012 is opposite to that of the substrate 10, and it forms a PN junction with the substrate 10. In some embodiments, the material of the second sub-doped conductive region 1012 is the same as that of the substrate 10.

[0077] The solar cell may also include a second passivation layer 6. The second passivation layer 6 is located on the surface of the second sub-doped conductive region 1012 away from the substrate 10, providing good passivation for the front side of the substrate 10, reducing the defect state density on the front side of the substrate 10, and effectively suppressing carrier recombination on the front side of the substrate 10. The second passivation layer 6 also provides good anti-reflection, reducing the reflection of incident light from the front side of the substrate 10 and improving the utilization rate of incident light by the substrate 10.

[0078] The material of the second passivation layer 6 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0079] In some embodiments, the second passivation layer 6 may be a single-layer structure. In some embodiments, the second passivation layer 6 may also be a multilayer structure, wherein the materials of each layer in the multilayer structure may be different from each other, or, a portion of the layers may be made of different materials, while the remaining portion may be made of the same material. For example, the second passivation layer 6 may be a multilayer structure of silicon nitride and aluminum oxide layers.

[0080] A plurality of second electrodes 13 are arranged at intervals along a first direction X, and each of the plurality of second electrodes 13 extends along a second direction Y.

[0081] In some embodiments, the second electrode 13 is located on the surface of the second sub-doped conductive region 1012 and is in electrical contact with the second sub-doped conductive region 1012.

[0082] In other embodiments, the second electrode 13 is located on the surface of the second passivation layer 6 and is in electrical contact with the second sub-doped conductive region 1012.

[0083] It should be noted that the electrical connection between the two actually means that both are made of conductive materials and are directly connected or connected through other conductive materials. Therefore, when the photovoltaic cell is generating electricity, there is an electrical connection between the two.

[0084] The solar cell disclosed herein includes an electrode comprising a blocking portion, an attachment portion, a conductive portion, and a main body portion arranged sequentially along a direction away from the substrate. The blocking portion directly contacts the doped conductive region, effectively establishing a stable electrical connection. The attachment portion is located above the blocking portion, helping to enhance the bonding strength between the electrode as a whole and the substrate. The conductive portion is disposed on the side of the attachment portion away from the substrate, providing a path for current conduction between the main body portion and the blocking portion. This disclosure not only optimizes the interface characteristics between the electrode and the doped conductive region but also improves current conduction efficiency and structural stability, thereby improving the overall electrical performance and reliability of the solar cell.

[0085] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0086] In some embodiments, the density of the blocking portion 111 is greater than the density of the attaching portion 112.

[0087] In thin film or coating technology, density refers to the concentration of microscopic defects such as pores, voids, and grain boundaries within a material. Higher density results in a denser structure, fewer pores, and a more continuous atomic arrangement. Since the barrier portion 111 is in direct contact with the doped conductive region 101 on the silicon substrate 10, its core function is to effectively block the diffusion of upper-layer metal atoms into the silicon substrate. High density significantly reduces through-hole defect channels, thereby enhancing the barrier capability. Therefore, the barrier portion 111 is designed with a higher density structure to ensure effective blocking of diffusing metal atoms into the silicon substrate.

[0088] In some embodiments, the material of the blocking portion 111 is aluminum oxide or titanium nitride.

[0089] Both aluminum oxide and titanium nitride can form highly dense, pinhole-free thin film structures through atomic layer deposition, sputtering, and other processes. This effectively blocks the diffusion of copper atoms into the silicon substrate during subsequent processes, thereby effectively preventing the formation of highly reactive defects by copper atoms in the silicon substrate and avoiding the resulting loss of battery efficiency.

[0090] Among them, aluminum oxide not only has excellent diffusion blocking ability, but also provides good chemical passivation effect due to its internal fixed negative charge and saturation effect on silicon surface dangling bonds, further reducing the interfacial recombination rate and improving the open circuit voltage and conversion efficiency of the battery; while titanium nitride provides reliable blocking function and has high conductivity, which is beneficial to reducing contact resistance.

[0091] In some embodiments, the material of the attachment portion 112 is nickel or a copper-nickel alloy.

[0092] It is understandable that nickel exhibits good interfacial compatibility with the doped conductive region 101 on the silicon substrate 10, enabling the formation of an ohmic connection with low contact resistance under appropriate process conditions, while significantly enhancing the bonding strength between the electrode 11 and the substrate 10. Using a copper-nickel alloy as the material for the attachment portion 112 can improve material compatibility with the upper body portion 114 while maintaining good adhesion performance, which is beneficial for subsequent electroplating processes. Therefore, selecting nickel or a copper-nickel alloy helps to achieve reliable interfacial electrical connections and mechanical stability in the multilayer electrode 11 structure.

[0093] In some embodiments, when the material of the attachment portion 112 is a copper-nickel alloy, the mass percentage of nickel in the attachment portion 112 is 5% to 20%.

[0094] In the attachment portion 112 made of copper-nickel alloy, when the nickel content is not less than 5%, it is sufficient to form an effective metal-silicon interaction at the interface, improve wettability and provide the necessary adhesion strength; while when the nickel content does not exceed 20%, it can avoid a significant increase in resistivity or an increase in material brittleness due to excessive nickel ratio, while also taking into account compatibility with the upper conductive portion 113.

[0095] Within this range, the attachment portion 112 is typically made of copper as the base and nickel as the alloying element. This retains the high conductivity of copper and enhances the interfacial bonding ability with the blocking portion 111 and the substrate 10 through the introduction of nickel. Furthermore, by adjusting the proportion of nickel in the attachment portion 112, the coefficient of thermal expansion can be adjusted, and the adhesion and conductivity can be optimized.

[0096] In some embodiments, the thickness of the attachment portion 112 is greater than the thickness of the blocking portion 111.

[0097] The core function of the blocking part 111 is to block the diffusion of metal atoms. Therefore, as long as the structure of the blocking part 111 achieves a film layer without pinholes and with complete coverage, a relatively thin film layer can achieve effective blocking; an excessively thick film layer may introduce stress, cracking, or increase contact resistance.

[0098] The main function of the attachment portion 112 is to provide mechanical bonding and interfacial compatibility. Therefore, it needs a certain thickness to form a continuous and uniform cover layer, thereby buffering the thermal expansion differences between the upper and lower materials, withstanding the mechanical / chemical stress during subsequent electroplating or lamination processes, and ensuring a good metallurgical bond with the upper conductive portion 113. Therefore, the attachment portion 112 needs to be thicker than the blocking portion 111 to fully exert its structural support and adhesion functions.

[0099] In some embodiments, the thickness of the blocking portion 111 is 2nm to 5nm; for example, 2nm to 3nm, 3nm to 4nm, or 4nm to 5nm.

[0100] In some embodiments, the thickness of the blocking portion 111 can be 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, or 5nm, etc.

[0101] On the one hand, the core function of the blocking part 111 is to block the diffusion of metal atoms. Therefore, as long as the structure of the blocking part 111 achieves a film without pinholes and with complete coverage, a relatively thin film can achieve effective blocking. On the other hand, the blocking part 111 needs to be thin enough to ensure that charge carriers can reach the upper attachment part 112 through the tunneling effect.

[0102] Therefore, limiting the thickness of the blocking portion 111 to 2nm~5nm can satisfy its function of blocking the diffusion of metal atoms, while avoiding the obstruction of carrier transport due to excessive thickness, thus ensuring that an efficient electrical connection is formed between the electrode 11 and the doped conductive region 101.

[0103] In some embodiments, the thickness of the attachment portion 112 is 95nm to 105nm; for example, 95nm to 98nm, 98nm to 102nm, or 102nm to 105nm.

[0104] In some embodiments, the thickness of the attachment portion 112 can be 95nm, 96nm, 97nm, 98nm, 99nm, 100nm, 101nm, 102nm, 103nm, 104nm, or 105nm, etc.

[0105] The thickness of the attachment portion 112 is in the range of 95nm to 105nm, which can ensure that the attachment portion 112 has strong adhesion and good conductivity.

[0106] refer to Figure 3In some embodiments, the conductive part 113 is a network structure composed of conductive nanowires.

[0107] In some embodiments, the conductive portion 113 is not a continuous and dense thin film, but a mesh structure composed of interconnected conductive paths, which ensures current conduction capability while also being lightweight, having high bonding strength and excellent mechanical stability.

[0108] Nanowires themselves possess excellent conductivity, and the network structure they form can construct efficient current transmission channels. At the same time, the gaps in the network structure and the relative slippage between nanowires can effectively absorb deformation caused by thermal cycling or mechanical stress, thereby improving the structural reliability of the electrode.

[0109] In some embodiments, the nanowires may be silver nanowires, copper nanowires, or doped metal oxide nanowires.

[0110] In some embodiments, the diameter of the conductive nanowire is 10 nm to 50 nm; for example, 10 nm to 15 nm, 15 nm to 35 nm, or 35 nm to 50 nm.

[0111] In some embodiments, the diameter of the conductive nanowire can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, or 50nm.

[0112] In the electrode 11 structure disclosed herein, the conductive portion 113 is located above the attachment portion 112 and below the main body portion 114. It needs to ensure good electrical contact with the lower attachment portion 112 and provide a uniform and stable nucleation substrate for the upper main body portion 114. If the diameter of the conductive nanowire is less than 10 nm, the nanowire is too thin, and its surface atomic ratio increases significantly. It is prone to oxidation, agglomeration, or even melting during subsequent heat treatment or electroplating, resulting in poor structural stability. At the same time, the small number of contact points and small contact area in the randomly stacked network of excessively thin nanowires leads to a higher overall resistance. Conversely, if the diameter of the nanowire exceeds 50 nm, the nanowire is too thick, which will significantly increase the surface roughness of the electrode 11. Under subsequent lamination or mechanical stress, it may cause local stress concentration, affecting the reliability of interlayer bonding. In addition, the larger the diameter of the nanowire, the smaller the specific surface area per unit mass, which weakens the advantages of the nanowire network structure in terms of interface anchoring and stress buffering. Therefore, controlling the diameter of nanowires within the range of 10nm to 50nm can achieve a good balance between conductivity, structural stability, specific surface area and surface morphology. This is beneficial for forming a uniform and interconnected conductive network, and can also ensure reliable interfacial bonding between the upper and lower layers.

[0113] In some embodiments, the mesh porosity of the network structure is 60% to 90%; for example, 60% to 70%, 70% to 80%, or 80% to 90%.

[0114] In some embodiments, the mesh porosity of the network structure can be 60%, 65%, 70%, 75%, 80%, 85%, or 90%, etc.

[0115] It should be noted that porosity refers to the percentage of void volume in a material to its total volume. The mesh porosity of the network structure refers to the proportion of space not occupied by conductive material in the network structure of the conductive part 113; for example, a mesh porosity of 80% means that 80% of the entire conductive part 113 is void and 20% is conductive nanowires.

[0116] In some embodiments, the network structure of the conductive portion 113 has a high porosity of 60% to 90%. On the one hand, high porosity means less conductive material is used, which can significantly reduce material costs. On the other hand, the high-porosity structure provides numerous channels for the upper body portion 114, allowing metal ions to penetrate deeply, encapsulate the nanowires, and form a strong anchoring bond. If the porosity is too low, the network is too dense, making it difficult for the upper material to wet the interior, easily leading to poor adhesion or interface delamination. Furthermore, the numerous voids can act as stress buffers, effectively absorbing deformation during thermal cycling or mechanical bending and preventing the electrode 11 from cracking.

[0117] It should be noted that despite the high porosity, as long as the nanowires are fully interwoven and there are enough contact points, a continuous conductive path can still be formed.

[0118] If the porosity exceeds 90%, the nanowire density is too low, resulting in insufficient contact points and potentially discontinuous conductive networks, leading to increased resistance or even open circuits. If it falls below 60%, the material usage increases, raising costs and simultaneously reducing permeability and flexibility. Therefore, a porosity of 60%–90% strikes a good balance between conductivity, cost, processability, and reliability.

[0119] In some embodiments, the main body 114 contains copper, which may be copper or a copper alloy.

[0120] In the electrode 11 of the solar cell, the main body 114 is located on the outermost layer and serves as the main current collection and transmission channel, directly contacting the solder ribbon, conductive adhesive, or stringing equipment. Copper has excellent conductivity and its cost is much lower than that of silver. Therefore, introducing copper into the main body 114 is beneficial for achieving high conductivity and low-cost metallization.

[0121] In some embodiments, the thickness of the main body 114 is 5μm to 10μm; for example, 5μm to 6μm, 6μm to 8μm, or 8μm to 10μm.

[0122] In some embodiments, the thickness of the main body 114 can be 5μm, 6μm, 7μm, 8μm, 9μm or 10μm, etc.

[0123] It should be noted that the thickness of the main body 114 is not less than 5μm, which can ensure sufficient current-carrying cross-sectional area and effectively reduce resistance loss; at the same time, it meets the requirements of string welding or crimping processes, avoiding burn-through or deformation during welding due to excessive thinness; in addition, a certain thickness can also improve corrosion resistance and oxidation resistance, ensuring the reliability of the battery in long-term outdoor use.

[0124] A thickness of no more than 10μm can avoid material waste and increased costs. At the same time, a thicker metal layer has a larger difference in thermal expansion coefficient with the silicon substrate 10, which can easily lead to stress accumulation, causing cell warping or electrode 11 delamination. In addition, excessive thickness may also affect the adhesion between the cell and the encapsulation film during module lamination, reducing the encapsulation yield.

[0125] Therefore, the thickness of the main body 114 is in the range of 5μm to 10μm, which can achieve a good balance between conductivity, mechanical strength, process compatibility and cost control.

[0126] In some embodiments, the sheet resistance of the conductive part 113 is less than 10 Ω / sq.

[0127] It should be noted that sheet resistance is an indicator of the lateral conductivity of the conductive part 113.

[0128] When a solar cell is operating, the photocurrent needs to be transversely transmitted within electrode 11 to the main grid or solder joints. If the sheet resistance of the conductive part 113 is too high, significant Joule heat loss will occur, reducing the fill factor and conversion efficiency. A sheet resistance of less than 10 Ω / sq is a reasonable level for high-performance thin-film electrodes, effectively supporting fine grid designs and reducing transmission losses.

[0129] In some embodiments, the conductive part 113 employs a discontinuous structure such as a nanowire network. Its conductivity is highly dependent on the overlap density and contact quality between the nanowires. A sheet resistance of less than 10 Ω / sq indicates that the network structure has formed a good flow path, the contact resistance is controllable, and the overall conductivity meets the requirements.

[0130] In addition, a lower sheet resistance can reduce the conductive burden on the upper body 114 and improve the overall robustness of the electrode 11.

[0131] In some embodiments, the contact resistivity between the electrode 11 and the doped conductive region 101 is 0.2 mΩ·cm² to 0.5 mΩ·cm²; for example, 0.2 mΩ·cm² to 0.3 mΩ·cm², 0.3 mΩ·cm² to 0.4 mΩ·cm², or 0.4 mΩ·cm² to 0.5 mΩ·cm², etc.

[0132] In some embodiments, the contact resistivity between the electrode 11 and the doped conductive region 101 can be 0.2 mΩ·cm², 0.25 mΩ·cm², 0.3 mΩ·cm², 0.35 mΩ·cm², 0.4 mΩ·cm², 0.45 mΩ·cm², or 0.5 mΩ·cm², etc.

[0133] It should be noted that contact resistivity represents the resistance of an interface per unit area, reflecting the ease with which charge carriers pass through the metal / semiconductor interface; the lower the contact resistivity, the better the ohmic contact and the more efficient the current transmission.

[0134] In some embodiments, nickel in the attachment portion 112 forms nickel silicide with silicon to reduce contact resistance, such that the contact resistivity between the electrode and the doped conductive region 101 is in the range of 0.2 mΩ·cm² to 0.5 mΩ·cm², so as to achieve good ohmic contact.

[0135] refer to Figure 4 In another aspect, this disclosure provides a method for preparing a solar cell, comprising at least the following steps: S1: Provide a substrate, at least one side of which has a doped conductive region.

[0136] The following explanation uses TOPCON solar cells as an example.

[0137] refer to Figure 5 In some embodiments, the substrate 10 may be doped, for example, by ion implantation to diffuse dopant elements into the substrate 10.

[0138] In some embodiments, a texturing process is performed on at least one of the front or back surfaces of the substrate 10 to form a texturing surface on at least one of the front or back surfaces of the substrate 10.

[0139] A second sub-doped conductive region 1012 is formed in the substrate 10. The doping element type of the second sub-doped conductive region 1012 is opposite to that of the substrate 10. In some embodiments, taking the N-type doping element type of the substrate 10 as an example, the method for forming the second sub-doped conductive region 1012 may include: An initial substrate is provided, and a diffusion process is performed on the initial substrate surface to diffuse a P-type dopant element from the surface of the initial substrate into a portion of the initial substrate, thereby transforming the portion of the initial substrate with diffused P-type dopant element into a second sub-doped conductive region 1012. The remaining portion of the initial substrate forms substrate 10. In some embodiments, the diffusion process may be an ion implantation process.

[0140] A tunneling layer 2 is formed on the back side of the substrate 10.

[0141] In some embodiments, a tunneling layer 2 may be formed on the back side of the substrate 10 using a deposition process, which may include either atomic layer deposition or chemical vapor deposition.

[0142] In some embodiments, the material of the tunneling layer 2 may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0143] A first sub-doped conductive region 1011 is formed on the surface of the tunneling layer 2 away from the substrate 10. The material of the first sub-doped conductive region 1011 may be at least one of amorphous silicon, polycrystalline silicon, or silicon carbide.

[0144] Taking polysilicon as an example, as the material of the first sub-doped conductive region 1011, in some embodiments, the method of forming the first sub-doped conductive region 1011 may include: An intrinsic polysilicon layer is formed on the surface of the tunneling layer 2 using a deposition process, such as atomic layer deposition. The intrinsic polysilicon layer is then doped to introduce elements, forming the first sub-doped conductive region 1011.

[0145] In some embodiments, the doping process may include depositing a dopant source on the surface of the intrinsic polysilicon layer away from the substrate 10, the dopant source comprising a first dopant element. In some embodiments, the first dopant element may be an N-type dopant element. In some embodiments, the N-type dopant source may be a pentavalent element or a compound, such as phosphorus or a phosphorus-containing compound, such as phosphorus trichloride.

[0146] While depositing a doped source on the back side of substrate 10, oxygen is introduced and the temperature is increased to push the first doped element in the doped source into the intrinsic polysilicon layer, forming the first sub-doped conductive region 1011.

[0147] S2: An electrode is formed on the surface of the doped conductive region, and the electrode is electrically connected to the doped conductive region.

[0148] refer to Figure 2 A first electrode 12 is formed on the surface of the first sub-doped conductive region 1011, and the first electrode 12 is electrically connected to the first sub-doped conductive region 1011.

[0149] In some embodiments, the method for fabricating a solar cell further includes forming a first passivation layer 4 on the surface of the first sub-doped conductive region 1011 away from the substrate 10.

[0150] In some embodiments, the method of forming the first passivation layer 4 may include: forming the first passivation layer 4 on the surface of the first sub-doped conductive region 1011 using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0151] refer to Figure 2 The method for preparing a solar cell further includes forming a second electrode 13 on the surface of the second sub-doped conductive region 1012, wherein the second electrode 13 is electrically connected to the second sub-doped conductive region 1012.

[0152] In some embodiments, the method for fabricating a solar cell further includes forming a second passivation layer 6 on the surface of the second sub-doped conductive region 1012 away from the substrate 10.

[0153] In some embodiments, the method of forming the second passivation layer 6 may include: forming the second passivation layer 6 on the surface of the second sub-doped conductive region 1012 using a PECVD method.

[0154] refer to Figure 6 S2 includes at least the following steps: S21: A barrier portion is formed on the surface of the doped conductive region, and the barrier portion is electrically connected to the doped conductive region.

[0155] S22: An adhesion portion is formed on the surface of the blocking portion.

[0156] S23: A conductive part is formed on the surface of the attachment part.

[0157] S24: A main body is formed on the surface of the conductive part.

[0158] refer to Figures 7 to 11 The following description uses the formation of a first electrode 12 on the surface of the first sub-doped conductive region 1011 as an example.

[0159] refer to Figure 7 Forming a barrier portion 111 on the surface of the first sub-doped conductive region 1011 includes: performing image processing on the surface of the first sub-doped conductive region 1011 to obtain a groove region.

[0160] refer to Figure 8 Using the first deposition process, a barrier 111 is formed in the groove region I.

[0161] It should be noted that the groove region I is the gate line region, which is the region where the first electrode 12 is subsequently generated.

[0162] refer to Figure 9 An attachment portion 112 is formed on the surface of the blocking portion 111.

[0163] refer to Figure 10 A conductive portion 113 is formed on the surface of the attachment portion 112.

[0164] refer to Figure 11 A main body portion 114 is formed on the surface of the conductive portion 113.

[0165] It is understandable that the step of forming the second electrode 13 on the surface of the second sub-doped conductive region 1012 is similar to the steps described above, and will not be repeated here.

[0166] The fabrication method of this solar cell constructs an electrode structure with clearly defined interlayer functions by sequentially forming a barrier portion, an adhesion portion, a conductive portion, and a main body portion on the surface of the doped conductive region. The barrier portion directly contacts and electrically connects with the doped conductive region, providing a stable interface foundation for the overall electrode; the adhesion portion enhances the bonding strength between the layers within the electrode; the conductive portion facilitates lateral current collection and transmission; and the main body portion provides a reliable conductive path for external electrical connections. This multilayer structure works synergistically to help reduce contact resistance, improve electrode adhesion, and enhance the electrical performance and reliability of the cell.

[0167] In some embodiments, image processing of the surface of the doped conductive region includes: etching the surface of the doped conductive region with an etching solution; the etching solution is an aqueous solution of hydrofluoric acid.

[0168] For example, photosensitive ink is sequentially printed on the front and back of the battery. After drying and curing, the predetermined grid line area is patterned and exposed. The photosensitive ink in the exposed area is removed using an alkaline solution. The passivation layer on the front and back of the battery is etched using a hydrofluoric acid aqueous solution to selectively remove the passivation layer in the grid line area, thereby forming the groove area I.

[0169] In some embodiments, the process parameters of the first deposition process include: a process temperature of 140°C to 160°C, for example, 140°C to 160°C, 140°C to 160°C, or 140°C to 160°C; and a precursor of trimethylaluminum and an aqueous solution.

[0170] In some embodiments, the process temperature of the first deposition process can be 140°C, 145°C, 150°C, 155°C, or 160°C, etc.

[0171] For example, in the process of forming alumina, trimethylaluminum is used as the aluminum source and aqueous solution is used as the oxygen source. Through alternating pulses of atomic layer deposition process, alumina film is generated on the surface of groove region I by self-limiting reaction.

[0172] The first deposition process can be atomic layer deposition (ALD), magnetron sputtering, or chemical vapor deposition (CVD).

[0173] In some embodiments, a second deposition process is used to form an attachment portion 112 on the surface of the barrier portion 111.

[0174] The second deposition process can be ALD deposition, magnetron sputtering, or CVD deposition, etc.

[0175] In some embodiments, a third deposition process is used to form a conductive portion 113 on the surface of the attachment portion 112.

[0176] The third deposition process can be spin coating.

[0177] In some embodiments, forming a main body 114 on the surface of the conductive portion 113 includes: forming the main body 114 on the surface of the conductive portion 113 using a pulse electroplating process. The process parameters of the pulse electroplating process include: a current density of 1ASD to 10ASD; for example, 1ASD to 3ASD, 3ASD to 7ASD, or 7ASD to 10ASD, etc., and a current pulse duty cycle of 10% to 50%; for example, 10% to 50%, 10% to 50%, or 10% to 50%, etc.

[0178] Compared to DC electroplating, pulse electroplating improves coating uniformity and better controls deposition rate and grain size by periodically switching current on and off.

[0179] In some embodiments, the current density of the pulse electroplating process is 1ASD, 2ASD, 3ASD, 4ASD, 5ASD, 6ASD, 7ASD, 8ASD, 9ASD, or 10ASD, etc.

[0180] Controlling the current density within the range of 1ASD to 10ASD ensures a stable deposition process, avoids inefficiency due to excessively low current, improves the deposition rate, and prevents problems such as burning, porosity, or rough coating caused by excessively high current.

[0181] In some embodiments, the duty cycle of the current pulse in the pulse electroplating process is 10%, 20%, 30%, 40%, or 50%, etc.

[0182] Duty cycle refers to the percentage of time the electrode is energized within one pulse cycle. A duty cycle controlled between 10% and 50% provides sufficient off-time, allowing ions to diffuse and replenish fully on the electrode surface, effectively mitigating concentration polarization and contributing to the formation of a denser body with lower internal stress 114.

[0183] In some embodiments, after forming the main body portion 114 on the surface of the conductive portion 113, the preparation method further includes removing the mask.

[0184] For example, the substrate with electroplated front and back is immersed in an alkaline solution of potassium hydroxide or sodium hydroxide, so that the photosensitive ink on the surface reacts with the alkaline solution and dissolves in the water.

[0185] In some embodiments, the preparation method further includes: annealing treatment.

[0186] For example, the substrate after mask removal is placed in a nitrogen atmosphere for annealing to further enhance the ohmic contact and interfacial adhesion of the electrodes.

[0187] In some embodiments, the annealing temperature is 300℃~500℃ and the annealing time is 10 minutes~30 minutes.

[0188] The solar cell disclosed herein includes an electrode comprising a barrier portion, an attachment portion, a conductive portion, and a main body portion arranged sequentially along a direction away from the substrate. The barrier portion directly contacts the doped conductive region, effectively establishing a stable electrical connection. The attachment portion, located above the barrier portion, helps enhance the bonding strength between the electrode as a whole and the substrate. The conductive portion, located on the side of the attachment portion away from the substrate, provides a pathway for current conduction between the main body portion and the barrier portion. This disclosure not only optimizes the interface characteristics between the electrode and the doped conductive region but also improves current conduction efficiency and structural stability, thereby improving the overall electrical performance and reliability of the solar cell. Furthermore, the barrier portion, made of high-density alumina or titanium nitride, effectively blocks the diffusion of diffusing metal atoms into the silicon substrate. The attachment portion, made of nickel or a copper-nickel alloy, helps achieve reliable interfacial electrical connections and mechanical stability in a multilayer electrode structure. In addition, by rationally setting the thickness of each part of the electrode, the structural reliability and conductivity of the electrode are improved. Moreover, the conductive portion is configured as a network structure composed of conductive nanowires, ensuring current conduction capability while also possessing lightweight, high bonding strength, and excellent mechanical stability. At the same time, by reasonably setting the mesh porosity of the network structure, conductivity, cost, processability, and reliability can be balanced.

[0189] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including a plurality of solar cells as described in the above embodiments, or a plurality of solar cells manufactured by the method for preparing solar cells in the above embodiments. The photovoltaic module provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0190] Figure 12 This is a partial three-dimensional structural diagram of a photovoltaic module provided in an embodiment of the present disclosure; Figure 13 for Figure 12 A schematic diagram of a cross-sectional structure along the cross-sectional direction NN1.

[0191] refer to Figure 12 and Figure 13 The photovoltaic module provided in this embodiment includes: a battery string, an encapsulating film 201, and a cover plate 202.

[0192] The battery string is formed by connecting multiple solar cells as described in the above embodiments, or by connecting multiple solar cells formed by the preparation methods of the solar cells in the above embodiments.

[0193] It should be noted that solar cells are electrically connected to form multiple cell strings, which are electrically connected in series and / or parallel. Since solar cells include segmented cells, and these segmented cells are formed by dividing a whole solar cell, the reduced current in the segmented cells can improve the power loss of the photovoltaic module, thereby increasing the photoelectric conversion efficiency of the photovoltaic module.

[0194] In one or more embodiments, reference is made to Figure 13 As shown, multiple battery strings can be electrically connected through conductive strip 203. Figure 13 This illustration only depicts one possible positional relationship between solar cells, where the electrodes of the solar cells with the same polarity are arranged in the same direction, or in other words, the electrodes of each solar cell with the positive polarity are arranged facing the same side, thereby connecting the different sides of two adjacent solar cells with conductive strips. In some embodiments, the solar cells can also be arranged with electrodes of different polarities facing the same side, that is, the electrodes of multiple adjacent solar cells are arranged in the order of first polarity, second polarity, and first polarity, respectively, then the conductive strip connects two adjacent cells on the same side.

[0195] In one or more embodiments, there is no spacing between the solar cells, that is, the solar cells overlap each other.

[0196] refer to Figure 13 The encapsulating film 201 is used to cover the surface of the battery string.

[0197] In one or more embodiments, the encapsulating film includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0198] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module no longer has the concept of a first encapsulation layer and a second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film.

[0199] refer to Figure 11 The cover plate 202 is used to cover the surface of the encapsulating film 201 away from the battery string.

[0200] In one or more embodiments, the cover plate can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate facing the encapsulating film can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0201] In one or more embodiments, reference is made to Figure 12 As shown, the solar cells 100 in the battery string are arranged along the direction U, and the main grids of two adjacent solar cells 100 in the battery string are staggered in the direction Y. For photovoltaic modules, by setting the main grids of two adjacent solar cells 100 in the battery string to be staggered in the direction Y, the different potentials of the photovoltaic modules can be tested, thereby improving the reliability of the test results.

[0202] In one or more embodiments, the solar cell includes, but is not limited to, one or any combination of PERC (Passivated Emitter Rear Cell), IBC (Interdigitated Back Contact), TOPCon (Tunnel Oxide Passivated Contact), HIT / HJT (Heterojunction Technology) cells, thin-film solar cells, and tandem solar cells. Thin-film solar cells include, but are not limited to, perovskite thin-film solar cells, copper indium selenide (CIGS) thin-film solar cells, gallium arsenide (GaAs) thin-film solar cells, and cadmium sulfide (CdS) thin-film solar cells. Tandem solar cells include, but are not limited to, perovskite cells stacked with crystalline silicon cells, perovskite cells stacked with perovskite cells, and perovskite cells stacked with thin-film cells.

[0203] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: A substrate, wherein at least one side of the substrate has a doped conductive region; An electrode, electrically connected to the doped conductive region; wherein the electrode comprises: A blocking portion, which is electrically connected to the doped conductive region; An attachment portion, the attachment portion being located on the side of the blocking portion away from the substrate; A conductive portion, the conductive portion being located on the side of the attachment portion away from the substrate; The main body is located on the side of the conductive portion away from the substrate.

2. The solar cell according to claim 1, characterized in that, The material of the blocking part is aluminum oxide or titanium nitride.

3. The solar cell according to claim 1, characterized in that, The material of the attachment part is nickel or a copper-nickel alloy.

4. The solar cell according to claim 3, characterized in that, When the material of the attachment part is a copper-nickel alloy, the mass percentage of nickel in the attachment part is 5% to 20%.

5. The solar cell according to claim 1, characterized in that, The thickness of the attachment portion is greater than the thickness of the blocking portion.

6. The solar cell according to claim 1 or 5, characterized in that, The thickness of the blocking part is 2nm~5nm.

7. The solar cell according to claim 1 or 5, characterized in that, The thickness of the attached portion is 95nm~105nm.

8. The solar cell according to claim 1, characterized in that, The conductive part is a network structure composed of conductive nanowires.

9. The solar cell according to claim 8, characterized in that, The diameter of the conductive nanowire is 10 nm to 50 nm.

10. The solar cell according to claim 8, characterized in that, The mesh porosity of the network structure is 60%~90%.

11. The solar cell according to claim 1, characterized in that, The thickness of the main body is 5μm~10μm.

12. A method for preparing a solar cell, characterized in that, include: A substrate is provided, wherein at least one side of the substrate has a doped conductive region; An electrode is formed on the surface of the doped conductive region, and the electrode is electrically connected to the doped conductive region; wherein forming the electrode includes: A blocking portion is formed on the surface of the doped conductive region, and the blocking portion is electrically connected to the doped conductive region; An adhesion portion is formed on the surface of the blocking portion; A conductive portion is formed on the surface of the attachment portion; A main body portion is formed on the surface of the conductive portion.

13. The method for preparing a solar cell according to claim 12, characterized in that, The process of forming a barrier portion on the surface of the doped conductive region includes: The surface of the doped conductive region is imaged to obtain a groove region; The first deposition process is used to form the barrier portion in the groove region.

14. The method for preparing a solar cell according to claim 13, characterized in that, The process parameters of the first deposition process include: a process temperature of 140℃~160℃, and a precursor of trimethylaluminum and an aqueous solution.

15. The method for preparing a solar cell according to claim 12, characterized in that, The method of forming a main body portion on the surface of the conductive portion includes: The main body is formed on the surface of the conductive part using a pulse electroplating process. The process parameters of the pulse electroplating process include: current density of 1ASD~10ASD and current pulse duty cycle of 10%~50%.

16. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple solar cells as described in any one of claims 1 to 11, or by connecting solar cells prepared by the method for preparing solar cells as described in any one of claims 12 to 15; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film away from the battery string.

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