Back contact cell and preparation method, preparation equipment and photovoltaic module thereof

CN122248843BActive Publication Date: 2026-09-11JINKO SOLAR (HAINING) CO LTS
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Patent Information

Application Number
CN202610660201.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-05-13
Publication Date
2026-09-11
Estimated Expiration
2046-05-13

AI Technical Summary

Technical Problem

[0003]本申请实施例提供了一种背接触电池片及其制备方法、制备设备和光伏组件,以利于解决现有技术中细栅对不同极性主栅的交替而间断,影响载流子收集的技术问题

Benefits of technology

[0005]本实施例中,通过设置用于与焊带连接的第一焊栅和第二焊栅,且使第一细栅和第二细栅分别与第一焊栅和第二焊栅连接,从而能够将第一细栅和第二细栅收集的电流快速传导第一焊栅和第二焊栅上,并传输至焊带上,提升电流传输速率。同时,使第一焊栅和第二焊栅分别设置于硅衬底的对角区域,即第一焊栅和第二焊栅设置于第一细栅和第二细栅布置区域的两端,便于实现第一细栅和第二细栅的全贯穿设计。另外,第一焊栅包括沿第一方向延伸的第一延伸部,以使沿第一方向间隔设置的多条第一细栅均能够与第一延伸部连接,且第二焊栅包括沿第一方向延伸的第三延伸部,以使沿第一方向间隔设置的多条第二细栅均能够与第三延伸部连接。

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Abstract

The application relates to the technical field of photovoltaic modules, in particular to a back contact cell, a preparation method and a preparation device thereof, and a photovoltaic module. The back contact cell comprises a silicon substrate and a plurality of first fine grids and a plurality of second fine grids located on the back surface of the silicon substrate. The first fine grids and the second fine grids are spaced apart. The back contact cell further comprises a first solder grid and a second solder grid for being connected with a solder strip, and the first solder grid and the second solder grid are arranged in opposite corner regions of the silicon substrate. The first solder grid comprises a first extension part and a second extension part which are perpendicular to each other, and the second solder grid comprises a third extension part and a fourth extension part which are perpendicular to each other. The first extension part and the third extension part extend along a first direction, and the second extension part and the fourth extension part extend along a second direction. The first fine grid is connected with the first extension part, and the second fine grid is connected with the third extension part. By canceling the main grid design, the first fine grid and the second fine grid can be designed in a penetrating mode, so that the collection effect of carriers is improved.
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Description

Technical Field

[0001] This application relates to the field of photovoltaic module technology, specifically to a back contact solar cell, its preparation method, preparation equipment, and photovoltaic module. Background Technology

[0002] Photovoltaic modules can convert solar energy into electrical energy, offering advantages such as being pollution-free, not geographically limited, and inexhaustible, making them a major direction for developing new energy sources. Photovoltaic modules mainly consist of photovoltaic cells, photovoltaic glass, encapsulating film, backsheet, and frame. Back-contact cells, as a type of photovoltaic cell, have both positive and negative electrodes located on the back side of the cell. The electrode design typically involves main grids connecting to fine grids, with the fine grids arranged in an alternating interdigitated pattern, and the grids discontinuous as different polarity main grids alternate. Summary of the Invention

[0003] This application provides a back-contact solar cell, its preparation method, preparation equipment, and photovoltaic module, which helps to solve the technical problem in the prior art where the fine grid alternates and is intermittent with the main grid of different polarities, affecting carrier collection.

[0004] In a first aspect, embodiments of this application provide a back-contact solar cell, the back-contact solar cell comprising a silicon substrate and a plurality of first fine gates and a plurality of second fine gates located on the back side of the silicon substrate; the first fine gates and the second fine gates are spaced apart along a first direction; The back contact cell further includes a first weld gate and a second weld gate for connection with the solder strip. The first weld gate and the second weld gate are respectively disposed in diagonal regions of the silicon substrate. The first weld gate includes a first extension and a second extension that are perpendicular to each other, and the second weld gate includes a third extension and a fourth extension that are perpendicular to each other. The first extension and the third extension extend along a first direction, and the second extension and the fourth extension extend along a second direction. The first fine gate is connected to the first extension, and the second fine gate is connected to the third extension.

[0005] In this embodiment, by providing a first and a second weld gate for connection with the solder ribbon, and connecting the first and second fine gates to the first and second weld gates respectively, the current collected by the first and second fine gates can be rapidly conducted to the first and second weld gates and transmitted to the solder ribbon, thereby improving the current transmission rate. Simultaneously, the first and second weld gates are respectively located in diagonal regions of the silicon substrate, i.e., at both ends of the area where the first and second fine gates are arranged, facilitating a full-through design of the first and second fine gates. Furthermore, the first weld gate includes a first extension extending along a first direction, allowing multiple first fine gates spaced apart along the first direction to connect to the first extension, and the second weld gate includes a third extension extending along the first direction, allowing multiple second fine gates spaced apart along the first direction to connect to the third extension.

[0006] Meanwhile, by eliminating the main gate design and placing the first and second gates in diagonal regions of the silicon substrate, the current generated on the first and second fine gates is collected, respectively. In the region between the first and second gates, the first and second fine gates can be a through-type design, without interruption due to avoiding the main gate structure. This increases the coverage area of ​​the first and second fine gates, improves carrier collection efficiency, and significantly reduces the risk of leakage due to contact between the fine gates and the main gate. Furthermore, eliminating the large main gate structure also reduces the fabrication cost of the back-contact solar cells.

[0007] In one specific embodiment, the back contact cell further includes a first connecting line that connects a plurality of first fine grids and a second extension; the back contact cell further includes a second connecting line that connects a plurality of second fine grids and a fourth extension.

[0008] In one specific embodiment, the first connecting line and the second connecting line extend along the first direction.

[0009] In one specific embodiment, the back contact cell is further provided with an insulating layer, the insulating layer covering at least a portion of the structure of the first fine grid and the second fine grid; the insulating layer is provided with a first clearance hole and a second clearance hole, the first connecting line is connected to the first fine grid through the first clearance hole, and the second connecting line is connected to the second fine grid through the second clearance hole.

[0010] In one specific embodiment, the diameter D1 of the first connecting line satisfies D1≤200μm, and the diameter D2 of the second connecting line satisfies D2≤200μm.

[0011] In one specific embodiment, the minimum distance L1 between the first weld gate and the end of the silicon substrate satisfies 5μm≤L1≤30μm, and the minimum distance L2 between the second weld gate and the end of the silicon substrate satisfies 5μm≤L2≤30μm.

[0012] In one specific embodiment, the width L3 of the first weld gate satisfies 50μm≤L3≤300μm, and the width L4 of the second weld gate satisfies 50μm≤L4≤300μm.

[0013] In one specific embodiment, a first doped region and a second doped region are disposed on the back side of the silicon substrate, the first fine gate and the first bond gate are disposed in the first doped region, and the second fine gate and the second bond gate are disposed in the second doped region; a spacer region is provided between the first doped region and the second doped region, and the width of the spacer region satisfies 5μm≤L5≤50μm.

[0014] Secondly, embodiments of this application provide a method for preparing a back contact solar cell, the method comprising: Preparation of silicon substrates; A first doped region, a second doped region, and a spacer region are formed on the back side of the silicon substrate; A first fine gate and a first weld gate are prepared in the first doped region, and a second fine gate and a second weld gate are prepared in the second doped region; Wherein, along a first direction, the first fine gate and the second fine gate are spaced apart; the first bond gate and the second bond gate are respectively disposed in diagonal regions of the silicon substrate; the first bond gate includes a first extension and a second extension that are perpendicular to each other, and the second bond gate includes a third extension and a fourth extension that are perpendicular to each other; the first extension and the third extension extend along the first direction, and the second extension and the fourth extension extend along a second direction; the first fine gate is connected to the first extension, and the second fine gate is connected to the third extension.

[0015] In one specific embodiment, after preparing the first fine grid, the first weld grid, the second fine grid, and the second weld grid, the method for preparing the back contact solar cell further includes: An insulating layer is prepared on the back side of the silicon substrate; A first clearance hole and a second clearance hole are formed on the insulating layer, and the first clearance hole and the second clearance hole are spaced apart along the first direction; A first connecting line and a second connecting line are formed on the insulating layer. The first connecting line is connected to a plurality of first fine gates through a first clearance hole, and the second connecting line is connected to a plurality of second fine gates through a second clearance hole.

[0016] Thirdly, embodiments of this application provide a fabrication apparatus for fabricating back-contact solar cells, the fabrication apparatus comprising: A texturing module is used to clean and texturize the silicon substrate; The doping module is used to generate the first doped region and the second doped region. Etching module, used to form spacer regions; A passivation module for forming a passivation layer on the back side of the silicon substrate; A printing module is used to fabricate the first fine gate, the first weld gate, the second fine gate, and the second weld gate.

[0017] Fourthly, embodiments of this application provide a photovoltaic module, the photovoltaic module including a plurality of back contact cells, the plurality of back contact cells being arranged along the second direction and electrically connected to form a cell string; the photovoltaic module further includes a first solder strip and a second solder strip, the first solder strip being located at the end of the cell string and used to connect the first grid or the second grid; the second solder strip being located between adjacent back contact cells and used to connect the first grid and the second grid of adjacent back contact cells.

[0018] In one specific embodiment, the minimum distance L6 between the end of the first weld gate or the end of the second weld gate and the first weld strip satisfies ≥30μm; the minimum distance L7 between the end of the first weld gate and the end of the second weld gate and the second weld strip satisfies ≥30μm. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the photovoltaic module provided in this application in a specific embodiment; Figure 2 for Figure 1 A schematic diagram of the structure of the back contact battery cell; Figure 3 for Figure 2 Schematic diagram of the structure of the silicon substrate; Figure 4 for Figure 1 A schematic diagram of the structure of the back contact battery cell in another specific embodiment; Figure 5 for Figure 1 A schematic diagram of the structure of the battery string; Figure 6 for Figure 5 Perspective view; Figure 7 for Figure 6 A magnified view of part I in the middle; Figure 8 for Figure 6 A magnified view of part II.

[0021] Figure label: 100 - Photovoltaic module; 10 - Cell layer; 20 - First encapsulation layer; 30 - Second encapsulation layer; 40 - First cover plate; 50 - Second cover plate; 1- Battery string; 11-Back contact cell; 111-Silicon substrate; 112 - First fine grid; 113 - Second fine grid; 114 - First weld gate; 114a - First extension; 114b - Second extension; 115 - Second weld gate; 115a - Third extension; 115b - Fourth extension; 116 - First connecting line; 117 - Second connecting line; 118 - Insulation layer; 118a - First clearance hole; 118b - Second clearance hole; 119 - First doped region; 120 - Second doped region; 121-Interval Zone; 122 - First back contact cell; 123 - Second back contact cell; 124 - Third back contact cell; 2-First weld strip; 3-Second welding strip. Detailed Implementation

[0022] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0023] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0024] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0026] Photovoltaic modules convert solar energy into electrical energy, offering advantages such as being pollution-free, not geographically limited, and inexhaustible, making them a major direction for developing new energy sources. Photovoltaic modules mainly consist of photovoltaic cells, photovoltaic glass, encapsulating film, backsheet, and frame. Back-contact cells, a type of photovoltaic cell, have both positive and negative electrodes located on the back side of the cell. The electrode design typically involves a main grid connecting to a fine grid, with the fine grid arranged in an alternating interdigitated pattern. The fine grid is discontinuous as it alternates with different polarity main grids, resulting in a significant area not covered by the fine grid, thus affecting the carrier collection rate of the back-contact cell.

[0027] To solve the above technical problems, such as Figure 1 As shown, this application provides a photovoltaic module 100, which includes a battery layer 10, a cover plate, and an encapsulation layer. Along the thickness direction of the photovoltaic module 100, the cover plate located on the upper layer of the photovoltaic module 100 is a first cover plate 40, and the cover plate located on the lower layer of the photovoltaic module 100 is a second cover plate 50. A first encapsulation layer 20 is disposed between the first cover plate 40 and the battery layer 10, and a second encapsulation layer 30 is disposed between the second cover plate 50 and the battery layer 10, and the above structural layers are laminated together.

[0028] In this embodiment of the application, the battery layer 10 includes a plurality of back-contact battery cells 11, such as Figure 2As shown, the back contact solar cell 11 includes a silicon substrate 111 and a plurality of first fine gates 112 and a plurality of second fine gates 113 located on the back side of the silicon substrate 111. The first fine gates 112 and the second fine gates 113 are spaced apart along a first direction. In the back contact solar cell 11, both the first fine gates 112 and the second fine gates 113 are disposed on the back side of the silicon substrate 111, and the polarities of the first fine gates 112 and the second fine gates 113 are opposite, so that the front side of the back contact solar cell 11 is unobstructed, thereby increasing the effective light-receiving area of ​​the back contact solar cell 11 and improving the light absorption efficiency of the back contact solar cell 11. The polarity of the first fine gate 112 and the second fine gate 113 is determined by the doped region on the back side of the silicon substrate 111. The back side of the silicon substrate 111 can be formed with P-type doped regions and N-type doped regions spaced apart by ion implantation or diffusion processes. The first fine gate 112 can be disposed in the P-type doped region and the second fine gate 113 can be disposed in the N-type doped region. Alternatively, the first fine gate 112 can be disposed in the N-type doped region and the second fine gate 113 can be disposed in the P-type doped region, and ohmic contacts can be formed with the P-type doped region and the N-type doped region respectively to achieve current collection.

[0029] The back contact cell 11 also includes a first weld gate 114 and a second weld gate 115 for connection with the solder ribbon. The first weld gate 114 and the second weld gate 115 are respectively disposed in diagonal regions of the silicon substrate 111. The first weld gate 114 includes a first extension 114a and a second extension 114b that are perpendicular to each other, and the second weld gate 115 includes a third extension 115a and a fourth extension 115b that are perpendicular to each other. The first extension 114a and the third extension 115a extend along a first direction, and the second extension 114b and the fourth extension 115b extend along a second direction. A first fine gate 112 is connected to the first extension 114a, and a second fine gate 113 is connected to the third extension 115a.

[0030] By providing a first weld gate 114 and a second weld gate 115 for connection with the solder ribbon, and connecting the first fine gate 112 and the second fine gate 113 to the first weld gate 114 and the second weld gate 115 respectively, the current collected by the first fine gate 112 and the second fine gate 113 can be rapidly conducted to the first weld gate 114 and the second weld gate 115 and transmitted to the solder ribbon, thereby improving the current transmission rate. Simultaneously, by positioning the first weld gate 114 and the second weld gate 115 in diagonal regions of the silicon substrate 111, i.e., at both ends of the area where the first fine gate 112 and the second fine gate 113 are arranged, it is easier to achieve a full-through design of the first fine gate 112 and the second fine gate 113. In addition, the first weld gate 114 includes a first extension 114a extending along a first direction, so that a plurality of first fine gates 112 spaced apart along the first direction can be connected to the first extension 114a, and the second weld gate 115 includes a third extension 115a extending along the first direction, so that a plurality of second fine gates 113 spaced apart along the first direction can be connected to the third extension 115a.

[0031] Compared to related technologies, the back contact solar cell 11 in this embodiment eliminates the main grid design and sets a first gate 114 and a second gate 115 in the diagonal region of the silicon substrate 111 to collect the current generated on the first fine gate 112 and the second fine gate 113, respectively. In the region between the first gate 114 and the second gate 115, the first fine gate 112 and the second fine gate 113 can be a through-type design, without interruption due to avoiding the main grid structure. This increases the coverage area of ​​the first fine gate 112 and the second fine gate 113, improves carrier collection efficiency, and greatly reduces the risk of leakage due to contact between the fine gate and the main grid. Furthermore, eliminating the large main grid structure also reduces the manufacturing cost of the back contact solar cell 11.

[0032] In this embodiment, the first direction can be the length direction of the back contact battery cell 11, and the second direction can be the width direction of the back contact battery cell 11.

[0033] In some embodiments, such as Figure 1As shown, the width L3 of the first weld gate 114 satisfies 50μm≤L3≤300μm. For example, the width L3 of the first weld gate 114 can be 50μm, 100μm, 200μm, 250μm, 300μm, etc., and the width L4 of the second weld gate 115 satisfies 50μm≤L4≤300μm. For example, the width L4 of the second weld gate 115 can be 50μm, 100μm, 200μm, 250μm, 300μm, etc. This makes the widths of the first weld gate 114 and the second weld gate 115 larger, which can reduce the resistance of the first weld gate 114 and the second weld gate 115 themselves, reduce the loss in the current transmission process, and also increase the contact area between the first weld gate 114 and the second weld gate 115 and the welding strip, improve the uniformity of stress distribution, and enhance the reliability of the connection.

[0034] Furthermore, in other embodiments, the widths of the first weld gate 114 and the second weld gate 115 can be other values, which can be adaptively adjusted according to actual conditions. The widths of the first weld gate 114 and the second weld gate 115 can be the same or different.

[0035] In the above embodiments, the first fine gate 112, the second fine gate 113, the first weld gate 114, and the second weld gate 115 can all be made of the same material, for example, they can all be made of one or more of the following materials: silver paste, copper paste, or silver-coated copper paste. Meanwhile, the width of the first weld gate 114 and the second weld gate 115 is greater than the width of the first fine gate 112 and the second fine gate 113, in order to improve the current collection effect of the first weld gate 114 and the second weld gate 115 on the first fine gate 112 and the second fine gate 113.

[0036] In the above embodiments, such as Figure 2 As shown, the minimum distance L1 between the first weld gate 114 and the end of the silicon substrate 111 satisfies 5μm≤L1≤30μm. For example, L1 can be 5μm, 10μm, 15μm, 20μm, 30μm, etc. The minimum distance L2 between the second weld gate 115 and the end of the silicon substrate 111 satisfies 5μm≤L1≤30μm. For example, L2 can be 5μm, 10μm, 15μm, 20μm, 30μm, etc. By limiting the minimum distance between the weld gate and the end of the silicon substrate 111, it is possible to prevent part of the structure of the first weld gate 114 and the second weld gate 115 from exceeding the range of the silicon substrate 111, thus preventing leakage.

[0037] Furthermore, in other embodiments, L1 and L2 can also be other specific values, which can be adaptively adjusted according to the actual situation. The values ​​of L1 and L2 can be the same or different.

[0038] In some embodiments, such as Figure 2 and Figure 3As shown, a first doped region 119 and a second doped region 120 are disposed on the back side of the silicon substrate 111. A first fine gate 112 and a first bond gate 114 are disposed in the first doped region 119, and a second fine gate 113 and a second bond gate 115 are disposed in the second doped region 120. By partitioning the first fine gate 112 and the first bond gate 114, and the second fine gate 113 and the second bond gate 115, the polarities of the first fine gate 112 and the first bond gate 114, and the second fine gate 113 and the second bond gate 115 can be made opposite. For example, the first doped region 119 can be a P-type doped region so that the first fine gate 112 and the first bond gate 114 are positive gate lines, and the second doped region 120 can be an N-type doped region so that the second fine gate 113 and the second bond gate 115 are negative gate lines. Alternatively, the first doped region 119 can be an N-type doped region so that the first fine gate 112 and the first bond gate 114 are negative gate lines, and the second doped region 120 can be a P-type doped region so that the second fine gate 113 and the second bond gate 115 are positive gate lines.

[0039] A spacer region 121 is also provided between the first doped region 119 and the second doped region 120, serving as a physical barrier between them. The spacer region 121 prevents the formation of a leakage path due to direct contact, thus avoiding short circuits caused by direct recombination of charge carriers. The spacer region 121 can be an isolation trench structure formed by laser or etching, blocking the lateral migration of charge carriers. Simultaneously, the first fine gate 112 and the first weld gate 114, the second fine gate 113 and the second weld gate 115 are respectively disposed within the first doped region 119 and the second doped region 120, which also achieves isolation through the spacer region 121, preventing them from contacting each other and causing short circuits.

[0040] The width of the spacing region 121 satisfies 5μm≤L5≤50μm. For example, L5 can be 5μm, 20μm, 30μm, 40μm, 50μm, etc., so that there is a certain spacing between the first fine grid 112 and the second weld grid 115, the second fine grid 113 and the first weld grid 114 along the second direction, and there is also a certain spacing between the first fine grid 112 and the second fine grid 113 along the first direction. This avoids short circuits due to contact and prevents the effective power generation area from decreasing due to the excessive width of the spacing region 121, which would affect the output power of the back contact cell 11.

[0041] In addition, in other embodiments, the width of the interval 121 can be other values, which can be adaptively adjusted according to the actual situation.

[0042] In some embodiments, such as Figure 2 and Figure 4As shown, the back contact cell 11 also includes a first connecting line 116, which connects a plurality of first fine grids 112 and a second extension 114b. The plurality of first fine grids 112 are spaced apart along a first direction, and the ends of the plurality of first fine grids 112 are connected to the first extension 114a. With this design, the plurality of first fine grids 112 can also be electrically connected to the second extension 114b of the first weld grid 114 through the first connecting line 116, thereby establishing two current transmission channels between the first fine grids 112 and the first weld grid 114, further improving the current transmission rate between the first fine grids 112 and the first weld grid 114.

[0043] Meanwhile, the back contact cell 11 also includes a second connecting line 117, which connects a plurality of second fine grids 113 and a fourth extension 115b. The plurality of second fine grids 113 are spaced apart along the first direction, and the ends of the plurality of second fine grids 113 are connected to the third extension 115a. Through this design, the plurality of second fine grids 113 can also be electrically connected to the fourth extension 115b of the second weld grid 115 through the second connecting line 117, thereby establishing two current transmission channels between the second fine grids 113 and the second weld grid 115, further improving the current transmission rate between the second fine grids 113 and the second weld grid 115.

[0044] In the above embodiments, the first connecting line 116 and the second connecting line 117 can be conductive adhesive. The material of the first connecting line 116 and the second connecting line 117 can also be the same as the material of the first fine gate 112 or the second fine gate 113.

[0045] In some embodiments, such as Figure 4 As shown, the first connecting line 116 extends along a first direction. As also shown, a plurality of first fine gates 112 are spaced apart along the first direction, allowing the first connecting line 116 to extend along the first direction so that all the first fine gates 112 can be electrically connected to the first connecting line 116. This also reduces the required length of the first connecting line 116, lowering costs.

[0046] Meanwhile, the second connecting line 117 extends along the first direction, as shown in the figure. Multiple second fine gates 113 are spaced apart along the first direction, allowing the second connecting line 117 to extend along the first direction so that all the second fine gates 113 can be electrically connected to the second connecting line 117. This also reduces the required length of the second connecting line 117, lowering costs.

[0047] In the above embodiments, the diameter D1 of the first connecting line 116 satisfies D1≤200μm. For example, the diameter D1 of the first connecting line 116 can be 20μm, 50μm, 100μm, 150μm, 200μm, etc., and the diameter D2 of the second connecting line 117 satisfies D1≤200μm. For example, the diameter D2 of the second connecting line 117 can be 20μm, 50μm, 100μm, 150μm, 200μm, etc. By limiting the diameters of the first connecting line 116 and the second connecting line 117, the current transmission effect of the first connecting line 116 and the second connecting line 117 is improved.

[0048] Furthermore, in other embodiments, the diameters of the first connecting line 116 and the second connecting line 117 can be other values, which can be adaptively adjusted according to actual conditions. The diameters of the first connecting line 116 and the second connecting line 117 can be the same or different.

[0049] In some embodiments, such as Figure 2 and Figure 4 As shown, the back contact cell 11 is also provided with an insulating layer 118, which covers at least a portion of the structure of the first grid 112 and the second grid 113.

[0050] like Figure 4 As shown, the insulating layer 118 is provided with a first clearance hole 118a, and the first connecting line 116 is connected to the first fine grid 112 through the first clearance hole 118a. Specifically, along the thickness direction of the back contact cell 11, the insulating layer 118 simultaneously covers the first fine grid 112 and the second fine grid 113. The first clearance hole 118a is provided in the region of the insulating layer 118 corresponding to the first fine grid 112. The first connecting line 116 can be electrically connected to the first fine grid 112 through the first clearance hole 118a, and the first connecting line 116 and the second fine grid 113 can be isolated by the insulating layer 118 to avoid short circuits.

[0051] Meanwhile, the insulating layer 118 is also provided with a second clearance hole 118b, through which the second connecting line 117 is connected to the second fine grid 113. Specifically, along the thickness direction of the back contact cell 11, the insulating layer 118 covers both the first fine grid 112 and the second fine grid 113. A second clearance hole 118b is provided in the area of ​​the insulating layer 118 corresponding to the second fine grid 113. The second connecting line 117 can be electrically connected to the second fine grid 113 through the second clearance hole 118b, and the second connecting line 117 and the first fine grid 112 can be isolated by the insulating layer 118 to avoid short circuits.

[0052] The width of the first clearance hole 118a can be the same as the width of the first doped region 119, so that the first connecting line 116 can be electrically connected to the first fine gate 112 through the first clearance hole 118a, and the width of the second clearance hole 118b can be the same as the width of the second doped region 120, so that the second connecting line 117 can be electrically connected to the second fine gate 113 through the second clearance hole 118b.

[0053] In some embodiments, such as Figure 2 , Figure 5 and Figure 6 As shown ( Figure 6 The dashed line in the middle shows the structure of the first solder strip 2 and the second solder strip 3. Multiple back-contact cells 11 in the cell layer of the photovoltaic module are arranged along the second direction and electrically connected to form a cell string 1.

[0054] The photovoltaic module also includes a first solder strip 2, which is located at the end of the cell string 1 and is used to connect the first solder grid 114 or the second solder grid 115. Taking the cell string 1 as an example, which includes three back contact cells 11 arranged sequentially along the second direction, the three back contact cells 11 can be the first back contact cell 122, the second back contact cell 123, and the third back contact cell 124, respectively. The first solder strip 2 is used to connect with the first solder grid 114 of the first back contact cell 122 and the second solder grid 115 of the third back contact cell 124. With this design, the first solder strip 2 can be set in the end area of ​​the back contact cell 11, reducing the stress on the middle area of ​​the back contact cell 11, reducing the risk of warping of the back contact cell 11, and also reducing the shading of the back light-receiving area of ​​the back contact cell 11, improving the absorption of reflected or scattered light on the back of the back contact cell 11, and improving the bifaciality of the back contact cell 11.

[0055] The photovoltaic module also includes a second solder strip 3, which is located between adjacent back contact cells 11 and is used to connect the first weld gate 114 and the second weld gate 115 of the adjacent back contact cells 11. The second solder strip 3 may be T-shaped so that it can be used to connect the second weld gate 115 of the first back contact cell 122 and the first weld gate 114 of the second back contact cell 123. The second solder strip 3 can also be used to connect the second weld gate 115 of the second back contact cell 123 and the first weld gate 114 of the third back contact cell 124 to realize the series connection of the first back contact cell 122, the second back contact cell 123 and the third back contact cell 124.

[0056] This design allows the second solder strips 3 to be positioned at the end regions of the back contact cell 11, reducing stress on the middle region of the back contact cell 11, lowering the risk of warping, and also reducing shading of the back light-receiving area of ​​the back contact cell 11, improving the absorption of reflected or scattered light on the back of the back contact cell 11, and increasing the bifaciality of the back contact cell 11.

[0057] In the above embodiments, such as Figure 2 , Figure 6 and Figure 7 As shown, the minimum distance L6 between the end of the first weld gate 114 or the end of the second weld gate 115 and the first solder strip 2 is ≥30μm. For example, in the corresponding area of ​​the first back contact cell 122, the minimum distance between the first weld gate 114 and the first solder strip 2 is ≥30μm, specifically 30μm, 35μm, 40μm, 45μm, 50μm, etc. This can increase the contact area between the first solder strip 2 and the first weld gate 114, improve the current collection and transmission effect, and also improve the connection reliability between the first solder strip 2 and the first weld gate 114. Meanwhile, the arrangement of the second weld gate 115 and the first solder strip 2 is the same as described above, and will not be repeated here.

[0058] like Figure 2 , Figure 6 and Figure 8 As shown, the minimum distance L7 between the end of the first weld gate 114 and the end of the second weld gate 115 and the second weld strip 3 is ≥30μm. For example, the minimum distance L7 between the second weld strip 3 between the first back contact cell 122 and the second back contact cell 123, the minimum distance between the second weld gate 115 of the first back contact cell 122 and the second weld strip 3, and the minimum distance between the first weld gate 114 of the second back contact cell 123 and the second weld strip 3 are both ≥30μm. Specifically, it can be 30μm, 35μm, 40μm, 45μm, 50μm, etc. This can increase the contact area between the second weld strip 3 and the first weld gate 114 and the second weld gate 115, improve the current collection and transmission effect, and also improve the connection reliability between the second weld strip 3 and the first weld gate 114 and the second weld gate 115. Meanwhile, the minimum distance between the second weld grid 115 of the first back contact cell 122 and the second weld strip 3, and the minimum distance between the first weld grid 114 of the second back contact cell 123 and the second weld strip 3, both satisfy ≥30μm and have the technical effects described above, which will not be elaborated here.

[0059] Furthermore, in other embodiments, L6 and L7 can also be other specific values, which can be adaptively adjusted according to the actual situation. L6 and L7 can be the same or different.

[0060] This application embodiment also provides a method for preparing a back contact battery cell 11, which is used to prepare the above-mentioned back contact battery cell 11. The preparation method includes the following steps: S11: Fabrication of silicon substrate 111; S12: A first doped region 119, a second doped region 120, and a spacer region 121 are formed on the back side of the silicon substrate 111; S13: A first fine gate 112 and a first weld gate 114 are prepared in the first doped region 119, and a second fine gate 113 and a second weld gate 115 are prepared in the second doped region 120; Along a first direction, a first fine gate 112 and a second fine gate 113 are spaced apart. A first bond gate 114 and a second bond gate 115 are respectively disposed in diagonal regions of the silicon substrate 111. The first bond gate 114 includes a first extension 114a and a second extension 114b that are perpendicular to each other, and the second bond gate 115 includes a third extension 115a and a fourth extension 115b that are perpendicular to each other. The first extension 114a and the third extension 115a extend along the first direction, and the second extension 114b and the fourth extension 115b extend along a second direction. The first fine gate 112 is connected to the first extension 114a, and the second fine gate 113 is connected to the third extension 115a.

[0061] This design approach enables a through-type design of the first fine gate 112 and the second fine gate 113, increasing the coverage area of ​​the first fine gate 112 and the second fine gate 113 and improving carrier collection efficiency.

[0062] In some embodiments, after step S13 described above, the method for preparing the back contact cell 11 further includes the following steps: S14: An insulating layer 118 is prepared on the back side of the silicon substrate 111; S15: A first clearance hole 118a and a second clearance hole 118b are formed on the insulating layer 118, and the first clearance hole 118a and the second clearance hole 118b are spaced apart along the first direction. S16: A first connecting line 116 and a second connecting line 117 are prepared on the insulating layer 118. The first connecting line 116 is connected to a plurality of first fine gates 112 through a first clearance hole 118a, and the second connecting line 117 is connected to a plurality of second fine gates 113 through a second clearance hole 118b.

[0063] In this embodiment, after the first fine gate 112, the first weld gate 114, the second fine gate 113, and the second weld gate 115 are fabricated, an insulating layer 118 is coated on the back side of the silicon substrate 111. During coating, a certain number of openings are retained to form the first clearance hole 118a and the second clearance hole 118b, thereby realizing the electrical connection between the first connecting line 116 and the first fine gate 112, the second connecting line 117 and the second fine gate 113, and simultaneously realizing the isolation between the first connecting line 116 and the second fine gate 113, and between the second connecting line 117 and the first fine gate 112. The insulating layer 118 can be coated on the entire back side of the silicon substrate 111, or the insulating layer 118 can be coated only on the areas corresponding to the first fine gate 112 and the second fine gate 113.

[0064] This application embodiment also provides a fabrication apparatus for fabricating the back contact solar cell 11 in the above embodiments. The fabrication apparatus includes a texturing module, a doping module, an etching module, a passivation module, and a printing module. The texturing module is used to clean and texturize the silicon substrate 111, and may specifically include an RCA cleaning machine and an alkaline texturing machine. The doping module is used to generate a first doped region 119 and a second doped region 120, which can be prepared by ion implantation or mask diffusion. When using ion implantation, the doping module may include an ion implanter; when using mask diffusion, the doping module may include a photolithography machine and a diffusion furnace. The etching module is used to form a spacer region 121, and may include a laser etching machine. The passivation module is used to form a passivation layer on the back side of the silicon substrate 111, and may include an ALD device or a PECVD device. The printing module is used to prepare the first fine grid 112, the first weld grid 114, the second fine grid 113 and the second weld grid 115. It can be prepared by screen printing or by electroplating.

[0065] In some embodiments, the fabrication apparatus may further include a coating module. After the first fine gate 112, the first weld gate 114, the second fine gate 113, and the second weld gate 115 are fabricated, the coating module can be used to coat an insulating adhesive on the back side of the silicon substrate 111 to form an insulating layer 118. After the coating is completed, the printing module can also be used to fabricate the first connecting line 116 and the second connecting line 117.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back contact battery cell, characterized in that, The back contact cell includes a silicon substrate and a plurality of first fine gates and a plurality of second fine gates located on the back side of the silicon substrate; the first fine gates and the second fine gates are spaced apart along a first direction; The back contact solar cell further includes a first weld gate and a second weld gate for connection with the solder strip. The first weld gate and the second weld gate are respectively disposed in diagonal regions of the silicon substrate. The first weld gate includes a first extension and a second extension that are perpendicular to each other, and the second weld gate includes a third extension and a fourth extension that are perpendicular to each other. The first extension and the third extension extend along a first direction, and the second extension and the fourth extension extend along a second direction. The back contact solar cell further includes a first connecting line and a second connecting line. Wherein, the first fine gate is connected to the first extension, and the second fine gate is connected to the third extension; the first connecting line connects multiple first fine gates and second extensions, and the second connecting line connects multiple second fine gates and the fourth extension.

2. The back contact battery cell according to claim 1, characterized in that, The first connecting line and the second connecting line extend along the first direction.

3. The back contact battery cell according to claim 1, characterized in that, The back contact cell is further provided with an insulating layer, which covers at least a portion of the structure of the first grid and the second grid; The insulating layer is provided with a first clearance hole and a second clearance hole. The first connecting line is connected to the first fine grid through the first clearance hole, and the second connecting line is connected to the second fine grid through the second clearance hole.

4. The back contact battery cell according to claim 1, characterized in that, The diameter D1 of the first connecting line satisfies D1≤200μm, and the diameter D2 of the second connecting line satisfies D2≤200μm.

5. The back contact battery cell according to any one of claims 1-4, characterized in that, The minimum distance L1 between the first weld gate and the end of the silicon substrate satisfies 5μm≤L1≤30μm, and the minimum distance L2 between the second weld gate and the end of the silicon substrate satisfies 5μm≤L2≤30μm.

6. The back contact battery cell according to any one of claims 1-4, characterized in that, The width L3 of the first weld gate satisfies 50μm≤L3≤300μm, and the width L4 of the second weld gate satisfies 50μm≤L4≤300μm.

7. The back contact battery cell according to any one of claims 1-4, characterized in that, The back side of the silicon substrate is provided with a first doped region and a second doped region, the first fine gate and the first bond gate are disposed in the first doped region, and the second fine gate and the second bond gate are disposed in the second doped region; There is a spacer region between the first doped region and the second doped region, and the width of the spacer region satisfies 5μm≤L5≤50μm.

8. A method for preparing a back contact solar cell, characterized in that, The method for preparing the back contact battery cell includes: Preparation of silicon substrates; A first doped region, a second doped region, and a spacer region are formed on the back side of the silicon substrate; A first fine gate and a first weld gate are prepared in the first doped region, and a second fine gate and a second weld gate are prepared in the second doped region; An insulating layer is prepared on the back side of the silicon substrate; A first clearance hole and a second clearance hole are formed on the insulating layer, and the first clearance hole and the second clearance hole are spaced apart along a first direction; A first connecting line and a second connecting line are formed on the insulating layer. The first connecting line is connected to a plurality of first fine gates through the first clearance hole, and the second connecting line is connected to a plurality of second fine gates through the second clearance hole. Wherein, along the first direction, the first fine gate and the second fine gate are spaced apart; the first bond gate and the second bond gate are respectively disposed in the diagonal region of the silicon substrate; the first bond gate includes a first extension and a second extension that are perpendicular to each other, and the second bond gate includes a third extension and a fourth extension that are perpendicular to each other; the first extension and the third extension extend along the first direction, and the second extension and the fourth extension extend along the second direction; the first fine gate is connected to the first extension, and the second fine gate is connected to the third extension; the first connecting line connects a plurality of the first fine gates and the second extensions, and the second connecting line connects a plurality of the second fine gates and the fourth extensions.

9. A preparation apparatus, characterized in that, The fabrication equipment is used to fabricate the back contact battery cell according to any one of claims 1-7, and the fabrication equipment comprises: A texturing module is used to clean and texturize the silicon substrate; The doping module is used to generate the first doped region and the second doped region. Etching module, used to form spacer regions; A passivation module for forming a passivation layer on the back side of the silicon substrate; A printing module is used to fabricate the first fine gate, the first weld gate, the second fine gate, and the second weld gate.

10. A photovoltaic module, characterized in that, The photovoltaic module includes a plurality of back-contact solar cells as described in any one of claims 1-7, wherein the plurality of back-contact solar cells are arranged along the second direction and electrically connected to form a cell string; The photovoltaic module further includes a first solder strip and a second solder strip. The first solder strip is located at the end of the cell string and is used to connect the first grid or the second grid. The second solder strip is located between adjacent back contact cells and is used to connect the first grid and the second grid of adjacent back contact cells.

11. The photovoltaic module according to claim 10, characterized in that, The minimum distance L6 between the end of the first weld gate or the end of the second weld gate and the first weld strip is ≥30μm; the minimum distance L7 between the end of the first weld gate and the end of the second weld gate and the second weld strip is ≥30μm.

Citation Information

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