Solar cell and method of manufacturing the same, solar cell module, photovoltaic device

Abstract

This application provides a solar cell, a method for fabricating the same, a solar cell module, and a photovoltaic device. The solar cell comprises a substrate, a doped polycrystalline silicon layer, a passivation layer, a barrier layer, and a perovskite top cell layer, stacked sequentially. The passivation layer has a groove exposed on the surface of the substrate. The solar cell also includes conductive grid lines disposed within the groove, and the barrier layer covers the conductive grid lines. The barrier layer comprises a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer. This application achieves efficient carrier transport between the top and bottom cells by setting a groove on the passivation layer and placing the conductive grid lines within the groove, thereby improving the working performance of the solar cell. Furthermore, by setting a barrier layer composed of a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer to isolate the conductive grid lines from the perovskite top cell layer, the problem of poor interface stability is solved, extending the lifespan of the solar cell.

Description

Technical Field

[0001] This application belongs to the field of solar cell technology, specifically relating to solar cells and their preparation methods, solar cell modules, and photovoltaic equipment. Background Technology

[0002] For TBC-perovskite tandem solar cells, related technologies simply deposit a transparent conductive layer and a perovskite layer on the front side of the TBC without designing a dedicated carrier interconnection structure. The conductive grid lines still use traditional pure silver screen printing, and no protective structure is designed for the interface characteristics between the perovskite and TBC. This results in low interconnection efficiency between the top and bottom cells, severe current mismatch, and the conductive grid lines are in direct or close contact with the perovskite layer without an effective barrier structure, leading to poor interface stability and rapid lifespan decay. Summary of the Invention

[0003] In view of this, the first aspect of this application provides a solar cell, the solar cell comprising a substrate, a doped polycrystalline silicon layer, a passivation layer, a barrier layer, and a perovskite top cell layer stacked sequentially, the passivation layer having a receiving groove exposed on the surface of the substrate, the solar cell further comprising conductive grid lines disposed in the receiving groove, and the barrier layer covering the conductive grid lines; The barrier layer comprises a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer.

[0004] In this configuration, along the arrangement direction from the substrate to the passivation layer, the self-assembled monolayer, the titanium dioxide layer, and the 2D perovskite layer are sequentially stacked. Alternatively, along the arrangement direction from the substrate to the passivation layer, the 2D perovskite layer, the titanium dioxide layer, and the self-assembled monolayer are stacked sequentially.

[0005] The material of the self-assembled monolayer includes at least one of 3-mercaptopropionic acid and trimethyl phosphate; And / or, the material of the 2D perovskite layer includes (PEA)2PbI4.

[0006] The thickness of the self-assembled monolayer is 3 nm to 4 nm. And / or, the thickness of the titanium dioxide layer is 30nm~40nm; And / or, the thickness of the 2D perovskite layer is 10nm~15nm; And / or, the total thickness of the barrier layer is 45nm~60nm.

[0007] The perovskite top cell layer is a 2D and 3D composite perovskite layer, and the band gap of the 2D and 3D composite perovskite layer is 1.65eV~1.75eV.

[0008] The materials of the 2D and 3D composite perovskite layer include MAI, FAI, and CsBr; wherein the molar ratio of MAI, FAI, and CsBr is (0.5~0.7):(0.25~0.45):(0.04~0.06).

[0009] The conductive grid line includes a stacked metal seed layer and an electroplated metal layer, wherein the material of the electroplated metal layer includes at least one of copper-tin alloy and silver-copper alloy.

[0010] A second aspect of this application provides a solar cell module comprising the solar cell provided in the first aspect of this application.

[0011] A third aspect of this application provides a photovoltaic device, which includes a solar cell module as provided in the second aspect of this application.

[0012] The fourth aspect of this application provides a method for preparing a solar cell, the method comprising: Provide substrate; A doped polysilicon layer is formed on the substrate; A passivation layer is formed on the side of the doped polysilicon layer opposite to the substrate, the passivation layer having a receiving groove exposed on the surface of the substrate; A conductive grid line is formed within the receiving groove; A barrier layer is formed covering the conductive gate lines, the barrier layer comprising a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer; A perovskite top cell layer is formed on the side of the barrier layer opposite to the substrate.

[0013] The solar cells, their fabrication methods, solar cell modules, and photovoltaic devices provided in this application achieve efficient carrier transport between the top and bottom cells by setting accommodating grooves on the passivation layer and placing conductive grid lines within the accommodating grooves, thereby improving the working performance of the solar cells. Furthermore, by setting a barrier layer composed of a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer, the conductive grid lines are isolated from the perovskite top cell layer, thus solving the problem of poor interface stability and extending the lifespan of the solar cells. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0015] Figure 1 This is a schematic diagram of the structure of a solar cell provided in one embodiment of this application.

[0016] Figure 2This is a schematic diagram of the structure of a solar cell provided in one embodiment of this application.

[0017] Figure 3 This is a schematic flowchart illustrating a method for fabricating a solar cell according to an embodiment of this application.

[0018] Labeling: Solar cell 1, substrate 11, doped polycrystalline silicon layer 12, passivation layer 13, containment trench 131, barrier layer 14, self-assembled monolayer 141, titanium dioxide layer 142, 2D perovskite layer 143, perovskite top cell layer 15, conductive grid line 16, metal seed layer 161, electroplated metal layer 162. Detailed Implementation

[0019] The following are preferred embodiments of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

[0020] Before introducing the technical solution of this application, let's go over the technical issues in related technologies in detail.

[0021] Traditional TBC and tandem cell metallization relies on pure silver grid lines, with silver consumption reaching 65mg / cell to 80mg / cell, accounting for 30% to 35% of the total cell cost. This results in high silver consumption costs and limited potential for cost reduction. Although existing electroplating copper technology can reduce silver consumption, pure copper grid lines are prone to ion diffusion and have poor welding reliability, with welding tensile strength ≤1.5N / mm, which cannot meet the needs of module mass production.

[0022] Existing TBC-perovskite stacks lack a dedicated interconnect structure, hindering the efficient injection of perovskite carriers into the TBC bottom cell. Current collection efficiency is only 80%–85%, resulting in low interconnect efficiency between the top and bottom cells and severe current mismatch. Furthermore, the perovskite and TBC bandgap matching is poor; the perovskite bandgap is 1.55 eV–1.60 eV, leading to a current mismatch rate of 10%–15%, resulting in a stack efficiency of ≤30%.

[0023] In existing technologies, conductive grid lines are typically made of pure silver or pure copper. These grid lines are in direct or close contact with the perovskite layer without effective barrier structures, resulting in poor interface stability and rapid lifespan degradation. Specifically, firstly, ion diffusion is rapid; after 1000 hours of damp heat testing, the copper / silver ion concentration in the perovskite layer is ≥2×10⁻⁶. 16 atoms / cm 3 Second, significant chemical corrosion occurs, with residual electroplating reagents reacting with perovskite precursors, resulting in film crystallinity ≤80%. Third, thermal expansion mismatch occurs, with the thermal expansion coefficients of the metal and perovskite differing by 5 to 6 times, and the interface delamination rate ≥40% after temperature cycling. Finally, the efficiency decays by 30% to 50% after 1000 hours of damp heat testing, far below the industrial lifespan requirements.

[0024] In view of this, in order to solve the above problems, please refer to the following: Figures 1-2 This embodiment provides a solar cell 1, which includes a substrate 11, a doped polycrystalline silicon layer 12, a passivation layer 13, a barrier layer 14, and a perovskite top cell layer 15 stacked sequentially. The passivation layer 13 has a receiving groove 131 exposed on the surface of the substrate 11. The solar cell 1 also includes conductive grid lines 16 disposed in the receiving groove 131, and the barrier layer 14 covers the conductive grid lines 16.

[0025] The barrier layer 14 includes a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143.

[0026] Optionally, solar cell 1 is a TBC-perovskite tandem cell.

[0027] The substrate 11 serves multiple functions, including light absorption, carrier generation, carrier transport, and mechanical support, supporting the entire thin film layer and electrodes of the battery. Optionally, the substrate 11 is a silicon wafer. More preferably, the substrate 11 is an n-type silicon wafer.

[0028] Furthermore, the solar cell 1 also includes a tunneling oxide layer disposed between the substrate 11 and the doped polycrystalline silicon layer 12, the doped polycrystalline silicon layer 12 including a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer.

[0029] The substrate 11, the tunneling oxide layer, the doped polysilicon layer 12, and the passivation layer 13 are stacked sequentially.

[0030] The tunneling oxide layer is used to achieve selective carrier tunneling. Optionally, the thickness of the tunneling oxide layer is 1 nm to 2 nm, specifically, for example, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, or 2 nm. Optionally, the material of the tunneling oxide layer includes silicon dioxide.

[0031] Optionally, a back-side thermal oxidation process is used to grow a 1.5 nm SiO2 tunnel oxide layer on the substrate 11, with an oxidation temperature of 600 °C and an oxygen flow rate of 200 sccm.

[0032] The P-type polysilicon layer is used to form a PN junction and collect holes. Optionally, the P-type polysilicon layer is a boron-doped polysilicon layer. Optionally, the thickness of the P-type polysilicon layer is 280nm~320nm, specifically, examples include 280nm, 285nm, 290nm, 295nm, 300nm, 305nm, 310nm, 315nm, or 320nm, etc.

[0033] The N-type polysilicon layer is used to achieve field passivation and electron collection. Optionally, the N-type polysilicon layer is a phosphorus-doped polysilicon layer. Optionally, the thickness of the N-type polysilicon layer is 180nm~220nm, specifically, examples include 180nm, 185nm, 190nm, 195nm, 200nm, 205nm, 210nm, 215nm, or 220nm, etc.

[0034] Optionally, a 300 nm intrinsic polycrystalline silicon layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature of 620 °C and a silane flow rate of 50 sccm.

[0035] Subsequently, boron doping was performed using a single-mask laser with a wavelength of 532 nm, a pulse width of 50 ns, and a spot energy of 0.6 J / cm². 2 A P-type polycrystalline silicon layer is formed, which has a P-type polycrystalline silicon region with a width of 500 μm and a boron doping concentration of 4 × 10⁻⁶. 19 cm -3 .

[0036] Then, a 200 nm phosphorus-doped polycrystalline silicon layer was deposited using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 450 °C and a phosphine flow rate of 30 sccm. Laser grooving was then performed on the phosphorus-doped polycrystalline silicon layer at a wavelength of 355 nm and a laser power of 10 W, forming an N-type polycrystalline silicon region and an isolation region. The width of the N-type polycrystalline silicon region was 500 μm, and the phosphorus doping concentration was 2 × 10⁻⁶. 20 cm -3 The width of the isolation region is 60 μm; finally, the doping is activated by annealing at 950℃ for 30 min.

[0037] The passivation layer 13 is used to achieve chemical passivation and field-effect passivation. Optionally, the material of the passivation layer 13 includes silicon nitride.

[0038] Optionally, the thickness of the passivation layer 13 is 60nm~80nm, specifically for example, 60nm, 62nm, 64nm, 66nm, 68nm, 70nm, 72nm, 74nm, 76nm, 78nm, or 80nm.

[0039] Optionally, the refractive index of the passivation layer 13 is 2.0 to 2.2.

[0040] Optionally, SiN xThe passivation layer 13 was deposited using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) processes at a deposition temperature of 400℃, a furnace tube pressure of 2 torr to 5 torr, a silane to ammonia flow ratio of 1:3, an RF power of 300W, and a surface recombination velocity of 85cm / s. Furthermore, the corresponding areas of the gate lines were marked using photolithography, and window positions for the accommodating groove 131 were reserved to ensure alignment of the subsequent conductive gate lines 16 with the P-type and N-type polysilicon regions, with an alignment accuracy of ±2μm.

[0041] The passivation layer 13 has a receiving trench 131 that penetrates the passivation layer 13, the doped polycrystalline silicon layer 12, and the tunneling oxide layer along the thickness direction of the solar cell 1, and exposes the substrate 11. The position of the receiving trench 131 corresponds to the P-type polycrystalline silicon region and the N-type polycrystalline silicon region of the doped polycrystalline silicon layer 12, so that the conductive grid lines 16 subsequently formed in the receiving trench 131 can be aligned with the P-type polycrystalline silicon region and the N-type polycrystalline silicon region.

[0042] Optionally, the line width of the receiving groove 131 is 25μm~35μm, and preferably, the line width of the receiving groove 131 is 30μm.

[0043] Optionally, the depth of the receiving groove 131 is 80nm~100nm, and preferably, the depth of the receiving groove 131 is 90nm.

[0044] Optionally, the receiving groove 131 is prepared using an ultraviolet laser.

[0045] Further optionally, the wavelength of the ultraviolet laser is 345nm~365nm, and preferably, the wavelength of the ultraviolet laser is 355nm.

[0046] And / or, the power of the ultraviolet laser is 6W~10W, preferably, the power of the ultraviolet laser is 8W.

[0047] And / or, the scanning speed of the ultraviolet laser is 700 mm / s to 900 mm / s, preferably, the scanning speed of the ultraviolet laser is 800 mm / s.

[0048] For example, an ultraviolet laser with a wavelength of 355nm, a power of 8W, and a scanning speed of 800mm / s is used to open a window on the passivation layer 13, precisely penetrating the passivation layer 13 to expose the substrate 11. The opening deviation is ≤1μm, and there is no damage to the substrate 11, resulting in an accommodating groove 131 with a linewidth of 30μm and a depth of 90nm.

[0049] Furthermore, after opening the window, the battery semi-finished product is cleaned with plasma. The plasma is Ar gas, the cleaning power is 100W, and the cleaning time is 30s, in order to remove residual impurities in the windowed area of ​​the accommodating tank 131 and improve the reliability of subsequent ohmic contacts.

[0050] In one embodiment, the conductive gate line 16 includes a stacked metal seed layer 161 and an electroplated metal layer 162, wherein the material of the electroplated metal layer 162 includes at least one of copper-tin alloy and silver-copper alloy.

[0051] For example, the electroplated metal layer 162 includes a copper-tin alloy electroplated layer.

[0052] For example, the electroplated metal layer 162 includes a silver-copper alloy electroplated layer.

[0053] For example, the electroplated metal layer 162 includes a copper-tin alloy electroplated layer and a silver-copper alloy electroplated layer.

[0054] Optionally, the tin content in the copper-tin alloy is 0.5% to 2% to suppress the diffusion of copper ions.

[0055] Optionally, the copper content in the silver-copper alloy is 1% to 3% to suppress copper ion diffusion.

[0056] The metal seed layer 161 includes at least one of a titanium seed layer and a silver seed layer. The metal seed layer 161 can improve the adhesion between the gate line and the windowed area of ​​the receiving groove 131, ensuring that the adhesion between the electroplated metal layer 162 and the windowed area of ​​the receiving groove 131 is ≥5 N / mm. 2 .

[0057] For example, metal seed layer 161 includes a titanium seed layer.

[0058] For example, the metal seed layer 161 includes a silver seed layer.

[0059] For example, the metal seed layer 161 includes a titanium seed layer and a silver seed layer.

[0060] Optionally, the thickness of the titanium seed layer is 6nm to 10nm, specifically for example, 6nm, 6.5nm, 7nm, 7.5nm, 8nm, 8.5nm, 9nm, 9.5nm, or 10nm.

[0061] Optionally, the thickness of the silver seed layer is 70nm~90nm, specifically for example, 70nm, 72nm, 74nm, 76nm, 78nm, 80nm, 82nm, 84nm, 86nm, 88nm, or 90nm.

[0062] Optionally, a titanium seed layer and a silver seed layer are used by magnetron sputtering, with a vacuum degree of 5×10⁻⁶. -4 Pa, the thickness of the titanium seed layer is 8 nm, and the thickness of the silver seed layer is 80 nm.

[0063] Then, the semi-finished battery was activated using argon-oxygen plasma to reduce contact resistance. The argon to oxygen flow ratio was 9:1, the activation power was 100W, and the activation time was 60s, which reduced the contact resistance to <3mΩ·cm. 2 .

[0064] Next, patterned copper-tin alloy main gate and fine gate are electroplated; the electroplating solution includes 90 g / L copper sulfate, 1 g / L stannous sulfate, 60 g / L sulfuric acid, and 0.3 g / L brightener, with a current density of 3 A / dm³. 2 The electroplating temperature was 30℃ and the electroplating time was 15min to obtain a fine grid line width of 30μm and a thickness of 12μm.

[0065] Subsequently, acetone was used to remove the adhesive for 10 minutes, followed by vacuum drying at a vacuum degree of 10. -3 The drying temperature was 100℃ and the drying time was 40 min to obtain a battery semi-finished product with a residual water content of <40 ppm, thus avoiding corrosion of the subsequent perovskite layer.

[0066] The barrier layer 14 is used to isolate the conductive grid lines 16 from the perovskite top cell layer 15, solving the problem of poor interface stability and extending the service life of the solar cell 1.

[0067] The barrier layer 14 includes a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143.

[0068] The self-assembled monolayer 141 can also be called a SAMs layer.

[0069] Furthermore, along the arrangement direction from the substrate 11 to the passivation layer 13, the self-assembled monolayer 141, the titanium dioxide layer 142, and the 2D perovskite layer 143 are sequentially stacked.

[0070] Alternatively, along the arrangement direction from the substrate 11 to the passivation layer 13, the 2D perovskite layer 143, the titanium dioxide layer 142, and the self-assembled monolayer 141 are stacked sequentially.

[0071] Furthermore, the material of the self-assembled monolayer 141 includes at least one of 3-mercaptopropionic acid and trimethyl phosphate.

[0072] And / or, the material of the 2D perovskite layer 143 includes (PEA)2PbI4.

[0073] Furthermore, the thickness of the self-assembled monolayer 141 is 3nm to 4nm, specifically for example, 3nm, 3.2nm, 3.4nm, 3.6nm, 3.8nm, or 4nm, etc.

[0074] And / or, the thickness of the titanium dioxide layer 142 is 30nm~40nm, specifically for example, 30nm, 32nm, 34nm, 36nm, 38nm, or 40nm, etc.

[0075] And / or, the thickness of the 2D perovskite layer 143 is 10nm~15nm, specifically for example, 10nm, 11nm, 12nm, 13nm, 14nm, or 15nm, etc.

[0076] And / or, the total thickness of the barrier layer 14 is 45nm~60nm, specifically for example, 45nm, or 46nm, or 47nm, or 48nm, or 49nm, or 50nm, or 52nm, or 54nm, or 56nm, or 58nm, or 60nm, etc.

[0077] Optionally, in-situ deposition can be performed within the same vacuum chamber to avoid oxidation of the electroplated grid lines.

[0078] Optionally, the self-assembled monolayer 141 is prepared as follows: it is soaked in 0.05 mol / L 3-mercaptopropionic acid solution and anhydrous ethanol solvent for 30 min to form a 3 nm SAMs layer.

[0079] Titanium dioxide layer 142 was prepared using atomic layer deposition (ALD) process: titanium tetrachloride was used as the titanium source, deionized water was used as the oxygen source, the deposition temperature was 100℃, and the growth rate was 0.1 nm / cycle to form a 30 nm titanium dioxide layer 142.

[0080] 2D perovskite layer 143 was prepared by spin coating: 0.1 mol / L (PEA)2PbI4 solution was used, the spin coating speed was 4000 rpm, and the spin coating time was 30 s; then, it was annealed at 90℃ for 10 min to form a 10 nm 2D perovskite layer 143.

[0081] Ultimately, the total thickness of the barrier layer 14 is 43 nm, and the ion permeability is <8 × 10⁻⁶. -11 cm 2 / s.

[0082] The perovskite top cell layer 15 is used to filter out high-energy photons and allow low-energy photons to pass through to the bottom cell. The perovskite top cell layer 15 and the bottom cell work together to improve the performance of the solar cell 1.

[0083] The perovskite top cell layer 15 is a 2D and 3D composite perovskite layer, and the band gap of the 2D and 3D composite perovskite layer is 1.65eV~1.75eV.

[0084] Specific examples of the band gap of 2D and 3D composite perovskite layers include 1.65 eV, 1.66 eV, 1.67 eV, 1.68 eV, 1.69 eV, 1.70 eV, 1.71 eV, 1.72 eV, 1.73 eV, 1.74 eV, and 1.75 eV.

[0085] Furthermore, the materials of the 2D and 3D composite perovskite layer include MAI, FAI, and CsBr; wherein the molar ratio of MAI, FAI, and CsBr is (0.5~0.7):(0.25~0.45):(0.04~0.06).

[0086] Optionally, a 400 nm PbI2 underlayer is vacuum-deposited, wherein the vacuum level is 5 × 10⁻⁶. -4 The deposition rate was 0.3 nm / s, and the substrate temperature was 70 °C. Then, the substrate was immersed in a mixed solution at room temperature for 10 min. The mixed solution consisted of isopropanol-based MAI, FAI, and CsBr, with a molar ratio of 0.6:0.35:0.05 and a concentration of 0.1 mol / L. Next, the substrate was annealed at 110 °C for 30 min to form a 500 nm 2D / 3D composite perovskite layer with a band gap of 1.70 eV and a crystallinity of 92%.

[0087] Optionally, the solar cell 1 also includes an electrode layer disposed on the side of the perovskite top cell layer 15 facing away from the substrate 11.

[0088] Alternatively, the electrode layer may be made of ITO.

[0089] Optionally, a 100 nm ITO electrode layer is formed by magnetron sputtering. The sheet resistance of the electrode layer is 15 Ω / □, and the light transmittance of the electrode layer is 86%.

[0090] Optionally, an Ag mesh is laser-written onto the back side of substrate 11. The Ag mesh has a linewidth of 10 μm, a spacing of 500 μm, and a thickness of 60 nm. Then, a 30 nm NiOx hole transport layer is spin-coated and annealed at 150 °C for 20 min. Next, a 50 nm PCBM electron transport layer is formed by vacuum evaporation. Following this, Cu and Ag back electrodes are magnetron sputtered, with a Cu layer of 180 nm and an Ag layer of 80 nm. Finally, a double-glass encapsulation is performed using POE encapsulant with a water vapor permeability of <10%. -5 g / (m 2 • 24h), vacuum lamination at 140℃ for 18min, thereby completing the encapsulation of solar cell 1.

[0091] Optionally, the silver consumption of solar cell 1 is ≤12mg / cell.

[0092] And / or, the tandem conversion efficiency of solar cell 1 is ≥33.2%.

[0093] And / or, the efficiency degradation of solar cell 1 is ≤9.8% after 1000h of damp heat test at 85℃ / 85%RH.

[0094] And / or, the current collection efficiency of solar cell 1 is ≥95.8%.

[0095] And / or, the current mismatch rate of solar cell 1 is ≤4.8%.

[0096] In summary, the solar cell 1 provided in this application achieves efficient carrier transport between the top and bottom cells by setting a receiving groove 131 on the passivation layer 13 and placing the conductive grid line 16 in the receiving groove 131, thereby improving the working performance of the solar cell 1. Furthermore, by setting a barrier layer 14 composed of a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143, the conductive grid line 16 is isolated from the perovskite top cell layer 15, thereby solving the problem of poor interface stability and extending the service life of the solar cell 1.

[0097] This application adopts a dedicated carrier interconnect structure design for TBC front side: an integrated structure with electroplated copper-tin alloy fine gate, silver-copper alloy main gate and laser-received slot 131 window, which solves the core pain point that traditional TBC cannot efficiently interconnect with perovskite, and achieves a balance between low silver consumption and high welding reliability.

[0098] This application also adopts a composite barrier layer 14 design. The barrier layer 14 achieves triple functions of ion diffusion blocking, chemical corrosion protection, and thermal expansion mismatch mitigation through the synergistic effect of the three-layer structure, thus solving the industry problem of poor interface stability between metal grid lines and perovskite.

[0099] This application also designs a perovskite bandgap for precise control and structural optimization, controlling the bandgap of the 2D and 3D composite perovskite layer to be 1.65~1.75eV, forming a perfect spectral complement to the TBC bottom cell (bandgap 1.12eV), reducing the current mismatch rate and improving the stacking efficiency.

[0100] This application also provides a solar cell module, which includes the solar cell 1 provided above in this application.

[0101] This application also provides a photovoltaic device, which includes a solar cell module as described above.

[0102] The solar cell module and photovoltaic equipment provided in this application adopt the solar cell 1 provided in this application as described above. The solar cell 1 achieves efficient carrier transport between the top and bottom cells by setting a receiving groove 131 on the passivation layer 13 and placing the conductive grid line 16 in the receiving groove 131, thereby improving the working performance of the solar cell 1. Furthermore, by setting a barrier layer 14 composed of a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143, the conductive grid line 16 is isolated from the perovskite top cell layer 15, thereby solving the problem of poor interface stability and extending the service life of the solar cell 1.

[0103] Please refer to this as well. Figures 1-3 This application also provides a method for preparing a solar cell 1, the method comprising: S100 provides substrate 11.

[0104] Optionally, the substrate 11 may be pretreated to remove the damaged layer of the substrate 11 and clean the substrate 11.

[0105] Optionally, an N-type single-crystal silicon wafer measuring 183mm × 183mm, with a resistivity of 5Ω·cm and a thickness of 140μm is selected as substrate 11. Then, an alkaline texturing process is used to form a 2μm~3μm pyramidal textured surface. The alkaline texturing solution includes NaOH and IPA, the process temperature is 80℃, and the process time is 18min. Subsequently, the damaged layer is removed by acid washing. The acid washing solution includes HF and HNO3, with a molar ratio of HF to HNO3 of 1:5, and the washing time is 6min. Next, the substrate is cleaned with ultrapure water (resistivity ≥18MΩ·cm) and then dried with nitrogen gas to ensure that the water content on the surface of substrate 11 is <20ppm.

[0106] S200, a doped polysilicon layer 12 is formed on the substrate 11.

[0107] The doped polysilicon layer 12 includes a P-type polysilicon layer and an N-type polysilicon layer. Optionally, the P-type polysilicon layer is a boron-doped polysilicon layer. Optionally, the N-type polysilicon layer is a phosphorus-doped polysilicon layer.

[0108] Optionally, a 300 nm intrinsic polycrystalline silicon layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process at a deposition temperature of 620 °C and a silane flow rate of 50 sccm.

[0109] Subsequently, boron doping was performed using a single-mask laser with a wavelength of 532 nm, a pulse width of 50 ns, and a spot energy of 0.6 J / cm². 2 A P-type polycrystalline silicon layer is formed, which has a P-type polycrystalline silicon region with a width of 500 μm and a boron doping concentration of 4 × 10⁻⁶. 19 cm-3 .

[0110] Then, a 200 nm phosphorus-doped polycrystalline silicon layer was deposited using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 450 °C and a phosphine flow rate of 30 sccm. Laser grooving was then performed on the phosphorus-doped polycrystalline silicon layer at a wavelength of 355 nm and a laser power of 10 W, forming an N-type polycrystalline silicon region and an isolation region. The width of the N-type polycrystalline silicon region was 500 μm, and the phosphorus doping concentration was 2 × 10⁻⁶. 20 cm -3 The width of the isolation region is 60 μm; finally, the doping is activated by annealing at 950℃ for 30 min.

[0111] S300, a passivation layer 13 is formed on the side of the doped polysilicon layer 12 away from the substrate 11, the passivation layer 13 having a receiving groove 131 exposed on the surface of the substrate 11.

[0112] Optionally, SiN x The passivation layer 13 is deposited using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) processes at a deposition temperature of 400℃, a furnace tube pressure of 2 to 5 torr, a silane to ammonia flow ratio of 1:3, an RF power of 300W, and a surface recombination velocity of 85 cm / s. Furthermore, the corresponding areas of the gate lines are marked using photolithography, and window positions for the accommodating groove 131 are reserved to ensure alignment of the subsequent conductive gate lines 16 with the P-type and N-type polysilicon regions, with an alignment accuracy of ±2μm.

[0113] The location of the receiving trench 131 corresponds to the P-type polysilicon region and N-type polysilicon region of the doped polysilicon layer 12, so that the conductive gate line 16 formed in the receiving trench 131 can be aligned with the P-type polysilicon region and N-type polysilicon region.

[0114] Optionally, the receiving groove 131 is prepared using an ultraviolet laser.

[0115] The ultraviolet laser can precisely penetrate the passivation layer 13 to expose the substrate 11 with a windowing deviation of ≤1μm and no damage to the substrate 11.

[0116] Further optionally, the wavelength of the ultraviolet laser is 345nm~365nm, and preferably, the wavelength of the ultraviolet laser is 355nm.

[0117] And / or, the power of the ultraviolet laser is 6W~10W, preferably, the power of the ultraviolet laser is 8W.

[0118] And / or, the scanning speed of the ultraviolet laser is 700 mm / s to 900 mm / s, preferably, the scanning speed of the ultraviolet laser is 800 mm / s.

[0119] For example, an ultraviolet laser with a wavelength of 355nm, a power of 8W, and a scanning speed of 800mm / s is used to open a window on the passivation layer 13, precisely penetrating the passivation layer 13 to expose the substrate 11. The opening deviation is ≤1μm, and there is no damage to the substrate 11, resulting in an accommodating groove 131 with a linewidth of 30μm and a depth of 90nm.

[0120] Furthermore, after opening the window, the battery semi-finished product is cleaned with plasma. The plasma is Ar gas, the cleaning power is 100W, and the cleaning time is 30s, in order to remove residual impurities in the windowed area of ​​the accommodating tank 131 and improve the reliability of subsequent ohmic contacts.

[0121] S400, forming a conductive grid line 16 disposed in the receiving groove 131.

[0122] Furthermore, the conductive gate line 16 includes a stacked metal seed layer 161 and an electroplated metal layer 162, wherein the material of the electroplated metal layer 162 includes at least one of copper-tin alloy and silver-copper alloy.

[0123] The metal seed layer 161 includes at least one of a titanium seed layer and a silver seed layer.

[0124] Optionally, a titanium seed layer and a silver seed layer are used by magnetron sputtering, with a vacuum degree of 5×10⁻⁶. -4 Pa, the thickness of the titanium seed layer is 8 nm, and the thickness of the silver seed layer is 80 nm.

[0125] Then, the semi-finished battery was activated using argon-oxygen plasma to reduce contact resistance. The argon to oxygen flow ratio was 9:1, the activation power was 100W, and the activation time was 60s, which reduced the contact resistance to <3mΩ·cm. 2 .

[0126] Next, patterned copper-tin alloy main gate and fine gate are electroplated; the electroplating solution includes 90 g / L copper sulfate, 1 g / L stannous sulfate, 60 g / L sulfuric acid, and 0.3 g / L brightener, with a current density of 3 A / dm³. 2 The electroplating temperature was 30℃ and the electroplating time was 15min to obtain a fine grid line width of 30μm and a thickness of 12μm.

[0127] Subsequently, acetone was used to remove the adhesive for 10 minutes, followed by vacuum drying at a vacuum degree of 10. -3 The drying temperature was 100℃ and the drying time was 40 min to obtain a battery semi-finished product with a residual water content of <40 ppm, thus avoiding corrosion of the subsequent perovskite layer.

[0128] S500, forming a barrier layer 14 covering the conductive gate line 16, the barrier layer 14 including a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143.

[0129] Furthermore, along the arrangement direction from the substrate 11 to the passivation layer 13, the self-assembled monolayer 141, the titanium dioxide layer 142, and the 2D perovskite layer 143 are sequentially stacked.

[0130] Alternatively, along the arrangement direction from the substrate 11 to the passivation layer 13, the 2D perovskite layer 143, the titanium dioxide layer 142, and the self-assembled monolayer 141 are stacked sequentially.

[0131] Optionally, in-situ deposition can be performed within the same vacuum chamber to avoid oxidation of the electroplated grid lines.

[0132] Optionally, the self-assembled monolayer 141 is prepared as follows: it is soaked in 0.05 mol / L 3-mercaptopropionic acid solution and anhydrous ethanol solvent for 30 min to form a 3 nm SAMs layer.

[0133] Titanium dioxide layer 142 was prepared using atomic layer deposition (ALD) process: titanium tetrachloride was used as the titanium source, deionized water was used as the oxygen source, the deposition temperature was 100℃, and the growth rate was 0.1 nm / cycle to form a 30 nm titanium dioxide layer 142.

[0134] 2D perovskite layer 143 was prepared by spin coating: 0.1 mol / L (PEA)2PbI4 solution was used, the spin coating speed was 4000 rpm, and the spin coating time was 30 s; then, it was annealed at 90℃ for 10 min to form a 10 nm 2D perovskite layer 143.

[0135] Ultimately, the total thickness of the barrier layer 14 is 43 nm, and the ion permeability is <8 × 10⁻⁶. -11 cm 2 / s.

[0136] S600, a perovskite top cell layer 15 is formed on the side of the barrier layer 14 opposite to the substrate 11.

[0137] Furthermore, the perovskite top cell layer 15 is a 2D and 3D composite perovskite layer, and the band gap of the 2D and 3D composite perovskite layer is 1.65eV~1.75eV.

[0138] Furthermore, the materials of the 2D and 3D composite perovskite layer include MAI, FAI, and CsBr; wherein the molar ratio of MAI, FAI, and CsBr is (0.5~0.7):(0.25~0.45):(0.04~0.06).

[0139] Optionally, a 400 nm PbI2 underlayer is vacuum-deposited, wherein the vacuum level is 5 × 10⁻⁶. -4 The deposition rate was 0.3 nm / s, and the substrate temperature was 70 °C. Then, the substrate was immersed in a mixed solution at room temperature for 10 min. The mixed solution consisted of isopropanol-based MAI, FAI, and CsBr, with a molar ratio of 0.6:0.35:0.05 and a concentration of 0.1 mol / L. Next, the substrate was annealed at 110 °C for 30 min to form a 500 nm 2D / 3D composite perovskite layer with a band gap of 1.70 eV and a crystallinity of 92%.

[0140] The perovskite top cell layer 15 is prepared by a two-step process of vapor deposition and solution treatment, without strong polar solvents, and with the addition of isopropanol-based precursor solution, which improves the film quality of the perovskite top cell layer 15.

[0141] Optionally, the solar cell 1 also includes an electrode layer disposed on the side of the perovskite top cell layer 15 facing away from the substrate 11.

[0142] Alternatively, the electrode layer may be made of ITO.

[0143] Optionally, a 100 nm ITO electrode layer is formed by magnetron sputtering. The sheet resistance of the electrode layer is 15 Ω / □, and the light transmittance of the electrode layer is 86%.

[0144] Optionally, an Ag mesh is prepared by laser direct writing, with a linewidth of 10 μm, a spacing of 500 μm, and a thickness of 60 nm. Then, a 30 nm NiOx hole transport layer is spin-coated and annealed at 150 °C for 20 min. Next, a 50 nm PCBM electron transport layer is formed by vacuum evaporation. Following this, Cu and Ag back electrodes are magnetron sputtered, with a Cu layer of 180 nm and an Ag layer of 80 nm. Finally, a double-glass encapsulation is performed using POE encapsulant, with a water vapor permeability of <10%. -5 g / (m 2 • 24h), vacuum lamination at 140℃ for 18min, thereby completing the encapsulation of solar cell 1.

[0145] In summary, the method for fabricating the solar cell 1 provided in this application achieves efficient carrier transport between the top and bottom cells by setting a receiving groove 131 on the passivation layer 13 and placing the conductive grid line 16 in the receiving groove 131, thereby improving the working performance of the solar cell 1. Furthermore, by setting a barrier layer 14 composed of a self-assembled monolayer 141, a titanium dioxide layer 142, and a 2D perovskite layer 143, the conductive grid line 16 is isolated from the perovskite top cell layer 15, thereby solving the problem of poor interface stability and extending the service life of the solar cell 1.

[0146] Furthermore, this application achieves a synergistic improvement in interconnect efficiency, stability, and mass production compatibility by designing and optimizing the parameters and cycle time of processes such as laser windowing, electroplating activation, barrier layer 14 deposition, and perovskite film formation.

[0147] To make the objectives and advantages of this application clearer, the effects of the solar cells of this application will be further explained in detail below with reference to specific embodiments 1-3.

[0148] Example 1: The first step is substrate treatment: An N-type monocrystalline silicon wafer with a diameter of 183mm × 183mm, a resistivity of 5Ω·cm, and a thickness of 140μm is selected as the substrate. Then, an alkaline texturing process is used to form a 2μm~3μm pyramidal textured surface. The alkaline texturing solution includes NaOH and IPA, the process temperature is 80℃, and the process time is 18min. Next, the damaged layer is removed by acid washing. The acid washing solution includes HF and HNO3, with a molar ratio of HF to HNO3 of 1:5, and the washing time is 6min. Then, the substrate is cleaned with ultrapure water (resistivity ≥18MΩ·cm) and dried with nitrogen gas to ensure the water content on the substrate surface is <20ppm.

[0149] The second step is the fabrication of the back structure of the TBC bottom cell: a 1.5nm SiO2 tunnel oxide layer is grown on the substrate using a back thermal oxidation process at an oxidation temperature of 600℃ and an oxygen flow rate of 200sccm.

[0150] A 300 nm intrinsic polycrystalline silicon layer was deposited using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature of 620 °C and a silane flow rate of 50 sccm.

[0151] Subsequently, boron doping was performed using a single-mask laser with a wavelength of 532 nm, a pulse width of 50 ns, and a spot energy of 0.6 J / cm². 2 A P-type polycrystalline silicon layer is formed, which has a P-type polycrystalline silicon region with a width of 500 μm and a boron doping concentration of 4 × 10⁻⁶. 19 cm -3 .

[0152] Then, a 200 nm phosphorus-doped polycrystalline silicon layer was deposited using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 450 °C and a phosphine flow rate of 30 sccm. Laser grooving was then performed on the phosphorus-doped polycrystalline silicon layer at a wavelength of 355 nm and a laser power of 10 W, forming an N-type polycrystalline silicon region and an isolation region. The width of the N-type polycrystalline silicon region was 500 μm, and the phosphorus doping concentration was 2 × 10⁻⁶. 20 cm -3 The width of the isolation region is 60 μm; finally, the doping is activated by annealing at 950℃ for 30 min.

[0153] The third step is to prepare the passivation layer: SiN is deposited using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) processes. x The passivation layer was deposited at a temperature of 400℃, a furnace tube pressure of 2 torr to 5 torr, a silane to ammonia flow ratio of 1:3, a refractive index of 2.1, an RF power of 300W, and a surface recombination velocity of 85 cm / s. Furthermore, the corresponding areas for the gate lines were marked using photolithography, and window positions for the accommodating trenches were reserved to ensure alignment of the subsequent conductive gate lines with the P-type and N-type polysilicon regions, with an alignment accuracy of ±2μm.

[0154] The fourth step is to form a accommodating groove: an ultraviolet laser with a wavelength of 355nm, a power of 8W, and a scanning speed of 800mm / s is used to open a window on the passivation layer, accurately penetrating the passivation layer to expose the substrate. The opening deviation is ≤1μm, with no substrate damage, resulting in an accommodating groove with a linewidth of 30μm and a depth of 90nm.

[0155] Furthermore, after opening the window, plasma cleaning of the battery semi-finished product is carried out. The plasma is Ar gas, the cleaning power is 100W, and the cleaning time is 30s, in order to remove residual impurities in the windowed area of ​​the receiving tank and improve the reliability of subsequent ohmic contacts.

[0156] Step 5: Fabrication of conductive gate lines: Titanium and silver seed layers are fabricated using magnetron sputtering at a vacuum level of 5 × 10⁻⁶. -4 Pa, the thickness of the titanium seed layer is 8 nm, and the thickness of the silver seed layer is 80 nm.

[0157] Then, the semi-finished battery was activated using argon-oxygen plasma to reduce contact resistance. The argon to oxygen flow ratio was 9:1, the activation power was 100W, and the activation time was 60s, which reduced the contact resistance to <3mΩ·cm. 2 .

[0158] Next, patterned copper-tin alloy main gate and fine gate are electroplated; the electroplating solution includes 90 g / L copper sulfate, 1 g / L stannous sulfate, 60 g / L sulfuric acid, and 0.3 g / L brightener, with a current density of 3 A / dm³. 2 The electroplating temperature was 30℃ and the electroplating time was 15min to obtain a fine grid line width of 30μm and a thickness of 12μm.

[0159] Subsequently, acetone was used to remove the adhesive for 10 minutes, followed by vacuum drying at a vacuum degree of 10. -3The drying temperature was 100℃ and the drying time was 40 min to obtain a battery semi-finished product with a residual water content of <40 ppm, thus avoiding corrosion of the subsequent perovskite layer.

[0160] Step 6: Preparation of the barrier layer: In-situ deposition within the same vacuum chamber to avoid oxidation of the electroplated gate lines. The formation sequence is "SAMs layer, titanium dioxide layer, 2D perovskite layer". The preparation method of the self-assembled monolayer is as follows: Immersion in 0.05 mol / L 3-mercaptopropionic acid solution and anhydrous ethanol solvent for 30 min to form a 3 nm SAMs layer.

[0161] Atomic layer deposition (ALD) was used to prepare a titanium dioxide layer: titanium tetrachloride was used as the titanium source, deionized water was used as the oxygen source, the deposition temperature was 100℃, and the growth rate was 0.1 nm / cycle to form a 30 nm titanium dioxide layer.

[0162] 2D perovskite layers were prepared by spin coating: 0.1 mol / L (PEA)2PbI4 solution was used, the spin coating speed was 4000 rpm, and the spin coating time was 30 s; then, the layers were annealed at 90 °C for 10 min to form 10 nm 2D perovskite layers.

[0163] Ultimately, the total thickness of the barrier layer is 43 nm, and the ion permeability is <8 × 10⁻⁶. -11 cm 2 / s.

[0164] Step 7: Fabrication of the perovskite top solar cell layer: Vacuum evaporation of a 400nm PbI2 underlayer, wherein the vacuum degree is 5×10⁻⁶. - 4 The deposition rate was 0.3 nm / s, and the substrate temperature was 70 °C. Then, the substrate was immersed in a mixed solution at room temperature for 10 min. The mixed solution consisted of isopropanol-based MAI, FAI, and CsBr, with a molar ratio of 0.6:0.35:0.05 and a concentration of 0.1 mol / L. Next, the substrate was annealed at 110 °C for 30 min to form a 500 nm 2D / 3D composite perovskite layer with a band gap of 1.70 eV and a crystallinity of 92%.

[0165] Step 8: Electrode layer fabrication and solar cell encapsulation: A 100nm ITO electrode layer is formed by magnetron sputtering. The sheet resistance of the electrode layer is 15Ω / □, and the light transmittance is 86%. An Ag mesh is fabricated by laser direct writing, with a linewidth of 10μm, a spacing of 500μm, and a thickness of 60nm. Then, a 30nm NiOx hole transport layer is formed by spin coating and annealed at 150℃ for 20min. Next, a 50nm PCBM electron transport layer is formed by vacuum evaporation. Following this, Al and Ag back electrodes are sputtered by magnetron sputtering, with an Al layer of 180nm and an Ag layer of 80nm. Finally, double-glass encapsulation is performed using POE encapsulant, with a water vapor transmittance <10%. -5 g / (m 2 • 24h), vacuum lamination at 140℃ for 18min completes the encapsulation of the solar cell.

[0166] The performance of the solar cell prepared in Example 1 was tested, and the test results are as follows: The solar cell has a conversion efficiency of 33.6%, an open-circuit voltage of 2.12V, and a short-circuit current of 18.5mA / cm². 2 The fill factor of the solar cell is 83.2%.

[0167] The silver consumption of the solar cell is 12mg / cell, which is 81.5% less than that of traditional pure silver grid lines; the welding pull force of the solar cell is 2.4N / m; the efficiency of the solar cell decays to 8.5% after 1000h of 85℃ / 85%RH damp heat test; the current collection rate of the solar cell is 96.3% and the current mismatch rate of the solar cell is 4.2%.

[0168] Example 2: The first step is to process the substrate; the second step is to prepare the back structure of the TBC bottom cell in the same way as in Example 1.

[0169] The third step is to prepare the passivation layer: 75nm SiN is deposited using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer was deposited at 410℃, with a silane to ammonia flow ratio of 1:2.8, an RF power of 320W, a refractive index of 2.15, and a surface recombination rate of 82cm / s. Furthermore, the corresponding areas for the gate lines were marked using photolithography, and window positions for the accommodating grooves were reserved to ensure alignment of the subsequent conductive gate lines with the P-type and N-type polysilicon regions, achieving an alignment accuracy of ±2μm.

[0170] The fourth step is to form a accommodating groove: an ultraviolet laser with a wavelength of 355nm, a power of 7.5W, and a scanning speed of 750mm / s is used to open a window on the passivation layer, precisely penetrating the passivation layer to expose the substrate. The edge of the windowed area is free of burrs, the burr height is <20nm, the windowing deviation is ≤1μm, and there is no damage to the substrate, resulting in an accommodating groove with a linewidth of 28μm and a depth of 95nm.

[0171] Step 5: Fabrication of conductive gate lines: Titanium and silver seed layers are fabricated using magnetron sputtering at a vacuum level of 3 × 10⁻⁶. -4 Pa increases the density of the seed layer by 20%, and the porosity of the seed layer is <1%.

[0172] Then, the semi-finished battery was activated using argon-oxygen plasma to reduce contact resistance. The argon to oxygen flow ratio was 8.5:1.5, the activation power was 120W, and the activation time was 80s, which further reduced the contact resistance to <2.5mΩ·cm. 2 .

[0173] Next, patterned copper-tin alloy main gate and fine gate are electroplated; the electroplating solution includes 95 g / L copper sulfate, 1.2 g / L stannous sulfate, 55 g / L sulfuric acid, and 0.1 g / L brightener, with a current density of 2.8 A / dm³. 2 The electroplating temperature was 29℃, and the electroplating time was 16 min to obtain a fine gate linewidth of 28 μm and a thickness of 13 μm. Furthermore, the tin content in the electroplated copper-tin alloy was 1.2%, increasing the ion diffusion inhibition rate to 97%.

[0174] Subsequently, a mixture of acetone and anhydrous ethanol (volume ratio 1:1) was used to remove the adhesive, with a removal time of 12 minutes. This method resulted in a more thorough removal of residual electroplating solution, with the residual sulfate ion concentration being <1×10⁻⁶. -6 mol / L; then vacuum drying is performed at a vacuum degree of 10. -3 The drying process was carried out at 110°C for 45 minutes to obtain a battery semi-finished product with a residual water content of <30ppm, thus avoiding corrosion of the subsequent perovskite layer.

[0175] Step 6: Fabrication of the barrier layer: In-situ deposition within the same vacuum chamber to avoid oxidation of the electroplated gate lines. The deposition sequence is optimized to "2D perovskite layer, titanium dioxide layer, SAMs layer" to improve the interfacial adhesion between the 2D perovskite layer and the conductive gate lines.

[0176] 2D perovskite layers were prepared by spin coating: a 0.12 mol / L (PEA)₂PbI₄ solution was used, the spin coating speed was 4500 rpm, and the spin coating time was 30 s; then, the layers were annealed at 95 °C for 12 min to form a 12 nm 2D perovskite layer. A stable 2D perovskite layer was formed using a mixed solvent of DMF and DMSO, with a DMF to DMSO volume ratio of 9:1.

[0177] Titanium dioxide layers were prepared using atomic layer deposition (ALD): the titanium source was tetraisopropoxy titanium, the oxygen source was deionized water, the deposition temperature was 110℃, and the growth rate was 0.09 nm / cycle to form a 35 nm titanium dioxide layer with an ion permeability of <5 × 10⁻⁶. -11 cm 2 / s.

[0178] The self-assembled monolayer was prepared as follows: a 0.06 mol / L trimethyl phosphate solution and anhydrous ethanol were used to soak the layer for 35 min to form a 4 nm SAMs layer.

[0179] Ultimately, the total thickness of the barrier layer was 51 nm, and the carrier transport efficiency was improved by 3%.

[0180] Step 7: Fabrication of the perovskite top solar cell layer: Vacuum evaporation of a 420nm PbI2 underlayer, wherein the vacuum degree is 3×10⁻⁶. - 4 At a deposition rate of 0.25 nm / s and a substrate temperature of 75 °C, the density of the underlying layer was improved by 15%. Then, the substrate was immersed in a mixed solution at room temperature for 12 min. The mixed solution consisted of isopropanol-based MAI, FAI, and CsBr, with a molar ratio of 0.58:0.36:0.06 and a concentration of 0.11 mol / L. 0.005 mol / L of PEAI modifier was also added. Next, the substrate was annealed at 115 °C for 28 min to form a 520 nm 2D and 3D composite perovskite layer with a band gap of 1.72 eV, a crystallinity of 94%, and a phase separation inhibition rate improved to 98%.

[0181] Step 8: Fabrication of the electrode layer and encapsulation of the solar cell: A 110 nm ITO electrode layer was formed by magnetron sputtering. The sheet resistance of the electrode layer was 14 Ω / □, and the light transmittance was 87%. An Ag mesh was fabricated by laser direct writing, with a linewidth of 9 μm, a spacing of 480 μm, and a thickness of 65 nm, improving carrier collection efficiency by 2%. Then, a 35 nm NiOx hole transport layer was formed by spin coating and annealed at 160 °C for 18 min, achieving a 15% reduction in interfacial contact resistance. Next, a 55 nm PCBM electron transport layer was formed by vacuum evaporation. Finally, Al and Ag back electrodes were magnetron sputtered, with an Al layer of 190 nm and an Ag layer of 85 nm, achieving a contact resistance of <4 mΩ·cm. 2 Finally, a double-glass encapsulation was performed using POE encapsulating adhesive, with a water vapor transmission rate of <5×10⁻⁶. -8 g / (m 2 • 24h), vacuum lamination at 145℃ for 16min completes the encapsulation of the solar cell.

[0182] The performance of the solar cell prepared in Example 2 was tested, and the test results are as follows: The solar cell has a conversion efficiency of 34.2%, an open-circuit voltage of 2.15V, and a short-circuit current of 18.7mA / cm². 2 The fill factor of the solar cell is 84.1%.

[0183] The silver consumption of the solar cell is 11 mg / cell, which is 83.1% less than that of traditional pure silver grid lines; the welding pull force of the solar cell is 2.6 N / m; the efficiency degradation of the solar cell is 7.2% after 1000 hours of 85℃ / 85%RH damp heat testing; the efficiency degradation of the solar cell is 6.8% after 200 cycles of high-temperature cycling testing (-40℃~85℃); the current collection rate of the solar cell is 97.5%, and the current mismatch rate of the solar cell is 3.5%; the copper ion concentration in the perovskite layer is <3×10¹ 5 The atomic density per centimeter indicates that there is no significant ion diffusion.

[0184] Example 3: The first step is to process the substrate. The second step is to prepare the back structure of the TBC bottom battery, which is basically the same as in Example 1, except that the process parameters are as follows: the alkaline texturing time is shortened to 15 min, the alkaline texturing temperature is 82℃, the acid washing time is shortened to 5 min, and the total pretreatment cycle time is ≤25 min; the preparation of the back structure of the TBC bottom battery adopts a mass production compatible process, the annealing time is shortened to 25 min, and the surface recombination rate is <95 cm / s.

[0185] The third step is to prepare the passivation layer: 65nm SiN is deposited using plasma-enhanced chemical vapor deposition (PECVD). xThe passivation layer is deposited at a temperature of 390℃ with an RF power of 350W, achieving a deposition rate of 2nm / s and a cycle time of 3min. Furthermore, it incorporates pre-reserved window openings, utilizes mass-production photolithography templates, and boasts an alignment accuracy of ±2.5μm, making it suitable for high-speed mass production.

[0186] The fourth step is to form a receiving groove: using an ultraviolet laser with a wavelength of 355nm, a power of 12W, and a scanning speed of 1200mm / s, a window is opened on the passivation layer to precisely penetrate the passivation layer and expose the substrate, resulting in a receiving groove with a linewidth of 32μm and a depth of 85nm. The windowing cycle is shortened to 0.5min / piece, which is suitable for a production capacity of 6000 pieces / hour.

[0187] Step 5: Fabrication of conductive gate lines: Titanium and silver seed layers are fabricated using magnetron sputtering at a vacuum level of 5 × 10⁻⁶. -4 Pa, the thickness of the titanium seed layer is 7nm, the thickness of the silver seed layer is 75nm, the deposition rate is increased to 10nm / s, and the cycle time is shortened to 1min.

[0188] Then, argon-oxygen plasma was used to activate the semi-finished battery to reduce contact resistance. The argon to oxygen flow ratio was 9.5:0.5, the activation power was 150W, and the activation time was 40s, shortening the cycle time while ensuring a contact resistance <3.5mΩ·cm. 2 .

[0189] Next, patterned copper-tin alloy main gate and fine gate are electroplated; the electroplating solution includes 100 g / L copper sulfate, 0.8 g / L stannous sulfate, 50 g / L sulfuric acid, and 0.2 g / L brightener, with a current density of 3.5 A / dm³. 2 The electroplating temperature was 31℃ and the electroplating time was 12 min to obtain a fine grid linewidth of 32 μm and a thickness of 11 μm. Furthermore, the tin content in the electroplated copper-tin alloy was 0.8%, which met the requirements of low silver consumption while suppressing ion diffusion.

[0190] Subsequently, acetone solution was used to remove the adhesive for 8 minutes; then vacuum drying was performed at a vacuum degree of 10. - 3 Pa, drying temperature is 105℃, drying time is 30min, total electroplating process cycle time is ≤18min / piece.

[0191] Step 6, preparation of the barrier layer: The formation sequence is "SAMs layer, titanium dioxide layer, 2D perovskite layer". The preparation method of the self-assembled monolayer is as follows: using 0.04 mol / L 3-mercaptopropionic acid solution and anhydrous ethanol solvent, soaking for 25 min, shortening the cycle time by 5 min, to form a 5 nm SAMs layer.

[0192] Atomic layer deposition (ALD) was used to prepare a titanium dioxide layer: titanium tetrachloride was used as the titanium source, deionized water was used as the oxygen source, the deposition temperature was 120℃, the growth rate was 0.12nm / cycle, and a 25nm titanium dioxide layer was formed, with the deposition cycle shortened to 2min.

[0193] 2D perovskite layers were prepared by spin coating: a 0.09 mol / L (PEA)2PbI4 solution was used, the spin coating speed was 3500 rpm, the spin coating time was 25 s, and a stable 2D perovskite layer was formed using DMF solvent; then, the layer was annealed at 85 °C for 8 min to form an 8 nm 2D perovskite layer.

[0194] Ultimately, the total thickness of the barrier layer is 38 nm, and the ion permeability is <1×10⁻⁶. -10 cm 2 / s, total deposition rate ≤3min / piece.

[0195] Step 7: Fabrication of the perovskite top cell layer: A high-speed film deposition process was employed, with a 380nm PbI2 underlayer deposited under vacuum at a deposition rate of 0.4nm / s, a substrate temperature of 65℃, and a cycle time shortened to 1.5min. Then, the substrate was immersed in a mixed solution at room temperature for 8min. The mixed solution consisted of isopropanol-based MAI, FAI, and CsBr, with a molar ratio of 0.62:0.33:0.05, and a cycle time shortened by 2min. Next, the substrate was annealed at 105℃ for 25min to form a 480nm 2D and 3D composite perovskite layer with a band gap of 1.68eV and a crystallinity of 91%, suitable for high-speed film deposition.

[0196] Step 8: Electrode layer fabrication and solar cell encapsulation: A 90nm ITO electrode layer is formed by magnetron sputtering, with a deposition rate increased to 15nm / s and a cycle time shortened to 0.5min. An Ag mesh is fabricated using laser direct writing, with a linewidth of 11μm, a spacing of 520μm, and a thickness of 55nm, achieved at high speed with a cycle time ≤0.3min / wafer. Then, a 25nm NiOx hole transport layer is spin-coated and annealed at 140℃ for 15min. Next, a 45nm PCBM electron transport layer is formed by vacuum evaporation, with a deposition rate increased to 0.5nm / s. Following this, Al and Ag back electrodes are sputtered by magnetron sputtering, with a deposition rate increased to 20nm / s and a cycle time ≤0.5min / wafer. Finally, double-glass encapsulation is performed using POE encapsulating adhesive, following standard mass production line processes, with vacuum lamination at 135℃ for 15min and a cycle time ≤2min / wafer, thus completing the solar cell encapsulation.

[0197] Example 3 focuses more on minimizing silver consumption and mass production processes.

[0198] The performance of the solar cell prepared in Example 3 was tested, and the results are as follows: The solar cell has a conversion efficiency of 33.2%, an open-circuit voltage of 2.10V, and a short-circuit current of 18.3mA / cm². 2 The fill factor of the solar cell is 82.5%.

[0199] The silver consumption of the solar cell is 10mg / cell, which is 84.6% less than that of traditional pure silver grid lines; the welding pull force of the solar cell is 2.3N / m; the efficiency degradation of the solar cell is 9.8% after 1000h of 85℃ / 85%RH damp heat test; the total process cycle time is ≤28min / cell, which is compatible with the existing TBC production line with a capacity of 8000 cells / h and a yield of ≥95%; the current collection rate of the solar cell is 95.8% and the current mismatch rate of the solar cell is 4.8%; compared with the traditional TBC-perovskite tandem prototype, the overall cost of mass production is reduced by 35%.

[0200] In summary, the solar cells, their fabrication methods, solar cell modules, and photovoltaic equipment provided in this application have the following advantages: First, the cost of silver consumption is significantly reduced, and the economic efficiency of industrialization is significantly improved: by using copper-tin alloy fine grids and / or silver-copper alloy main grids to replace traditional pure silver grid lines, the silver consumption is reduced to 10mg / cell to 12mg / cell, which is 81.5% to 84.6% lower than the silver consumption of 65mg / cell to 80mg / cell in the existing technology; the overall cost of the battery is reduced by 30% to 35%, which solves the problem of silver price fluctuations restricting the photovoltaic industry and has the economics of large-scale promotion.

[0201] Second, the top and bottom cell interconnection efficiency is high, and the stacking efficiency breaks through the bottleneck: through parameter optimization of laser windowing to form the receiving groove, plasma activation process, and alloy grid structure design, the current collection rate is increased to 95.8%~97.5%, and the current mismatch rate is reduced to 3.5%~4.8%; the conversion efficiency of the stacked cell is stable at 33.2%~34.2%, while the existing TBC-perovskite stacked prototype is usually ≤30%, which is 10.7%~14.0% higher than the existing TBC-perovskite stacked prototype, and close to the upper limit of the stable theoretical efficiency of 35% for stacked cell conversion efficiency.

[0202] Third, the interface stability is greatly improved, and the service life meets the requirements of industrialization: the barrier layer can achieve the triple functions of "ion barrier + chemical protection + thermal expansion matching", the metal ion diffusion inhibition rate is ≥95%, and the copper ion concentration in the perovskite layer is <5×10¹ 5 atoms / cm 3The efficiency degradation is only 7.2%~9.8% after 1000 hours of humid heat testing at 85℃ / 85%RH. Existing TBC-perovskite tandem prototypes typically experience an efficiency degradation of 30%-50% after 1000 hours of humid heat testing at 85℃ / 85%RH. This application reduces the degradation by 67.3%~85.6%. In high-temperature cycling tests (-40℃~85℃, 200 cycles), the efficiency degradation is ≤6.8%, and the service life is expected to be ≥25 years, meeting the 25-year warranty requirements for photovoltaic power plants.

[0203] Fourth, the process is compatible with existing production lines and has high feasibility for mass production: the optimized preparation process has a total cycle time of ≤28min / piece, which is compatible with the existing TBC production line's mass production capacity of 8000 pieces / h; no new special equipment is required, only an electroplating module needs to be added to the existing production line, with a cost of ≤2 million yuan / line; the composite barrier layer deposition module has a cost of ≤1.5 million yuan / line; the transformation investment is low, with a single production line transformation cost of ≤3.5 million yuan; the process yield is ≥95%, which is far higher than the existing multilayer technology yield of ≤80%.

[0204] Fifth, it exhibits low carrier transport loss and excellent performance stability: the contact resistance between the electroplated grid lines and the TBC bottom cell is <3.5 mΩ·cm. 2 The series resistance of the composite barrier layer increases by less than 2%; the crystallinity of the perovskite top cell is ≥91%, and the carrier lifetime is improved to more than 1000ns, which is 30% higher than the existing technology; the UV resistance of the encapsulated module is ≤5% after 1000h of UV testing; the wind and sand resistance is ≤3% after simulated wind and sand testing, all of which are better than the industry standard.

[0205] Sixth, it has a wide range of applications and significant market value: The solar cells in this application can be widely used in ground-mounted photovoltaic power stations, distributed photovoltaics, building-integrated photovoltaics (BIPV) and other scenarios, and are especially suitable for harsh environments such as high humidity (such as in southern regions) and high temperature (such as in desert regions); based on an annual production of 10GW, it can reduce silver consumption by 650-800 tons / year, reduce costs by 3-4 billion yuan / year, and at the same time improve power generation efficiency by 10-14%, with an annual increase in power generation of ≥1.5 billion kWh, which has significant economic and social value.

[0206] Unless otherwise stated or in case of conflict, the terms or phrases used in this application shall have the following meanings: In this application, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0207] In this application, "one or more" refers to any one, any two, or any two or more of the listed items. "Several" refers to any two or more.

[0208] In this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0209] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part. They can refer to a mechanical connection or an electrical connection. They can refer to a direct connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0210] In this application, the terms "embodiment" and "implementation" mean that a specific feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The appearance of these phrases in various locations throughout the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this application can be combined with other embodiments. Furthermore, it should be understood that the features, structures, or characteristics described in the various embodiments of this application can be arbitrarily combined to form yet another embodiment that does not depart from the spirit and scope of the technical solution of this application, provided there is no contradiction between them.

[0211] The above description represents some embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes a substrate, a doped polycrystalline silicon layer, a passivation layer, a barrier layer, and a perovskite top cell layer stacked sequentially. The passivation layer has a receiving groove exposed on the surface of the substrate. The solar cell also includes conductive grid lines disposed in the receiving groove. The barrier layer covers the conductive grid lines. The barrier layer comprises a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer.

2. The solar cell as described in claim 1, characterized in that, Along the arrangement direction from the substrate to the passivation layer, the self-assembled monolayer, the titanium dioxide layer, and the 2D perovskite layer are stacked in sequence; Alternatively, along the arrangement direction from the substrate to the passivation layer, the 2D perovskite layer, the titanium dioxide layer, and the self-assembled monolayer are stacked sequentially.

3. The solar cell as described in claim 1, characterized in that, The material of the self-assembled monolayer includes at least one of 3-mercaptopropionic acid and trimethyl phosphate; And / or, the material of the 2D perovskite layer includes (PEA)2PbI4.

4. The solar cell as described in claim 1, characterized in that, The thickness of the self-assembled monolayer is 3 nm to 4 nm. And / or, the thickness of the titanium dioxide layer is 30nm~40nm; And / or, the thickness of the 2D perovskite layer is 10nm~15nm; And / or, the total thickness of the barrier layer is 45nm~60nm.

5. The solar cell as described in claim 1, characterized in that, The perovskite top cell layer is a 2D and 3D composite perovskite layer, and the band gap of the 2D and 3D composite perovskite layer is 1.65eV~1.75eV.

6. The solar cell as described in claim 5, characterized in that, The materials of the 2D and 3D composite perovskite layer include MAI, FAI, and CsBr; wherein the molar ratio of MAI, FAI, and CsBr is (0.5~0.7):(0.25~0.45):(0.04~0.06).

7. The solar cell according to claim 1, characterized in that, The conductive grid line includes a stacked metal seed layer and an electroplated metal layer, wherein the material of the electroplated metal layer includes at least one of copper-tin alloy and silver-copper alloy.

8. A solar cell module, characterized in that, The solar cell module includes the solar cell as described in any one of claims 1-7.

9. A photovoltaic device, characterized in that, The photovoltaic device includes the solar cell module as described in claim 8.

10. A method for preparing a solar cell, characterized in that, The preparation method includes: Provide substrate; A doped polysilicon layer is formed on the substrate; A passivation layer is formed on the side of the doped polysilicon layer opposite to the substrate, the passivation layer having a receiving groove exposed on the surface of the substrate; A conductive grid line is formed within the receiving groove; A barrier layer is formed covering the conductive gate lines, the barrier layer comprising a self-assembled monolayer, a titanium dioxide layer, and a 2D perovskite layer; A perovskite top cell layer is formed on the side of the barrier layer opposite to the substrate.

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