Light emitting diode with improved crystal quality and method of making the same

Abstract

This disclosure provides a light-emitting diode (LED) with improved crystal quality and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The fabrication method includes: forming a first semiconductor layer on a substrate; forming an active layer on the first semiconductor layer, the active layer comprising multiple stacked periodic structures, each periodic structure including alternately stacked quantum well layers and quantum barrier layers, wherein the growth temperature of the quantum well layers in each periodic structure increases sequentially along the stacking direction of the multiple periodic structures; and forming a second semiconductor layer on the active layer. The embodiments of this disclosure can improve the In atom clustering phenomenon and enhance the crystal quality of the active layer.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved crystal quality and a method for its fabrication. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, light-emitting diodes typically include a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on a substrate. For InGaN-based LEDs, the active layer often employs an InGaN / GaN multiple quantum well structure.

[0004] During the growth of InGaN quantum wells, due to the significant size difference between In and Ga atoms, and the low solid solubility of In in the GaN matrix, In atoms are prone to segregation within the quantum well plane when growth process parameters are not properly controlled, forming localized high-concentration aggregation regions (i.e., In atom clustering). In atom clusters induce band structure inhomogeneities within the quantum well, generating non-radiative recombination centers, directly leading to decreased LED luminous efficiency and broadened spectral half-width at half-maximum. Simultaneously, lattice stress concentration in the cluster regions exacerbates performance degradation during long-term LED operation, shortening device lifespan. Summary of the Invention

[0005] This disclosure provides a light-emitting diode with improved crystal quality and its fabrication method, which can mitigate the In atom clustering phenomenon and improve the crystal quality of the active layer. The technical solution is as follows: On one hand, this disclosure provides a method for fabricating a light-emitting diode, the method comprising: forming a first semiconductor layer on a substrate; forming an active layer on the first semiconductor layer, the active layer comprising a plurality of stacked periodic structures, the periodic structures comprising alternating stacked quantum well layers and quantum barrier layers, wherein the growth temperature of the quantum well layers in each periodic structure increases sequentially along the stacking direction of the plurality of periodic structures; and forming a second semiconductor layer on the active layer.

[0006] Optionally, forming an active layer on the first semiconductor layer includes: controlling the growth temperature to be between 700°C and 810°C to grow a quantum well layer of the first periodic structure; controlling the growth temperature of the quantum well layer of each subsequent periodic structure to increase progressively by a value based on the growth temperature of the previous periodic structure, until the stacking of the periodic structures with a set number of layers is completed, and the growth temperature of the quantum well layer of the last periodic structure is less than or equal to 810°C.

[0007] Optionally, the progressive value ranges from 0.2℃ to 0.8℃.

[0008] Optionally, growing the quantum well layer of each of the periodic structures includes: linearly increasing the flux of the In source from 100 sccm to 800 sccm to 1000 sccm to 5000 sccm, and linearly decreasing the flux of the Ga source from 300 sccm to 1000 sccm to 100 sccm to 500 sccm to grow an InGaN layer for a first duration; and maintaining the flux of the In source and the flux of the Ga source to grow an InGaN layer for a second duration.

[0009] Optionally, the first duration is 5s to 40s, and the second duration is 15s to 120s.

[0010] Optionally, forming an active layer on the first semiconductor layer includes growing a strain compensation layer between the quantum well layer and the quantum barrier layer of each of the periodic structures, wherein the strain compensation layer includes an InAlGaN layer, and the content of In in the strain compensation layer is 1% to 10%, and the content of Al in the strain compensation layer is 5% to 20%.

[0011] Optionally, the thickness of the strain compensation layer is 0.5 nm to 2 nm.

[0012] On the other hand, this disclosure also provides a light-emitting diode, which includes a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially. The active layer includes a plurality of stacked periodic structures, and the periodic structures include alternating stacked quantum well layers and quantum barrier layers. Along the stacking direction of the plurality of periodic structures, the growth temperature of the quantum well layers in each periodic structure increases sequentially.

[0013] Optionally, the periodic structure further includes a strain compensation layer, which comprises an InAlGaN layer, wherein the In content is 1% to 10% and the Al content is 5% to 20%.

[0014] Optionally, the thickness of the strain compensation layer is 0.5 nm to 2 nm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The fabrication method provided in this disclosure, during the growth of quantum well layers with each periodic structure, increases the growth temperature periodically, enabling In atoms to achieve higher mobility at higher temperatures and promoting their uniform distribution within the GaN matrix. The temperature gradient effectively mitigates the rapid cooling effect at low temperatures, preventing In atoms from being frozen at defect sites, thereby reducing cluster density and preventing localized enrichment of In atoms within the quantum well. Furthermore, In atom clusters can cause localized lattice distortion, becoming stress concentration points and accelerating carrier trapping and hot carrier degradation. The gradient heating allows the In composition to fully relax at higher temperatures, releasing accumulated lattice strain and reducing the defect density at the quantum well / barrier interface. Simultaneously, the gradient heating mode avoids crystal defects caused by low-temperature growth, improving the crystal quality of the epitaxial layer. Uniform distribution of In atoms also reduces non-radiative recombination, improving the luminous efficiency of the light-emitting diode. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure.

[0018] The markings in the diagram are explained as follows: 10. Substrate; 21. AlN layer; 22. Nucleation layer; 23. U-shaped GaN layer; 30. First semiconductor layer; 40. Active layer; 41. Periodic structure; 411. Quantum well layer; 412. Quantum barrier layer; 413. Strain compensation layer; 50. Second semiconductor layer; 61. Low-temperature p-type AlGaN layer; 62. p-type electron blocking layer; 63. High-temperature p-type GaN layer; 64. p-type contact layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] In related technologies, In atom clustering is suppressed by lowering the growth temperature to inhibit In atom diffusion. However, low-temperature growth leads to a decrease in the crystal quality of the epitaxial layer (increased defect density), making it difficult to balance In atom uniformity and crystal quality.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Form a first semiconductor layer on the substrate.

[0022] Step S12: An active layer is formed on the first semiconductor layer. The active layer includes multiple stacked periodic structures. The periodic structures include alternating stacked quantum well layers and quantum barrier layers. Along the stacking direction of the multiple periodic structures, the growth temperature of the quantum well layers in each periodic structure increases sequentially.

[0023] Step S13: Form a second semiconductor layer on the active layer.

[0024] The fabrication method provided in this disclosure, during the growth of quantum well layers with each periodic structure, increases the growth temperature periodically, enabling In atoms to achieve higher mobility at higher temperatures and promoting their uniform distribution within the GaN matrix. The temperature gradient effectively mitigates the rapid cooling effect at low temperatures, preventing In atoms from being frozen at defect sites, thereby reducing cluster density and preventing localized enrichment of In atoms within the quantum well. Furthermore, In atom clusters can cause localized lattice distortion, becoming stress concentration points and accelerating carrier trapping and hot carrier degradation. The gradient heating allows the In composition to fully relax at higher temperatures, releasing accumulated lattice strain and reducing the defect density at the quantum well / barrier interface. Simultaneously, the gradient heating mode avoids crystal defects caused by low-temperature growth, improving the crystal quality of the epitaxial layer. Uniform distribution of In atoms also reduces non-radiative recombination, improving the luminous efficiency of the light-emitting diode.

[0025] The following steps may also be included before step S11: The first step is to provide a substrate as the basic support for epitaxial growth.

[0026] The substrate can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0027] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0028] In this embodiment of the present disclosure, the sapphire substrate can be subjected to high-temperature cleaning treatment in a hydrogen atmosphere at 1000°C to 1200°C for 5 min to 20 min, and then subjected to nitriding treatment.

[0029] In this embodiment of the disclosure, the sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment of the disclosure, the sapphire substrate is baked for 15 minutes.

[0030] Specifically, the baking temperature can be from 1000°C to 1200°C, and the pressure in the MOCVD reaction chamber during baking can be from 100 mbar to 200 mbar.

[0031] The second step is to grow an AlN layer on the substrate.

[0032] Specifically, an AlN layer is deposited on a sapphire substrate using magnetron sputtering with a physical vapor deposition (PVD) device to obtain a buffer layer. The buffer layer is used to alleviate the lattice mismatch between the substrate and subsequent epitaxial layers.

[0033] The growth temperature in the PVD equipment is 400℃ to 800℃, the sputtering power is 3000W to 5000W, the pressure is 1mtorr to 20mtorr, and the AlN layer deposition thickness is 10nm to 50nm.

[0034] The third step involves placing the AlN-coated substrate into an MOCVD system to grow a 3D nucleation layer. The MOCVD reaction chamber temperature is maintained at 1030°C to 1100°C, and the reaction chamber pressure is controlled at 150 torr to 500 torr. Under a mixed atmosphere of nitrogen, hydrogen, and ammonia, the growth thickness of the nucleation layer ranges from 0.3 μm to 2 µm. The 3D nucleation layer can further optimize the surface flatness of the epitaxial layer.

[0035] The fourth step is to grow a U-shaped GaN layer on the nucleation layer.

[0036] In this embodiment, a U-shaped GaN layer is grown between the nucleation layer and the dislocation blocking layer. By setting the U-shaped GaN layer as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0037] The thickness of the u-shaped GaN layer is from 0.5 μm to 3 μm. For example, the thickness of the u-shaped GaN layer is 2 μm.

[0038] Specifically, undoped GaN buffer recovery layers are grown using MOCVD. U-shaped GaN layers with thicknesses ranging from 0.5 μm to 3 µm are grown in an MOCVD system with temperatures adjusted to 1000 °C to 1150 °C and growth pressures ranging from 100 to 500 torr. These U-shaped GaN layers are used to repair potential defects in the initial buffer layer, improving the quality of subsequent epitaxy.

[0039] Step S11 may include: growing an n-type layer on the u-type GaN layer.

[0040] Optionally, the n-type layer can be an n-type GaN layer. The thickness of the n-type layer is 0.5 μm to 3 μm. The dopant of the n-type layer is silane. The n-type GaN layer is the first semiconductor layer closest to the substrate in the LED structure, providing an electron injection channel for subsequent active layer growth.

[0041] Specifically, in an MOCVD system with a temperature adjusted to 1000℃ to 1150℃ and a growth pressure of 100 torr to 300 torr, an n-type doped GaN layer with a thickness of 0.5 μm to 3 µm is grown, and the Si doping concentration of the n-type GaN layer is 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 .

[0042] Step S12 may include the following steps: The first step is to control the growth temperature to 700℃ to 810℃ to grow the quantum well layer of the first periodic structure.

[0043] The initial growth temperature was controlled at 790℃, and the first periodic InGaN quantum well layer was grown under a growth pressure of 200 Torr. This balances the initial migration ability of In atoms with avoiding the volatilization of In components due to excessively high temperatures.

[0044] After growing the quantum well layer, the GaN quantum barrier layer is then grown at a controlled temperature of 850℃ to 880℃. This temperature range is higher than that of the quantum well layer, ensuring the crystal quality of the quantum barrier layer and creating a quantum confinement effect through the temperature difference.

[0045] For example, the growth temperature of the quantum barrier layer is 860°C.

[0046] The second step is to control the growth temperature of the quantum well layer of each subsequent periodic structure to increase progressively from the growth temperature of the previous periodic structure, until the stacking of the periodic structure with the set number of layers is completed, and the growth temperature of the quantum well layer of the last periodic structure is less than or equal to 810℃.

[0047] For example, the increment value ranges from 0.2℃ to 0.8℃. For instance, an increment value of 0.4℃. This gradient heating avoids interference from sudden temperature changes on the migration of In atoms.

[0048] After the first cycle is completed, the growth temperature of the quantum well layer in each subsequent cycle is increased by 0.2℃ to 0.8℃ based on the previous cycle, achieving a gradual temperature increase.

[0049] Optionally, the quantum well layers for growing each periodic structure include: In the first growth stage, the flow rate of the In source is linearly increased from 100 sccm to 800 sccm to 1000 sccm to 5000 sccm, and the flow rate of the Ga source is linearly decreased from 300 sccm to 1000 sccm to 100 sccm to 500 sccm, to grow the first InGaN layer for the first duration.

[0050] For example, the first duration is 5 to 40 seconds.

[0051] For example, in the first growth stage, the flow rate of the In source is linearly increased from 300 sccm to 3000 sccm, and the flow rate of the Ga source is linearly decreased from 500 sccm to 320 sccm.

[0052] By controlling the dynamic changes in the flow rates of the In source (triethylin, TEIn) and the Ga source (triethylgallium, TEGa) in the MOCVD system, an InGaN layer of the first duration is grown.

[0053] Among them, the TEIn flow rate increases linearly from 100 sccm to 800 sccm to 1000 sccm to 5000 sccm, and the TEGa flow rate decreases linearly from 300 sccm to 1000 sccm to 100 sccm to 500 sccm.

[0054] By dynamically adjusting the ratio of "In increasing and Ga decreasing", In atoms can be rapidly induced to nucleate uniformly in the GaN matrix during the low-temperature start-up phase. This avoids the local enrichment of In atoms due to low mobility in the constant flow mode of related technologies, and lays a uniform initial state for the migration and rearrangement of In atoms under subsequent gradient heating.

[0055] In the second growth stage, the flow rates of the In source and the Ga source are maintained to grow an InGaN layer for a second duration.

[0056] For example, the second duration is 15s to 120s.

[0057] For example, the flow rate of the In source is kept at 3000 sccm and the flow rate of the Ga source is kept at 320 sccm.

[0058] After completing the first stage, the final flow rates of TEIn and TEGa are kept constant, and the InGaN layer is grown for the second duration. In the second stage, flow rate adjustment is stopped to maintain the stoichiometry of the InGaN layer at a constant flow rate, thus avoiding compositional fluctuations caused by flow rate variations.

[0059] This ensures the uniformity of the well layer thickness by maintaining a stable flow rate, while gradient heating further enhances the surface mobility of In atoms, promoting the full diffusion of the uniform In nuclei formed in the first stage, eliminating microscale compositional fluctuations, and ultimately obtaining a quantum well layer with a complete lattice and uniform composition.

[0060] Optionally, forming an active layer on the first semiconductor layer further includes growing a strain compensation layer between the quantum well layer and the quantum barrier layer of each periodic structure.

[0061] The strain compensation layer includes an InAlGaN layer, in which the content of In is 1% to 10% and the content of Al is 5% to 20%.

[0062] The strain compensation layer reduces strain-induced band bending by alleviating interfacial stress; at the same time, the high Al content of the InAlGaN layer enhances the barrier height at the interface and suppresses carrier leakage.

[0063] For example, the thickness of the strain compensation layer is 0.5 nm to 2 nm.

[0064] In this embodiment of the disclosure, the growth process of a single periodic structure can be performed using the following steps: In the first step, when growing the InGaN quantum well layer, a pure nitrogen atmosphere is used, with a pressure of 200 Torr to 500 Torr and a temperature of 700°C to 810°C.

[0065] The growth temperature of the quantum well layer in the first periodic structure is 700℃ to 810℃, and increases by 0.2℃ to 0.8℃ in each subsequent period. The growth temperature of the quantum well layer in the last periodic structure is ≤810℃.

[0066] For example, in each periodic structure, the thickness of the InGaN layer is 1.5 nm to 6 nm.

[0067] Specifically, the InGaN layer is grown by adjusting the source flux in stages during the growth of each periodic structure.

[0068] In the first growth stage, the In source flux is linearly increased from 300 sccm to 3000 sccm, and the Ga source flux is linearly decreased from 500 sccm to 320 sccm, with an InGaN layer growth time of 5 s to 40 s. In the second growth stage, the In source flux is kept at 3000 sccm and the Ga source flux is kept at 320 sccm, with an InGaN layer growth time of 15 s to 120 s, forming an InGaN quantum well layer.

[0069] The second step is to immediately grow a strain compensation layer after the InGaN quantum well layer is grown, as a transition layer between the quantum well layer and the quantum barrier layer.

[0070] Among them, the strain compensation layer uses In x Al y Ga 1-x-y The N-layer has an In component x = 1%~10% (trace amounts of In increase the lattice constant) and an Al component y = 5%~20% (Al decreases the lattice constant). The ratio of x to y neutralizes the lattice mismatch between InGaN and GaN.

[0071] For example, the strain compensation layer is 0.5 nm to 2 nm, and the ultrathin strain compensation layer avoids weakening the quantum confinement effect.

[0072] The growth temperature of the strain compensation layer is 800℃ to 850℃, which is slightly higher than the maximum temperature of the quantum well layer but lower than the conventional growth temperature of the GaN quantum barrier layer. The growth pressure is 100 Torr to 300 Torr, which is connected to the pressure of the subsequent GaN quantum barrier layer. The atmosphere is a mixture of nitrogen and hydrogen.

[0073] The third step is to grow a GaN quantum barrier layer on the strain compensation layer to complete a periodic structure.

[0074] During the growth of GaN quantum barrier layers, a mixed atmosphere of nitrogen and hydrogen is used, the growth pressure is controlled at 100 Torr to 300 Torr, and the growth temperature is controlled at 800℃ to 960℃.

[0075] For example, the thickness of the GaN quantum barrier layer is 8 nm to 20 nm to ensure sufficient barrier height to confine charge carriers.

[0076] Step S13 may include: growing a p-type layer on the active layer.

[0077] The p-type layer includes a low-temperature p-type AlGaN layer, a p-type electron blocking layer, a high-temperature p-type GaN layer, and a p-type contact layer, which are sequentially stacked on the active layer.

[0078] For example, the p-type electron blocking layer can be a p-type Al y Ga 1-yThe N (0.1 < y < 0.5) layer, and the thickness of the p-type electron blocking layer can be 10 nm to 100 nm.

[0079] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer and the high-temperature p-type GaN layer are doped with Mg.

[0080] Exemplarily, the low-temperature p-type AlGaN layer includes Al w Ga 1-w N layer, where 0.1 < w < 0.3.

[0081] The Mg doping concentration of the low-temperature p-type AlGaN layer is 5×10 20 cm -3 to 1×10 21 cm -3 ; the Mg doping concentration of the high-temperature p-type GaN layer is 1×10 18 cm -3 to 1×10 20 cm -3 .

[0082] Among them, the thickness of the low-temperature p-type AlGaN layer can be 10 nm to 100 nm. For example, the thickness of the low-temperature p-type GaN layer can be 80 nm.

[0083] Among them, the thickness of the high-temperature p-type GaN layer can be 10 nm to 100 nm. For example, the thickness of the low- and high-temperature p-type GaN layer can be 50 nm.

[0084] When growing the low-temperature p-type AlGaN layer, adjust the growth temperature to 700 °C to 800 °C, and grow the low-temperature p-type AlGaN layer in an environment with a growth pressure of 200 torr to 500 torr, with a thickness of 10 nm to 100 nm.

[0085] When growing the p-type electron blocking layer, adjust the growth temperature to 800 °C to 1000 °C, and the growth pressure is 50 torr to 300 torr.

[0086] When growing the high-temperature p-type GaN layer, control the growth pressure in an environment of 200 torr to 600 torr, the growth temperature is 800 °C to 1000 °C, and grow a p-type GaN layer with a thickness of 10 nm to 100 nm.

[0087] When growing the p-type contact layer, control the growth temperature to 850 °C to 1000 °C, control the growth pressure to 100 torr to 300 torr, and grow a p-type contact layer with a thickness of 1 nm to 30 nm.

[0088] Among them, the Mg doping concentration in the p-type contact layer is 1×10 20 to 1×10 21 cm-3 .

[0089] After step S13, the preparation method may further include annealing the light-emitting diode.

[0090] After epitaxial growth is completed, the temperature of the reaction chamber is lowered to 650°C to 850°C and annealed in an N2 atmosphere for 5 to 15 minutes. Then, it is gradually lowered to room temperature. Subsequently, the chip is fabricated through cleaning, deposition, photolithography and etching processes.

[0091] In specific implementation, embodiments of this disclosure may use high-purity H2 and / or N2 as carrier gas, TEGa or TMGa as Ga source, TMIn as In source, SiH4 as n-type dopant, TMAl as aluminum source, ammonia as N source, and Cp2Mg as p-type dopant.

[0092] The method for fabricating a light-emitting diode provided in this disclosure avoids the local enrichment of In atoms in the quantum well by gradient temperature control and segmented Mo source flow rate adjustment; combined with an InAlGaN strain compensation layer, the diffusion of In atoms caused by lattice stress is reduced. The chip fabricated by this light-emitting diode shows a reduction in the full width at half maximum (FWHM) of light emitted by 0.5 nm to 2 nm, and the uniformity of In atom distribution is improved by 10% to 30%.

[0093] Furthermore, the gradient heating mode avoids crystal defects caused by low-temperature growth. X-ray diffraction (XRD) tests show that the full width at half maximum (FWHM) of the (002) plane diffraction peak of the quantum well layer is reduced by 10 arcsec to 50 arcsec, indicating excellent crystal quality.

[0094] Meanwhile, the uniform distribution of In atoms reduces non-radiative recombination, improving LED luminous efficiency by 1% to 5%; at the same time, strain compensation reduces device attenuation rate, and the luminous flux attenuation rate is less than 1% to 5% after working at a constant current of 20mA for 1000 hours.

[0095] Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 2 As shown, the light-emitting diode includes a first semiconductor layer 30, an active layer 40 and a second semiconductor layer 50 stacked sequentially. The active layer 40 includes multiple stacked periodic structures 41. Each periodic structure 41 includes alternating stacked quantum well layers 411 and quantum barrier layers 412. Along the stacking direction of the multiple periodic structures 41, the growth temperature of the quantum well layers 411 in each periodic structure 41 increases sequentially.

[0096] The active layer 40 of the light-emitting diode provided in this embodiment includes multiple stacked periodic structures 41. During the growth of the quantum well layer 411 of each periodic structure 41, the growth temperature is increased periodically to allow In atoms to achieve higher mobility at higher temperatures, promoting their uniform distribution within the GaN matrix. The temperature gradient effectively mitigates the rapid cooling effect at low temperatures, preventing In atoms from being frozen at defect sites, thereby reducing cluster density and preventing local enrichment of In atoms within the quantum well. Furthermore, In atom clusters can cause local lattice distortion, becoming stress concentration points and accelerating carrier trapping and hot carrier degradation. Gradient heating allows the In composition to fully relax at higher temperatures, releasing accumulated lattice strain and reducing the defect density at the quantum well / barrier interface. Simultaneously, the gradient heating mode avoids crystal defects caused by low-temperature growth, improving the crystal quality of the epitaxial layer. Uniform distribution of In atoms also reduces non-radiative recombination, improving the luminous efficiency of the light-emitting diode.

[0097] Optionally, the quantum well layer 411 of the periodic structure 41 is an InGaN layer, and the thickness of the InGaN layer is 1.5 nm to 6 nm.

[0098] Specifically, when growing the InGaN layer of each periodic structure 41, the InGaN layer is grown by adjusting the source flow rate in stages.

[0099] For example, in the first growth stage, the flow rate of the In source is linearly increased from 300 sccm to 3000 sccm, and the flow rate of the Ga source is linearly decreased from 500 sccm to 320 sccm, with an InGaN layer grown for 5 to 40 s. In the second growth stage, the flow rate of the In source is kept at 3000 sccm and the flow rate of the Ga source is kept at 320 sccm, with an InGaN layer grown for 15 to 120 s, forming an InGaN quantum well layer 411.

[0100] Optionally, such as Figure 2 As shown, the periodic structure 41 also includes a strain compensation layer 413, which includes an InAlGaN layer. In the strain compensation layer 413, the content of In is 1% to 10%, and the content of Al is 5% to 20%.

[0101] Among them, the strain compensation layer 413 adopts In x Al y Ga 1-x-y The N-layer has an In component x = 1%~10% (trace amounts of In increase the lattice constant) and an Al component y = 5%~20% (Al decreases the lattice constant). The ratio of x to y neutralizes the lattice mismatch between InGaN and GaN.

[0102] For example, the strain compensation layer 413 is 0.5 nm to 2 nm, and the ultrathin strain compensation layer 413 avoids weakening the quantum confinement effect.

[0103] The growth temperature of the strain compensation layer 413 is 800°C to 850°C, which is slightly higher than the maximum temperature of the quantum well layer 411 and lower than the conventional growth temperature of the GaN quantum barrier layer 412. The growth pressure is 100 Torr to 300 Torr, which is connected to the pressure of the subsequent GaN quantum barrier layer 412. The atmosphere is a mixture of nitrogen and hydrogen.

[0104] Optionally, the quantum barrier layer 412 of the periodic structure 41 is a GaN layer.

[0105] During the growth of GaN quantum barrier layer 412, a mixed atmosphere of nitrogen and hydrogen was used, the growth pressure was controlled at 100 Torr to 300 Torr, and the growth temperature was controlled at 800℃ to 960℃.

[0106] For example, the GaN quantum barrier layer 412 has a thickness of 8 nm to 20 nm to ensure sufficient barrier height to confine charge carriers.

[0107] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a buffer layer, a nucleation layer 22 and a u-shaped GaN layer 23 stacked in sequence, with the first semiconductor layer 30 located on the u-shaped GaN layer 23.

[0108] Optionally, the buffer layer includes AlN layers 21 stacked sequentially.

[0109] In the above implementation, AlN layer 21 serves as the initial transition layer. Although there is a mismatch between the lattice constant of AlN and the substrate, its high melting point and chemical stability can effectively prevent substrate impurities from diffusing to subsequent layers, providing a clean and low-defect initial nucleation substrate for nucleation layer 22 and reducing the interface energy barrier for subsequent GaN nucleation.

[0110] Among them, AlN layer 21 is an AlN layer 21 grown at a temperature between 400℃ and 800℃.

[0111] For example, the nucleation layer 22 may be a GaN layer or an AlGaN layer.

[0112] The nucleation layer 22 alleviates the lattice mismatch between the AlN layer 21 and the u-shaped GaN layer 23 through the merging growth of small-sized island structures. This reduces initial stress concentration, provides a uniform, low-defect nucleation platform for the u-shaped GaN layer 23, and optimizes subsequent crystal quality.

[0113] The thickness of the nucleation layer 22 can be from 0.3 μm to 0.5 μm.

[0114] Among them, the U-shaped GaN layer 23 grows laterally epitaxially at high temperatures, that is, it expands along the substrate plane, forming a flat surface with a low dislocation density through a two-dimensional growth mode, providing a buffer substrate with low defects and high flatness for the subsequent dislocation blocking layer and epitaxial layer. At the same time, its wide bandgap characteristic can initially reduce electron leakage and assist in carrier confinement in the subsequent active layer 40.

[0115] Exemplarily, the thickness of the U-shaped GaN layer 23 is 0.5 μm to 3 μm. Exemplarily, the thickness of the U-shaped GaN layer 23 is 2 μm.

[0116] Optionally, as Figure 2 shown, the light-emitting diode may further include a substrate 10. The substrate is a substrate for carrying the epitaxial layer, and the buffer layer is stacked on the substrate.

[0117] Exemplarily, the substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0118] As an example, in the embodiments of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat substrate.

[0119] Optionally, one of the first semiconductor layer 30 and the second semiconductor layer 50 is an n-type layer, and the other of the first semiconductor layer 30 and the second semiconductor layer 50 is a p-type layer.

[0120] Optionally, the n-type layer can be an n-type GaN layer. The thickness of the n-type layer is 0.5 μm to 3 μm.

[0121] Among them, the dopant of the n-type layer is silane, and the concentration of doped silane can be 5×10 18 cm -3 to 5×10 19 cm -3 .

[0122] Optionally, the active layer 40 may include 8 to 15 periods of quantum well layers 411 and quantum barrier layers 412.

[0123] Among them, the quantum well layer 411 includes an In x Ga 1-x N layer, 0.2 < x < 0.5, and the thickness of each quantum well layer 411 can be 1.5 nm to 6 nm.

[0124] Among them, the quantum barrier layer 412 includes a GaN or AlGaN layer, and the thickness of each quantum barrier layer 412 can be 8 nm to 20 nm.

[0125] Optionally, the p-type layer further includes a low-temperature p-type AlGaN layer 61, a p-type electron blocking layer 62, a high-temperature p-type GaN layer 63, and a p-type contact layer 64. The low-temperature p-type AlGaN layer 61, the p-type electron blocking layer 62, the high-temperature p-type GaN layer 63, and the p-type contact layer 64 are sequentially stacked on the active layer 40.

[0126] Exemplarily, the p-type electron blocking layer 62 can be a p-type Al y Ga 1-y N layer, where 0.1 < yk < 0.5, and the thickness of the p-type electron blocking layer 62 can be 10 nm to 100 nm.

[0127] If the thickness of the p-type electron blocking layer 62 is too thin, the blocking effect on electrons will be reduced. If the thickness of the p-type electron blocking layer 62 is too thick, the absorption of light by the p-type electron blocking layer 62 will increase, resulting in a decrease in the light emission efficiency of the LED.

[0128] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer 61 and the high-temperature p-type GaN layer 63 are doped with Mg.

[0129] The Mg doping concentration of the low-temperature p-type AlGaN layer 61 is 5×10 20 cm -3 to 1×10 21 cm -3 The Mg doping concentration of the high-temperature p-type GaN layer 63 is 1×10 18 cm -3 to 1×10 20 cm -3 .

[0130] Among them, the thickness of the low-temperature p-type AlGaN layer 61 can be 10 nm to 100 nm. For example, the thickness of the low-temperature p-type AlGaN layer 61 can be 80 nm.

[0131] Among them, the thickness of the high-temperature p-type GaN layer 63 can be 10 nm to 100 nm. For example, the thickness of the high-temperature p-type GaN layer 63 can be 50 nm.

[0132] Optionally, the thickness of the p-type contact layer 64 can be 1 nm to 30 nm. As an example, in the embodiments of the present disclosure, the thickness of the p-type contact layer 64 is 20 nm.

[0133] Among them, the p-type contact layer 64 is a p-type GaN layer, and the Mg doping concentration of the p-type GaN layer is 1×10 20 cm -3 to 1×10 21 cm -3 .

[0134] If the thickness of the p-type contact layer 64 is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the thickness of the p-type contact layer 64 is too thick, it will increase the absorption of light by the p-type contact layer 64, thereby reducing the luminous efficiency of the LED.

[0135] The mean data of characterization defect density tested on the same XRD testing machine are compared in Table 1 below: Table 1

[0136] The conventional quantum well structure epitaxial wafer fabrication process includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The epitaxial wafer fabricated in this embodiment includes a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The active layer is fabricated using the method described above.

[0137] The defect density 002 refers to the degree of orientation dispersion corresponding to a specific set of atomic planes (002 crystal planes) in a crystal, mainly reflecting the density of screw dislocations. For hexagonal crystal systems, the 002 crystal plane is usually parallel to the c-axis.

[0138] The higher the defect density value, the greater the defect density of the film.

[0139] As can be seen from the data in Table 1 above, the defect density of the light-emitting diode provided by the embodiments of this disclosure is effectively reduced, which can improve the radiative recombination efficiency and improve the light-emitting effect of the light-emitting diode.

[0140] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: A first semiconductor layer is formed on the substrate; An active layer is formed on the first semiconductor layer. The active layer includes multiple stacked periodic structures. The periodic structures include alternating stacked quantum well layers and quantum barrier layers. Along the stacking direction of the multiple periodic structures, the growth temperature of the quantum well layers in each periodic structure increases sequentially. A second semiconductor layer is formed on the active layer.

2. The preparation method according to claim 1, characterized in that, Forming an active layer on the first semiconductor layer includes: The growth temperature was controlled at 700℃ to 810℃ to grow the first quantum well layer of the periodic structure. The growth temperature of the quantum well layer of each subsequent periodic structure is increased progressively from the growth temperature of the previous periodic structure until the stacking of the periodic structures with a set number of layers is completed, and the growth temperature of the quantum well layer of the last periodic structure is less than or equal to 810°C.

3. The preparation method according to claim 2, characterized in that, The progressive value ranges from 0.2℃ to 0.8℃.

4. The preparation method according to any one of claims 1 to 3, characterized in that, The quantum well layers for growing each of the aforementioned periodic structures include: The flow rate of the In source was linearly increased from 100 sccm to 800 sccm to 1000 sccm to 5000 sccm, and the flow rate of the Ga source was linearly decreased from 300 sccm to 1000 sccm to 100 sccm to 500 sccm to grow the first InGaN layer. Maintain the flow rates of the In source and the Ga source to grow a second InGaN layer of the same length.

5. The preparation method according to claim 4, characterized in that, The first duration is 5s to 40s, and the second duration is 15s to 120s.

6. The preparation method according to any one of claims 1 to 3, characterized in that, Forming an active layer on the first semiconductor layer includes: A strain compensation layer is grown between the quantum well layer and the quantum barrier layer of each of the periodic structures. The strain compensation layer includes an InAlGaN layer, wherein the In content is 1% to 10% and the Al content is 5% to 20%.

7. The preparation method according to claim 6, characterized in that, The thickness of the strain compensation layer is 0.5 nm to 2 nm.

8. A light-emitting diode, characterized in that, The light-emitting diode includes a first semiconductor layer (30), an active layer (40), and a second semiconductor layer (50) stacked sequentially. The active layer (40) includes multiple stacked periodic structures (41). Each periodic structure (41) includes alternating stacked quantum well layers (411) and quantum barrier layers (412). Along the stacking direction of the multiple periodic structures (41), the growth temperature of the quantum well layers (411) in each periodic structure (41) increases sequentially.

9. The light-emitting diode according to claim 8, characterized in that, The periodic structure (41) further includes a strain compensation layer (413), which includes an InAlGaN layer. In the strain compensation layer (413), the content of In is 1% to 10% and the content of Al is 5% to 20%.

10. The light-emitting diode according to claim 9, characterized in that, The thickness of the strain compensation layer (413) is 0.5 nm to 2 nm.

Images