Method for manufacturing light emitting diode chip and light emitting diode chip

Abstract

This disclosure discloses a method for fabricating a light-emitting diode (LED) chip and the LED chip itself, belonging to the field of semiconductor technology. The fabrication method includes fabricating an epitaxial layer comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; etching mesa trenches on the epitaxial layer, the mesa trenches extending from the second semiconductor layer to the first semiconductor layer; fabricating a hard mask having holes, the inner contour of which has a trapezoidal cross-section in the epitaxial growth direction, with the lower base of the trapezoid closer to the epitaxial layer than the upper base; depositing a metal film based on the hard mask, such that at least a portion of the metal film fills the holes; peeling off the metal film outside the holes, retaining the metal film inside the holes as a silver mirror layer; and removing the hard mask. The embodiments of this disclosure ensure that the silver mirror layer enhances the brightness of the LED chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a light-emitting diode (LED) chip and the LED chip itself. Background Technology

[0002] A light-emitting diode (LED) chip is a semiconductor device that can convert electrical energy into light energy.

[0003] In related technologies, a silver mirror layer is present on one side of the epitaxial layer of a light-emitting diode (LED) chip. This silver mirror layer acts as a reflective layer, effectively reflecting the light generated by the epitaxial layer and thus improving the brightness of the LED chip. To fabricate the silver mirror layer, a magnetron sputtering device is used to deposit a metal film, followed by a negative photoresist lift-off process to ensure that the silver mirror layer remains only at the desired locations.

[0004] However, due to the strong filling capability of magnetron sputtering equipment, there is a significant over-sputtering problem, resulting in the final silver mirror layer size being 3-5µm larger than the design size. Therefore, to avoid short circuits caused by the excessively large silver mirror layer, the size of the silver mirror layer is intentionally designed to be smaller, which limits the effect of the silver mirror layer on improving brightness. Summary of the Invention

[0005] This disclosure provides a method for fabricating a light-emitting diode (LED) chip and an LED chip thereof, which can effectively solve the problem of silver mirror layer over-plating. The technical solution is as follows: On one hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode chip, including: An epitaxial layer is prepared, the epitaxial layer comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; Mesa trenches are etched on the epitaxial layer, and the mesa trenches extend from the second semiconductor layer to the first semiconductor layer; A hard mask is prepared, the hard mask having holes, the inner contour of the holes having a trapezoidal cross-section in the epitaxial growth direction, and the lower base of the trapezoid being closer to the epitaxial layer than the upper base; Based on the hard mask, a metal film is deposited such that at least a portion of the metal film fills the holes; Peel off the metal film layer outside the hole, leaving the metal film layer inside the hole as a silver mirror layer; Remove the hard mask.

[0006] In one implementation of this disclosure, the preparation of the hard mask includes: A first submask is deposited on one side of the epitaxial layer; A second sub-mask is deposited on the side of the first sub-mask opposite to the epitaxial layer, and the etching rate of the second sub-mask is less than that of the first sub-mask. Sub-holes are sequentially etched in the second sub-mask and the first sub-mask, and the two sub-holes are connected to form the hole.

[0007] In one implementation of this disclosure, the first sub-mask is a silicon dioxide layer and the second sub-mask is an aluminum oxide layer.

[0008] In one implementation of this disclosure, the preparation of the hard mask further includes: The deposition thickness of the first sub-mask is set to 200~1200nm; The deposition thickness of the second sub-mask is set to 20~120nm.

[0009] In one implementation of this disclosure, before etching the mesa trench on the epitaxial layer, the fabrication method includes: A transparent conductive layer is prepared on one side of the epitaxial layer.

[0010] In one implementation of this disclosure, peeling off the metal film layer outside the hole includes: An adhesive film layer is attached to the side of the metal film layer that faces away from the hard mask; The adhesive film layer and the metal film layer that are adhered to the adhesive film layer are peeled off together.

[0011] In one implementation of this disclosure, after removing the hard mask, the fabrication method includes: A protective layer is prepared such that it covers the silver mirror layer, the sidewalls of the mesa trench, and the first semiconductor layer; A first electrode hole and a second electrode hole are etched on the protective layer. The first electrode hole is located on the protective layer at the position corresponding to the first semiconductor layer, and one end of the first electrode hole extends through the first semiconductor layer. The second electrode hole is located on the protective layer at the position corresponding to the silver mirror layer, and one end of the second electrode hole extends through the silver mirror layer. A first electrode and a second electrode are prepared such that the first electrode passes through the first electrode hole and contacts the first semiconductor layer, and the second electrode passes through the second electrode hole and contacts the silver mirror layer.

[0012] On the other hand, this disclosure provides a light-emitting diode chip, which is fabricated by the fabrication method described in the preceding aspect. The light-emitting diode chip includes an epitaxial layer and a silver mirror layer. The epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. The epitaxial layer has a mesa trench that extends from the second semiconductor layer to the first semiconductor layer. The silver mirror layer is located on one side of the second semiconductor layer. The cross-section of the silver mirror layer in the epitaxial growth direction is trapezoidal, and the lower base of the trapezoid is closer to the epitaxial layer than the upper base.

[0013] In one implementation of this disclosure, the light-emitting diode switch chip further includes a transparent conductive layer; The transparent conductive layer is located between the epitaxial layer and the silver mirror layer.

[0014] In one implementation of this disclosure, the light-emitting diode switch chip further includes a protective layer; The protective layer covers the silver mirror layer, the sidewalls of the mesa trench, and the first semiconductor layer.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The fabrication method provided in this disclosure is used to fabricate a light-emitting diode (LED) chip with a silver mirror layer. In the fabrication process, an epitaxial layer is first fabricated and etched to obtain mesa trenches. Then, a hard mask with holes is fabricated on one side of the epitaxial layer to accommodate subsequently deposited metal films. Next, a metal film is deposited based on the hard mask. After deposition, a portion of the metal film is located inside the holes, and the other portion is located outside the holes. Since the cross-section of the inner contour of the hole in the epitaxial growth direction is trapezoidal, and the lower base of the trapezoid is closer to the epitaxial layer than the upper base, the metal film inside the hole and the metal film outside the hole are separated. Thus, by peeling off the metal film outside the hole, only the metal film inside the hole can be retained, and the retained metal film serves as the silver mirror layer. Finally, the hard mask is removed.

[0016] In other words, a hard mask is used to separate the metal film layer into a portion located inside the holes and a portion located outside the holes, making it easier to peel off the portion of the metal film layer located outside the holes. Compared to the negative adhesive lift-off process in related technologies, this design effectively solves the problem of over-plating, ensuring that the size of the silver mirror layer meets the design requirements, thereby guaranteeing the brightness of the LED chip. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure; Figure 2 This is a flowchart of another method for fabricating a light-emitting diode chip provided in this disclosure embodiment; Figure 3 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the preparation process provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the structure of a light-emitting diode chip provided in an embodiment of this disclosure.

[0019] Icon labels: 10. Epitaxial layer; 110, First semiconductor layer; 120, Active layer; 130, Second semiconductor layer; 140, Mesa trench; 20. Hard mask; 210. Hole; 211. Sub-hole; 220. First sub-mask; 230. Second sub-mask; 30. Silver mirror layer; 40. Transparent conductive layer; 50. Protective layer; 510, First electrode hole; 520, Second electrode hole; 610. First electrode; 620. Second electrode; 70. Substrate. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] ADB (Adaptive Driving Beam) is a new type of vehicle lighting system that has been widely used in automobiles, especially in new energy vehicles.

[0022] In related technologies, the main light-emitting device of ADB (Advanced Driver Assistance) headlights is a light-emitting diode (LED) chip. The LED chip mainly consists of an epitaxial layer, with a silver mirror layer on one side. The silver mirror layer acts as a reflective layer, effectively reflecting the light generated by the epitaxial layer, thereby improving the brightness of the LED chip. In fabricating the silver mirror layer, a magnetron sputtering device is used to deposit a metal film, and then a negative adhesive lift-off process is used to ensure that the silver mirror layer remains only in the desired locations.

[0023] However, due to the strong filling capability of magnetron sputtering equipment, there is a significant over-sputtering problem, resulting in the final silver mirror layer size being 3-5µm larger than the design size. Therefore, to avoid short circuits caused by the excessively large silver mirror layer, the size of the silver mirror layer is intentionally designed to be smaller, which limits the effect of the silver mirror layer on improving brightness.

[0024] To address the aforementioned technical problems, this disclosure provides a method for fabricating a light-emitting diode (LED) chip. Figure 1 For a flowchart of the fabrication method of this light-emitting diode chip, please refer to [link / reference]. Figure 1 In this embodiment, the preparation method includes: Step 101: Prepare epitaxial layer 10.

[0025] The epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially.

[0026] Step 102: Etch the mesa trench 140 on the epitaxial layer 10.

[0027] The mesa trench 140 extends from the second semiconductor layer 130 to the first semiconductor layer 110.

[0028] Step 103: Prepare hard mask 20.

[0029] The hard mask 20 has a hole 210. The inner contour of the hole 210 has a trapezoidal cross section in the epitaxial growth direction, and the lower base of the trapezoid is closer to the epitaxial layer 10 than the upper base.

[0030] Step 104: Deposit a metal film based on the hard mask 20 such that at least a portion of the metal film fills the holes 210.

[0031] Step 105: Peel off the metal film layer outside the hole 210, and retain the metal film layer inside the hole 210 as the silver mirror layer 30.

[0032] Step 106: Remove hard mask 20.

[0033] The fabrication method provided in this disclosure is used to fabricate a light-emitting diode (LED) chip having a silver mirror layer 30. In the fabrication of the LED chip, an epitaxial layer 10 is first fabricated and etched to obtain mesa trenches. Then, a hard mask 20 is fabricated on one side of the epitaxial layer 10. The hard mask 20 has holes 210 for accommodating subsequently deposited metal films. Next, a metal film is deposited based on the hard mask 20. After deposition, a portion of the metal film is located inside the holes 210, and another portion is located outside the holes 210. Because the cross-section of the inner contour of the holes 210 in the epitaxial growth direction is trapezoidal, and the lower base of the trapezoid is closer to the epitaxial layer 10 than the upper base, the metal film inside the holes 210 and the metal film outside the holes 210 are separated. In this way, by peeling off the metal film layer outside the hole 210, only the metal film layer inside the hole 210 can be retained, and the retained metal film layer serves as the silver mirror layer 30. Finally, the hard mask 20 is removed.

[0034] In other words, the metal film layer is divided into a portion inside the hole 210 and a portion outside the hole 210 by the hard mask 20, making the portion of the metal film layer outside the hole 210 easier to peel off. Compared with the negative adhesive lift-off process in related technologies, this design effectively solves the problem of over-plating, ensuring that the size of the silver mirror layer 30 meets the design requirements, thereby ensuring the brightness of the light-emitting diode chip.

[0035] Figure 2 For another method of fabricating a light-emitting diode chip provided in this disclosure, see [link to relevant documentation]. Figure 2 In this embodiment, the preparation method includes: Step 201: Provide a substrate 70.

[0036] For example, the substrate 70 is a sapphire substrate, a silicon substrate, or other light-emitting diode chip substrate material.

[0037] Step 202: Prepare epitaxial layer 10.

[0038] The epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially.

[0039] For example, an epitaxial layer 10 is deposited using metal-organic chemical vapor deposition (MOCVD).

[0040] For example, the first semiconductor layer 110 is of a first conductivity type, the second semiconductor layer 130 is of a second conductivity type, and the second conductivity type is different from the first conductivity type. In this embodiment, the first semiconductor layer 110 is an N-type GaN layer, the active layer 120 is a quantum well layer, and the second semiconductor layer 130 is a P-type GaN layer.

[0041] Of course, in other embodiments, the first semiconductor layer 110 may be a P-type GaN layer, the active layer 120 may be a quantum well layer, and the second semiconductor layer 130 may be an N-type GaN layer. This disclosure does not limit this.

[0042] Step 203: Prepare a transparent conductive layer 40 on one side of the epitaxial layer 10.

[0043] For example, the transparent conductive layer 40 is an indium tin oxide (ITO) layer, which can be prepared by magnetron sputtering and pulsed laser deposition.

[0044] Step 204: Etching to obtain mesa trench 140 (see...) Figure 3 ).

[0045] In this embodiment, the mesa trench 140 extends from the transparent conductive layer 40, the second semiconductor layer 130, the active layer 120, to the first semiconductor layer 110.

[0046] In step 204, the mesa trench 140 is etched by photolithography using inductively coupled plasma (ICP) etching.

[0047] Step 205: Prepare hard mask 20.

[0048] In this embodiment, step 205 includes: Step 2051: Deposit a first submask 220 on one side of the epitaxial layer 10.

[0049] For example, the first sub-mask 220 is a silicon dioxide layer.

[0050] In step 2051, the deposition thickness of the first sub-mask 220 is set to 200~1200nm.

[0051] Step 2052: Deposit a second sub-mask 230 on the side of the first sub-mask 220 facing away from the epitaxial layer 10 (see...) Figure 4 The corrosion rate of the second sub-mask 230 is less than that of the first sub-mask 220.

[0052] For example, the second sub-mask 230 is an aluminum oxide layer.

[0053] In step 2052, the deposition thickness of the second sub-mask 230 is set to 20~120nm.

[0054] Step 2053: Sub-holes 211 are sequentially etched in the second sub-mask 230 and the first sub-mask 220, and the two sub-holes 211 are connected to form a hole 210. The inner contour of the hole 210 has a trapezoidal cross-section in the epitaxial growth direction, and the lower base of the trapezoid is closer to the epitaxial layer 10 than the upper base.

[0055] In step 2053, the hard mask 20 is first photolithographically etched, and the second sub-mask 230 and the first sub-mask 220 are etched using an ICP process (see...). Figure 5 Then, the second sub-mask 230 and the first sub-mask 220 are laterally etched using BOE solution to obtain the sub-hole 211 (see...). Figure 6 ).

[0056] Because the etching rate of the second sub-mask 230 is significantly lower than that of the first sub-mask 220, the degree of lateral etching (i.e., side etching) occurring on the lower first sub-mask 220 will be much greater than that on the upper second sub-mask 230 under the same etching time. Therefore, this objective difference in etching rate naturally results in an inverted trapezoidal cross-sectional morphology that is narrower at the top and wider at the bottom. This structure significantly simplifies the process operation, eliminating the need for complex multiple tilting etching steps, and enabling the high-yield and high-consistency fabrication of holes 210 that meet the requirements for membrane breakage.

[0057] Furthermore, since the silicon dioxide layer and the aluminum oxide layer exhibit extremely different corrosion rates in fluorine-containing etching solutions (such as buffered oxide etchant BOE), with the silicon dioxide layer having a much higher corrosion rate than the aluminum oxide layer, the use of these two specific material stacking combinations can achieve rapid lateral etching of the first sub-mask 220 and lateral retention of the second sub-mask 230 with extremely high process tolerance, effectively improving the fabrication yield.

[0058] Furthermore, by setting the thickness of the first sub-mask 220 within the range of 200~1200nm, sufficient height difference space is provided for the subsequent deposition of the silver mirror layer 30, while avoiding the difficulty of etching penetration caused by excessive thickness accumulation. At the same time, by limiting the thickness of the second sub-mask 230 to 20~120nm, it can be quickly perforated and guided by the etchant, and its thickness is sufficient to maintain reliable support at the top of the hole 210.

[0059] Step 206: Deposit a metal film based on the hard mask 20 such that at least a portion of the metal film fills the hole 210.

[0060] Step 207: Peel off the metal film layer outside the hole 210, and retain the metal film layer inside the hole 210 as the silver mirror layer 30.

[0061] In this embodiment, step 207 includes: First, an adhesive film is attached to the side of the metal film layer that faces away from the hard mask 20.

[0062] Then, the adhesive film layer, along with the metal film layer that adheres to it, is peeled off together.

[0063] Because a large area of ​​the waste metal film layer outside the holes 210 is exposed on the outermost surface of the hard mask 20, and is separated from the metal film layer inside the holes 210 by the cutting of the trapezoidal holes 210, the waste metal film layer can be firmly grasped and torn off together by directly attaching an adhesive film layer, relying on physical adhesion. This purely mechanical dry stripping method is very simple and quick to operate, avoiding the expensive and highly polluting organic stripping solutions or acetone solvents used in traditional lift-off processes. In this way, not only is the stripping efficiency improved, but the green environmental protection of the production environment and the safety of operators are also ensured.

[0064] For example, the adhesive film layer is a blue film or an adhesive backing film, etc. During application, a constant-pressure flexible roller is used to remove air bubbles. After peeling off the adhesive film layer together with the metal film layer, the peeled waste material can be placed on a heating table and heated to remove its stickiness and separate the waste material.

[0065] Step 208: Remove hard mask 20 (see...) Figure 7 ).

[0066] The remaining hard mask 20 was etched using BOE solution.

[0067] Step 209: Prepare protective layer 50.

[0068] The protective layer 50 covers the silver mirror layer 30, the sidewalls of the mesa trench 140, and the first semiconductor layer 110.

[0069] Step 2010: Etch the first electrode hole 510 and the second electrode hole 520 on the protective layer 50.

[0070] The first electrode hole 510 is located at the position of the protective layer 50 corresponding to the first semiconductor layer 110, and one end of the first electrode hole 510 extends through the first semiconductor layer 110. The second electrode hole 520 is located at the position of the protective layer 50 corresponding to the silver mirror layer 30, and one end of the second electrode hole 520 extends through the silver mirror layer 30.

[0071] In step 2010, the first electrode hole 510 and the second electrode hole 520 are processed using ICP etching process or BOE (Buffered Oxide Etchant) etching process.

[0072] Step 2011: Fabrication of the first electrode 610 and the second electrode 620 (see...) Figure 8 ).

[0073] The first electrode 610 passes through the first electrode hole 510 and contacts the first semiconductor layer 110, and the second electrode 620 passes through the second electrode hole 520 and contacts the silver mirror layer 30.

[0074] Because the protective layer 50 fully covers the exposed portions of the silver mirror layer 30 and the epitaxial layer 10, especially the exposed PN junction sidewalls at the mesa trench 140, it forms a dense physical barrier that cuts off the path for external moisture and oxygen to corrode the silver mirror layer 30, thus avoiding the risk of the silver mirror layer 30 turning black and the chip leaking current.

[0075] This disclosure provides a light-emitting diode chip. Figure 8 This is a schematic diagram of the structure of the light-emitting diode chip, combined with... Figure 8 In this embodiment, the light-emitting diode chip includes an epitaxial layer 10 and a silver mirror layer 30. The epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The epitaxial layer 10 has a mesa trench 140 extending from the second semiconductor layer 130 to the first semiconductor layer 110. The silver mirror layer 30 is located on one side of the second semiconductor layer 130. The cross-section of the silver mirror layer 30 in the epitaxial growth direction is trapezoidal, and the lower base of the trapezoid is closer to the epitaxial layer 10 than the upper base.

[0076] In this embodiment, the LED switching chip also includes a transparent conductive layer 40, which is located between the epitaxial layer 10 and the silver mirror layer 30.

[0077] In the above implementation, since the transparent conductive layer 40 is sandwiched between the epitaxial layer 10 and the silver mirror layer 30, and the transparent conductive layer 40 has excellent lateral charge transport capability, it can guide the injected charge to achieve uniform distribution in the lateral plane before entering the active layer 120 to generate recombination light emission. Therefore, it effectively prevents dark spots or local overheating caused by excessive local current in the light-emitting diode chip, greatly improves the light emission uniformity of the chip plane, and at the same time, as a transition layer, it also optimizes the adhesion of the silver mirror layer 30.

[0078] In this embodiment, the LED switching chip further includes a protective layer 50. The protective layer 50 covers the silver mirror layer 30, the sidewalls of the mesa trench 140, and the first semiconductor layer.

[0079] In this embodiment, the protective layer 50 covers the silver mirror layer 30, which is easily oxidized and sulfided, and can block the intrusion and penetration of water vapor, oxygen and various harmful ions in the external environment, thereby extending the service life and light decay maintenance rate of the light-emitting diode chip in the harsh high temperature and high humidity environment of the vehicle.

[0080] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0081] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A method for fabricating a light-emitting diode chip, characterized in that, include: An epitaxial layer (10) is prepared, the epitaxial layer (10) comprising a first semiconductor layer (110), an active layer (120), and a second semiconductor layer (130) stacked sequentially. A mesa trench (140) is etched on the epitaxial layer (10), the mesa trench (140) extending from the second semiconductor layer (130) to the first semiconductor layer (110). A hard mask (20) is prepared, the hard mask (20) having holes (210), the inner contour of the holes (210) having a trapezoidal cross section in the epitaxial growth direction, and the lower base of the trapezoid being closer to the epitaxial layer (10) than the upper base. Based on the hard mask (20), a metal film is deposited such that at least a portion of the metal film fills the hole (210); The metal film layer outside the hole (210) is peeled off, and the metal film layer inside the hole (210) is retained as the silver mirror layer (30). Remove the hard mask (20).

2. The preparation method according to claim 1, characterized in that, The preparation of the hard mask (20) includes: A first submask (220) is deposited on one side of the epitaxial layer (10); A second sub-mask (230) is deposited on the side of the first sub-mask (220) opposite to the epitaxial layer (10), and the etching rate of the second sub-mask (230) is less than that of the first sub-mask (220). Sub-holes (211) are sequentially etched in the second sub-mask (230) and the first sub-mask (220), and the two sub-holes (211) are connected to form the hole (210).

3. The preparation method according to claim 2, characterized in that, The first sub-mask (220) is a silicon dioxide layer, and the second sub-mask (230) is an aluminum oxide layer.

4. The preparation method according to claim 2, characterized in that, The preparation of the hard mask (20) also includes: The deposition thickness of the first sub-mask (220) is set to 200~1200nm; The deposition thickness of the second sub-mask (230) is set to 20~120nm.

5. The preparation method according to claim 1, characterized in that, Before etching the mesa trench (140) on the epitaxial layer (10), the fabrication method includes: A transparent conductive layer (40) is prepared on one side of the epitaxial layer (10).

6. The preparation method according to claim 1, characterized in that, Peeling off the metal film layer outside the hole (210) includes: An adhesive film is attached to the side of the metal film layer that is opposite to the hard mask (20); The adhesive film layer and the metal film layer that are adhered to the adhesive film layer are peeled off together.

7. The preparation method according to claim 1, characterized in that, After removing the hard mask (20), the preparation method includes: Prepare a protective layer (50) such that the protective layer (50) covers the silver mirror layer (30), the sidewall of the mesa trench (140), and the first semiconductor layer (110); A first electrode hole (510) and a second electrode hole (520) are etched on the protective layer (50). The first electrode hole (510) is located on the protective layer (50) at the position corresponding to the first semiconductor layer (110), and one end of the first electrode hole (510) extends through the first semiconductor layer (110). The second electrode hole (520) is located on the protective layer (50) at the position corresponding to the silver mirror layer (30), and one end of the second electrode hole (520) extends through the silver mirror layer (30). Prepare a first electrode (610) and a second electrode (620) such that the first electrode (610) passes through the first electrode hole (510) and contacts the first semiconductor layer (110), and the second electrode (620) passes through the second electrode hole (520) and contacts the silver mirror layer (30).

8. A light-emitting diode chip, characterized in that, The light-emitting diode chip is prepared by the preparation method according to any one of claims 1 to 7, and includes an epitaxial layer (10) and a silver mirror layer (30). The epitaxial layer (10) includes a first semiconductor layer (110), an active layer (120), and a second semiconductor layer (130) stacked sequentially. The epitaxial layer (10) has a mesa trench (140) that extends from the second semiconductor layer (130) to the first semiconductor layer (110). The silver mirror layer (30) is located on one side of the second semiconductor layer (130). The cross-section of the silver mirror layer (30) in the epitaxial growth direction is trapezoidal, and the lower base of the trapezoid is closer to the epitaxial layer (10) than the upper base.

9. The light-emitting diode chip according to claim 8, characterized in that, The light-emitting diode switch chip also includes a transparent conductive layer (40). The transparent conductive layer (40) is located between the epitaxial layer (10) and the silver mirror layer (30).

10. The light-emitting diode chip according to claim 8, characterized in that, The LED switch chip also includes a protective layer (50). The protective layer (50) covers the silver mirror layer (30), the sidewalls of the mesa trench (140), and the first semiconductor layer.

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