Light emitting diode and method of manufacturing the same

Abstract

This disclosure provides a light-emitting diode and a method for fabricating the same. The method includes: sequentially growing a buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer to form a first semiconductor layer, wherein the composite functional layer includes multiple sublayers, and the growth temperature of the multiple sublayers gradually increases along the growth direction; fabricating an active layer on the first semiconductor layer; and fabricating a second semiconductor layer on the active layer.

Description

Technical Field

[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for fabricating the same. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that emits light. It has advantages such as energy saving and high durability, and has been widely used in lighting and display fields.

[0003] The related technology provides a method for fabricating a light-emitting diode, the method comprising: fabricating a first semiconductor layer; fabricating an active layer on the first semiconductor layer; and fabricating a second semiconductor layer on the active layer.

[0004] When LEDs are fabricated using the above method, micron-sized regular hexagonal or inverted triangular pyramidal defects will be generated on the surface of the second semiconductor layer. These defects may penetrate the active layer, forming current leakage paths, causing the LED to break down prematurely at low voltage, reducing its operating life and reliability, and thus seriously damaging the performance and yield of the LED. Summary of the Invention

[0005] This disclosure provides a light-emitting diode and its fabrication method, which can reduce defects on the surface of the second semiconductor layer and improve the reliability and luminous efficiency of the light-emitting diode. The technical solution is as follows: A method for fabricating a light-emitting diode is provided, the method comprising: A buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer are grown sequentially to form a first semiconductor layer. The composite functional layer includes multiple sub-layers, and the growth temperature of the multiple sub-layers gradually increases along the growth direction. An active layer is fabricated on the first semiconductor layer; A second semiconductor layer is fabricated on the active layer.

[0006] Optionally, the plurality of sublayers include a first coarsening sublayer, a second coarsening sublayer, and a planarization sublayer stacked sequentially; Growing the composite functional layer includes: The first roughened sublayer is prepared using a first temperature. On the first roughened sublayer, a second roughened sublayer is formed at a second temperature, wherein the second temperature is higher than the first temperature; On the second roughened sublayer, the planarization sublayer is made at a third temperature, which is higher than the second temperature.

[0007] Optionally, the step of fabricating the first roughened sublayer at a first temperature includes: The first roughened sublayer is prepared under the conditions of a first temperature of 1050~1060℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0008] Optionally, the process of fabricating the second roughened sublayer at a second temperature includes: The second roughened sublayer is produced under the following conditions: a second temperature of 1080~1090℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0009] Optionally, the planarization sublayer is fabricated using a third temperature, including: The planarization sublayer is fabricated under the conditions of a third temperature of 1120~1130℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0010] Optionally, the thickness of the first roughening sublayer is 0.03~0.07μm; the thickness of the second roughening sublayer is 0.72~0.76μm; and the thickness of the planarization sublayer is 0.75~0.79μm.

[0011] On the other hand, a light-emitting diode is provided, the light-emitting diode comprising: a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially; The first semiconductor layer includes a buffer layer, a composite functional layer, an unintentionally doped GaN layer and a doped GaN layer stacked sequentially. The composite functional layer includes multiple sub-layers, and the growth temperature of the multiple sub-layers gradually increases along the growth direction.

[0012] Optionally, the plurality of sublayers includes a first coarsening sublayer, a second coarsening sublayer, and a planarization sublayer, which are sequentially stacked on the buffer layer.

[0013] Optionally, the thickness of the first roughening sublayer is 0.03~0.07μm; the thickness of the second roughening sublayer is 0.72~0.76μm; and the thickness of the planarization sublayer is 0.75~0.79μm.

[0014] Optionally, the first roughening sublayer, the second roughening sublayer, and the planarization sublayer can be GaN layers.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment of the present disclosure, the first semiconductor layer of the light-emitting diode includes a buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer grown sequentially. The buffer layer can provide nucleation centers to improve the crystal quality of subsequent layers; the undoped GaN layer can help grow a higher quality active region; and the doped GaN layer can provide carrier transport channels.

[0016] Furthermore, growing the composite functional layer using a gradient heating method can gradually increase the growth temperature of the composite functional layer, thereby avoiding excessively rapid growth of the composite functional layer due to a single high-temperature growth, which could lead to defects in the composite functional layer. Using gradient heating can more precisely control the growth state of the composite functional layer, thereby creating a flat surface and avoiding defects caused by uneven bottoms during subsequent layer fabrication, significantly improving the reliability of the light-emitting diode chip. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for fabricating a light-emitting diode provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another method for fabricating a light-emitting diode provided in this disclosure embodiment; Figure 3 This is a comparison diagram of the surface roughness of light-emitting diodes provided in the embodiments of this disclosure and light-emitting diodes provided in related technologies; Figure 4 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 5 This is a comparison diagram of the light-emitting diode provided in the embodiments of this disclosure and the light-emitting diode provided in related technologies; Figure 6 This is a temperature-time line graph of the fabrication of a composite functional layer for a light-emitting diode provided in the embodiments of this disclosure and related technologies.

[0019] The attached figures are labeled as follows: 100: Substrate; 101: First semiconductor layer; 102: Active layer; 103: Second semiconductor layer; 11: Buffer layer; 12: Composite functional layer; 13: Unintentionally doped GaN layer; 14: Doped GaN layer; 121: First coarsened sublayer; 122: Second coarsened sublayer; 123: Flattening sublayers; X: Small, granular defects. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 1 The method includes the following steps: S11. A buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer are grown sequentially to form a first semiconductor layer. The composite functional layer includes multiple sub-layers, and the growth temperature of the multiple sub-layers gradually increases along the growth direction.

[0022] S12. An active layer is fabricated on the first semiconductor layer.

[0023] S13. A second semiconductor layer is fabricated on the active layer.

[0024] In this embodiment, the first semiconductor layer of the light-emitting diode includes a buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer grown sequentially. The buffer layer provides nucleation centers, improving the crystal quality of subsequent layers; the undoped GaN layer facilitates the growth of a higher-quality active region; and the doped GaN layer provides carrier transport channels. Furthermore, the composite functional layer is grown using a gradient heating method, which gradually increases the growth temperature of the composite functional layer. This avoids excessively rapid growth at a single high temperature, which could lead to defects in the composite functional layer. Gradient heating also allows for more precise control of the growth state of the composite functional layer, resulting in a smooth surface and preventing defects caused by uneven bottom surfaces during subsequent layer fabrication, significantly improving the reliability of the light-emitting diode chip.

[0025] Figure 2 This is a flowchart of another method for fabricating a light-emitting diode provided in this disclosure. See also... Figure 2 The method includes the following steps: S21. Fabricate a buffer layer on the substrate.

[0026] In the embodiments disclosed herein, the substrate can be any one of the following: patterned sapphire substrate (PPS), Si substrate, and SiC substrate.

[0027] For example, the substrate is a patterned sapphire substrate.

[0028] In this embodiment of the disclosure, the buffer layer may be a GaN layer or an AlN layer.

[0029] In this implementation, there is usually a large difference in lattice constant between the substrate material (such as sapphire) and the epitaxial material (such as GaN). This difference leads to a large number of dislocations and other crystal defects during epitaxial growth. The buffer layer can serve as a transition layer to alleviate lattice mismatch, reduce dislocation propagation, and thus improve the crystal quality of the epitaxial layer.

[0030] For example, the buffer layer can be a GaN layer.

[0031] In the embodiments disclosed herein, the above-mentioned semiconductor layer can be grown using a Veeco K465i, C4, or RB metal-organic chemical vapor deposition (MOCVD) apparatus or an AIXTRON MOCVD apparatus. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N-type source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.

[0032] S22. Create a composite functional layer on the buffer layer.

[0033] In one example, step S22 includes: The first step is to create the first roughened sublayer using the first temperature.

[0034] The first roughening sublayer serves as a low-temperature nucleation layer. At low temperatures, atomic surface diffusion is restricted, maintaining the discrete island-like morphology of the grains, thus forming the first roughening sublayer. Furthermore, a second roughening sublayer and a planarization sublayer are subsequently grown on the surface of this first roughening sublayer.

[0035] In this embodiment of the disclosure, TMGa, N2, NH3 and H2 are introduced into an organometallic chemical vapor deposition apparatus, and a first roughening sublayer is fabricated at a first temperature.

[0036] In this embodiment of the disclosure, the first roughened sublayer is a GaN layer.

[0037] In this implementation, the first roughened sublayer is a GaN layer. The GaN layer and the underlying buffer layer have a lattice height match, which can effectively reduce the interface stress and dislocation density during the epitaxial structure growth process and ensure crystal quality.

[0038] In this embodiment of the disclosure, the thickness of the first roughened sublayer is 0.03~0.07μm.

[0039] In this implementation, the thickness of the first coarsening sublayer is 0.03~0.07μm. The relatively thin thickness can limit the size of the discrete island-like structures in the first coarsening sublayer, increase the nucleation density, and make them easier to be filled and merged by the subsequent second coarsening sublayer.

[0040] For example, the thickness of the first roughened sublayer is 0.05 μm.

[0041] In this embodiment of the disclosure, the first roughened sublayer is prepared under the conditions of a first temperature of 1050~1060℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0042] In this implementation, a first temperature of 1050~1060℃ restricts atomic surface diffusion, maintaining the discrete island-like morphology of the grains and thus forming a rough surface. This significantly increases the diffusion length of atoms on the buffer layer surface, resulting in a more uniform distribution and more reasonable spacing of crystal nuclei, preventing a large number of small islands from crowding together, thereby creating a good foundation for the subsequent growth of the second roughening sublayer and planarization sublayer. A pressure of 190~210 torr can increase the growth rate while preventing the deposition of reaction products on the chamber walls of the MOCVD equipment. A rotation speed of 690~710 r / s ensures thorough mixing of the reaction gases, and the gas mixing flow makes the temperature within the deposition equipment more uniform.

[0043] For example, a core layer was fabricated under the conditions of a first temperature of 1055°C, a pressure of 200 torr, and a rotation speed of 700 r / s.

[0044] The second step is to create a second roughened sublayer on the first roughened sublayer using a second temperature, which is higher than the first temperature.

[0045] The second coarsening sublayer serves to stabilize the merging layer and promote uniform lateral growth.

[0046] In this embodiment of the disclosure, the second roughened sublayer is a GaN layer.

[0047] In this implementation, the second coarsened sublayer is a GaN layer. GaN growth can continuously bend, block, and annihilate penetrating dislocations, thereby ensuring that the island-like morphology of the first coarsened sublayer is completely filled and promoting lateral uniform growth.

[0048] In this embodiment of the disclosure, the thickness of the second roughened sublayer is 0.72~0.76 μm.

[0049] In this implementation, the thickness of the second roughening sublayer is 0.72~0.76μm, which is relatively thick. The thickness is sufficient to ensure that the island-like morphology of the first roughening sublayer is completely filled, so that the second roughening sublayer and the first roughening sublayer are seamlessly connected, thereby initially forming a smooth surface.

[0050] For example, the thickness of the second coarsened sublayer is 0.74 μm.

[0051] In this embodiment of the disclosure, a second roughened sublayer is produced under the conditions of a second temperature of 1080~1090℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0052] In this implementation, the second temperature is 1080~1090℃. By increasing the temperature, the island-like morphology of the first roughened sublayer merges with that of the second roughened sublayer, promoting the lateral growth of the second roughened sublayer. This allows the second roughened sublayer to fill in the island-like morphology of the first roughened sublayer, and the smooth surface of the second roughened sublayer provides a flat growth platform for the subsequent growth of the planarization sublayer. The pressure is 190~210 torr, which can increase the growth rate while preventing the deposition of reaction products on the cavity wall of the organometallic chemical vapor deposition equipment. The rotation speed is 690~710 r / s, which ensures thorough mixing of the reaction gases and a more uniform temperature within the deposition equipment.

[0053] For example, a second roughened sublayer was produced under the conditions of a second temperature of 1085°C, a pressure of 200 torr, and a rotation speed of 700 r / s.

[0054] The third step involves creating a planarization sublayer on the second roughened sublayer at a third temperature, which is higher than the second temperature.

[0055] The planarization sublayer serves to repair the structure at high temperatures, eliminate grain boundary stress, and complete densification growth, thereby smoothing the island-like structure.

[0056] In this embodiment of the disclosure, the planarization sublayer is a GaN layer.

[0057] In this implementation, the planarization sublayer is a GaN layer. The lateral epitaxial growth characteristics of GaN can be used to fill the surface unevenness formed by the roughening of the first two layers, thereby achieving interface planarization and providing a flat substrate for the high-quality growth of the subsequent active layer.

[0058] In this embodiment of the disclosure, the thickness of the planarization sublayer is 0.75~0.79μm.

[0059] In this implementation, the thickness of the planarization sublayer is 0.75~0.79μm. Sufficient thickness can cover the second coarsening sublayer, forming a denser planarization sublayer, and finally obtaining a planarization sublayer with the fewest defects and the lowest roughness.

[0060] For example, the thickness of the planarization sublayer is 0.77 μm.

[0061] In this embodiment of the disclosure, a planarization sublayer is fabricated under the conditions of a third temperature of 1120~1130°C, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

[0062] In this implementation, the third temperature is 1120~1130℃, close to the upper limit of GaN decomposition temperature. This allows the second roughened sublayer to eliminate grain boundary stress and complete densification growth at high temperatures, minimizing the surface roughness of the planarized sublayer and providing conditions for subsequent epitaxial growth. The pressure is 190~210 torr, which can increase the growth rate while avoiding the deposition of reaction products in the organometallic chemical vapor deposition equipment. The rotation speed is 690~710 r / s, which ensures thorough mixing of the reaction gases and more uniform temperature within the deposition equipment.

[0063] In this embodiment of the disclosure, a planarization sublayer is fabricated under the conditions of a third temperature of 1125°C, a pressure of 200 torr, and a rotation speed of 700 r / s.

[0064] In the embodiments disclosed herein, the roughness of the first roughening sublayer, the second roughening sublayer, and the planarization sublayer gradually decreases.

[0065] In this implementation, the roughness of the first roughened sublayer, the second roughened sublayer, and the planarization sublayer gradually decreases. This design can provide a smooth surface for subsequent layer growth, thereby avoiding the generation of micron-sized regular hexagonal or inverted triangular pyramidal defects on the surface of the second semiconductor layer during subsequent fabrication, thus improving the performance and yield of the light-emitting diode.

[0066] Figure 3 This is a comparison diagram of the surface roughness of light-emitting diodes provided in the embodiments of this disclosure and light-emitting diodes provided in related technologies. See also... Figure 3 The triangle represents the surface roughness ratio of the light-emitting diode surface provided in the embodiments of this disclosure. The circle represents the surface roughness ratio of the light-emitting diode surface in related art light-emitting diodes. The horizontal axis represents the number of diodes, and the vertical axis represents the roughness ratio. Figure 3 As can be seen, the surface roughness ratio (SRR) of the light-emitting diode provided by the related technology is 24.5, while the SRR of the light-emitting diode provided in this embodiment is 24.9. The higher the SRR value, the smoother the surface.

[0067] S23. Fabricate an undoped GaN layer on the composite functional layer.

[0068] In the embodiments disclosed herein, the undoped GaN layer can improve the quality of the light-emitting diode and provide a more ideal substrate for the subsequent growth of epitaxial layers.

[0069] In the embodiments disclosed herein, the thickness of the undoped GaN layer can be 2.4~2.8 μm.

[0070] For example, the thickness of the undoped GaN layer is 2.6 μm.

[0071] S24. A doped GaN layer is fabricated on the undoped GaN layer. The buffer layer, the composite functional layer, the undoped GaN layer, and the doped GaN layer constitute the first semiconductor layer.

[0072] In this embodiment of the disclosure, the doped GaN layer is an N-type semiconductor layer, such as an N-type GaN layer.

[0073] In this embodiment of the disclosure, the N-type GaN layer is a Si-doped GaN layer.

[0074] In this embodiment of the disclosure, the Si doping concentration can be 2.75%. 10 19 ~2.95 10 19 cm 3 .

[0075] In this embodiment of the disclosure, the Si doping concentration is 2.85%. 10 19 cm 3 .

[0076] In the embodiments disclosed herein, the thickness of the doped GaN layer can be 1.1~1.3 μm.

[0077] For example, the thickness of the doped GaN layer is 1.2 μm.

[0078] S25. An active layer is fabricated on the first semiconductor layer.

[0079] In this embodiment of the disclosure, the active layer is a multi-quantum well layer, such as an InGaN / GaN multi-quantum well structure.

[0080] In the embodiments disclosed herein, the thickness of the InGaN layer is 3.0~3.5nm, the thickness of the GaN layer is 9.0~10nm, and the number of periods of the InGaN / GaN multi-quantum-well structure is 10~12.

[0081] For example, the thickness of the active layer is 3.3 nm for the InGaN layer and 9.5 nm for the GaN layer, and the number of periods of the InGaN / GaN multi-quantum-well structure is 11.

[0082] S26. Fabricate a second semiconductor layer on the active layer.

[0083] In this embodiment of the disclosure, the second semiconductor layer is a P-type semiconductor layer, such as a P-type GaN layer.

[0084] In this embodiment of the disclosure, the P-type GaN layer is a Mg-doped GaN layer.

[0085] In this embodiment of the disclosure, the Mg doping concentration can be 1.18. 10 20 ~1.38 10 20 atoms / cm 3 .

[0086] For example, the Mg doping concentration is 1.28%. 10 20 atoms / cm 3 .

[0087] In this embodiment of the disclosure, the thickness of the second semiconductor layer can be 40~42nm.

[0088] For example, the thickness of the second semiconductor layer is 41 nm.

[0089] Optionally, the method further includes: graphically processing the above structure to form a stepped structure; fabricating a current spreading layer on the top surface of the step; fabricating a passivation layer to cover the stepped structure and the current spreading layer; and fabricating an electrode layer.

[0090] Figure 4 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 4 The light-emitting diode includes a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 stacked sequentially.

[0091] The first semiconductor layer 101 includes a buffer layer 11, a composite functional layer 12, an unintentionally doped GaN layer 13, and a doped GaN layer 14 stacked sequentially. The composite functional layer 12 is grown in a gradient heating manner.

[0092] In this embodiment, the first semiconductor layer of the light-emitting diode includes a buffer layer, a composite functional layer, an undoped GaN layer, and a doped GaN layer grown sequentially. The buffer layer provides nucleation centers, improving the crystal quality of subsequent layers. The composite functional layer provides a smooth surface for subsequent layer growth, preventing micron-sized regular hexagonal or inverted triangular pyramidal defects from forming on the surface of the second semiconductor layer during subsequent fabrication, thus improving the performance and yield of the light-emitting diode. The undoped GaN layer helps grow a higher-quality active region. The doped GaN layer provides carrier transport channels. Furthermore, growing the composite functional layer using a gradient heating method gradually increases the growth temperature, avoiding excessively rapid growth at a single high temperature, which could lead to defects in the composite functional layer. Gradient heating allows for more precise control of the growth state of the composite functional layer, resulting in a smooth surface and preventing defects caused by uneven bottom surfaces during subsequent layer fabrication, significantly improving the reliability of the light-emitting diode chip.

[0093] In this embodiment of the disclosure, the first roughening sublayer 121, the second roughening sublayer 122, and the planarization sublayer 123 can be GaN layers.

[0094] In this implementation, the first roughening sublayer is a GaN layer. The GaN layer and the underlying buffer layer have a high lattice match, which can effectively reduce the interface stress and dislocation density during the epitaxial growth process and ensure crystal quality. The second roughening sublayer is a GaN layer. GaN growth can continuously bend, block and annihilate penetrating dislocations, thereby ensuring that the island-like morphology of the first roughening sublayer is completely filled and promoting lateral uniform growth. The planarization sublayer is a GaN layer. The lateral epitaxial growth characteristics of GaN can be used to fill the surface unevenness defects formed by the roughening of the first two layers, realize interface planarization, and provide a flat substrate for the high-quality growth of the subsequent active layer.

[0095] In this embodiment of the disclosure, the thickness of the first roughened sublayer 121 is 0.03~0.07μm.

[0096] In this implementation, the thickness of the first coarsening sublayer is 0.03~0.07μm. The relatively thin thickness can limit the size of the discrete island-like morphology in the first coarsening sublayer, increase the nucleation density, and make it easier for the subsequent second coarsening sublayer to fill and merge it.

[0097] For example, the thickness of the first roughened sublayer 121 is 0.05 μm.

[0098] In this embodiment of the disclosure, the thickness of the second roughened sublayer 122 is 0.72~0.76 μm.

[0099] In this implementation, the thickness of the second roughening sublayer is 0.72~0.76μm, which is relatively thick. The thickness is sufficient to ensure that the island-like morphology of the first roughening sublayer is completely filled, so that the second roughening sublayer and the first roughening sublayer are seamlessly connected, thereby initially forming a smooth surface.

[0100] For example, the thickness of the second roughened sublayer 122 is 0.74 μm.

[0101] In this embodiment of the disclosure, the thickness of the planarization sublayer 123 is 0.75~0.79μm.

[0102] In this implementation, the thickness of the planarization sublayer is 0.75~0.79μm. Sufficient thickness can cover the second coarsening sublayer, forming a denser planarization sublayer, and finally obtaining a planarization sublayer with the fewest defects and the lowest roughness.

[0103] For example, the thickness of the planarization sublayer 123 is 0.77 μm.

[0104] In the embodiments disclosed herein, the roughness of the first roughening sublayer 121, the second roughening sublayer 122, and the planarization sublayer 123 gradually decreases.

[0105] In this implementation, the roughness of the first roughened sublayer, the second roughened sublayer, and the planarization sublayer gradually decreases. This design can provide a smooth surface for subsequent layer growth, thereby avoiding the generation of micron-sized regular hexagonal or inverted triangular pyramidal defects on the surface of the second semiconductor layer during subsequent fabrication, thus improving the performance and yield of the light-emitting diode.

[0106] In this embodiment of the present disclosure, the surface roughness of the first roughening sublayer 121 is greater than the surface roughness of the second roughening sublayer 122, and the surface roughness of the second roughening sublayer 122 is greater than the surface roughness of the planarization sublayer 123.

[0107] In this embodiment of the disclosure, the light-emitting diode may further include a substrate 100.

[0108] The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are sequentially stacked on the substrate 100.

[0109] In this embodiment of the disclosure, the substrate 100 can be any one of a sapphire patterned substrate, a Si substrate, or a SiC substrate, and the material of the substrate 100 is not limited in this embodiment of the disclosure.

[0110] For example, substrate 100 is a patterned sapphire substrate.

[0111] In this embodiment of the disclosure, the buffer layer 11 can be a GaN layer or an AlN layer.

[0112] In this implementation, there is usually a large difference in lattice constant between the substrate material (such as sapphire) and the epitaxial material (such as GaN). This difference leads to a large number of dislocations and other crystal defects during epitaxial growth. The buffer layer can serve as a transition layer to alleviate lattice mismatch, reduce dislocation propagation, and thus improve the crystal quality of the epitaxial layer.

[0113] For example, buffer layer 11 can be a GaN layer.

[0114] In this embodiment of the disclosure, the doped GaN layer 14 can be an N-type semiconductor layer.

[0115] Among them, the doped GaN layer 14 can be an N-type GaN layer, such as a Si-doped GaN layer.

[0116] In this embodiment of the disclosure, the Si doping concentration can be 2.75%. 10 19 ~2.95 10 19 cm 3 .

[0117] For example, the Si doping concentration is 2.85%. 10 19 cm 3 .

[0118] In this embodiment of the disclosure, the thickness of the doped GaN layer 14 can be 1.1~1.3 μm.

[0119] For example, the thickness of the doped GaN layer 14 is 1.2 μm.

[0120] In this embodiment of the disclosure, the active layer 102 can be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well structure.

[0121] In the embodiments disclosed herein, the thickness of the InGaN layer is 3.0~3.5nm, the thickness of the GaN layer is 9.0~10nm, and the number of periods of the InGaN / GaN multi-quantum-well structure is 10~12.

[0122] For example, the thickness of the active layer is 3.3 nm for the InGaN layer and 9.5 nm for the GaN layer, and the number of periods of the InGaN / GaN multi-quantum-well structure is 11.

[0123] In this embodiment of the disclosure, the second semiconductor layer 103 may be a P-type semiconductor layer. The second semiconductor layer 103 can be a P-type GaN layer.

[0124] In this embodiment of the disclosure, the thickness of the second semiconductor layer 103 can be 40~42nm.

[0125] For example, the thickness of the second semiconductor layer 103 is 41 nm.

[0126] It is worth noting that, in the embodiments of this disclosure, the structure can be selectively added or reduced based on the structure of the light-emitting diode described above, and this disclosure does not limit this.

[0127] Figure 5 This is a comparison diagram of the light-emitting diode (LED) provided in the embodiments of this disclosure and the LED provided in related technologies. See also... Figure 5 The left image shows a light-emitting diode (LED) provided by related technologies, which shows that the surface of the LED has many small granular defects X. The right image shows an LED provided by an embodiment of this disclosure, which shows that the surface of the LED is smooth and free of small defects.

[0128] Figure 6 This is a temperature-time line graph of the fabrication of a composite functional layer for a light-emitting diode (LED) according to embodiments of this disclosure and related technologies. See also... Figure 6 The solid line represents the temperature and time curve for fabricating the composite functional layer of a light-emitting diode according to the embodiments of this disclosure, while the dashed line represents the temperature and time curve for fabricating the composite functional layer of a light-emitting diode according to related technologies. In the embodiments of this disclosure, the temperature of the composite functional layer increases in three gradients over time, ultimately resulting in a light-emitting diode with a smooth surface and no small defects.

[0129] Table 1 below is a parameter table for various embodiments provided in this disclosure. As can be seen from Table 1, this disclosure provides embodiment parameters, where temperature is in °C, pressure is in torr, rotation speed is in r / s, and thickness is in μm. The embodiments in this disclosure are those provided in the foregoing specification. Examples D1, D2, and D3 are embodiments provided in related technologies. Using the parameters provided in Table 1, a light-emitting diode with a smooth surface and no small defects is finally fabricated.

[0130] Table 1

[0131] Table 2 below compares the surface defects of the light-emitting diodes (LEDs) provided in the embodiments of this disclosure with those provided in related technologies. The surface morphology of the LEDs was quantitatively designed using a Zeiss microscope. Table 2 shows that the defect density of the LEDs provided in the embodiments of this disclosure is significantly reduced.

[0132] Table 2

[0133] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for fabricating a light-emitting diode, characterized in that, The method includes: A buffer layer (11), a composite functional layer (12), an undoped GaN layer (13), and a doped GaN layer (14) are grown sequentially to form a first semiconductor layer (101). The composite functional layer (12) includes multiple sub-layers, and the growth temperature of the multiple sub-layers gradually increases along the growth direction. An active layer (102) is fabricated on the first semiconductor layer (101); A second semiconductor layer (103) is fabricated on the active layer (102).

2. The method for fabricating a light-emitting diode according to claim 1, characterized in that, The plurality of sublayers include a first coarsening sublayer (121), a second coarsening sublayer (122), and a planarization sublayer (123) stacked in sequence. The growth of the composite functional layer (12) includes: The first roughened sublayer (121) is prepared using a first temperature. On the first roughened sublayer, a second roughened sublayer (122) is formed at a second temperature, which is higher than the first temperature; On the second roughened sublayer (122), the planarization sublayer (123) is made at a third temperature, which is higher than the second temperature.

3. The method for fabricating a light-emitting diode according to claim 2, characterized in that, The process of fabricating the first roughened sublayer (121) at a first temperature includes: The first roughened sublayer (121) is prepared under the conditions of a first temperature of 1050~1060℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

4. The method for fabricating a light-emitting diode according to claim 2, characterized in that, The process of fabricating the second roughened sublayer (122) at a second temperature includes: The second roughened sublayer (122) is prepared under the following conditions: temperature of 1080~1090℃, pressure of 190~210 torr, and rotation speed of 690~710 r / s.

5. The method for fabricating a light-emitting diode according to claim 2, characterized in that, The planarization sublayer (123) is fabricated using a third temperature, including: The planarization sublayer (123) is fabricated under the conditions of a third temperature of 1120~1130℃, a pressure of 190~210 torr, and a rotation speed of 690~710 r / s.

6. The method for fabricating a light-emitting diode according to any one of claims 2 to 5, characterized in that, The thickness of the first roughening sublayer (121) is 0.03~0.07μm; the thickness of the second roughening sublayer (122) is 0.72~0.76μm; and the thickness of the planarization sublayer (123) is 0.75~0.79μm.

7. A light-emitting diode, characterized in that, The light-emitting diode includes: a first semiconductor layer (101), an active layer (102), and a second semiconductor layer (103) stacked sequentially. The first semiconductor layer (101) includes a buffer layer (11), a composite functional layer (12), an unintentionally doped GaN layer (13), and a doped GaN layer (14) stacked sequentially. The composite functional layer (12) includes multiple sub-layers, and the growth temperature of the multiple sub-layers gradually increases along the growth direction.

8. The light-emitting diode according to claim 7, characterized in that, The plurality of sublayers include a first coarsening sublayer (121), a second coarsening sublayer (122), and a flattening sublayer (123) that are sequentially stacked on the buffer layer (11).

9. The light-emitting diode according to claim 8, characterized in that, The thickness of the first roughening sublayer (121) is 0.03~0.07μm; the thickness of the second roughening sublayer (122) is 0.72~0.76μm; and the thickness of the planarization sublayer (123) is 0.75~0.79μm.

10. The light-emitting diode according to any one of claims 7 to 9, characterized in that, The first roughening sublayer (121), the second roughening sublayer (122), and the planarization sublayer (123) are GaN layers.

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