Micro-led chip and preparation method thereof

Abstract

This invention relates to the field of optoelectronic manufacturing technology, specifically disclosing a Micro-LED chip and its fabrication method. The fabrication method includes: forming an epitaxial layer on a substrate; forming conductive steps and isolation trenches on the epitaxial layer to obtain a first intermediate; immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain a second intermediate; the silane coupling agent contains a first active group and a second active group, the first active group being methoxy or ethoxy, and the second active group being amino; heat-treating the second intermediate in an inert atmosphere for a second preset time to obtain a third intermediate; forming a protective layer on the third intermediate; the protective layer's E... g ≥4.0 eV; A first through-hole and a second through-hole are formed on the protective layer to obtain a fourth intermediate; A first electrode and a second electrode are formed on the fourth intermediate. Implementing this invention can improve the luminous efficiency and reliability of Micro-LED chips.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a Micro-LED chip and its fabrication method. Background Technology

[0002] In LED manufacturing, dry etching processes such as inductively coupled plasma (ICP) or reactive ion etching (RIE) are used to define pixel units and form isolation mesa. However, high-energy plasma physically bombards the GaN lattice, causing nitrogen (N) atoms on the sidewall surfaces to be selectively sputtered, leaving behind a large number of unsaturated, chemically reactive gallium (Ga) dangling bonds. These dangling bonds readily combine with water and oxygen molecules in the air to form stable oxides or hydroxides such as Ga-O and Ga-OH, introducing a high density of interface states in the semiconductor bandgap. These interface states act as nonradiative recombination centers and charge traps, triggering a series of severe device performance degradations, collectively known as the "sidewall damage effect." Due to their smaller size, the sidewall damage effect is more pronounced in Micro-LEDs, significantly reducing luminous efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a Micro-LED chip and its preparation method, which can weaken the sidewall damage effect and improve the luminous efficiency.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a Micro-LED chip, comprising: Provide substrate; An epitaxial layer is formed on the substrate; wherein the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; A conductive step and an isolation trench are formed on the epitaxial layer to obtain a first intermediate. The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time to obtain a second intermediate; wherein the silane coupling agent contains a first active group and a second active group, the first active group being methoxy or ethoxy, and the second active group being amino. The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; wherein, the E of the protective layer g ≥4.0eV; A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate. A first electrode and a second electrode are formed on the fourth intermediate; wherein the first electrode is electrically connected to the conductive step through a first through-hole, and the second electrode is electrically connected to the second semiconductor layer through a second through-hole.

[0005] As an improvement to the above technical solution, in the step of immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain the second intermediate: The silane coupling agent is one or more of γ-aminopropyltriethoxysilane, N-(β-aminoethyl)-γ-aminopropyltriethoxysilane, and (N-(β-aminoethyl)-γ-aminopropylmethyldimethoxysilane), and the concentration of the silane coupling agent in the modified solution is 1 mmol / L to 5 mmol / L. The temperature of the modified solution is 25℃~70℃, and the first preset time is 6h~24h.

[0006] As an improvement to the above technical solution, in the step of heat-treating the second intermediate in an inert atmosphere for a second preset time to obtain the third intermediate: The inert atmosphere is a nitrogen atmosphere or an argon atmosphere, the heat treatment temperature is 120℃~150℃, and the second preset time is 0.3h~1h.

[0007] As an improvement to the above technical solution, the protective layer is an AlN layer or an AlGaN layer with a thickness of 10nm~20nm.

[0008] As an improvement to the above technical solution, in the step of forming a protective layer on the side where the epitaxial layer of the third intermediate is located: An AlN layer is formed using PEALD as a protective layer. The formation process parameters include: The pulse time of TMAl is 0.05s~0.15s, the pulse time of NH3 is 3s~10s, the plasma power is 100W~300W, and the deposition temperature is 300℃~350℃; the purging gas is N2, and the purging time is 10s~20s.

[0009] As an improvement to the above technical solution, the step of forming a protective layer on the side where the epitaxial layer of the third intermediate is located includes: A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; The protective layer was annealed in a nitrogen atmosphere; The annealing temperature is 400℃~450℃, and the annealing time is 0.5min~2min.

[0010] As an improvement to the above technical solution, the step of forming conductive steps and isolation trenches on the epitaxial layer to obtain the first intermediate includes: A conductive step and an isolation trench are formed on the epitaxial layer to obtain a fifth intermediate. The fifth intermediate is processed using a plasma ashing process to obtain the first intermediate; The process parameters for plasma ashing include: plasma power of 20W~100W, chamber pressure of 50mtorr~100mtorr, and O2 flow rate of 10sccm~40sccm.

[0011] As an improvement to the above technical solution, the step of immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain the second intermediate includes: The first intermediate was immersed in a modified solution containing a silane coupling agent and reacted for a first preset time; then it was washed sequentially with toluene and ethanol to obtain the second intermediate.

[0012] As an improvement to the above technical solution, the first semiconductor layer is an N-type GaN layer and the second semiconductor layer is a P-type GaN layer.

[0013] Accordingly, the present invention also discloses a Micro-LED chip, which is prepared by the above-described Micro-LED chip preparation method.

[0014] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, the method for fabricating a Micro-LED chip involves etching conductive steps and isolation trenches onto an epitaxial layer, followed by immersion in a modified solution containing a silane coupling agent for reaction, and then heat treatment in an inert atmosphere to form a protective layer. By reacting in the modified solution containing the silane coupling agent and then heat-treating in an inert atmosphere, a monolayer can be formed through interfacial bonding of dangling bonds, effectively reducing damage. Furthermore, by using a silane coupling agent containing amino groups, the subsequently formed protective layer can be precisely bonded to the monolayer, achieving complete coverage of surfaces with high aspect ratios and complex three-dimensional structures, such as isolation trenches. This effectively reduces the interfacial state density, suppresses sidewall leakage current, improves carrier injection efficiency, significantly reduces non-radiative recombination, and improves luminous efficiency. Simultaneously, the protective layer of the present invention also provides stable chemical protection for the sidewalls, improving the reliability of the Micro-LED chip. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for fabricating a Micro-LED chip according to an embodiment of the present invention. Detailed Implementation

[0016] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0018] The following embodiments are provided for the purpose of illustrating various embodiments of the present invention and are not intended to limit the invention in any way. Those skilled in the art will understand that variations and other uses as defined in the claims are included within the spirit and scope of the invention. Unless otherwise specified, the materials, reagents, etc., used in the following embodiments are commercially available.

[0019] In this invention, terms such as "first aspect" and "second aspect" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features.

[0020] Unless otherwise specified, the temperature parameters in this invention can be either constant temperature processing or processing within a certain temperature range. The constant temperature processing allows temperature fluctuations within the precision range controlled by the instrument.

[0021] Please see Figure 1 As a first aspect of the present invention, the present invention provides a method for fabricating a Micro-LED chip, which includes the following steps: S1: Provides a substrate; S2: An epitaxial layer is formed on the substrate; S3: Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the first intermediate; S4: Immerse the first intermediate in a modified solution containing a silane coupling agent and react for a first preset time to obtain the second intermediate; S5: Heat-treat the second intermediate in an inert atmosphere for a second preset time to obtain the third intermediate; S6: A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; S7: A first via exposing a conductive step and a second via exposing a second semiconductor layer are formed on the protective layer to obtain a fourth intermediate; S8: Form the first electrode and the second electrode on the fourth intermediate; The silane coupling agent contains a first active group and a second active group, wherein the first active group is methoxy or ethoxy, and the second active group is amino; the protective layer E g ≥4.0eV.

[0022] Based on the above preparation method, by reacting in a modified solution containing a silane coupling agent and then heat-treating under an inert atmosphere, a monolayer can be formed through interfacial bonding of dangling bonds, effectively reducing damage. Furthermore, by using a silane coupling agent containing amino groups, the subsequently formed protective layer can be precisely bonded to the monolayer, achieving complete coverage of surfaces with high aspect ratios and complex three-dimensional structures, such as isolation trenches. This effectively reduces the interfacial state density, suppresses sidewall leakage current, improves carrier injection efficiency, significantly reduces non-radiative recombination, and enhances luminous efficiency. Simultaneously, the protective layer also provides stable chemical protection for the sidewalls, improving the reliability of the Micro-LED chip.

[0023] Specifically, in step S1, the substrate is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. Preferably, it is a sapphire substrate.

[0024] Specifically, in step S2, the first semiconductor layer is an N-type GaAs layer, an N-type GaN layer, or an N-type AlGaN layer, but is not limited to these. The active layer is an InGaN-GaN type multiple quantum well layer, an InGaN-AlGaN type multiple quantum well layer, an AlGaN-AlGaN type multiple quantum well layer, or an AlGaInP-AlGaInP type multiple quantum well layer, but is not limited to these. The second semiconductor layer is a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited to these. Preferably, in some embodiments, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN-GaN type multiple quantum well layer, and the second semiconductor layer is a P-type GaN layer.

[0025] Specifically, in step S3, conductive steps and isolation trenches can be formed using dry etching or wet etching processes, but are not limited to these. The conductive steps expose the first semiconductor layer to form a first electrode electrically connected to the first semiconductor layer later. The isolation trenches expose the substrate to facilitate the separation of the Micro-LED chip later.

[0026] Preferably, in some embodiments, step S3 includes: S31. Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the fifth intermediate; S32. The fifth intermediate is processed by plasma ashing process to obtain the first intermediate; The process parameters for plasma ashing include: plasma power of 20W~100W, exemplarily 30W, 40W, 50W, 60W, 70W, 80W, or 90W, but not limited thereto; preferably, plasma power is 30W~60W. Chamber pressure is 50mtorr~100mtorr, exemplarily 55mtorr, 60mtorr, 65mtorr, 70mtorr, 75mtorr, 80mtorr, 85mtorr, or 90mtorr, but not limited thereto. Preferably, chamber pressure is 50mtorr~80mtorr. O2 flow rate is 10sccm~40sccm, exemplarily 15sccm, 20sccm, 25sccm, 30sccm, or 35sccm, but not limited thereto. Preferably, O2 flow rate is 10sccm~20sccm.

[0027] Plasma ashing treatment can effectively remove photoresist residues and organic contaminants from the surface of the fifth intermediate, while also forming a uniformly covered hydroxyl group on its surface, providing an excellent interfacial chemical bonding basis for the subsequent self-assembly of the silane coupling agent.

[0028] Specifically, in step S4, the silane coupling agent is one or more of γ-aminopropyltriethoxysilane, N-(β-aminoethyl)-γ-aminopropyltriethoxysilane, N-(β-aminoethyl)-γ-aminopropylmethyldimethoxysilane, and dimethylaminopropylmethyldiethoxysilane, but is not limited thereto. Preferably, the silane coupling agent is one or more of γ-aminopropyltriethoxysilane, N-(β-aminoethyl)-γ-aminopropyltriethoxysilane, and N-(β-aminoethyl)-γ-aminopropylmethyldimethoxysilane; more preferably, it is γ-aminopropyltriethoxysilane.

[0029] Specifically, in step S4, the concentration of the silane coupling agent in the modified solution is 0.5~5 mmol / L, exemplarily 1 mmol / L, 1.5 mmol / L, 2.0 mmol / L, 2.5 mmol / L, 3.0 mmol / L, 3.5 mmol / L, 4.0 mmol / L, or 4.5 mmol / L, but not limited thereto. Preferably, the concentration of the silane coupling agent in the modified solution is 1 mmol / L~5 mmol / L, more preferably 2.0 mmol~3.5 mmol / L.

[0030] Specifically, in step S4, the temperature of the modified solution (i.e., the reaction temperature) is 20~80℃, exemplarily 25℃, 30℃, 35℃, 40℃, 45℃, 50℃, 55℃, 60℃, 65℃, or 70℃, but not limited thereto. Preferably, it is 25℃~70℃, more preferably 50~70℃. A higher reaction temperature can increase the molecular diffusion rate, promote surface diffusion and rearrangement, and thus obtain a monolayer with higher order.

[0031] Specifically, in step S4, the first preset time is 5h to 24h, exemplarily 6h, 8h, 10h, 12h, 14h, 16h, 18h, 20h or 22h, but not limited to these. Preferably it is 6h to 24h, more preferably 12h to 18h.

[0032] Preferably, in some embodiments, in step S4, the first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time; then it is washed sequentially with toluene and ethanol to obtain the second intermediate. Washing removes unbonded free silane molecules and byproducts.

[0033] Specifically, in step S5, by heat-treating the second intermediate in an inert atmosphere, the reaction between the ethoxy / methoxy groups in the silane coupling agent and the dangling bonds on the substrate surface can be promoted to form stable Si-O-Ga bonds, thereby enhancing the stability of the monolayer.

[0034] Specifically, in step S5, the inert atmosphere can be a nitrogen atmosphere, an argon atmosphere, a helium atmosphere, or a mixture thereof, but is not limited to these. Preferably, the inert atmosphere is a nitrogen atmosphere or an argon atmosphere.

[0035] Specifically, in step S5, the heat treatment temperature is 100℃~150℃, exemplarily 110℃, 120℃, 130℃ or 140℃, but not limited thereto. Preferably it is 120℃~150℃, more preferably 130℃~140℃.

[0036] Specifically, in step S5, the heat treatment time (i.e. the second preset time) is 0.2h to 2h, exemplarily 0.5h, 1.0h, 1.5h or 1.8h; preferably 0.3h to 1h, more preferably 0.3h to 0.8h.

[0037] Specifically, in step S6, the E of the protective layer g ≥4.0 eV. More specifically, the protective layer can be an AlN layer, an AlGaN layer, or a SiN layer. xThe protective layer may be, but is not limited to, an AlN layer or an AlGaN layer, preferably, in some embodiments, with a thickness of 10 nm to 20 nm. Using an AlN or AlGaN protective layer of the aforementioned thickness can significantly reduce surface defect density and improve luminous efficiency.

[0038] More preferably, in some embodiments, an AlN layer is formed by PEALD as a protective layer. The formation process parameters include: a pulse time of TMAl of 0.05s to 0.15s, exemplarily 0.07s, 0.09s, 0.11s, or 0.13s, but not limited thereto; a pulse time of NH3 of 3s to 10s, exemplarily 3.5s, 5s, 6.5s, 8s, or 9.5s, but not limited thereto; a plasma power of 100W to 300W, exemplarily 120W, 160W, 200W, 240W, or 280W, but not limited thereto; and a purge gas of N2, with a purge time of 10s to 20s, exemplarily 12s, 14s, 16s, or 18s, but not limited thereto. Specifically, the deposition temperature is 300℃~350℃. If the deposition temperature is too high, it can easily lead to monolayer decomposition, making it difficult to effectively guide the growth of the protective layer; when the deposition temperature is too low, the formed protective layer will not be dense enough, affecting the passivation effect and interface stability. For example, the deposition temperature is 320℃, 330℃ or 340℃, preferably 320℃~330℃.

[0039] Preferably, in some embodiments, step S6 includes: S61. A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; S62. Anneal the protective layer in a nitrogen atmosphere; Specifically, annealing in a nitrogen atmosphere can reduce hydrogen impurities, release stress, and improve the crystal quality of the protective layer.

[0040] Specifically, the annealing temperature is 400℃~450℃, exemplarily 410℃, 420℃, 430℃ or 440℃, but not limited thereto. The annealing time is 0.5min~2min, exemplarily 0.8min, 1.2min, 1.5min or 1.8min, but not limited thereto.

[0041] Specifically, in step S7, the first through-hole and the second through-hole can be formed by dry etching or wet etching.

[0042] Specifically, in step S8, the first electrode and the second electrode can be formed by electron beam evaporation or magnetron sputtering processes, but are not limited to these.

[0043] Accordingly, as a second aspect of the present invention, the present invention also provides a Micro-LED chip, which is prepared by the above-described preparation method.

[0044] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a method for fabricating a Micro-LED chip, which includes the following steps: (1) Provide a substrate; The substrate is a sapphire substrate.

[0045] (2) An epitaxial layer is formed on the substrate; The epitaxial layer includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN type multiple quantum well layer), and a second semiconductor layer (P-type GaN layer) sequentially stacked on the substrate.

[0046] (3) Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the first intermediate; (4) The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time. Then, it is washed with toluene and ethanol in sequence to obtain the second intermediate. The silane coupling agent was γ-aminopropyltriethoxysilane, and the concentration of the silane coupling agent in the modified solution was 2.8 mmol / L. The reaction temperature was 55℃, and the first preset time was 14 h.

[0047] (5) The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; The inert atmosphere is argon, the heat treatment temperature is 135℃, and the second preset time is 40min.

[0048] (6) A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; An AlGaN layer is formed using MOCVD as a protective layer. The Al content in the AlGaN layer is 0.7%, and its thickness is 18 nm.

[0049] (7) A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate; (8) Form the first electrode and the second electrode on the fourth intermediate; The first electrode is electrically connected to the conductive step through the first through hole, and the second electrode is electrically connected to the second semiconductor layer through the second through hole.

[0050] Example 2 This embodiment provides a method for fabricating a Micro-LED chip, which includes the following steps: (1) Provide a substrate; The substrate is a sapphire substrate.

[0051] (2) An epitaxial layer is formed on the substrate; The epitaxial layer includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN type multiple quantum well layer), and a second semiconductor layer (P-type GaN layer) sequentially stacked on the substrate.

[0052] (3) Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the first intermediate; (4) The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time. Then, it is washed with toluene and ethanol in sequence to obtain the second intermediate. The silane coupling agent was γ-aminopropyltriethoxysilane, and the concentration of the silane coupling agent in the modified solution was 2.8 mmol / L. The reaction temperature was 55℃, and the first preset time was 14 h.

[0053] (5) The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; The inert atmosphere is argon, the heat treatment temperature is 135℃, and the second preset time is 40min.

[0054] (6) A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; The AlN layer was formed using PEALD as a protective layer. The formation process parameters included: a TMAl pulse time of 0.11 s, an NH3 pulse time of 5 s, a plasma power of 230 W, and a deposition temperature of 340 °C; the purge gas was N2, and the purge time was 15 s. The thickness of the protective layer was 15 nm.

[0055] (7) A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate; (8) Form the first electrode and the second electrode on the fourth intermediate; The first electrode is electrically connected to the conductive step through the first through hole, and the second electrode is electrically connected to the second semiconductor layer through the second through hole.

[0056] Example 3 This embodiment provides a method for fabricating a Micro-LED chip, which includes the following steps: (1) Provide a substrate; The substrate is a sapphire substrate.

[0057] (2) An epitaxial layer is formed on the substrate; The epitaxial layer includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN type multiple quantum well layer), and a second semiconductor layer (P-type GaN layer) sequentially stacked on the substrate.

[0058] (3) Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the fifth intermediate; (4) The fifth intermediate is processed by plasma ashing process to obtain the first intermediate; The process parameters for plasma ashing include: plasma power of 55W, chamber pressure of 68mtorr, and O2 flow rate of 12sccm.

[0059] (5) The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time. Then, it is washed with toluene and ethanol in sequence to obtain the second intermediate. The silane coupling agent was γ-aminopropyltriethoxysilane, and the concentration of the silane coupling agent in the modified solution was 2.8 mmol / L. The reaction temperature was 55℃, and the first preset time was 14 h.

[0060] (6) The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; The inert atmosphere is argon, the heat treatment temperature is 135℃, and the second preset time is 40min.

[0061] (7) A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; The AlN layer was formed using PEALD as a protective layer. The formation process parameters included: a TMAl pulse time of 0.11 s, an NH3 pulse time of 5 s, a plasma power of 230 W, and a deposition temperature of 340 °C; the purge gas was N2, and the purge time was 15 s. The thickness of the protective layer was 15 nm.

[0062] (8) A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate; (9) Form the first electrode and the second electrode on the fourth intermediate; The first electrode is electrically connected to the conductive step through the first through hole, and the second electrode is electrically connected to the second semiconductor layer through the second through hole.

[0063] Example 4 This embodiment provides a method for fabricating a Micro-LED chip, which includes the following steps: (1) Provide a substrate; The substrate is a sapphire substrate.

[0064] (2) An epitaxial layer is formed on the substrate; The epitaxial layer includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN type multiple quantum well layer), and a second semiconductor layer (P-type GaN layer) sequentially stacked on the substrate.

[0065] (3) Conductive steps and isolation trenches are formed on the epitaxial layer to obtain the fifth intermediate; (4) The fifth intermediate is processed by plasma ashing process to obtain the first intermediate; The process parameters for plasma ashing include: plasma power of 55W, chamber pressure of 68mtorr, and O2 flow rate of 12sccm.

[0066] (5) The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time. Then, it is washed with toluene and ethanol in sequence to obtain the second intermediate. The silane coupling agent was γ-aminopropyltriethoxysilane, and the concentration of the silane coupling agent in the modified solution was 2.8 mmol / L. The reaction temperature was 55℃, and the first preset time was 14 h.

[0067] (6) The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; The inert atmosphere is argon, the heat treatment temperature is 135℃, and the second preset time is 40min.

[0068] (7) A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; The AlN layer was formed using PEALD as a protective layer. The formation process parameters included: a TMAl pulse time of 0.11 s, an NH3 pulse time of 5 s, a plasma power of 230 W, and a deposition temperature of 340 °C; the purge gas was N2, and the purge time was 15 s. The thickness of the protective layer was 15 nm.

[0069] (8) Anneal the protective layer in a nitrogen atmosphere; The annealing temperature was 420℃ and the annealing time was 1.5 min.

[0070] (9) A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate; (10) Form the first electrode and the second electrode on the fourth intermediate; The first electrode is electrically connected to the conductive step through the first through hole, and the second electrode is electrically connected to the second semiconductor layer through the second through hole.

[0071] Comparative Example 1 This comparative example provides a method for fabricating a Micro-LED chip, which differs from Example 1 in that: Steps (4) to (5) are not included. In step (6), a SiO2 layer is deposited by PECVD as a protective layer.

[0072] Everything else is the same as in Example 1.

[0073] Comparative Example 2 This comparative example provides a method for fabricating a Micro-LED chip, which differs from Example 1 in that: Steps (4) to (5) are not included.

[0074] Everything else is the same as in Example 1.

[0075] Comparative Example 3 This comparative example provides a method for fabricating a Micro-LED chip, which differs from Example 1 in that: Step (6) is not included.

[0076] Everything else is the same as in Example 1.

[0077] The Micro-LED chips obtained in Examples 1 to 4 and Comparative Examples 1 to 3 were tested, and the brightness improvement rate was calculated based on the data of Comparative Example 1. The specific results are shown in the table below:

[0078] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of the present invention to facilitate a specific and detailed understanding of the technical solution of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0079] It should be understood that any technical solutions obtained by those skilled in the art based on the technical solutions provided in this invention through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this patent should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A method for fabricating a Micro-LED chip, characterized in that, include: Provide substrate; An epitaxial layer is formed on the substrate; wherein the epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; A conductive step and an isolation trench are formed on the epitaxial layer to obtain a first intermediate. The first intermediate is immersed in a modified solution containing a silane coupling agent and reacted for a first preset time to obtain a second intermediate; wherein the silane coupling agent contains a first active group and a second active group, the first active group being methoxy or ethoxy, and the second active group being amino. The second intermediate is heat-treated in an inert atmosphere for a second preset time to obtain the third intermediate; A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; wherein, the E of the protective layer g ≥4.0eV; A first via exposing the conductive step and a second via exposing the second semiconductor layer are formed on the protective layer to obtain a fourth intermediate. A first electrode and a second electrode are formed on the fourth intermediate; wherein the first electrode is electrically connected to the conductive step through a first through-hole, and the second electrode is electrically connected to the second semiconductor layer through a second through-hole.

2. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, In the step of immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain the second intermediate: The silane coupling agent is one or more of γ-aminopropyltriethoxysilane, N-(β-aminoethyl)-γ-aminopropyltriethoxysilane, and (N-(β-aminoethyl)-γ-aminopropylmethyldimethoxysilane), and the concentration of the silane coupling agent in the modified solution is 1 mmol / L to 5 mmol / L. The temperature of the modified solution is 25℃~70℃, and the first preset time is 6h~24h.

3. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, In the step of heat-treating the second intermediate in an inert atmosphere for a second preset time to obtain the third intermediate: The inert atmosphere is a nitrogen atmosphere or an argon atmosphere, the heat treatment temperature is 120℃~150℃, and the second preset time is 0.3h~1h.

4. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, The protective layer is an AlN layer or an AlGaN layer, with a thickness of 10nm to 20nm.

5. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, In the step of forming a protective layer on the side where the epitaxial layer of the third intermediate is located: An AlN layer is formed using PEALD as a protective layer. The formation process parameters include: The pulse time of TMAl is 0.05s~0.15s, the pulse time of NH3 is 3s~10s, the plasma power is 100W~300W, and the deposition temperature is 300℃~350℃; the purging gas is N2, and the purging time is 10s~20s.

6. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, The step of forming a protective layer on the side where the epitaxial layer of the third intermediate is located includes: A protective layer is formed on the side where the epitaxial layer of the third intermediate is located; The protective layer was annealed in a nitrogen atmosphere; The annealing temperature is 400℃~450℃, and the annealing time is 0.5min~2min.

7. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, The step of forming conductive steps and isolation trenches on the epitaxial layer to obtain the first intermediate includes: A conductive step and an isolation trench are formed on the epitaxial layer to obtain a fifth intermediate. The fifth intermediate is processed using a plasma ashing process to obtain the first intermediate; The process parameters for plasma ashing include: plasma power of 20W~100W, chamber pressure of 50mtorr~100mtorr, and O2 flow rate of 10sccm~40sccm.

8. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, The step of immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain the second intermediate includes: The first intermediate was immersed in a modified solution containing a silane coupling agent and reacted for a first preset time; then it was washed sequentially with toluene and ethanol to obtain the second intermediate.

9. The method for fabricating a Micro-LED chip as described in claim 1, characterized in that, The first semiconductor layer is an N-type GaN layer, and the second semiconductor layer is a P-type GaN layer.

10. A Micro-LED chip, characterized in that, It is prepared by the method for preparing a Micro-LED chip as described in any one of claims 1 to 9.

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