Micro light emitting diode chip and display panel

Abstract

This invention relates to a miniature light-emitting diode (LED) chip and a display panel. The miniature LED chip includes: a miniature LED array comprising multiple miniature LEDs configured to emit light; each miniature LED includes a light-emitting mesa comprising: a first type epitaxial layer; a light-emitting layer below the first type epitaxial layer, the light-emitting layer comprising multiple stacked quantum well layers; and a second type epitaxial layer below the light-emitting layer. The miniature LED chip provided by this invention has a light-emitting layer comprising multiple stacked quantum well layers and a quantum barrier layer. The quantum barrier layer has a weaker blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of light-emitting quantum wells and improving the luminous efficiency of the LED. Placing an electron blocking layer between the P-type semiconductor structure and the light-emitting stack can effectively control the electron concentration of the light-emitting layer, improve the electron-hole balance in the light-emitting layer, and effectively improve the luminous efficiency of the LED.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and particularly to micro light-emitting diode chips and display panels. Background Technology

[0002] Micro-LEDs (Micro Light Emitting Diodes) are an emerging display technology that is gaining increasing importance due to their use in various applications, including self-emitting microdisplays, visible light communication, and optogenetics. Micro-LED technology uses micrometer-scale LEDs as pixel units, miniaturizing and arraying the LED structure, and then mass-producing these micro-LED chips onto a TFT or CMOS backplane to form a high-density display panel. Compared to traditional LEDs, Micro LEDs offer better strain relaxation, higher light extraction efficiency, more uniform current diffusion, and higher output performance. Micro LEDs also boast advantages such as improved thermal performance, faster response times, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and higher current density. Micro-LEDs are hailed as the next generation of display technology and are receiving increasing attention.

[0003] The light-emitting layer of a miniature light-emitting diode (LED) includes a quantum well structure, which has a higher radiative recombination rate of electrons and holes, resulting in advantages such as high luminous efficiency, tunable emission wavelength, and low operating voltage. Therefore, quantum well structures are increasingly being used in display technology to improve the performance of display devices.

[0004] However, existing micro LED chips still have many problems, such as low light extraction efficiency (WPE, also known as electro-optical conversion efficiency), which needs to be further improved. Summary of the Invention

[0005] To address some or all of the problems in the prior art, the present invention provides a miniature light-emitting diode chip, comprising:

[0006] A miniature light-emitting diode array, the miniature light-emitting diode array comprising a plurality of miniature light-emitting diodes configured to emit light, wherein each miniature light-emitting diode includes a light-emitting mesa, wherein the light-emitting mesa comprises:

[0007] Type I epitaxial layer;

[0008] A light-emitting layer, located above the first type of epitaxial layer, the light-emitting layer comprising multiple...

[0009] A stacked quantum well layer; and

[0010] The second type of epitaxial layer is located above the light-emitting layer.

[0011] Furthermore, the light-emitting layer also includes multiple quantum barrier layers, which are stacked at intervals with the quantum well layer.

[0012] Furthermore, the light-emitting layer comprises 5-20 light-emitting stacks, each of which includes a quantum barrier layer and a quantum well layer.

[0013] Furthermore, the ratio of quantum barrier layers to quantum well layers in each luminescent stack is 1:1.

[0014] Furthermore, the light-emitting layer includes:

[0015] m first stacks are stacked on top of each other, which are close to the second type of epitaxial layer and each first stack includes a strained quantum barrier layer and a strained quantum well layer from top to bottom, where m is a natural number and the strained quantum barrier layer and strained quantum well layer in the first stack are arranged alternately.

[0016] n overlapping second layers, adjacent to the first type epitaxial layer, and each second layer comprising, from top to bottom, a quantum well layer and a quantum barrier layer, where n is a natural number and the quantum barrier layer and quantum well layer in the second layer are arranged alternately; and

[0017] A light-emitting transition layer is located between the m first stacked layers and the n second stacked layers.

[0018] Furthermore, 3 ≤ m ≤ 10; and / or

[0019] 5≤n≤20.

[0020] Furthermore, m = 5 and n = 8.

[0021] Furthermore, the micro LED chip is a blue or green micro LED chip.

[0022] Furthermore, the light-emitting layer also includes an electron blocking layer, which is located below the light-emitting stack.

[0023] Furthermore, the light-emitting stack is an InGaN / GaN layer, an InGaN / AlGaN layer, or an InGaAs / AlGaAs layer.

[0024] Furthermore, the material of the light-emitting transition layer is InGaN, GaN, or AlGaN.

[0025] Furthermore, the electron blocking layer is made of InGaN, GaN, AlGaN, InGaAs, or AlGaAs.

[0026] Furthermore, the thickness of the strained quantum well layer ranges from 1 nm to 5 nm, and the thickness of the strained quantum barrier layer ranges from 1 nm to 20 nm; and / or

[0027] The thickness of the quantum well layer ranges from 1 nm to 5 nm, and the thickness of the quantum barrier layer ranges from 1 nm to 20 nm.

[0028] Furthermore, the thickness of the light-emitting transition layer ranges from 10 nm to 200 nm.

[0029] Furthermore, the thickness of the electron blocking layer ranges from 10nm to 200nm.

[0030] Furthermore, the first type of epitaxial layer is a P-type semiconductor structure, and the second type of epitaxial layer is an N-type semiconductor structure; or

[0031] The second type of epitaxial layer is a P-type semiconductor structure, and the first type of epitaxial layer is an N-type semiconductor structure;

[0032] The P-type semiconductor structure includes a P-type doped layer; the N-type semiconductor structure includes an N-type doped layer.

[0033] Furthermore, the P-type semiconductor structure also includes a confinement layer located on top of the P-type doped layer.

[0034] Furthermore, the P-type semiconductor structure also includes a waveguide layer, which is located above the confinement layer.

[0035] Furthermore, the P-type semiconductor structure also includes a P-type transition layer, which is located on the waveguide layer.

[0036] Furthermore, the P-type doped layer includes P-type doped particles, wherein the P-type doped particles include at least one of Mg, C, and Zn.

[0037] Furthermore, the material of the P-type doped layer is at least two of Ga, N, As, Al, In, and P.

[0038] Furthermore, the material of the confining layer is at least two of Ga, N, As, Al, In, and P.

[0039] Furthermore, the waveguide layer is made of at least two of the following materials: Ga, N, As, Al, In, and P.

[0040] Furthermore, the material of the P-type transition layer includes at least two of Ga, N, As, Al, In, and P.

[0041] Furthermore, the thickness of the P-type doped layer ranges from 10 nm to 100 nm.

[0042] Furthermore, the thickness of the confinement layer ranges from 10 nm to 100 nm.

[0043] Furthermore, the thickness of the waveguide layer ranges from 50nm to 200nm.

[0044] Furthermore, the thickness of the P-type transition layer ranges from 10 nm to 200 nm.

[0045] Furthermore, the N-type semiconductor structure also includes an N-type transition layer, which is located below the N-type doped layer.

[0046] Furthermore, the N-type doped layer comprises N-type doped particles, wherein the N-type doped particles comprise at least one of Si and Te.

[0047] Furthermore, the material of the N-type doped layer is at least two of Ga, N, As, Al, In, and P.

[0048] Furthermore, the material of the N-type transition layer includes at least two of Ga, N, As, Al, In, and P.

[0049] Furthermore, the thickness of the N-type doped layer ranges from 100 nm to 3000 nm.

[0050] Furthermore, the thickness of the N-type transition layer ranges from 10 nm to 200 nm.

[0051] Furthermore, the micro LED chip also includes:

[0052] The driving module includes a driving backplane and a bonding layer.

[0053] Furthermore, the micro LED chip also includes:

[0054] A current extension structure is located between the micro LEDs and is arranged to surround the micro LEDs in an electrical contact manner.

[0055] Furthermore, the micro LED chip also includes:

[0056] A microlens is disposed on the upper surface of the micro-light-emitting diode.

[0057] Furthermore, the driving backplane includes driving electrodes, with each micro LED corresponding to one driving electrode, and the driving electrodes are electrically connected to the bonding layer.

[0058] Furthermore, the material of the driving electrode is one or more alloys of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0059] Furthermore, the bonding layer is made of one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0060] Furthermore, the miniature light-emitting diode also includes:

[0061] An ohmic contact layer is located on the lower surface of the light-emitting platform and is electrically connected to the bonding layer.

[0062] A top conductive layer, located on the side and top surfaces of the light-emitting platform, is electrically connected to the current-spreading structure; and

[0063] A passivation barrier layer, which at least partially covers the side surface of the light-emitting platform and is located between the light-emitting platform and the top conductive layer.

[0064] Furthermore, the first type of epitaxial layer is electrically connected to the ohmic contact layer;

[0065] The second type of epitaxial layer is electrically connected to the top conductive layer.

[0066] Furthermore, the electrode polarity of the ohmic contact layer is opposite to that of the electrode polarity of the top conductive layer.

[0067] Furthermore, adjacent top conductive layers are connected to each other, so that all top conductive layers are connected into a whole.

[0068] Furthermore, adjacent passivation isolation layers are connected, and all passivation isolation layers are connected into a whole.

[0069] Furthermore, the material of the passivation barrier layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0070] Furthermore, the bottom lateral dimension of the light-emitting platform is larger than the top lateral dimension.

[0071] Furthermore, the tilt angle of the sidewall of the light-emitting platform ranges from 60° to 85°.

[0072] Furthermore, the bottom lateral dimension of the light-emitting platform does not exceed 3 micrometers.

[0073] Furthermore, the top lateral dimension of the light-emitting platform does not exceed 1.5 micrometers.

[0074] Furthermore, the bottoms of adjacent current extension structures are connected, and all current extension structures are connected as a whole.

[0075] Furthermore, the longitudinal cross-section of adjacent current-spreading structures exhibits a bifurcated peak shape.

[0076] Furthermore, the longitudinal cross-sectional shapes of adjacent current-extending structures are asymmetrical.

[0077] Furthermore, the material of the current spreading structure is one or more alloys of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

[0078] Furthermore, the microlens has an upper curvature portion and a lower spacer portion.

[0079] Furthermore, the lower spacer of the microlens has a height of 0.5 to 3 micrometers; and / or

[0080] The height of the upper curvature portion of the microlens is 0.5 to 2 micrometers; and / or

[0081] The spherical width of the microlens is 3 to 4 micrometers.

[0082] Furthermore, the microlens is in the shape of a perfect hemisphere.

[0083] Furthermore, the material of the microlens is silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, or aluminum oxide.

[0084] Furthermore, the adjacent microlenses are spaced apart from the micro-light-emitting diodes.

[0085] Furthermore, the sides of adjacent microlenses are separated to form a gap, the bottom of which is higher than the top of the light-emitting platform.

[0086] Furthermore, the sides of adjacent microlenses are separated to form a gap, the bottom of which is lower than the top of the light-emitting platform.

[0087] Furthermore, the microlens includes a closed air gap inside.

[0088] The present invention also provides a display panel including the aforementioned micro light-emitting diode chip.

[0089] The technical solution provided by this invention has the following beneficial effects:

[0090] 1. The micro light-emitting diode (LED) chip provided by this invention comprises a light-emitting layer consisting of multiple stacked quantum well layers and a quantum barrier layer. The quantum barrier layer has a weak blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of light-emitting quantum wells and improving the luminous efficiency of the LED. Placing an electron blocking layer between the P-type semiconductor structure and the light-emitting stack can effectively control the electron concentration in the light-emitting layer, improving the electron-hole balance in the light-emitting layer and effectively improving the luminous efficiency of the LED. Adding a light-emitting transition layer in the middle of the light-emitting stack can reduce the electron mobility in the quantum wells, providing a certain degree of blocking effect on electrons and balancing the electron-hole concentration in the light-emitting layer. Furthermore, using a strained layer quantum well structure in the stack can enhance the overlap of wave functions of electrons and holes, improving the radiative recombination efficiency of charge carriers, thereby increasing the luminous intensity.

[0091] 2. Microlenses are spaced apart from the micro-LEDs, and current spreading structures are set between the micro-LEDs to avoid optical crosstalk between adjacent micro-LEDs. Microlenses can focus the light emitted by the micro-LEDs, and current spreading structures can reflect the light emitted by the micro-LEDs, thereby improving the brightness of the micro-LED display chip and thus improving the light extraction efficiency of the micro-LEDs. Attached Figure Description

[0092] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0093] Figure 1 A top view schematic diagram of a miniature light-emitting diode chip according to an embodiment of the present invention is shown;

[0094] Figure 2 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0095] Figure 3 A cross-sectional structural schematic diagram of a light-emitting platform according to an embodiment of the present invention is shown;

[0096] Figure 4 A cross-sectional structural schematic diagram of the light-emitting platform according to another embodiment of the present invention is shown;

[0097] Figure 5 A cross-sectional structural schematic diagram of the light-emitting platform according to another embodiment of the present invention is shown;

[0098] Figure 6A top view schematic diagram of the current extension structure of a micro light-emitting diode chip according to an embodiment of the present invention is shown;

[0099] Figure 7 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown;

[0100] Figure 8 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to yet another embodiment of the present invention is shown; and

[0101] Figure 9 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown;

[0102] Figure 10 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown. Detailed Implementation

[0103] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0104] In this invention, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this invention does not necessarily refer to the same embodiment in all instances.

[0105] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0106] In this invention, unless otherwise specified, "upper surface", "lower surface" and "side surface" are used only to describe the surfaces that distinguish the same component.

[0107] In this invention, unless otherwise specified, the quantifiers “one” and “one” do not exclude scenarios involving multiple elements, and the quantifiers “multiple” and “many” refer to one or more elements.

[0108] In this invention, the term "configuration" refers to setting the shape, structure, material and / or function of a target object to achieve a desired technical effect. "Configuration" includes a variety of alternative technical means to achieve the technical effect, which become apparent from the teachings of this application.

[0109] In this invention, the term "located at the bottom of the light-emitting platform" refers to the side of the light-emitting platform facing away from the microlens, the term "located at the top of the light-emitting platform" refers to the side of the light-emitting platform facing the microlens, and the term "side of the light-emitting platform" refers to the two sides between the top and the bottom.

[0110] In this invention, the term "profile of the metal layer" refers to the maximum dimension, such as length, within a plane (or a plane perpendicular to the thickness) formed by the length and width of the metal layer. Similarly, the bottom profile of the light-emitting platform refers to the maximum dimension, such as length, of the light-emitting platform within a bottom plane (i.e., a plane perpendicular to the thickness at the bottom).

[0111] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0112] Figure 1 A top view schematic diagram of a miniature light-emitting diode chip according to an embodiment of the present invention is shown. Figure 1 It includes a miniature light-emitting diode 101, a microlens 102, and a current-expanding structure 103. Figure 2 A longitudinal cross-sectional schematic diagram of a micro LED chip according to an embodiment of the present invention is shown. As shown, the micro LED chip includes a driving module, a micro LED 101, a current spreading structure 103, and a microlens 102. The driving module includes a driving backplane 108 and a bonding layer 110. The micro LED 101 includes a light-emitting mesa 105, an ohmic contact layer 104, a top conductive layer 107, and a passivation barrier layer 106. The micro LED 101 is disposed on the upper surface of the driving module. The current spreading structure 103 is located between the micro LEDs 101 and is arranged to surround the micro LEDs 101 in an electrical contact manner. The microlens 102 is disposed on the upper surface of the micro LED, with adjacent microlenses 102 spaced apart from the micro LEDs 101. In one embodiment, the micro LED chip is a blue or green light-emitting micro LED chip.

[0113] Each micro-LED chip has a size not exceeding 1 cm, preferably not exceeding 5 mm. The micro-LEDs are formed in an array within the micro-LED display chip, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro-LED structure is in the nanometer range, for example, 20 nm to 100 nm. Each micro-LED can form at least a portion of the pixel elements on the micro-LED display chip.

[0114] For convenience, "upward" is used to indicate away from the driving backplate 108, "downward" indicates towards the driving backplate 108, "horizontal plane" is used to indicate a plane parallel to the upper surface of the driving backplate 108, "tilted plane" is used to indicate a plane not parallel to the upper surface of the driving backplate 108, and other directional terms such as top, bottom, above, below, directly below, and under are also interpreted accordingly. In one embodiment, the driving backplate 108 includes a substrate, driving circuitry, and driving electrodes 109. Each micro LED corresponds to one driving electrode, and the driving electrode 109 is electrically connected to the bonding layer 110. In one embodiment, the material of the driving electrode is one or more alloys of the following metals: Ni, Al, Ti, Cu, Pt, and Au. In one embodiment, the substrate is a Si substrate. In another embodiment, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is approximately 700 micrometers thick. The driving circuitry forms individual pixel drivers to control the operation of each individual pixel LED device. The driving circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device.

[0115] In one embodiment, the micro-LED can be bonded to the surface of the driving backplane 108 via the bonding layer 110, and the bonding can be accomplished through eutectic bonding, thermo-press bonding, and transient liquid phase (TLP) bonding. In one embodiment, the bonding layer 110 can be disposed on the driving backplane 108. In another embodiment, the bonding layer 110 is grown on the driving backplane 108. In one embodiment, the thickness of the bonding layer 110 is 0.1 micrometers to 3 micrometers. In a preferred embodiment, the thickness of the bonding layer 110 is 0.6 micrometers. In some embodiments, the material of the bonding layer 110 is one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 110 can also be used as a reflector to reflect light emitted from the LED structure above.

[0116] In some embodiments, the driving backplane 108 may be an integrated circuit (IC) board. The micro-LEDs are electrically connected to the driving backplane 108, which controls the lighting and extinguishing of the micro-LEDs. In some embodiments, the IC board may be electrically connected to each micro-LED in the micro-LED array via separate metal interconnects. In some embodiments, each micro-LED may be individually electrically controlled by the IC board. In some embodiments, the IC board may be electrically connected to the electrodes of the micro-LED display chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the micro-LEDs. In some embodiments, the dielectric layer may also be formed in the gaps between interconnects.

[0117] This miniature LED chip comprises multiple miniature LED arrays, each array containing multiple miniature LEDs. The driving method for these miniature LEDs is, for example, a passive matrix (PM) drive, where the cathodes of all the miniature LEDs in each array are connected to a common cathode line NL, while miniature LEDs with the same number in each array are connected to their respective anode lines PL. Thus, the on / off state and brightness of each LED can be individually controlled by adjusting the type of the corresponding cathode and anode lines.

[0118] In some embodiments, the micro-light-emitting diodes (LEDs) can be arranged in a regular or irregular manner on the upper surface of the driving module, serving as pixels of the micro-LED chip. The micro-LEDs include: an ohmic contact layer 104 located on the lower surface of the light-emitting mesa 105, and electrically connected to the bonding layer 110; a top conductive layer 107 located on the side and top surfaces of the light-emitting mesa 105, and electrically connected to the current spreading structure 103; and a passivation barrier layer 106 at least partially covering the side surfaces of the light-emitting mesa, and located between the light-emitting mesa 105 and the top conductive layer 107. In some embodiments, the passivation barrier layer 106 covers a portion of the top surface of the light-emitting mesa 105.

[0119] In some embodiments, the electrode polarity of the ohmic contact layer 104 is opposite to that of the top conductive layer 107. The ohmic contact layer 104 may be, for example, a P-electrode or an anode electrode, and the top conductive layer 107 may be an electrode with the opposite polarity to that of the ohmic contact layer 104, such as an N-electrode or a cathode electrode. In one embodiment, the ohmic contact layer, the top conductive layer, and their connecting components may be one or more combinations of graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0120] In one embodiment, adjacent top conductive layers are connected, and all top conductive layers are connected as a whole. In one embodiment, adjacent passivation isolation layers are connected, and all passivation isolation layers are connected as a whole. In one embodiment, the material of the passivation isolation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0121] In some embodiments, a top conductive layer may be formed on the top surface of the micro-LED array. In some embodiments, the top conductive layer may be shared by all micro-LEDs in the micro-LED array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro-LED array may include a single-layer micro-LED structure. In some embodiments, the micro-LED array may include a multi-layer vertically stacked micro-LED structure.

[0122] In one embodiment, the light-emitting mesa can be a trapezoidal platform, with the bottom lateral dimension being larger than the top lateral dimension. In one embodiment, the inclination angle of the sidewalls of the light-emitting mesa ranges from 60° to 85°. In one embodiment, the bottom lateral dimension of the light-emitting mesa does not exceed 3 micrometers. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 micrometers. In one embodiment, the lateral dimension of the bonding layer is larger than the bottom lateral dimension of the light-emitting mesa.

[0123] like Figure 2As shown, the light-emitting mesa 105 includes a first-type epitaxial layer 1052, a second-type epitaxial layer 1051, and a light-emitting layer 1053 located between them. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer. In some embodiments, the light-emitting mesa of each micro-LED in the micro-LED array can be a micrometer-scale light-emitting mesa. In some embodiments, the micrometer-scale light-emitting mesa may include, from bottom to top, the first-type epitaxial layer, the light-emitting layer, and the second-type epitaxial layer. That is, in the three-layer structure, the first-type epitaxial layer is closest to the driving backplane 108; the light-emitting layer is located above the first-type epitaxial layer and further away from the driving backplane 108; and the second-type epitaxial layer is located above the light-emitting layer and furthest away from the driving backplane 108.

[0124] like Figure 2 As shown, the light-emitting mesa 105 includes a first-type epitaxial layer 1052, a second-type epitaxial layer 1051, and a light-emitting layer 1053 located between them. The first-type epitaxial layer is electrically connected to an ohmic contact layer. The second-type epitaxial layer is electrically connected to a top conductive layer. In some embodiments, the light-emitting mesa of each micro-LED in the micro-LED array can be a micrometer-scale light-emitting mesa. In some embodiments, the micrometer-scale light-emitting mesa may include, from bottom to top, a first-type epitaxial layer, a light-emitting layer, and a second-type epitaxial layer. That is, in the three-layer structure, the first-type epitaxial layer is closest to the driving backplane 108; the light-emitting layer is located above the first-type epitaxial layer and further away from the driving backplane 108; the second-type epitaxial layer is located above the light-emitting layer and furthest away from the driving backplane 108. In some embodiments, the light-emitting layer is formed by a plurality of stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The primary substrate material of the first type of light-emitting mesa may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; additionally, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type of epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary substrate material of the second type of epitaxial layer may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the second type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0125] In some embodiments, the first type of epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer can be a material layer of a second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first type of epitaxial layer can be a material layer of a first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer includes a multi-quantum-well layer and an electron-blocking layer. The multi-quantum-well layer is an InGaN / GaN multi-quantum-well layer, an InGaN / AlGaN multi-quantum-well layer, or an InGaAs / AlGaAs multi-quantum-well layer. In some embodiments, the light-emitting layer further includes an electron-blocking layer disposed on a first side of the light-emitting layer, the first side referring to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0126] In some embodiments, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0127] In some embodiments, one of the first type epitaxial layer and the second type epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al. x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. Furthermore, in these embodiments, the thickness of the N-type cladding layer is no greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e⁻¹. 17 cm -3 up to 1e 18 cm -3 The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e⁻¹. 18cm -3 up to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm.

[0128] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al. x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such embodiments, the thickness of the P-type cladding layer is no greater than 380 nm, for example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0129] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first-doped P-type transition layer formed on the P-type cladding layer, and a second-doped P-type transition layer formed on the first-doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0130] In some embodiments, the material of the first doped P-type transition layer is (Al) x Ga 1-x ) y In 1-yP, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example, 30 nm.

[0131] In some embodiments, the material of the second doped P-type transition layer is Al. x Ga 1-x As, where x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0132] In some embodiments, the doping concentration of the second-doped P-type transition layer is greater than the doping density of the first-doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second-doped P-type transition layer.

[0133] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second-doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second-doped P-type transition layer is 2 to 4 times that of the first-doped P-type transition layer.

[0134] For example, the doping concentration of the first doped P-type transition layer is greater than 1e. 18 cm -3 The doping density of the second-doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 Within the range, the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0135] Figures 3-5 The diagram shows cross-sectional structural schematics of the light-emitting platform according to three different embodiments of the present invention.

[0136] like Figure 3 As shown, the light-emitting mesa includes: a first-type epitaxial layer 22, a second-type epitaxial layer 21, and a light-emitting layer 23. The first-type epitaxial layer 22 is a P-type semiconductor structure, which includes a P-type doped layer. The light-emitting layer 23 is located above the first-type epitaxial layer 22 and includes multiple stacked quantum well layers. The second-type epitaxial layer 21 is located above the light-emitting layer 23 and is an N-type semiconductor structure, which includes an N-type doped layer.

[0137] like Figure 3As shown, the first type epitaxial layer 22, i.e., the film layer of the P-type semiconductor structure, sequentially includes a P-type doped layer 22a, a confinement layer 22b, a waveguide layer 22c, and a P-type transition layer 22d from bottom to top. The P-type doped layer 22a serves as a P-type electrode to provide holes. In one embodiment, the material of the P-type doped layer 22a is at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the P-type doped layer 22a ranges from 10 nm to 100 nm. The confinement layer 22b is used for close contact with the P-type doped layer 22a, and the two are lattice-matched. In one embodiment, the material of the confinement layer 22b is at least two of Ga, N, As, Al, In, and P, such as InAlGaN. In one embodiment, the thickness of the confinement layer 22b ranges from 10 nm to 100 nm. The waveguide layer 22c has good light transmittance, which is beneficial for reducing the light loss of the light-emitting layer 23. In one embodiment, the waveguide layer 22c is not doped with N-type or P-type particles. The lattice of the waveguide layer 22c matches the lattice of the light-emitting layer 23, ensuring the device performance and lifespan of the light-emitting diode of the present invention. In one embodiment, the material of the waveguide layer 22c is at least two of Ga, N, As, Al, In, and P, such as InAlGaN. In one embodiment, the thickness of the waveguide layer 22c ranges from 50 nm to 200 nm. The P-type transition layer 22d is used for the film formation transition between the P-type doped layer and the light-emitting layer, and the film formation process can be different from that of the P-type doped layer. In one embodiment, the material of the P-type transition layer 22d is at least two of Ga, N, As, Al, In, and P. In one embodiment, the thickness of the P-type transition layer 22d ranges from 10 nm to 200 nm. In one embodiment, the P-type doped layer 22a, the confinement layer 22b, the waveguide layer 22c, and the P-type transition layer 22d may include P-type dopant particles, wherein the P-type dopant particles include at least one of Mg, C, and Zn. In one embodiment, the first type epitaxial layer may further include a window layer, and a P-type ohmic contact layer may be formed below the window layer.

[0138] like Figure 3As shown, the light-emitting layer 23 includes multiple quantum barrier layers 23a, multiple quantum well layers 23b, and a light-emitting transition layer 232. The quantum barrier layers 23a and quantum well layers 23b are stacked alternately, with one quantum barrier layer and one quantum well layer forming a light-emitting stack. In one embodiment, the light-emitting layer includes a total of 5-20 light-emitting stacks. The light-emitting layer 23 includes m first stacks and n second stacks, with the m first stacks located above the light-emitting transition layer 232 and the n second stacks located below the light-emitting transition layer 232. The m stacked first stacks are close to the second type epitaxial layer 21, and each first stack includes a strained quantum barrier layer and a strained quantum well layer from top to bottom, where m is a natural number, and the strained quantum barrier layer and strained quantum well layer in the first stack are arranged alternately. n overlapping second layers, adjacent to the first type epitaxial layer 22, and each second layer comprising a quantum well layer and a quantum barrier layer from top to bottom, where n is a natural number and the quantum barrier layers and quantum well layers in the second layers are alternately arranged. The number of light-emitting layers below the light-emitting transition layer 232 may be different from the number of light-emitting layers above the light-emitting transition layer 232. In one embodiment, 3 ≤ m ≤ 10; and / or 5 ≤ n ≤ 20. In one embodiment, m = 5 and n = 8. In one embodiment, the light-emitting layers are InGaN / GaN layers, InGaN / AlGaN layers, or InGaAs / AlGaAs layers. In one embodiment, the material of the light-emitting transition layer 232 is InGaN, GaN, or AlGaN. In one embodiment, the thickness of the quantum well layer 23b ranges from 1 nm to 5 nm, and the thickness of the quantum barrier layer 23a ranges from 1 nm to 20 nm. In one embodiment, the thickness of the light-emitting transition layer 232 ranges from 10 nm to 200 nm.

[0139] like Figure 3As shown, the second type of epitaxial layer 21, i.e., the N-type semiconductor structure film layer, sequentially includes an N-type doped layer 21a and an N-type transition layer 21b from bottom to top. The N-type doped layer 21a serves as an N-type electrode to provide electrons. In one embodiment, the material of the N-type doped layer 21a is at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the N-type doped layer 21a ranges from 100 nm to 3000 nm. The N-type transition layer 21b is used for the film formation transition between the N-type doped layer 21a and the light-emitting layer, and the film formation process can be different from that of the N-type doped layer 21a. In one embodiment, the material of the N-type transition layer 21b is at least two of Ga, N, As, Al, In, and P. In one embodiment, the thickness of the N-type transition layer 21b ranges from 10 nm to 200 nm. In one embodiment, the N-type doped layer 21a and the N-type transition layer 21b may include N-type dopant particles, wherein the N-type dopant particles include at least one of Si and Te. In one embodiment, the first type of epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0140] The light-emitting layer consists of multiple stacked quantum well layers and quantum barrier layers. The quantum barrier layer has a weaker blocking effect on holes, which can increase the migration distance of holes, thereby increasing the number of light-emitting quantum wells and improving the luminous efficiency of the light-emitting diode.

[0141] like Figure 4 As shown, the light-emitting mesa includes: a first-type epitaxial layer 32, a second-type epitaxial layer 31, and a light-emitting layer 33. The first-type epitaxial layer 32 is a P-type semiconductor structure, which includes a P-type doped layer. The light-emitting layer 33 is located above the first-type epitaxial layer 32 and includes multiple stacked quantum well layers. The second-type epitaxial layer 31 is located above the light-emitting layer 33 and is an N-type semiconductor structure, which includes an N-type doped layer.

[0142] like Figure 4 As shown, the P-type semiconductor structure includes a P-type doped layer 32. The P-type doped layer 32 serves as a P-type electrode to provide holes. In one embodiment, the material of the P-type doped layer 32 comprises at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the P-type doped layer 32 ranges from 10 nm to 100 nm. In one embodiment, the P-type doped layer 32 may include P-type dopant particles, wherein the P-type dopant particles include at least one of Mg, C, and Zn.

[0143] like Figure 4As shown, the light-emitting layer 33 includes multiple quantum barrier layers 33a, multiple quantum well layers 33b, an electron blocking layer 331, and a light-emitting transition layer 332. The quantum barrier layers 33a and quantum well layers 33b are stacked alternately, with one quantum barrier layer and one quantum well layer forming a light-emitting stack. In one embodiment, the light-emitting layer includes a total of 5-20 light-emitting stacks. The light-emitting layer 33 includes m first stacks and n second stacks, with the m first stacks located above the light-emitting transition layer 332 and the n second stacks located below the light-emitting transition layer 332. The m stacked first stacks are close to the second-type epitaxial layer 31, and each first stack includes a strained quantum barrier layer and a strained quantum well layer from top to bottom, where m is a natural number, and the strained quantum barrier layer and strained quantum well layer in the first stack are arranged alternately. n overlapping second layers, adjacent to the first type epitaxial layer 32, each second layer comprising a quantum well layer and a quantum barrier layer from top to bottom, where n is a natural number and the quantum barrier layers and quantum well layers in the second layers are alternately arranged. The number of light-emitting layers below the light-emitting transition layer 232 may be different from the number of light-emitting layers above the light-emitting transition layer 232. In one embodiment, 3 ≤ m ≤ 10; and / or 5 ≤ n ≤ 20. In one embodiment, m = 5 and n = 8. In one embodiment, the light-emitting layers are InGaN / GaN layers, InGaN / AlGaN layers, or InGaAs / AlGaAs layers. In one embodiment, the material of the light-emitting transition layer 332 is InGaN, GaN, or AlGaN. In one embodiment, the thickness of the quantum well layer 33b ranges from 1 nm to 5 nm, and the thickness of the quantum barrier layer 33a ranges from 1 nm to 20 nm. In one embodiment, the thickness of the light-emitting transition layer 332 ranges from 10 nm to 200 nm. An electron blocking layer 331 is located below the light-emitting layers. In one embodiment, the electron blocking layer 331 is made of InGaN, GaN, AlGaN, InGaAs, or AlGaAs. In one embodiment, the thickness of the electron blocking layer ranges from 10 nm to 200 nm.

[0144] like Figure 4As shown, the second type of epitaxial layer 31, i.e., the N-type semiconductor structure film layer, sequentially includes an N-type doped layer 31a and an N-type transition layer 31b from bottom to top. The N-type doped layer 31a serves as an N-type electrode to provide electrons. In one embodiment, the material of the N-type doped layer 31a is at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the N-type doped layer 31a ranges from 100 nm to 3000 nm. The N-type transition layer 31b is used for the film formation transition between the N-type doped layer 31a and the light-emitting layer, and the film formation process can be different from that of the N-type doped layer 31a. In one embodiment, the material of the N-type transition layer 31b is at least two of Ga, N, As, Al, In, and P. In one embodiment, the thickness of the N-type transition layer 31b ranges from 10 nm to 200 nm. In one embodiment, the N-type doped layer 31a and the N-type transition layer 31b may include N-type dopant particles, wherein the N-type dopant particles include at least one of Si and Te.

[0145] Placing an electron blocking layer between the P-type semiconductor structure and the light-emitting stack can effectively control the electron concentration of the light-emitting layer, improve the balance of electrons and holes in the light-emitting layer, and effectively improve the luminous efficiency of the light-emitting diode.

[0146] like Figure 5 As shown, the light-emitting mesa includes: a first-type epitaxial layer 42, a second-type epitaxial layer 41, and a light-emitting layer 43. The first-type epitaxial layer 42 is a P-type semiconductor structure, which includes a P-type doped layer. The light-emitting layer 43 is located below the first-type epitaxial layer 42 and includes multiple stacked quantum well layers. The second-type epitaxial layer 41 is located below the light-emitting layer 43 and is an N-type semiconductor structure, which includes an N-type doped layer.

[0147] like Figure 5As shown, the first type of epitaxial layer 42, i.e., the film layer of the P-type semiconductor structure, includes, from top to bottom, a P-type doped layer 42a, a confinement layer 42b, a waveguide layer 42c, and a P-type transition layer 42d. The P-type doped layer 42a serves as a P-type electrode to provide holes. In one embodiment, the material of the P-type doped layer 42a is at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the P-type doped layer 42a ranges from 10 nm to 100 nm. The confinement layer 42b is used for close contact with the P-type doped layer 42a, and the two are lattice-matched. In one embodiment, the material of the confinement layer 42b is at least two of Ga, N, As, Al, In, and P, such as InAlGaN. In one embodiment, the thickness of the confinement layer 42b ranges from 10 nm to 100 nm. The waveguide layer 42c has good light transmittance, which is beneficial for reducing the light loss of the light-emitting layer 43. In one embodiment, the waveguide layer 42c is not doped with N-type or P-type particles. The lattice of the waveguide layer 42c matches the lattice of the light-emitting layer 43, ensuring the device performance and lifespan of the light-emitting diode of the present invention. In one embodiment, the material of the waveguide layer 42c is at least two of Ga, N, As, Al, In, and P, such as InAlGaN. In one embodiment, the thickness of the waveguide layer 42c ranges from 50 nm to 200 nm. The P-type transition layer 42d is used for the film formation transition between the P-type doped layer and the light-emitting layer, and the film formation process can be different from that of the P-type doped layer. In one embodiment, the material of the P-type transition layer 42d is at least two of Ga, N, As, Al, In, and P. In one embodiment, the thickness of the P-type transition layer 42d ranges from 10 nm to 200 nm. In one embodiment, the P-type doped layer 42a, the confinement layer 42b, the waveguide layer 42c, and the P-type transition layer 42d may include P-type dopant particles, wherein the P-type dopant particles include at least one of Mg, C, and Zn.

[0148] like Figure 5As shown, the light-emitting layer 43 includes multiple quantum barrier layers 43a, multiple quantum well layers 43b, and a light-emitting transition layer 432. The quantum barrier layers 43a and quantum well layers 43b are stacked alternately, with one quantum barrier layer and one quantum well layer forming a light-emitting stack. In one embodiment, the light-emitting layer includes a total of 5-20 light-emitting stacks. The light-emitting layer 43 includes m first stacks and n second stacks, with the m first stacks located above the light-emitting transition layer 432 and the n second stacks located below the light-emitting transition layer 432. The m stacked first stacks are close to the second type epitaxial layer 41, and each first stack includes a strained quantum barrier layer and a strained quantum well layer from top to bottom, where m is a natural number, and the strained quantum barrier layer and strained quantum well layer in the first stack are arranged alternately. n overlapping second layers, adjacent to the first type epitaxial layer 42, and each second layer comprising a quantum well layer and a quantum barrier layer from top to bottom, where n is a natural number and the quantum barrier layers and quantum well layers in the second layers are alternately arranged. The number of light-emitting layers below the light-emitting transition layer 432 may be different from the number of light-emitting layers above the light-emitting transition layer 432. In one embodiment, 3 ≤ m ≤ 10; and / or 5 ≤ n ≤ 20. In one embodiment, m = 5 and n = 8. In one embodiment, the light-emitting layers are InGaN / GaN layers, InGaN / AlGaN layers, or InGaAs / AlGaAs layers. In one embodiment, the material of the light-emitting transition layer 432 is InGaN, GaN, or AlGaN. In one embodiment, the thickness of the quantum well layer 43b ranges from 1 nm to 5 nm, and the thickness of the quantum barrier layer 43a ranges from 1 nm to 20 nm. In one embodiment, the thickness of the light-emitting transition layer 432 ranges from 10 nm to 200 nm.

[0149] like Figure 5 As shown, the second type of epitaxial layer 41, i.e., the N-type semiconductor structure film layer, sequentially includes an N-type doped layer 41a and an N-type transition layer 41b from bottom to top. The N-type doped layer 41a serves as an N-type electrode to provide electrons. In one embodiment, the material of the N-type doped layer 41a is at least two of Ga, N, As, Al, In, and P, such as GaN. In one embodiment, the thickness of the N-type doped layer 41a ranges from 100 nm to 3000 nm. The N-type transition layer 41b is used for the film formation transition between the N-type doped layer 41a and the light-emitting layer, and the film formation process can be different from that of the N-type doped layer 41a. In one embodiment, the material of the N-type transition layer 41b is at least two of Ga, N, As, Al, In, and P. In one embodiment, the thickness of the N-type transition layer 41b ranges from 10 nm to 200 nm. In one embodiment, the N-type doped layer 41a and the N-type transition layer 41b may include N-type dopant particles, wherein the N-type dopant particles include at least one of Si and Te.

[0150] like Figure 2 As shown, the current extension structure 103 can reflect the light emitted by the micro LED, thereby significantly increasing the total light emission. Simultaneously, the current extension structure 103 can also isolate light, preventing optical crosstalk between adjacent LEDs. By arranging the current extension structure 103 to surround the micro LED in an electrical contact manner and electrically connecting it to the top conductive layer 107, the electrical contact area between the current extension structure 103 and the micro LED can be significantly increased. This allows the active layer (light-emitting layer) of the micro LED to emit light more uniformly, effectively avoiding light emission only at or near the electrical contact area or excessively high brightness at or near the electrical contact area.

[0151] Figure 6 A top view schematic diagram of the current expansion structure of a miniature light-emitting diode chip according to an embodiment of the present invention is shown. Figure 6 As shown, the bottoms of adjacent current extension structures 103 are connected, and all current extension structures are connected into a whole. Figure 6 In this embodiment, the top view (i.e., cross-sectional shape) of the micro-LED is circular, and the top view of the overall current expansion structure is the grid shape remaining after removing the circle. In one embodiment, the top view of the micro-LED may also be other suitable shapes, such as rectangles, squares, or regular polygons, and the top view of the overall current expansion structure is correspondingly the shape remaining after removing other suitable shapes, such as the grid shape remaining after removing rectangles, squares, or polygons. Figure 2 As shown, the longitudinal cross-sections of adjacent current extension structures exhibit a bifurcated peak shape. In one embodiment, the longitudinal cross-sectional shapes of adjacent current extension structures are asymmetrical, and their heights may differ; this is not a limitation.

[0152] In one embodiment, the material of the current spreading structure is one or more alloys of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

[0153] Figure 2 In this embodiment, the lateral dimension of the bottom of the microlens 102 is larger than the lateral dimension of the light-emitting area of ​​the micro-LED. In some embodiments, the lateral dimension of the bottom of the microlens 102 may be equal to the lateral dimension of the light-emitting area of ​​the micro-LED.

[0154] In some embodiments, a microlens 102 can cover multiple lensless micro-light-emitting diodes (LEDs). Multiple microlenses constitute a microlens array. The microlens array is disposed above the array of micro-LEDs, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro-LEDs, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-LEDs. The microlenses are primarily used to converge and / or collimate light rays; for example, the focal point of the microlens can be located within the light-emitting mesa of the micro-LEDs by adjusting parameters such as the thickness and curvature of the microlenses. The microlenses in the microlens array are typically identical. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. Figure 2 As shown, in one embodiment, the microlens 102 includes an upper curvature portion 1021 and a lower spacer portion 1022. In one embodiment, the typical shape of the lower spacer portion of each microlens 102 includes a circle, a square, a rectangle, and a hexagon. The individual microlenses in the microlens array of the display panel may be the same or different in terms of shape, curvature, optical power, size, base, and spacing.

[0155] In one embodiment, the centers of curvature of the sidewalls of the lower spacer do not coincide with the centers of curvature of the upper curvature portion. The thickness of the lower spacer is set such that the focal point of the microlens is located in the light-emitting platform of the micro-LED. In one embodiment, the height of the lower spacer of the microlens is 0.5 to 3 micrometers, and / or the height of the upper curvature portion of the microlens is 0.5 to 2 micrometers, and / or the spherical width of the microlens is 3 to 4 micrometers. In yet another embodiment, the microlens may, for example, be a perfect hemisphere.

[0156] In some embodiments, the microlens 102 may be a curved hemispherical shape. In some embodiments, the height of the microlens 102 is no greater than 2 micrometers. In some embodiments, the height of the microlens 102 is no greater than 1 micrometer. In some embodiments, the height of the microlens 102 is no greater than 0.5 micrometers. In some embodiments, the width of the microlens 102 is no greater than 4 micrometers. In some embodiments, the width of the microlens 102 is no greater than 3 micrometers. In some embodiments, the width of the microlens 102 is no greater than 2 micrometers. In some embodiments, the width of the microlens 102 is no greater than 1 micrometer. In some embodiments, the width-to-height ratio of the microlens 102 is greater than 2.

[0157] In some embodiments, the microlens 102 may be made of various materials that are transparent to light of various wavelengths emitted by the micro-light-emitting diode. Exemplary transparent materials for the microlens 102 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 102 is made of photoresist. In some embodiments, the microlens is deposited directly on the surface of the micro-light-emitting diode using chemical vapor deposition (CVD) technology.

[0158] Figure 7 A longitudinal cross-sectional schematic diagram of a miniature light-emitting diode chip according to another embodiment of the present invention is shown. Figure 7 As shown, the miniature light-emitting diode (LED) chip includes a driving module, a miniature LED, a current spreading structure 503, and a microlens 502. The driving module includes a driving backplate 508 and a bonding layer 510. The driving backplate 508 includes a driving electrode 509, which is electrically connected to the bonding layer 510. The microlens 502 includes an upper curvature portion 5021 and a lower spacer portion 5022. In one embodiment, the miniature LED chip is a blue or green LED chip. The miniature LED includes a light-emitting mesa 505, an ohmic contact layer 504, a top conductive layer 507, and a passivation barrier layer 506. The miniature LEDs are disposed on the upper surface of the driving module. The current spreading structure 503 is located between the miniature LEDs and is arranged to electrically contact the miniature LEDs.

[0159] like Figure 7As shown, microlenses 502 are arranged on the upper surface of the micro-light-emitting diodes (LEDs). Adjacent microlenses 502 are connected between the LEDs, and their sides are separated to form gaps, the bottom of which is higher than the top of the light-emitting mesa. In some embodiments, the driving backplane 508 can be an integrated circuit (IC) board. The LEDs are electrically connected to the driving backplane 508, which controls the lighting and extinguishing of the LEDs. In some embodiments, the LEDs can be arranged regularly or irregularly on the upper surface of the driving module, serving as pixels of the LED chip. An ohmic contact layer 504 is located on the lower surface of the light-emitting mesa 505 and is electrically connected to the bonding layer 510. A top conductive layer 507 is located on the side and top surfaces of the light-emitting mesa 505 and is electrically connected to the current spreading structure 503. A passivation barrier layer 506 at least partially covers the side surface of the light-emitting mesa, and the passivation barrier layer 506 is located between the light-emitting mesa 505 and the top conductive layer 507. In some embodiments, the passivation barrier layer 506 covers a portion of the top surface of the light-emitting mesa 505. The light-emitting mesa 505 includes a first type epitaxial layer 5052, a second type epitaxial layer 5051, and a light-emitting layer 5053 located between them. The first type epitaxial layer is electrically connected to an ohmic contact layer. The second type epitaxial layer is electrically connected to the top conductive layer.

[0160] Figure 7 The illustrated microLED chip has adjacent microlenses spaced apart, with the bottom of the spacer higher than the top of the light-emitting platform. This design prevents upward-emitted light from entering adjacent microLEDs, while side-emitted light is reflected by the current-spreading structures on either side, allowing all light to exit through the respective microlenses. Furthermore, the shorter spacing simplifies the microlens fabrication process.

[0161] Figure 8 A longitudinal cross-sectional schematic diagram of a miniature light-emitting diode chip according to another embodiment of the present invention is shown. Figure 8As shown, the miniature light-emitting diode (LED) chip includes a driving module, a miniature LED, a current spreading structure 603, and a microlens 602. The driving module includes a driving backplate 608 and a bonding layer 610. The driving backplate 608 includes a driving electrode 609, which is electrically connected to the bonding layer 610. The microlens 602 includes an upper curvature portion 6021 and a lower spacer portion 6022. In one embodiment, the miniature LED chip is a blue or green LED chip. The miniature LED includes a light-emitting mesa 605, an ohmic contact layer 604, a top conductive layer 607, and a passivation barrier layer 606. The miniature LEDs are disposed on the upper surface of the driving module. The current spreading structure 603 is located between the miniature LEDs and is arranged to electrically contact the miniature LEDs.

[0162] like Figure 8 As shown, microlenses 602 are arranged on the upper surface of the micro-light-emitting diodes (LEDs). Adjacent microlenses 602 are connected between the LEDs, and their sides are separated to form gaps, the bottom of which is lower than the top of the light-emitting mesa. In some embodiments, the driving backplane 608 may be an integrated circuit (IC) board. The LEDs are electrically connected to the driving backplane 608, which controls the LEDs' illumination and extinguishing. In some embodiments, the LEDs may be arranged regularly or irregularly on the upper surface of the driving module, serving as pixels of the LED chip. An ohmic contact layer 604 is located on the lower surface of the light-emitting mesa 605 and is electrically connected to the bonding layer 610. A top conductive layer 607 is located on the side and top surfaces of the light-emitting mesa 605. A passivation barrier layer 606 at least partially covers the side surfaces of the light-emitting mesa and is located between the light-emitting mesa 605 and the top conductive layer 607. In some embodiments, a passivation barrier layer 606 covers a portion of the top surface of the light-emitting mesa 605. The light-emitting mesa 605 includes a first-type epitaxial layer 6052, a second-type epitaxial layer 6051, and a light-emitting layer 6053 located between the two. The first-type epitaxial layer is electrically connected to an ohmic contact layer. The second-type epitaxial layer is electrically connected to a top conductive layer.

[0163] Figure 8The illustrated miniature light-emitting diode (LED) chip has adjacent microlenses with connecting portions and gaps on their sides, with the gaps located above the connecting portions and the bottom of the gaps lower than the top of the light-emitting mesa. This significantly suppresses the intrusion of light emitted laterally into adjacent LEDs. This is particularly advantageous when spacers are provided to increase the distance between the microlenses and the light-emitting mesa (e.g., so that the focal point of the microlens falls on the light-emitting mesa), because in this case, the sides are extended, and the longer gaps between the sides of the microlenses significantly suppress the intrusion of light from the side into adjacent LEDs.

[0164] Figure 9 A longitudinal cross-sectional schematic diagram of a micro light-emitting diode chip according to another embodiment of the present invention is shown. Figure 9 As shown, the miniature light-emitting diode (LED) chip includes a driving module, a miniature LED, a current spreading structure 703, and a microlens 702. The driving module includes a driving backplate 708 and a bonding layer 710. The driving backplate 708 includes a driving electrode 709, which is electrically connected to the bonding layer 710. The microlens 702 includes an upper curvature portion 7021 and a lower spacer portion 7022. In one embodiment, the miniature LED chip is a blue or green LED chip. The miniature LED includes a light-emitting mesa 705, an ohmic contact layer 704, a top conductive layer 707, and a passivation barrier layer 706. The miniature LEDs are disposed on the upper surface of the driving module. The current spreading structure 703 is located between the miniature LEDs and is arranged to electrically contact the miniature LEDs.

[0165] like Figure 9As shown, microlenses 702 are arranged on the upper surface of the micro-LEDs. Adjacent microlenses 702 are connected between the micro-LEDs, and the sides of adjacent microlenses 702 are separated to form gaps. Each microlens 702 includes a closed air gap 7023. In some embodiments, the driving backplane 708 may be an integrated circuit (IC) board. The micro-LEDs are electrically connected to the driving backplane 708, which controls the lighting and extinguishing of the micro-LEDs. In some embodiments, the micro-LEDs may be arranged in a regular or irregular manner on the upper surface of the driving module, serving as pixels of the micro-LED chip. An ohmic contact layer 704 is located on the lower surface of the light-emitting mesa 705 and is electrically connected to the bonding layer 710. A top conductive layer 707 is located on the side and top surfaces of the light-emitting mesa 705 and is electrically connected to the current extension structure 703. A passivation barrier layer 706 at least partially covers the side surface of the light-emitting mesa, and the passivation barrier layer 706 is located between the light-emitting mesa 705 and the top conductive layer 707. In some embodiments, the passivation barrier layer 706 covers a portion of the top surface of the light-emitting mesa 705. The light-emitting mesa 705 includes a first type epitaxial layer 7052, a second type epitaxial layer 7051, and a light-emitting layer 7053 located between them. The first type epitaxial layer is electrically connected to an ohmic contact layer. The second type epitaxial layer is electrically connected to the top conductive layer.

[0166] Figure 9 The illustrated miniature light-emitting diode chip has a gap within the microlens. This gap can suppress light from entering adjacent miniature light-emitting diodes, thereby suppressing optical crosstalk. For example, the gap can be positioned between the light-emitting mesa and the current spreading structure, or at the junction between two microlenses, such as between the bifurcation peaks of the current spreading structure. This allows for flexible placement of anti-optical crosstalk positions within the microlens.

[0167] Figure 10 A longitudinal cross-sectional schematic diagram of a miniature light-emitting diode chip according to another embodiment of the present invention is shown. Figure 10As shown, the miniature light-emitting diode (LED) chip includes a driving module, miniature LEDs, and a current spreading structure 803. The driving module includes a driving backplane 808 and a bonding layer 810. The driving backplane 808 includes driving electrodes 809, which are electrically connected to the bonding layer 810. In one embodiment, the miniature LED chip can be a blue or green LED chip. The miniature LED includes: a light-emitting mesa 805, an ohmic contact layer 804, a top conductive layer 807, and a passivation barrier layer 806. The miniature LEDs are disposed on the upper surface of the driving module. The current spreading structure 803 is located between the miniature LEDs and is arranged to electrically surround the miniature LEDs. Figure 10 As shown, the bonding layer 810 includes a first metal layer 8101 and a second metal layer 8102. The first metal layer 8101 is in direct contact with the ohmic contact layer 804 at the bottom of the light-emitting platform 805, and the second metal layer 8102 is located at the bottom of the bonding layer 810, wherein the outline of the first metal layer 8101 is smaller than the outline of the second metal layer 8102. In one embodiment, the material of the first metal layer is one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 810 may also be used as a reflector to reflect light emitted from the LED structure above.

[0168] In some embodiments, the driving backplane 808 may be an integrated circuit (IC) board. Miniature light-emitting diodes (LEDs) are electrically connected to the driving backplane 808, which controls the lighting and extinguishing of the LEDs. In some embodiments, the LEDs may be arranged in a regular or irregular manner on the upper surface of the driving module, serving as pixels of the LED chip. An ohmic contact layer 804 is located on the lower surface of the light-emitting mesa 805 and is electrically connected to the bonding layer 810. A top conductive layer 807 is located on the side and top surfaces of the light-emitting mesa 805 and is electrically connected to the current spreading structure 803. A passivation barrier layer 806 at least partially covers the side surfaces of the light-emitting mesa and is located between the light-emitting mesa 805 and the top conductive layer 807. In some embodiments, the passivation barrier layer 806 covers a portion of the top surface of the light-emitting mesa 805. The light-emitting mesa 805 includes a first-type epitaxial layer 8052, a second-type epitaxial layer 8051, and a light-emitting layer 8053 located between the two. The first-type epitaxial layer is electrically connected to the ohmic contact layer. The second-type epitaxial layer is electrically connected to the top conductive layer.

[0169] Figure 10The illustrated miniature LED chip features a current-spreading structure 803 that reflects the light emitted from the LED, significantly increasing the total light output. Simultaneously, the current-spreading structure 803 isolates light, preventing crosstalk between adjacent LEDs. By arranging the current-spreading structure 803 in an electrical contact manner around the LED and electrically connecting it to the top conductive layer 807, the electrical contact area between the current-spreading structure 803 and the LED is significantly increased. This allows the LED's light-emitting layer to emit light more uniformly, effectively preventing light emission only at or near the electrical contact area or excessively high brightness at or near the electrical contact area.

[0170] In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the spacing between the micro-LED arrays, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.

[0171] In one embodiment of the present invention, a display panel is also provided, the display panel including the above-described micro light-emitting diode display chip.

[0172] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A miniature light-emitting diode chip, characterized in that, include: A miniature light-emitting diode array, the miniature light-emitting diode array comprising a plurality of miniature light-emitting diodes configured to emit light, wherein each miniature light-emitting diode includes a light-emitting mesa, wherein the light-emitting mesa comprises: Type I epitaxial layer; A light-emitting layer, located above the first type of epitaxial layer, the light-emitting layer comprising a plurality of stacked quantum well layers; and The second type of epitaxial layer is located above the light-emitting layer.

2. The micro light-emitting diode chip according to claim 1, characterized in that, The light-emitting layer also includes multiple quantum barrier layers, which are stacked at intervals with the quantum well layer.

3. The micro light-emitting diode chip according to claim 2, characterized in that, The light-emitting layer comprises 5-20 light-emitting stacks, each of which includes a quantum barrier layer and a quantum well layer.

4. The micro light-emitting diode chip according to claim 3, characterized in that, The ratio of quantum barrier layers to quantum well layers in each luminescent stack is 1:

1.

5. The micro light-emitting diode chip according to claim 1, characterized in that, The light-emitting layer includes: m first stacks are stacked on top of each other, which are close to the second type of epitaxial layer and each first stack includes a strained quantum barrier layer and a strained quantum well layer from top to bottom, where m is a natural number and the strained quantum barrier layer and strained quantum well layer in the first stack are arranged alternately. n overlapping second layers, adjacent to the first type epitaxial layer, and each second layer comprising, from top to bottom, a quantum well layer and a quantum barrier layer, where n is a natural number and the quantum barrier layer and quantum well layer in the second layer are arranged alternately; and A light-emitting transition layer is located between the m first stacked layers and the n second stacked layers.

6. The miniature light-emitting diode chip according to claim 5, characterized in that, 3≤m≤10; and / or 5≤n≤20。 7. The micro light-emitting diode chip according to claim 5, characterized in that, m = 5 and n = 8.

8. The micro light-emitting diode chip according to claim 5, characterized in that, The micro LED chip is a blue or green micro LED chip.

9. The micro light-emitting diode chip according to claim 3, characterized in that, The light-emitting layer further includes an electron blocking layer, which is located below the light-emitting stack.

10. The micro light-emitting diode chip according to claim 3, characterized in that, The light-emitting stack is an InGaN / GaN layer, an InGaN / AlGaN layer, or an InGaAs / AlGaAs layer.

11. The micro light-emitting diode chip according to claim 5, characterized in that, The material of the light-emitting transition layer is InGaN, GaN, or AlGaN.

12. The micro light-emitting diode chip according to claim 9, characterized in that, The electron blocking layer is made of InGaN, GaN, AlGaN, InGaAs, or AlGaAs.

13. The micro light-emitting diode chip according to claim 5, characterized in that, The thickness of the strained quantum well layer ranges from 1 nm to 5 nm, and the thickness of the strained quantum barrier layer ranges from 1 nm to 20 nm; and / or The thickness of the quantum well layer ranges from 1 nm to 5 nm, and the thickness of the quantum barrier layer ranges from 1 nm to 20 nm.

14. The micro light-emitting diode chip according to claim 5, characterized in that, The thickness of the light-emitting transition layer ranges from 10 nm to 200 nm.

15. The micro light-emitting diode chip according to claim 9, characterized in that, The thickness of the electron blocking layer ranges from 10 nm to 200 nm.

16. The miniature light-emitting diode chip according to claim 1, characterized in that, The first type of epitaxial layer is a P-type semiconductor structure, and the second type of epitaxial layer is an N-type semiconductor structure; or The second type of epitaxial layer is a P-type semiconductor structure, and the first type of epitaxial layer is an N-type semiconductor structure; The P-type semiconductor structure includes a P-type doped layer; the N-type semiconductor structure includes an N-type doped layer.

17. The miniature light-emitting diode chip according to claim 16, characterized in that, The P-type semiconductor structure further includes a confinement layer located on top of the P-type doped layer.

18. The micro light-emitting diode chip according to claim 17, characterized in that, The P-type semiconductor structure further includes a waveguide layer, which is located above the confinement layer.

19. The micro light-emitting diode chip according to claim 18, characterized in that, The P-type semiconductor structure further includes a P-type transition layer, which is located on the waveguide layer.

20. The micro light-emitting diode chip according to claim 16, characterized in that, The P-type doped layer includes P-type doped particles, which include at least one of Mg, C, and Zn.

21. The micro light-emitting diode chip according to claim 16, characterized in that, The material of the P-type doped layer is at least two of Ga, N, As, Al, In, and P.

22. The micro light-emitting diode chip according to claim 17, characterized in that, The material of the confinement layer is at least two of Ga, N, As, Al, In, and P.

23. The micro light-emitting diode chip according to claim 18, characterized in that, The waveguide layer is made of at least two of the following materials: Ga, N, As, Al, In, and P.

24. The micro light-emitting diode chip according to claim 19, characterized in that, The material of the P-type transition layer includes at least two of Ga, N, As, Al, In, and P.

25. The micro light-emitting diode chip according to claim 16, characterized in that, The thickness of the P-type doped layer ranges from 10 nm to 100 nm.

26. The micro light-emitting diode chip according to claim 17, characterized in that, The thickness of the confinement layer ranges from 10 nm to 100 nm.

27. The micro light-emitting diode chip according to claim 18, characterized in that, The thickness of the waveguide layer ranges from 50nm to 200nm.

28. The micro light-emitting diode chip according to claim 19, characterized in that, The thickness of the P-type transition layer ranges from 10 nm to 200 nm.

29. The micro light-emitting diode chip according to claim 16, characterized in that, The N-type semiconductor structure further includes an N-type transition layer, which is located below the N-type doped layer.

30. The micro light-emitting diode chip according to claim 16, characterized in that, The N-type doped layer includes N-type doped particles, and the N-type doped particles include at least one of Si and Te.

31. The micro light-emitting diode chip according to claim 16, characterized in that, The material of the N-type doped layer is at least two of Ga, N, As, Al, In, and P.

32. The micro light-emitting diode chip according to claim 29, characterized in that, The material of the N-type transition layer is at least two of Ga, N, As, Al, In, and P.

33. The micro light-emitting diode chip according to claim 16, characterized in that, The thickness of the N-type doped layer ranges from 100 nm to 3000 nm.

34. The micro light-emitting diode chip according to claim 29, characterized in that, The thickness of the N-type transition layer ranges from 10 nm to 200 nm.

35. The micro light-emitting diode chip according to claim 1, characterized in that, Also includes: The driving module includes a driving backplane and a bonding layer.

36. The micro light-emitting diode chip according to claim 1, characterized in that, Also includes: A current extension structure is located between the micro LEDs and is arranged to surround the micro LEDs in an electrical contact manner.

37. The micro light-emitting diode chip according to claim 1, characterized in that, Also includes: A microlens is disposed on the upper surface of the micro-light-emitting diode.

38. The micro light-emitting diode chip according to claim 35, characterized in that, The driving backplane includes driving electrodes, with each micro LED corresponding to one driving electrode, and the driving electrodes are electrically connected to the bonding layer.

39. The micro light-emitting diode chip according to claim 38, characterized in that, The material of the driving electrode is one or more alloys of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

40. The micro light-emitting diode chip according to claim 35, characterized in that, The bonding layer is made of one or more alloys of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

41. The miniature light-emitting diode chip according to any one of claims 1-40, characterized in that, The miniature light-emitting diode also includes: An ohmic contact layer is located on the lower surface of the light-emitting platform and is electrically connected to the bonding layer. A top conductive layer, located on the side and top surfaces of the light-emitting platform, is electrically connected to the current-spreading structure; and A passivation barrier layer, which at least partially covers the side surface of the light-emitting platform and is located between the light-emitting platform and the top conductive layer.

42. The miniature light-emitting diode chip according to any one of claims 1-41, characterized in that, The first type of epitaxial layer is electrically connected to the ohmic contact layer; The second type of epitaxial layer is electrically connected to the top conductive layer.

43. The micro light-emitting diode chip according to claim 41, characterized in that, The electrode polarity of the ohmic contact layer is opposite to that of the electrode polarity of the top conductive layer.

44. The micro light-emitting diode chip according to claim 41, characterized in that, Adjacent top conductive layers are connected to each other, making all top conductive layers a single unit.

45. The micro light-emitting diode chip according to claim 41, characterized in that, The adjacent passivation isolation layers are connected, and all the passivation isolation layers are connected into a whole.

46. ​​The micro light-emitting diode chip according to claim 41, characterized in that, The passivation barrier layer is made of one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

47. The micro light-emitting diode chip according to claim 1, characterized in that, The bottom horizontal dimension of the light-emitting platform is greater than the top horizontal dimension.

48. The micro light-emitting diode chip according to claim 1, characterized in that, The tilt angle of the sidewall of the light-emitting platform ranges from 60° to 85°.

49. The micro light-emitting diode chip according to claim 1, characterized in that, The bottom lateral dimension of the light-emitting platform does not exceed 3 micrometers.

50. The micro light-emitting diode chip according to claim 1, characterized in that, The top lateral dimension of the light-emitting platform does not exceed 1.5 micrometers.

51. The micro light-emitting diode chip according to claim 36, characterized in that, The bottoms of adjacent current extension structures are connected, and all current extension structures are connected as a whole.

52. The miniature light-emitting diode chip according to claim 36, characterized in that, The longitudinal cross-section of the adjacent current-spreading structures exhibits a bifurcated peak shape.

53. The micro light-emitting diode chip according to claim 36, characterized in that, The longitudinal cross-sectional shapes of adjacent current-extending structures are asymmetrical.

54. The micro light-emitting diode chip according to claim 36, characterized in that, The material of the current spreading structure is one or more alloys of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu.

55. The micro light-emitting diode chip according to claim 37, characterized in that, The microlens has an upper curvature portion and a lower spacer portion.

56. The micro light-emitting diode chip according to claim 55, characterized in that, The height of the lower spacer portion of the microlens is 0.5 to 3 micrometers; and / or The height of the upper curvature portion of the microlens is 0.5 to 2 micrometers; and / or The spherical width of the microlens is 3 to 4 micrometers.

57. The micro light-emitting diode chip according to claim 37, characterized in that, The microlens is in the shape of a perfect hemisphere.

58. The micro light-emitting diode chip according to claim 37, characterized in that, The microlens is made of silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, or aluminum oxide.

59. The micro light-emitting diode chip according to claim 37, characterized in that, The adjacent microlenses are spaced apart from the micro-light-emitting diodes.

60. The miniature light-emitting diode chip according to claim 37, characterized in that, The sides of adjacent microlenses are separated to form a gap, the bottom of which is higher than the top of the light-emitting platform.

61. The miniature light-emitting diode chip according to claim 37, characterized in that, The sides of adjacent microlenses are separated to form a gap, the bottom of which is lower than the top of the light-emitting platform.

62. The micro light-emitting diode chip according to claim 37, characterized in that, The microlens includes a closed air gap inside.

63. A display panel, characterized in that, Includes a miniature light-emitting diode display chip according to any one of claims 1-62.

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