Micro light emitting diode with high light extraction efficiency, micro light emitting diode chip and manufacturing method thereof

Abstract

This invention discloses a high-light-emitting micro LED, comprising a light-emitting mesa and a passivation layer covering the sidewalls of the light-emitting mesa. The passivation layer is made of a material with a higher refractive index compared to silicon dioxide and aluminum oxide. The higher dielectric constant and refractive index enable sufficient passivation of pixel sidewall defects even with a thinner passivation layer, effectively suppressing surface recombination and non-radiative recombination of charge carriers, thereby improving the luminous efficiency of the Micro LED while enhancing luminous uniformity.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to a high light-emitting diode, a micro light-emitting diode chip, and a method for manufacturing the same. Background Technology

[0002] Micro LED (Micro Light Emitting Diode) microdisplay chips are a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. They integrate arrayed micron-sized LED units on an active addressable driver panel to enable the lighting and individual control of the LED units, thereby outputting the desired display image.

[0003] In the manufacturing process of Micro LEDs, dry etching and other processes are typically used to etch the MESA (Meta-Organic Acrylic Aperture Surface). During this process, numerous defects are formed in the sidewall regions of the Micro LED, leading to a decrease in the internal quantum efficiency of small-sized Micro LED devices and resulting in sidewall defects. Sidewall defects are the primary cause of the efficiency reduction in small-sized Micro LED devices.

[0004] Passivating pixel sidewall defects is one of the key technologies for improving the performance of Micro LED displays. By passivating pixel sidewall defects, the efficiency reduction caused by sidewall defects can be effectively reduced, thereby improving the external quantum efficiency (EQE) and internal quantum efficiency (IQE). Currently, most common passivation layers are made of SiO2 material using traditional chemical vapor deposition (CVD). However, as the size of Micro LED chips continues to shrink, the sidewall area ratio increases, leading to more severe sidewall luminescence problems, making SiO2 insufficient for meeting the requirements. Specifically, after photons are emitted from the multiple quantum wells of a Micro LED, total internal reflection (tir) occurs between the emitting mesa and the passivation layer, preventing some photons from passing through. Since SiO2 has a low refractive index, its total internal reflection loss is high, which in turn affects the luminous efficiency of the Micro LED chip. Summary of the Invention

[0005] To address some or all of the problems of the prior art, the first aspect of the present invention provides a high-light-emitting micro-light-emitting diode, comprising:

[0006] A light-emitting platform, which can be used to emit light; and

[0007] A passivation layer covers the side surface of the light-emitting platform, and the refractive index of the passivation layer material is higher than that of silicon dioxide and aluminum oxide.

[0008] Furthermore, the refractive index of the passivation layer material is not less than 1.9.

[0009] Furthermore, the passivation layer is made of aluminum nitride (AlN), silicon nitride (SiN), or hafnium oxide (HfO2).

[0010] Furthermore, the passivation layer is fabricated using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0011] Furthermore, the thickness of the passivation layer is 20 to 1000 nanometers.

[0012] Furthermore, the light-emitting mesa sequentially includes a first epitaxial layer, a light-emitting layer, and a second epitaxial layer.

[0013] Furthermore, the material of the second epitaxial layer is a material layer of the second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first conductivity type is different from the second conductivity type.

[0014] Furthermore, the light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an InGaAs / AlGaAs multi-quantum well layer.

[0015] Furthermore, an electron blocking layer is provided on the first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer.

[0016] Based on the high light-emitting micro light-emitting diodes as described above, a second aspect of the present invention provides a micro light-emitting diode chip, which includes a micro light-emitting diode array bonded to a driving backplane, wherein the micro light-emitting diode array includes a plurality of high reflectivity micro light-emitting diodes as described above.

[0017] Furthermore, the micro-LED array includes a continuous top conductive layer disposed above the micro-LED array and contacting and covering the top of each light-emitting platform.

[0018] Furthermore, a metal layer is provided on the surface of the driving backplane, and a plurality of IC copper pillars are provided on the driving backplane. The IC copper pillars are electrically connected to the metal layer, and each light-emitting mesa of the micro LED array area corresponds to one IC copper pillar.

[0019] Furthermore, the material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.

[0020] Furthermore, a second electrode is provided between adjacent light-emitting platforms.

[0021] Furthermore, the second electrode is a ring-shaped reflective electrode, which is disposed around the semiconductor light-emitting platform.

[0022] Furthermore, the second electrode between adjacent light-emitting mesa has at least two peaks.

[0023] Furthermore, the second electrodes are interconnected.

[0024] Furthermore, the micro LED chip also includes at least one first electrode, which is electrically connected to the IC copper pillar.

[0025] Furthermore, the polarity of the first electrode is opposite to that of the second electrode.

[0026] Furthermore, the micro-light-emitting diode chip also includes a microlens array, which is located above the micro-light-emitting diode array area and includes multiple microlenses, wherein at least one microlens is disposed on the surface of the conductive layer on top of the micro-light-emitting diode.

[0027] Furthermore, the microlens has an air gap inside.

[0028] Furthermore, there are gaps between adjacent micro-projection lenses, but they are at least partially connected.

[0029] A third aspect of the present invention provides a method for manufacturing a miniature light-emitting diode chip, comprising:

[0030] Forming a semiconductor light-emitting module;

[0031] The semiconductor light-emitting module is bonded to the driver backplane;

[0032] Step etching is performed on the semiconductor light-emitting module;

[0033] A passivation layer is formed on the sidewalls and surface of each pixel, wherein the material of the passivation layer is AlN;

[0034] A photolithographic etching opening is made above the corresponding pixel to expose at least a portion of the surface at the top of the pixel;

[0035] A top conductive layer is formed on the surface of the passivation layer;

[0036] A second electrode is formed at the interval of each pixel;

[0037] A first electrode is formed on the drive backplate; and

[0038] Deposited microlenses.

[0039] Furthermore, forming the semiconductor light-emitting module includes:

[0040] A second epitaxial layer, an electron blocking layer, a multilayer quantum well, and a first epitaxial layer are sequentially deposited on the substrate.

[0041] Furthermore, the step etching of the semiconductor light-emitting module includes:

[0042] The semiconductor light-emitting module is etched to form positive trapezoidal pixel structures.

[0043] Furthermore, the horizontal angle of the trapezoidal pixel is between 65° and 85°.

[0044] Furthermore, a passivation layer is formed on the sidewalls and surface of the pixel using an atomic layer deposition process.

[0045] Furthermore, the manufacturing method further includes:

[0046] Deep trench etching is performed at the intervals between each pixel, and the second electrode is disposed at the deep trench.

[0047] This invention provides a high-efficiency micro-light-emitting diode (LED) that uses ALD deposition of high-refractive-index materials such as AlN and SiN as the passivation layer for the light-emitting mesa. On one hand, ALD deposition offers higher film density compared to CVD deposition, thus better preventing damage to the light-emitting mesa from external environmental pollutants such as H2O and O2 during operation. On the other hand, compared to traditional SiO2, AlN and SiN have higher film density, dielectric constant, and refractive index, enabling them to effectively passivate pixel sidewall defects even with thinner thickness, effectively suppressing surface recombination and non-radiative recombination of charge carriers, thereby improving both the luminous efficiency and uniformity of the Micro LED. Specifically, because materials such as AlN and SiN have a higher refractive index than SiO2, they can significantly reduce total internal reflection losses at the interface between the light-emitting mesa and the passivation layer. Furthermore, AlN and SiN have higher dielectric constants, meaning stronger insulation, which can effectively reduce current leakage at the sidewalls of the light-emitting mesa. Meanwhile, due to the higher bond energy of Ga-N, AlN and SiN can effectively passivate the damage caused to GaN during the etching process. Attached Figure Description

[0048] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0049] Figure 1 A schematic diagram of a high-light-emission micro-light-emitting diode according to an embodiment of the present invention is shown;

[0050] Figure 2 This diagram illustrates the structure of a miniature light-emitting diode chip according to an embodiment of the present invention.

[0051] Figures 3A to 3D A schematic diagram showing a partial topography of a micro light-emitting diode chip according to different embodiments of the present invention;

[0052] Figure 4 A schematic flowchart illustrating a method for manufacturing a miniature light-emitting diode chip according to an embodiment of the present invention; and

[0053] Figures 5A to 5I The chip state is shown after each step of the method for manufacturing a miniature light-emitting diode chip according to the present invention has been performed. Detailed Implementation

[0054] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0055] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0056] It should be noted that the embodiments of the present invention describe the process steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.

[0057] In the fabrication of micro LED chips, processes such as dry etching are required to obtain the light-emitting mesa (MESA) to form pixels. However, sidewall defects can occur during this process. Currently, chemical vapor deposition (CVD) is often used to deposit SiO2 and / or Al2O3 materials as passivation layers for Micro LED pixels to passivate these sidewall defects. However, the film formed by CVD has low density, allowing external environmental pollutants such as H2O and O2 to easily penetrate the chip during operation, damaging the light-emitting mesa. Furthermore, the refractive index of SiO2 (1.45) and Al2O3 (1.65) results in significant total internal reflection losses during operation, affecting light extraction efficiency. To address these issues, one approach is to replace the passivation layer with a material with a higher refractive index. Another approach is to improve the deposition process to obtain a passivation layer with higher film density. Based on this, the present invention provides a high-efficiency micro-light-emitting diode (LED), which uses an ALD (Alternating Current Deposition) method to deposit a thin film with a high refractive index, such as AlN, as the passivation layer for the pixel of the micro-LED chip. Since the refractive index of AlN is approximately 1.9, much higher than that of SiO2 and Al2O3, it can significantly reduce total internal reflection losses at the interface between the light-emitting mesa and the passivation layer. Furthermore, compared to CVD (Continuous Chemical Deposition), ALD deposition offers higher film density, further preventing damage to the light-emitting mesa caused by H2O and O2 during the operation of the micro-LED chip. AlN also has a higher dielectric constant and stronger insulation properties, effectively reducing current leakage at the sidewalls. Simultaneously, due to the higher Ga-N bond energy, AlN can effectively passivate GaN from damage caused during etching. Therefore, using an ALD-deposited high-refractive-index thin film as the passivation layer for the pixel of the micro-LED chip allows for higher light extraction efficiency with a thinner passivation layer.

[0058] A miniature light-emitting diode (LED) chip includes an integrated circuit (IC) backplane and an array of miniature LEDs. The miniature LED array comprises multiple miniature LEDs. Each miniature LED can form at least a portion of a pixel element on the miniature LED chip.

[0059] In embodiments of the present invention, the size of each micro-LED chip is no more than 1 cm, preferably no more than 20 micrometers. The micro-LED structures are formed in an array within the micro-LED chips, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro-LED structures is in the nanometer range, for example, from 20 nm to 100 nm.

[0060] In some embodiments of the present invention, an integrated circuit (IC) backplane may be electrically connected to each micro-light-emitting diode in a micro-light-emitting diode array via separate metal interconnects. In some embodiments, each micro-light-emitting diode may be electrically controlled individually by the IC backplane. In some embodiments, the IC backplane may be electrically connected to the electrodes of the micro-light-emitting diode chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the micro-light-emitting diodes. In some embodiments, a dielectric layer may also be formed in the gaps between interconnects.

[0061] In some embodiments of the present invention, each micro-LED in the micro-LED array may include a micrometer-scale emitting mesa structure. In some embodiments, the emitting mesa structure may include, from bottom to top, a first type epitaxial layer, an emitting layer, and a second type epitaxial layer. That is, in the three-layer structure, the first type epitaxial layer is closest to the IC backplane; the emitting layer is located above the first type epitaxial layer and further away from the IC backplane; the second type epitaxial layer is located above the emitting layer and furthest away from the IC backplane. In some embodiments, the emitting layer is formed of multiple stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The main substrate material of the first type epitaxial layer may be, but is not limited to, Ga, N, As, P, In and includes, but is not limited to, waveguide layers, confinement layers, transition layers, and window layers; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary matrix material of the second type of epitaxial layer may be, but is not limited to, composed of at least two or more elements selected from Ga, N, As, P, In, and Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer.

[0062] In some embodiments, a top conductive layer may be formed on the top surface of the micro-LED array. In some embodiments, the top conductive layer may be shared by all micro-LEDs in the micro-LED array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro-LED array may include a single-layer micro-LED structure. In some embodiments, the micro-LED array may include a multi-layer vertically stacked micro-LED structure.

[0063] In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the spacing between the micro-LED arrays, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.

[0064] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0065] Figure 1 A schematic diagram of a high-light-emitting micro-light-emitting diode according to an embodiment of the present invention is shown. Figure 1 As shown, a high-efficiency micro LED includes a light-emitting mesa 101 and a passivation layer 102. The passivation layer 102 covers the sidewalls of the light-emitting mesa 101, and the refractive index of the passivation layer material is higher than that of SiO2 and Al2O3, for example, AlN, SiN, HfO2, etc. In one embodiment of the invention, the passivation layer 102 is fabricated using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In another embodiment of the invention, the thickness of the passivation layer 102 is 20 to 1000 nanometers. ALD-deposited AlN has higher film density, dielectric constant, and refractive index, which can fully passivate pixel sidewall defects while reducing thickness, effectively suppressing surface recombination and non-radiative recombination of charge carriers, improving the luminous efficiency of Micro LED while improving luminous uniformity.

[0066] In some embodiments of the present invention, the passivation layer also covers a portion of the top surface of the light-emitting platform, specifically, it covers the edge portion of the top surface of the light-emitting platform.

[0067] Based on the high light extraction efficiency of the micro light-emitting diodes mentioned above, Figure 2 A schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 2 As shown, the micro light-emitting diode chip 200 according to the present invention includes a micro light-emitting diode array, the micro light-emitting diode array including a plurality of high reflectivity micro light-emitting diodes as described above, the micro light-emitting diode array being bonded to a driving backplane 201 via a metal bonding layer 202.

[0068] In one embodiment of the present invention, the micro light-emitting diode array includes multiple light-emitting mesa and a continuous top conductive layer 205.

[0069] In one embodiment of the present invention, such as Figure 2As shown, the semiconductor light-emitting mesa includes a first epitaxial layer 231, a light-emitting layer 232, and a second epitaxial layer 233 deposited sequentially, wherein the light-emitting layer includes a multiple quantum well layer and an electron blocking layer. In one embodiment of the present invention, the light-emitting mesa of each micro-LED in the micro-LED array can be a micrometer-scale light-emitting mesa. In one embodiment of the present invention, the micrometer-scale light-emitting mesa may include, from bottom to top, a first type epitaxial layer, a light-emitting layer, and a second type epitaxial layer. That is, in the three-layer structure, the first type epitaxial layer is closest to the driving backplane; the light-emitting layer is located above the first type epitaxial layer and further away from the driving backplane; the second type epitaxial layer is located above the light-emitting layer and furthest away from the driving backplane. In one embodiment of the present invention, the light-emitting layer is formed by multiple stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In one embodiment of the present invention, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The primary substrate material of the first type of light-emitting mesa may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; additionally, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type of epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary substrate material of the second type of epitaxial layer may be, but is not limited to, materials such as Ga, N, As, P, In, or Al. Furthermore, the second type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in one embodiment of the invention, an ohmic contact layer may be formed on the confinement layer. In one embodiment of the invention, the first conductivity type is different from the second conductivity type.

[0070] In one embodiment of the present invention, the first epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second epitaxial layer can be a material layer of a second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer can be a material layer of a first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P. The multiple quantum well layer is an InGaN / GaN multiple quantum well layer, an InGaN / AlGaN multiple quantum well layer, or an InGaAs / AlGaAs multiple quantum well layer. The electron blocking device is disposed on a first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment of the present invention, the first epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer.

[0071] In one embodiment of the present invention, the light-emitting layer includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1- y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the light-emitting layer is a multiple quantum well (MQW).

[0072] In embodiments of the present invention, one of the first type epitaxial layer and the second type epitaxial layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer. The doped N-type contact layer is configured to be bonded to a bonding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al. x In 1-x P, where x ranges from 0.1 to 0.5, for example, x is 0.5. Furthermore, in these embodiments, the thickness of the N-type cladding layer is no greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e⁻¹. 17 cm -3 up to 1e 18 cm -3 In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer formed on the doped N-type contact layer. The doped N-type contact layer is configured to be bonded to the bonding layer. The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e⁻¹. 18 cm -3 up to 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al). x Ga 1-x ) y In 1-yP, where x ranges from 0.5 to 0.9 and y ranges from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example, 65 nm. In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer.

[0073] In some embodiments, the material of the P-type coating is Al. x In 1-x P, where x is 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type coating is no greater than 380 nm, for example, the thickness of the P-type coating is 360 nm.

[0074] In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0075] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first-doped P-type transition layer formed on the P-type cladding layer, and a second-doped P-type transition layer formed on the first-doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al). x Ga 1-x ) y In 1-y P, where x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example, 65 nm.

[0076] In some embodiments, the material of the first doped P-type transition layer is (Al) x Ga 1-x ) y In 1-y P, where x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example, 30 nm.

[0077] In some embodiments, the material of the second doped P-type transition layer is Al. x Ga 1-xAs, where x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0078] In some embodiments, the doping concentration of the second-doped P-type transition layer is greater than the doping density of the first-doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second-doped P-type transition layer.

[0079] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second-doped P-type transition layer. Furthermore, in some embodiments, the doping concentration of the second-doped P-type transition layer is 2 to 4 times that of the first-doped P-type transition layer.

[0080] For example, the doping concentration of the first doped P-type transition layer is greater than 1e. 18 cm -3 The doping density of the second-doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 Within the range, the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0081] Figures 3A to 3D A schematic diagram showing a partial topography of a micro light-emitting diode chip according to different embodiments of the present invention is provided. As shown in the figure, the semiconductor light-emitting mesa is stepped (…). Figure 3A and 3C ) or trapezoidal ( Figure 3B and 3D ).

[0082] In one embodiment of the present invention, the light-emitting platform can be arranged on the driving panel 201 in a regular or irregular manner as the pixel of the micro light-emitting diode chip.

[0083] The continuous top conductive layer 205 is disposed above the micro light-emitting diode array and contacts and covers the top of each light-emitting mesa. It is in electrical contact with the second epitaxial layer 233 of the light-emitting mesa, so as to connect the second epitaxial layers of each semiconductor light-emitting mesa in series. It is a transparent conductive layer.

[0084] like Figure 2As shown, there are gaps between the pixels formed by the various semiconductor light-emitting mesa, and a second electrode 206 is disposed at each gap, and the second electrode 206 is disposed on the surface of the continuous top conductive layer 205. In one embodiment of the present invention, the second electrode 206 is a ring-shaped reflective electrode, disposed around the light-emitting mesa, and is formed by magnetron sputtering or vapor deposition, and its material can be, for example, Al or Al alloy metal for the sidewall reflective mirror, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au, or other metal materials. In one embodiment of the present invention, the second electrodes are interconnected.

[0085] like Figure 3A and 3C As shown, in some embodiments of the present invention, a deep trench is provided at the partition between two adjacent light-emitting mesa surfaces. The deep trench penetrates the micro-light-emitting diode array; specifically, it penetrates the bottom stack of the partition, and the second electrode 206 is disposed at the deep trench. As shown, in one embodiment of the present invention, the second electrode between adjacent light-emitting mesa surfaces has at least two peaks. Figure 3B and 3D As shown, in some embodiments of the present invention, deep trenches are not provided at the interval between two adjacent light-emitting platforms, but a passivation isolation layer and a continuous top conductive layer are directly formed. Therefore, the surface of the continuous top conductive layer between two adjacent light-emitting platforms is a horizontal or substantially horizontal plane. The second electrode is formed here, and its morphological interface is trapezoidal or approximately trapezoidal. The surface of the second electrode is not higher than the highest point of the continuous top conductive layer.

[0086] As previously described, the surface and sides of the light-emitting mesa are covered with a passivation layer 204, but at least a portion of the surface of the second epitaxial layer 233 is exposed. The top conductive layer 205 is disposed on the surface of the passivation layer 204. The passivation layer not only reduces current leakage at the sidewalls but also passivates sidewall defects and prevents damage to the light-emitting mesa from water, oxygen, etc., during operation. In one embodiment of the invention, the passivation layer 204 is made of AlN material deposited by ALD, with a thickness of 20 nm to 1000 nm. AlN has a high refractive index, which can significantly reduce total internal reflection loss and improve light extraction efficiency. Figure 3A and 3B As shown, in some embodiments of the present invention, the passivation layer only covers the side surface of the light-emitting platform, but not the top surface, and the highest point of the passivation layer is flush with the top surface of the light-emitting platform. In these embodiments, the continuous top conductive layer covering the top of the light-emitting platform is horizontal or substantially horizontal in planar shape. And as... Figure 3C and 3DAs shown, in some embodiments of the present invention, the passivation layer not only covers the side surface of the light-emitting platform, but also covers the top edge of the light-emitting platform, and thus has a protrusion at the top edge of the light-emitting platform, so that the continuous top conductive layer 205 covering it also forms a protrusion at the top edge of the light-emitting platform.

[0087] In one embodiment of the present invention, the driving backplane 201 includes a substrate, a driving circuit, and IC copper pillars 211 connected to the driving circuit, and the micro-light-emitting diode array is electrically connected to the IC copper pillars 211. The substrate may be a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is approximately 700 micrometers thick. The driving circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device. As shown, the IC copper pillars 211 include a first IC copper pillar and a second IC copper pillar, wherein the first IC copper pillar is electrically connected to a first epitaxial layer of the semiconductor light-emitting module, and the second IC copper pillar is electrically connected to a first electrode 207. In one embodiment of the present invention, the polarity of the first electrode is opposite to that of the second electrode. In one embodiment of the present invention, each semiconductor light-emitting module has a common first electrode. The first electrode may be, for example, a P electrode or an anode electrode, and the second electrode is an electrode with a polarity opposite to that of the first electrode, such as an N electrode or a cathode electrode. In one embodiment of the invention, the first and second electrodes and their connecting components may be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO), or any combination thereof. In another embodiment of the invention, the first and second electrodes and their connecting components may be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO).

[0088] As shown in the figure, in one embodiment of the present invention, the micro-light-emitting diode chip further includes a microlens array. The microlens array is disposed above the micro-light-emitting diode array, wherein at least one microlens 208 is disposed on the surface of the conductive layer on top of the micro-light-emitting diode, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-light-emitting diode. The microlens is mainly used for focusing and / or collimating optical fibers; for example, the focal point of the microlens can be located in the light-emitting mesa of the micro-light-emitting diode by adjusting parameters such as the thickness and curvature of the microlens.

[0089] As shown in the figure, in one embodiment of the present invention, the microlenses of the microlens array correspond one-to-one with the light-emitting platform. Meanwhile, as... Figure 3A and3B As shown, in some embodiments of the present invention, adjacent microlenses have gaps between them and their bottoms are connected to each other. The bottom of the gap may be lower than the top of the light-emitting platform of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting platform, or located above the second electrode, or located between the two peaks of the second electrode. Figure 3C and 3D As shown, in some other embodiments of the present invention, adjacent microlenses are completely connected, but there is a gap at the connection. Furthermore, the bottom of the connection may be lower than the top of the light-emitting platform of the micro-light-emitting diode, or lower than the bottom of the light-emitting layer of the light-emitting platform, or located above the second electrode, or located between the two peaks of the second electrode.

[0090] In addition, such as Figures 3A to 3D As shown, in one embodiment of the present invention, the microlens has an air gap inside.

[0091] In an embodiment of the present invention, the microlens can be formed by multiple depositions. In the process of forming the microlens, a SiO2 film layer needs to be deposited first, and then ion etching is performed. The microlens 208 is formed on the surface of the passivation layer at the position corresponding to each light-emitting platform.

[0092] Figure 4 A schematic flowchart illustrating the manufacturing method of the micro light-emitting diode chip as described above is shown. Figure 4 As shown, a method for manufacturing a miniature light-emitting diode chip includes:

[0093] First, in step 401, as Figure 5A As shown, a semiconductor light-emitting module is provided. A second epitaxial layer 233, an electron blocking layer 2322, a multilayer quantum well 2321, and a first epitaxial layer 231 are sequentially deposited on a substrate 001, and then the substrate is thinned. In one embodiment of the present invention, the substrate may be a Si substrate, a SiC substrate, or a sapphire substrate.

[0094] Next, in step 402, as Figure 5BAs shown, the semiconductor light-emitting module is bonded to a driving backplane. The semiconductor light-emitting module is bonded to the driving backplane 201 to form a bonding layer. The driving backplane includes a driving circuit to provide driving signals to the micro-light-emitting diode chip and control the switching of pixels. The driving backplane is provided with a plurality of IC copper pillars 211, which, after being electrically interconnected with the semiconductor light-emitting module, enable control of the pixels. In one embodiment of the present invention, after chip bonding, the substrate of the semiconductor light-emitting module can be further thinned by grinding or laser lift-off to further thin the buffer layer structure, facilitating subsequent fabrication of the PN step structure. In embodiments of the present invention, the bonding process may, for example, employ thermosetting bonding, etc., which will not be elaborated further here.

[0095] Next, in step 403, as Figure 5C As shown, etched steps are formed. The semiconductor light-emitting module is subjected to step etching. By adjusting the photolithographic morphology, it is ion-etched to form positive trapezoidal structure pixels. In one embodiment of the present invention, the horizontal angle of the positive trapezoidal structure pixels can be, for example, 65° to 85°.

[0096] Next, in step 404, as Figure 5D As shown, deep trenches are etched. Further deep trench etching is performed at the intervals between each pixel, for example, using photolithography and IBE (Inert Gas Physical Etching) processes. It should be understood that this step may be omitted in some embodiments of the invention.

[0097] Next, in step 405, as Figure 5E As shown, a passivation layer is formed. A passivation layer 204 is formed on the sidewalls and surface of each pixel. In one embodiment of the invention, the passivation layer is formed by ALD deposition of an AlN film. After deposition, photolithographic etching is performed above the corresponding pixel to expose at least a portion of the surface of the second epitaxial layer. It should be understood that in other embodiments of the invention, other high-refractive-index materials can also be used to form the passivation layer; preferably, the refractive index of the material is not less than 1.9.

[0098] Next, in step 406, as Figure 5F As shown, a transparent conductive layer is formed. A top conductive layer 205 is formed on the surface of the passivation layer to achieve shared series connection of the second epitaxial layer for each pixel.

[0099] Next, in step 407, as Figure 5GAs shown, a second electrode is formed. An annular reflective electrode 206 is formed at the deep trench. In one embodiment of the invention, the annular reflective electrode is implemented using magnetron sputtering or vapor deposition. In another embodiment of the invention, the second electrode uses Al or Al alloy metal as the sidewall reflective mirror, and the electrode stack metal uses metal materials such as Ni, Al, Ti, Pt, and Au.

[0100] Next, in step 408, as Figure 5H As shown, a first electrode is formed. A first electrode 207 is formed on the drive backplane. The first electrode is connected to the IC copper pillar, which serves to protect and elevate the IC, and facilitates subsequent wire bonding.

[0101] Next, in step 409, as Figure 5I As shown, a microlens is deposited. SiO2 is deposited, and the photolithographic morphology is adjusted to form a microlens 208. In one embodiment of the present invention, a SiO2 film layer, i.e., the first transmission layer, is deposited by PECVD. The thickness of the film layer is approximately 2.5 to 3.5 μm. Subsequently, by adjusting the photolithographic morphology of the microlens, such as the resist thickness, exposure energy, and hardening temperature, the photolithographic array morphology at the corresponding pixel position is completed. The SiO2 material of the microlens passivation protective layer is ion-etched to form a hemispherical SiO2 microlens with a lens-like morphology, which can improve the light extraction efficiency to a certain extent. Thus, the initial structure of the micro-LED chip is formed. However, due to the poor step coverage of the SiO2 deposited by PECVD, microcracks easily form in the deep trenches of the pixels, causing diffuse reflection of the quantum well light source and reducing the light extraction efficiency of the microlens. In addition, due to the photolithography size and ion etching of the microlens, the overall radius of curvature, lower spacer height, spherical height, and lens spherical width of the microlens are all relatively small, failing to achieve the optimal conditions for the lens. Therefore, in some embodiments of the present invention, a secondary deposition can be performed to increase the radius of curvature, lower spacer height, spherical height, and lens spherical width of the microlens. In one embodiment of the present invention, the film thickness of the secondary SiO2 deposition needs to be determined based on the film thickness of the SiO2 deposited in the previous microlens and the etching morphology of the microlens. In one embodiment of the present invention, the film thickness of the secondary deposition is preferably 0.2 to 1 μm, and it can be performed in a single or multiple deposition operations. In one embodiment of the present invention, the secondary SiO2 deposition uses a mixed gas of SiH4 and N2O, with the ratio of SiH4 to N2O being 1:5. At the same time, the gas flow rate is controlled at a low level so that the deposition rate is much lower than that of the previous microlens deposition. The secondary deposition adopts a high vacuum environment process condition and a large flow rate of inert gas N2 to further improve the step coverage effect of the secondary SiO2 deposition, making it less prone to defects and even able to repair micro-defects in the previous microlens deposition, resulting in a better brightness improvement effect.

[0102] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A high light-emitting diode, characterized in that, include: A light-emitting platform, configured to emit light; as well as A passivation layer that covers at least a portion of the side surface of the light-emitting platform, and the material of the passivation layer having a higher refractive index compared to silicon dioxide and aluminum oxide.

2. The miniature light-emitting diode as described in claim 1, characterized in that, The refractive index of the passivation layer material is not less than 1.

9.

3. The miniature light-emitting diode as described in claim 1, characterized in that, The passivation layer is made of aluminum nitride, silicon nitride, or hafnium oxide.

4. The miniature light-emitting diode as described in claim 1, characterized in that, The passivation layer is fabricated using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

5. The miniature light-emitting diode as described in claim 1, characterized in that, The thickness of the passivation layer is 20 to 1000 nanometers.

6. The miniature light-emitting diode chip as described in claim 1, characterized in that, The passivation layer does not cover the top surface of the light-emitting platform, and the surface of the passivation layer is flush with the top surface of the light-emitting platform.

7. The micro light-emitting diode chip as described in claim 1, characterized in that, The passivation layer covers part of the top surface of the light-emitting platform.

8. The miniature light-emitting diode as described in claim 1, characterized in that, The light-emitting platform comprises, in sequence, a first epitaxial layer, a light-emitting layer, and a second epitaxial layer.

9. The miniature light-emitting diode as described in claim 8, characterized in that, The second epitaxial layer is a material layer of the second conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P, and the first conductivity type is different from the second conductivity type.

10. The miniature light-emitting diode as described in claim 1, characterized in that, The light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / Al GaN multi-quantum well layer, or an InGaAs / Al GaAs multi-quantum well layer.

11. The miniature light-emitting diode as described in claim 1, characterized in that, An electron blocking layer is provided on the first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer.

12. A miniature light-emitting diode chip, characterized in that, include: A miniature light-emitting diode chip array, comprising a plurality of miniature light-emitting diodes as described in any one of claims 1 to 11; as well as The driving backplane is bonded to the micro-LED array via a bonding layer.

13. The micro light-emitting diode chip as described in claim 12, characterized in that, The micro LED array includes a continuous top conductive layer disposed above the micro LED array and contacting and covering the top of each light-emitting platform.

14. The micro light-emitting diode chip as described in claim 12, characterized in that, The surface of the drive backplate is provided with a metal layer.

15. The micro light-emitting diode chip as described in claim 14, characterized in that, The drive backplane is provided with a plurality of IC copper pillars, which are electrically connected to the metal layer.

16. The micro light-emitting diode chip as described in claim 15, characterized in that, Each light-emitting mesa in the micro LED array region corresponds to an IC copper pillar.

17. The micro light-emitting diode chip as described in claim 14, characterized in that, The material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.

18. The micro light-emitting diode chip as described in claim 12, characterized in that, A second electrode is provided between adjacent light-emitting platforms.

19. The micro light-emitting diode chip as described in claim 18, characterized in that, The second electrode is a ring-shaped reflective electrode, which is arranged around the light-emitting platform.

20. The micro light-emitting diode chip as described in claim 18, characterized in that, A deep trench is provided between adjacent light-emitting platforms, the deep trench extends through the micro light-emitting diode array, and the second electrode is disposed at the deep trench.

21. The micro light-emitting diode chip as described in claim 20, characterized in that, The second electrode between adjacent light-emitting mesa has at least two peaks.

22. The micro light-emitting diode chip as described in claim 18, characterized in that, The second electrodes are interconnected.

23. The micro light-emitting diode chip as described in claim 15, characterized in that, Also includes: At least one first electrode is electrically connected to the copper pillar of the IC.

24. The micro light-emitting diode chip as described in claim 23, characterized in that, The polarity of the first electrode is opposite to that of the second electrode.

25. The micro light-emitting diode chip as described in claim 12, characterized in that, It also includes a microlens array, which is located above the micro-light-emitting diode array and includes multiple microlenses, wherein at least one microlens is disposed on the surface of the conductive layer on top of the micro-light-emitting diode.

26. The micro light-emitting diode chip as described in claim 12, characterized in that, It also includes a microlens array, which is located above the micro-light-emitting diode array and includes multiple microlenses, each of which corresponds to a light-emitting platform.

27. The micro light-emitting diode chip as described in claim 26, characterized in that, The microlens has an air gap inside.

28. The micro light-emitting diode chip as described in claim 26, characterized in that, Adjacent micro-projection lenses are interconnected, but there is a gap at the connection point.

29. The micro light-emitting diode chip as described in claim 26, characterized in that, The bottoms of adjacent micro-projection lenses are connected to each other.

30. A method for manufacturing a miniature light-emitting diode chip, characterized in that, Including the following steps: Forming a semiconductor light-emitting module; The semiconductor light-emitting module is bonded to the driving backplane; The semiconductor light-emitting module is subjected to step etching to form multiple pixels; A passivation layer is formed on the sidewalls and surface of each pixel, wherein the material of the passivation layer is AlN; A photolithographic etching is performed on the passivation layer above the corresponding pixel to expose at least a portion of the surface at the top of the pixel; A top conductive layer is formed on the surface of the passivation layer; A second electrode is formed at the interval of each pixel; A first electrode is formed on the drive backplate; as well as Deposited microlenses.

31. The manufacturing method as described in claim 30, characterized in that, The steps involved in forming a semiconductor light-emitting module are as follows: A second epitaxial layer, an electron blocking layer, a multilayer quantum well, and a first epitaxial layer are sequentially deposited on the substrate.

32. The manufacturing method as described in claim 30, characterized in that, The step etching process for the semiconductor light-emitting module includes the following steps: The semiconductor light-emitting module is etched to form positive trapezoidal pixel structures.

33. The manufacturing method as described in claim 32, characterized in that, The horizontal angle of the pixels in the trapezoidal structure is 65° to 85°.

34. The manufacturing method as described in claim 30, characterized in that, A passivation layer is formed on the sidewalls and surface of the pixels using an atomic layer deposition process.

35. The manufacturing method as described in claim 30, characterized in that, It also includes the following steps: Deep trench etching is performed at the intervals between each pixel, and the second electrode is disposed at the deep trench.

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