A micro light emitting diode chip
By improving the microlens design and multiple deposition processes, the microlens structure of the micro LED chip was optimized, solving the problem of poor brightness improvement in the existing technology and achieving higher light extraction efficiency and brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JADE BIRD DISPLAY (SHANGHAI) LTD
- Filing Date
- 2024-12-12
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248875A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of light-emitting diode technology, and in particular to a miniature light-emitting diode chip. Background Technology
[0002] Micro light-emitting diode (LED) microdisplay chips are a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. They integrate arrayed micron-sized LED units on an active addressable driver panel to realize the lighting and individual control of the LED units, thereby outputting the desired display image.
[0003] The core structure of a miniature light-emitting diode (LED) is a PN junction diode, which is made of a direct bandgap semiconductor material. When a forward bias voltage is applied to the upper and lower electrodes of the miniature LED, causing current to flow, electrons and holes recombine in the active region, simultaneously emitting single-color photons. To converge and collimate the light, existing miniature LEDs typically incorporate microlenses in the optical path.
[0004] Currently, microlens technology is based on CVD to deposit SiO2 films. Because the actual deposited film thickness varies from 2.5 to 4 μm, high deposition rates are typically used, which makes it prone to deposit defects and microcracks in deep trench areas. Furthermore, in the fabrication of micro-LEDs, after SiO2 deposition, a photoresist of suitable viscosity, such as positive resist, needs to be selected for wafer surface coating. Then, the light-shielding area of the exposure photomask is aligned with the pixel location, followed by exposure to form the microlens lithography pattern. Secondary full exposure and hard film baking processes are then used to improve the photoresist morphology. However, because existing processes struggle to achieve optimal microlens sphere width and height, optimal brightness improvement is difficult to achieve.
[0005] Therefore, there is a need for a solution that can effectively improve the brightness or luminous efficacy of micro LEDs. Summary of the Invention
[0006] To address some or all of the problems of existing technologies, this invention provides a miniature light-emitting diode chip, including...
[0007] A miniature light-emitting diode array region, comprising several miniature light-emitting diodes; and
[0008] A microlens array, located above a micro-light-emitting diode array region and comprising multiple microlenses, wherein at least one microlens is disposed on the surface of a conductive layer on top of the micro-light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro-light-emitting diode.
[0009] Furthermore, the micro-LED array region includes a continuous top conductive layer disposed above the micro-LED array region and contacting and covering the top of each micro-LED.
[0010] Furthermore, the micro light-emitting diode includes a bottom conductive bonding layer, the micro light-emitting diode is disposed on the bottom conductive bonding layer, and the horizontal profile of the bottom conductive bonding layer is greater than or equal to the horizontal profile of the micro light-emitting diode.
[0011] Furthermore, there is a gap between adjacent microlenses and their bottoms are connected to each other.
[0012] Furthermore, the micro LED includes a light-emitting mesa, and the bottom of the gap is lower than the top of the light-emitting mesa of the micro LED.
[0013] Furthermore, the light-emitting platform sequentially includes a first epitaxial layer, a light-emitting layer, and a second epitaxial layer, with the bottom of the gap being lower than the bottom of the light-emitting layer.
[0014] Furthermore, a second electrode is provided between adjacent light-emitting platforms, and the bottom of the gap is located above the second electrode.
[0015] Furthermore, the second electrode between adjacent light-emitting mesa has at least two peaks, and the bottom of the gap is located between the two peaks.
[0016] Furthermore, the second electrodes are interconnected.
[0017] Furthermore, the microlens has an upper curvature portion and a lower spacer portion.
[0018] Furthermore, the curvature centers of the sidewalls of the lower spacer do not coincide with the curvature centers of the upper curvature portion.
[0019] Furthermore, the thickness of the lower spacer is set such that the focal point of the microlens is located in the light-emitting platform of the micro-light-emitting diode.
[0020] Furthermore, the microlens has an air gap inside.
[0021] Furthermore,
[0022] The radius of curvature of the upper curvature portion of the microlens is 1.5 to 2.2 μm; and / or
[0023] The lower spacer of the microlens has a height of 0.2 to 1.6 μm; and / or
[0024] The height of the sphere at the upper curvature of the microlens is 1.2 to 2 μm; and / or
[0025] The spherical width of the microlens is 3 to 4.5 μm.
[0026] Furthermore, the material of the microlens is SiO2.
[0027] Furthermore, the microlens is in the shape of a perfect semicircle.
[0028] Furthermore, the spherical height of the upper curvature portion of the microlens is 1.2 to 2 μm, and the spherical height of the lower spacer portion is 0.2 to 1.8 μm.
[0029] Furthermore, the miniature light-emitting diode also includes:
[0030] A driving backplane has a metal layer on its surface. A plurality of IC copper pillars are disposed on the driving backplane. The IC copper pillars are electrically connected to the metal layer. The micro light-emitting diode array region is bonded to the driving backplane through a bottom conductive bonding layer. The micro light-emitting diode array region includes a plurality of semiconductor light-emitting mesa, each semiconductor light-emitting mesa corresponding to an IC copper pillar. The semiconductor light-emitting mesa includes a first epitaxial layer, a light-emitting layer and a second epitaxial layer deposited sequentially.
[0031] At least one first electrode is electrically connected to the copper pillar of the IC;
[0032] A passivation barrier layer is applied to the surface of the semiconductor light-emitting mesa, but at least a portion of the second epitaxial layer is exposed.
[0033] A continuous top conductive layer is disposed on the surface of the passivation barrier layer and is in electrical contact with the first epitaxial layer; and
[0034] The second electrode is disposed on the surface of the continuous top conductive layer.
[0035] Furthermore, the second electrode is a ring-shaped reflective electrode, which is disposed around the semiconductor light-emitting platform.
[0036] Furthermore, the polarity of the second electrode is opposite to that of the first electrode.
[0037] Furthermore, the material of the second epitaxial layer is a material layer of the second conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type comprising at least two or more elements of Ga, N, As, Al, In, and P; the first conductivity type is different from the second conductivity type.
[0038] Furthermore, the light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an InGaAs / AlGaAs multi-quantum well layer.
[0039] Furthermore, an electron blocking layer is provided on the first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer.
[0040] Furthermore, the material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.
[0041] Furthermore, the material of the passivation barrier layer is a SiO2 film or an Al2O3 film.
[0042] This invention provides a miniature light-emitting diode (LED) chip that improves the microlens by expanding the horizontal profile of the microlens from less than or equal to the maximum horizontal profile of the LED to a size greater than the maximum horizontal profile of the LED. This significantly increases the light-emitting area of the microlens in the horizontal direction, allowing more light emitted from the active layer to pass directly through the microlens without having to be reflected by sidewalls that may absorb light. This significantly improves the light extraction efficiency of the LED. Furthermore, this invention can also adjust the height of the lower spacer, radius of curvature, and lens spherical height by improving the microlens profile, thereby improving micro-defects in the lens and further effectively enhancing the brightness or luminous efficacy of the LED chip. The specific technical effects are as follows: the advantages of increasing the height of the lower gap are particularly: given a fixed radius of curvature, the light source primarily radiates from the top of the pixel. Increasing the radius of curvature and raising the height of the lower gap increases the radius of emitted light, reducing the emission angle between the microlens and the air interface of the same point light source, thus increasing the emission angle. A smaller radius of curvature, i.e., a larger microlens sphere width, is beneficial for light emission. Correspondingly, an increased sphere height, i.e., changing the original hemispherical height of the microlens, also allows escaping light to exit from the microlens. By changing the curvature, the total emission angle of the microlens is increased, making it less prone to total internal reflection, which is beneficial for light emission. Attached Figure Description
[0043] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.
[0044] Figure 1 This diagram illustrates the structure of a micro LED chip in the prior art.
[0045] Figure 2 A schematic front view of a micro light-emitting diode chip in the prior art is shown;
[0046] Figure 3 This diagram illustrates the structure of a miniature light-emitting diode chip according to an embodiment of the present invention.
[0047] Figure 4 A schematic front view of a miniature light-emitting diode chip according to an embodiment of the present invention is shown;
[0048] Figure 5 A schematic diagram of the morphology of a microlens according to an embodiment of the present invention is shown;
[0049] Figure 6 A schematic flowchart illustrating a method for manufacturing a miniature light-emitting diode chip according to an embodiment of the present invention is shown.
[0050] Figures 7A-7J The chip state is shown after each step of the manufacturing method of the micro light-emitting diode chip according to the present invention has been performed; and
[0051] Figures 8A-8D Several embodiments of forming microlenses by multiple depositions according to the present invention are shown. Detailed Implementation
[0052] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
[0053] In this invention, the term "horizontal profile" has the following meanings: for regular shapes, it refers to the horizontal dimension; for irregular shapes, it refers to the maximum horizontal dimension. For example, for a hemispherical microlens, its horizontal profile refers to its bottom diameter; for a cylindrical micro-light-emitting diode, its horizontal profile refers to the diameter of its cylindrical cross-section. The maximum horizontal profile refers to the maximum value of the aforementioned dimension.
[0054] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.
[0055] It should be noted that the embodiments of the present invention describe the process steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the process.
[0056] Currently, the microlens process is mainly based on CVD deposition of SiO2 films. Since the actual deposited film thickness varies from 2.5 to 4 μm, the deposition process typically uses a high deposition rate, which can lead to deposition defects and microcracks in deep trench areas. After deposition, a photoresist of suitable viscosity, such as a positive resist, is applied to the wafer surface. The light-shielding area of the photomask is then aligned with the pixel location, followed by exposure to form the microlens lithography pattern. A second full exposure and hard film baking are then performed to improve the photoresist morphology, causing it to shrink due to its photosensitivity and thermal properties, forming a hemispherical morphology. This completes the photolithography process. Subsequent ICP dry etching, a chemical etching-dominated ion etching process, is then performed. Based on the hemispherical morphology, a specific SiO2 etching time is set according to the actual deposited SiO2 thickness to obtain the remaining etching allowance. This results in a microlens-like structure. Figure 1 The microlens appearance is shown. Since the etching rate of SiO2 is relatively stable and highly controllable, the desired etching depth can be achieved by setting the etching time. The position of the microlens is photolithographically formed, creating a hemispherical SiO2 morphology. The sphere height refers to the height of the hemispherical SiO2, which is generally between 1.5 and 1.8 μm. Similarly, the sphere width is the diameter of the arc-shaped hemispherical shape. The distance from the sphere height to the top of the pixel is the height of the lower spacer. The radius of curvature can be considered as the curvature of the SiO2 hemispherical curve. The larger the radius of curvature, the larger the circle it represents, and the flatter the curve; the smaller the radius of curvature, the smaller the circle it represents, and the more curved the curve, and the greater the curvature.
[0057] However, through data simulation and multiple experimental verifications, the inventors discovered that a smaller radius of curvature, i.e., a larger microlens sphere width, is beneficial for light emission. Correspondingly, an increased sphere height, i.e., changing the original hemispherical height of the microlens, also allows escaping light to exit from the microlens. By changing the curvature, the total emission angle of the microlens is increased, making it less prone to total internal reflection, which is beneficial for light emission. In addition, to achieve a uniform lithographic pattern, the photoresist is generally not too thick, because the photoresist, as a mask layer, is also consumed during the etching process, and too much or too little etching will not result in a satisfactory microlens sphere height. The optimal effect is achieved when the sphere width and sphere height can form a perfect semicircle, i.e., twice the sphere height equals the sphere width.
[0058] Further research by the inventors revealed that the remaining amount in the lower spacer also affects the light emission effect. For the same sphere height and width, the lower spacer generally does not exceed the sphere height. In the current process, there are micro-gap defects in SiO2 on both sides of the lower spacer, which easily cause diffuse reflection of the light source. If the microlens lithography size is adjusted, this defect can be removed or reduced in the previous microlens etching process. The defect can be repaired by secondary SiO2 deposition.
[0059] In existing processes, etching inevitably results in suboptimal microlens sphere width and height. While these conditions can still improve brightness, the inventors have discovered that secondary deposition can achieve a better brightness enhancement effect.
[0060] Based on this, the present invention provides a micro light-emitting diode chip and its manufacturing method, which forms a microlens by multiple depositions to change the height of the lower spacer, radius of curvature and height of the lens sphere, thereby improving the micro-defects of the lens and effectively enhancing the luminous efficiency of the micro light-emitting diode chip.
[0061] A miniature light-emitting diode (LED) chip includes an integrated circuit (IC) backplane and an array of miniature LEDs. The miniature LED array comprises multiple miniature LEDs. Each miniature LED can form at least a portion of a pixel element on the miniature LED chip.
[0062] In embodiments of the present invention, the size of each micro-LED chip is no more than 1 cm, preferably no more than 20 micrometers. The micro-LED structures are formed in an array within the micro-LED chips, with resolutions such as 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro-LED structures is in the nanometer range, for example, from 20 nm to 100 nm.
[0063] In some embodiments of the present invention, an integrated circuit (IC) backplane may be electrically connected to each micro-light-emitting diode in a micro-light-emitting diode array via separate metal interconnects. In some embodiments, each micro-light-emitting diode may be electrically controlled individually by the IC backplane. In some embodiments, the IC backplane may be electrically connected to the electrodes of the micro-light-emitting diode chip via metal interconnects. In some embodiments, a dielectric layer may be formed in the gaps between the micro-light-emitting diodes. In some embodiments, a dielectric layer may also be formed in the gaps between interconnects.
[0064] In some embodiments of the present invention, each micro-LED in the micro-LED array may include a micrometer-scale emitting mesa structure. In some embodiments, the emitting mesa structure may include, from bottom to top, a first type epitaxial layer, an emitting layer, and a second type epitaxial layer. That is, in the three-layer structure, the first type epitaxial layer is closest to the IC backplane; the emitting layer is located above the first type epitaxial layer and further away from the IC backplane; the second type epitaxial layer is located above the emitting layer and furthest away from the IC backplane. In some embodiments, the emitting layer is formed of multiple stacked quantum well layers, particularly superlattice stacked quantum well layers. Preferably, the superlattice stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers. The main substrate material of the first type epitaxial layer may be, but is not limited to, Ga, N, As, P, In and includes, but is not limited to, waveguide layers, confinement layers, transition layers, and window layers; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers. The primary matrix material of the second type of epitaxial layer may be, but is not limited to, composed of at least two or more elements selected from Ga, N, As, P, In, and Al. Furthermore, the first type of epitaxial layer may, from top to bottom, include, but is not limited to, a confinement layer and a waveguide layer; additionally, in some embodiments, an ohmic contact layer may be formed on the confinement layer.
[0065] In some embodiments, a top conductive layer may be formed on the top surface of the micro-LED array. In some embodiments, the top conductive layer may be shared by all micro-LEDs in the micro-LED array. In some embodiments, the light-emitting layer may include at least one quantum well layer. In some embodiments, the micro-LED array may include a single-layer micro-LED structure. In some embodiments, the micro-LED array may include a multi-layer vertically stacked micro-LED structure.
[0066] In some embodiments, the micro-LED array may include blue micro-LEDs. In some embodiments, the spacing between the micro-LED arrays, i.e., the minimum center-to-center distance between the micro-LEDs, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro-LED chip may be between thousands and millions.
[0067] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.
[0068] Figure 3 A schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 3As shown, the micro-light-emitting diode chip 300 according to the present invention includes a driving backplate 301, a first electrode 302, a second electrode 303, a semiconductor light-emitting mesa 304, a passivation barrier layer 305, a top conductive layer 306, a passivation layer 307, and a microlens 308. The semiconductor light-emitting mesa forms a micro-light-emitting diode array region, and the microlens is disposed above the micro-light-emitting diode array region. At least one microlens is disposed on the surface of the conductive layer on top of the micro-light-emitting diode, forming a microlens array, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-light-emitting diode. The first electrode may be, for example, a P-electrode or an anode electrode, and the second electrode is an electrode with the opposite polarity to the first electrode, such as an N-electrode or a cathode electrode. In one embodiment of the present invention, the first and second electrodes and their connecting components may be made of materials such as graphene, ITO, aluminum-doped zinc oxide (AZO), or fluorine-doped tin oxide (FTO), or any combination of the above materials. In another embodiment of the present invention, the first and second electrodes and their connecting components may be made of non-transparent or transparent conductive materials, such as indium tin oxide (ITO). The semiconductor light-emitting mesa includes a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, and a light-emitting layer 342 sandwiched between the first semiconductor epitaxial layer 341 and the second semiconductor epitaxial layer 343. The light-emitting layer may be, but is not limited to, a multi-quantum-well light-emitting layer. The conductivity types of the first and second semiconductor epitaxial layers are different; for example, the first semiconductor epitaxial layer is N-type and the second semiconductor epitaxial layer is P-type, or vice versa. In this embodiment, the passivation barrier layer 305 covers the sidewall surface and part of the top surface of the semiconductor light-emitting mesa, or it may only cover the sidewall surface of the semiconductor light-emitting mesa, completely exposing the top surface. The top conductive layer 306 covers the exposed surface and sidewall surface of the semiconductor light-emitting mesa, the surface of the passivation barrier layer 305, and the gaps between adjacent semiconductor light-emitting mesas. Preferably, the sidewall surface of the first semiconductor epitaxial layer 341 has a stepped structure. The lateral width of the upper part of the first semiconductor epitaxial layer 341 is greater than the lateral width of the lower part of the first semiconductor epitaxial layer 341. Furthermore, the lateral widths of the light-emitting layer 342 and the second semiconductor epitaxial layer 343 are both smaller than the lateral width of the lower part of the first semiconductor epitaxial layer 341.
[0069] Please continue reading. Figure 3The passivation barrier layer 305 also has a stepped structure due to the aforementioned stepped structure of the first semiconductor epitaxial layer 341; the top conductive layer 306 also has a stepped structure due to the passivation barrier layer 305. The second electrode 303 is located on the top conductive layer 306 between adjacent semiconductor light-emitting mesa surfaces. In some embodiments, the top of the second electrode 303 is higher than the aforementioned stepped structure, and further higher than the light-emitting layer 342. In other embodiments, the second electrode 303 may even be higher than or flush with the top of the second semiconductor epitaxial layer 343.
[0070] Figure 5 A schematic diagram of the morphology of a microlens according to an embodiment of the present invention is shown. For example... Figure 5 As shown, in one embodiment of the present invention, the microlens 501 includes an upper curvature portion 511 and a lower spacer portion 512. In one embodiment of the present invention, the curvature centers of the sidewalls of the lower spacer portion do not coincide with the curvature centers of the upper curvature portion. The thickness of the lower spacer portion is set such that the focal point of the microlens is located in the light-emitting platform of the micro-light-emitting diode. In one embodiment of the present invention, the radius of curvature of the upper curvature portion of the microlens is 1.5 to 2.2 μm, and / or the height of the lower spacer portion of the microlens is 0.2 to 1.6 μm, and / or the spherical height of the upper curvature portion of the microlens is 1.2 to 2 μm, and / or the spherical width of the microlens is 3 to 4.5 μm. It should be noted that the upper curvature portion 511 of the present invention can also have other structures, not limited to a perfect semicircle. In some embodiments, the upper curvature portion 511 includes an upper part and a lower part. The upper part includes a portion of the surface where the central axis of the top of the microlens is located, and the lower part includes the surface of the upper curvature portion 511 near the lower spacer portion 512. The average radius of curvature of the surface of the upper part of the upper curvature portion is smaller than the average radius of curvature of the surface of the lower part of the upper curvature portion. It should be noted that the term "surface" as used here does not include the bottom of the microlens.
[0071] In another embodiment of the invention, the microlens may, for example, be a perfect semicircle. The height of the sphere in the curvature portion of the microlens is 1.2 to 2 μm, and the height of the sphere in the lower spacer portion is 0.2 to 1.8 μm.
[0072] like Figure 5As shown, in one embodiment of the invention, a gap 502 is provided between adjacent microlenses, and their bottoms are connected to each other. In some embodiments of the invention, the bottom 521 of the gap is higher than the top of the semiconductor light-emitting mesa 503. In still other embodiments of the invention, the bottom 521 of the gap is lower than the top of the semiconductor light-emitting mesa 503 and higher than the bottom of the semiconductor light-emitting mesa 503. In yet other embodiments of the invention, the bottom of the gap is located above the second electrode 504. Specifically, as shown, the second electrode between adjacent light-emitting mesa has at least two peaks 541, and the bottom of the gap is located between the two peaks.
[0073] In addition, such as Figure 5 As shown, in one embodiment of the present invention, the microlens may also have an air gap 505 inside. Each lens may have multiple air gaps, and the size and length of each air gap may be the same or different. Furthermore, within the same chip, the number of air gaps and / or the position and / or size of the air gaps in different microlenses may be the same or different. As shown, in some embodiments of the present invention, the air gap 505 is located at the edge of the microlens, specifically, for example, on both sides of the light-emitting platform 503, preferably between the light-emitting platform 503 and the second electrode 504. Also, as shown, in some embodiments of the present invention, the top of the air gap 505 is higher than the top of the light-emitting platform 503, and its bottom may be higher than or lower than the top of the light-emitting platform 503. As shown, in some embodiments of the present invention, the bottom of the air gap 505 is higher than the top of the second electrode 504; in other embodiments, the bottom of the air gap 505 is lower than the top of the second electrode 504. It should be noted that in other embodiments of the present invention, the microlens may also be without an air gap 505.
[0074] like Figure 5As shown, a passivation layer 507 is deposited on the sidewalls of the semiconductor light-emitting mesa 503, covering the sidewall surfaces of the semiconductor light-emitting mesa 503 and the sidewall surfaces of the bottom bonding layers between adjacent semiconductor light-emitting mesas. In some embodiments of the present invention, the passivation layer 507 may also cover part of the top surface of the semiconductor light-emitting mesa 503, specifically, the edge of the top surface of the semiconductor light-emitting mesa 503. The structure of the semiconductor light-emitting mesa 503 is the same as that of 303 described above, with an ohmic contact layer 508 located at the bottom of the semiconductor light-emitting mesa 503. The difference is that the width of the ohmic contact layer 508 is greater than the width of the first semiconductor epitaxial layer of the semiconductor light-emitting mesa 503; a bottom conductive layer 509 is located at the bottom of the ohmic contact layer 508; preferably, the top width of the bottom conductive layer 509 is the same as the bottom width of the ohmic contact layer 508. In other embodiments, the top width of the bottom conductive layer 509 and the bottom width of the ohmic contact layer 508 may not be the same. As shown in the figure, in one embodiment of the present invention, a deep trench is provided at the partition between two adjacent semiconductor light-emitting mesa, the deep trench penetrates the bottom bonding layer, and the second electrode 504 is located on the top conductive layer 506 on the surface of the deep trench.
[0075] In one embodiment of the invention, the microlens 308 is obtained by multiple depositions to form multiple transmission layers, such as a first transmission layer and a second transmission layer, wherein the second transmission layer is configured to include at least one of the following:
[0076] a) Radius of curvature of the microlens. Figure 8A A first embodiment of the present invention, which involves forming a microlens through multiple depositions, is shown, wherein the radius of curvature of the microlens, i.e., the curvature of the hemispherical curve of the microlens, is increased by depositing a second transmission layer 8021 (e.g., a SiO2 layer) on a first transmission layer 8011. The advantage of increasing the radius of curvature is particularly that, in a fixed pixel point light source, the angle at which total internal reflection occurs at the microlens-air interface increases, which is beneficial for increasing the emitted light flux.
[0077] b) Height of the lower spacer of the microlens. The height of the lower spacer is the distance from the height of the sphere to the top of the pixel. Figure 8B A second embodiment of the present invention, which forms a microlens through multiple depositions, is shown, wherein the height of the lower spacer portion of the microlens is increased by depositing a second transmission layer 8022 (e.g., a SiO2 layer) on the first transmission layer 8012. The advantage of increasing the height of the lower spacer portion is particularly that, given a fixed radius of curvature, since the light source primarily emits light from the top of the pixel, increasing the radius of curvature and raising the height of the lower spacer portion increases the emitted light radius, reduces the emission angle between the microlens and the air interface at the same point light source, and thus increases the emitted light angle.
[0078] c) The height of the microlens. Figure 8C A third embodiment of the microlens formation according to the present invention via multiple depositions is shown, wherein the spherical height of the microlens is increased by depositing a second transmission layer 8023 (e.g., a SiO2 layer) on a first transmission layer 8013. The advantages of increasing the spherical height of the microlens are particularly that: both the spherical height and spherical width parameters affect the radius of curvature; furthermore, according to data fitting results, appropriately increasing the spherical height and spherical width on the first transmission layer leads to better light emission; and...
[0079] d) The spherical width of the microlens. Figure 8D A fourth embodiment of the present invention is shown, in which a microlens is formed by multiple depositions, wherein the spherical width of the microlens is increased by depositing a second transmission layer 8024 (e.g., a SiO2 layer) on a first transmission layer 8014.
[0080] It should be noted that, depending on the application scenario, the above-mentioned multiple embodiments can be implemented simultaneously in the same microlens or in different microlenses.
[0081] Back Figure 3 ,like Figure 3As shown, in one embodiment of the present invention, the driving backplate 301 includes a substrate, a driving circuit, and IC copper pillars 311 connected to the driving circuit. The semiconductor light-emitting module 304 is electrically connected to the IC copper pillars 311. The substrate can be a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is approximately 700 micrometers thick. The driving circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device. As shown, the IC copper pillars 311 include a first IC copper pillar and a second IC copper pillar, wherein the first IC copper pillar is electrically connected to a first epitaxial layer of the semiconductor light-emitting module, and the second IC copper pillar is electrically connected to a first electrode 302. As shown, in one embodiment of the present invention, each semiconductor light-emitting module has a common first electrode 302. The driving backplate 301 also has a metal layer 312, through which the semiconductor light-emitting module can be bonded to the surface of the driving panel 301. In one embodiment of the present invention, a transparent conductive layer indium tin oxide (ITO) is disposed on the bottom surface of the semiconductor light-emitting module, i.e., the surface of its first epitaxial layer. A bonding metal stack is formed on the transparent conductive layer by vapor deposition. A bonding metal stack can also be disposed on the front surface of the driving backplate 301. The material of the bonding metal stack can be, for example, an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. The driving backplate of the semiconductor light-emitting module can be bonded, for example, by high-temperature, high-pressure bonding.
[0082] In an embodiment of the present invention, the micro-light-emitting diode chip includes multiple semiconductor light-emitting mesa 304, which can be arranged regularly or irregularly on the driving panel 301 as pixels of the micro-light-emitting diode chip. As shown in the figure, in one embodiment of the present invention, the semiconductor light-emitting mesa 304 includes a first epitaxial layer 341, a light-emitting layer, and a second epitaxial layer 344 deposited sequentially, wherein the light-emitting layer includes a multi-quantum well layer 342 and an electron blocking layer 343. In one embodiment of the present invention, the first epitaxial layer is an N-type GaN layer or an N-type AlGaN layer, and the second epitaxial layer is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second epitaxial layer can be a material layer of a second conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P, and the first epitaxial layer can be a material layer of a first conductivity type containing at least two or more elements of Ga, N, As, Al, In, and P. The multiple quantum well layer is an InGaN / GaN multiple quantum well layer, an InGaN / AlGaN multiple quantum well layer, or an InGaAs / AlGaAs multiple quantum well layer. The electron blocking device 343 is disposed on a first side of the light-emitting layer, where the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment of the invention, the first epitaxial layer may also be a P-type GaN layer or a P-type AlGaN layer, and the second epitaxial layer may be an N-type GaN layer or an N-type AlGaN layer. As shown in the figure, the semiconductor light-emitting mesa 304 is stepped.
[0083] The passivation barrier layer 305 covers the surface and side surfaces of the semiconductor light-emitting mesa 304, but exposes at least a portion of the surface of the second epitaxial layer 344. In one embodiment of the present invention, the passivation barrier layer 305 may be formed by CVD deposition of SiO2 or ALD deposition of Al2O3 film to effectively reduce chip leakage current.
[0084] The top conductive layer 306 is disposed on the surface of the passivation isolation layer and is in electrical contact with the second epitaxial layer, so as to connect the second epitaxial layers of each semiconductor light-emitting mesa 304 in series. It is a transparent conductive layer.
[0085] As shown in the figure, there are gaps between the pixels formed by the various semiconductor light-emitting mesa 304, and deep grooves are provided at the gaps. The second electrode 303 is disposed at the deep groove. In one embodiment of the present invention, the second electrode 303 is a ring-shaped reflective electrode, which is formed by magnetron sputtering or vapor deposition, and its material can be, for example, Al or Al alloy metal for the sidewall reflective mirror, and the electrode stack metal can be Ni, Al, Ti, Ni, Pt, Au, or other metal materials. In an embodiment of the present invention, the various second electrodes are connected to each other.
[0086] As mentioned above, in the embodiments of the present invention, the microlens 308 is formed by multiple depositions. In the process of forming the microlens, a microlens material layer needs to be deposited first. The lens material layer can be a SiO2 film layer, a transparent polymer material, etc., and then ion etching is performed. Therefore, in the embodiments of the present invention, the micro light-emitting diode chip also includes a passivation layer 307 covering the aforementioned structure surface. The microlens 308 is formed on the surface of the passivation layer 307 at the position corresponding to each semiconductor light-emitting module.
[0087] Figure 2 and Figure 4 The diagrams show front views of a conventional micro-LED chip and a micro-LED chip according to an embodiment of the present invention. It can be seen that, compared to conventional micro-LED chips, the microlens spacing between adjacent pixels in this application is smaller, improving the step coverage effect of the microlenses and avoiding micro-gap defects in the microlenses on both sides of the lower spacing portion, thus achieving a better brightness enhancement effect. Furthermore, the microlenses obtained by secondary deposition are approximately semi-circular, exhibiting optimal light extraction performance.
[0088] Figure 6 A schematic flowchart illustrating the manufacturing method of the micro light-emitting diode chip as described above is shown. Figure 6 As shown, a method for manufacturing a miniature light-emitting diode chip includes:
[0089] First, in step 601, as Figure 7A As shown, a semiconductor light-emitting module is provided. A second epitaxial layer 344, an electron blocking layer 343, a multilayer quantum well 342, and a first epitaxial layer 341 are sequentially deposited on a substrate 001. The substrate is then thinned. The ohmic contact of the first epitaxial layer can be, for example, a transparent conductive layer indium tin oxide (ITO). A bonding metal stack 3121 can be formed on the transparent conductive layer, for example, by vapor deposition, to form the semiconductor light-emitting module. In one embodiment of the invention, the substrate can be a Si substrate, a SiC substrate, or a sapphire substrate.
[0090] Next, in step 602, as Figure 7BAs shown, the semiconductor light-emitting module is bonded to a driving backplane. The semiconductor light-emitting module is bonded to the driving backplane 301. The driving backplane includes a driving circuit to provide driving signals to the micro-LED chip and control the switching of pixels. The driving backplane has several IC copper pillars 311, which are electrically interconnected with the semiconductor light-emitting module to control the pixels. Furthermore, the front side of the driving backplane is also deposited with a metal stack, wherein the electrode stack metal can be Cr, Al, Ti, Ni, Pt, Au, Sn, or other metal materials. The semiconductor light-emitting module and the driving backplane are bonded using a high-temperature, high-pressure bonding method. In one embodiment of the invention, after chip bonding, the substrate of the semiconductor light-emitting module can be thinned by grinding or laser lift-off to further thin the buffer layer structure, facilitating subsequent fabrication of the PN step structure.
[0091] Next, in step 603, as Figure 7C As shown, etched steps are formed. The semiconductor light-emitting module is subjected to step etching. By adjusting the photolithographic morphology, it is ion-etched to form positive trapezoidal structure pixels. In one embodiment of the present invention, the horizontal angle of the positive trapezoidal structure pixels can be, for example, 65° to 85°.
[0092] Next, in step 604, as Figure 7D As shown, deep trenches are etched. Further deep trench etching is performed at the intervals between individual pixels, for example, using photolithography and IBE (Inert Gas Physical Etching) processes.
[0093] Next, in step 605, as Figure 7E As shown, a passivation barrier layer is formed. A passivation barrier layer 305 is formed on the sidewalls and surface of each pixel. In one embodiment of the invention, the passivation barrier layer is formed by CVD deposition of a SiO2 film or ALD deposition of an Al2O3 film to reduce chip leakage current. After deposition, photolithography is performed to etch openings above the corresponding pixel to expose at least a portion of the surface of the N-type semiconductor layer.
[0094] Next, in step 606, as Figure 7F As shown, a transparent conductive layer is formed. A top conductive layer 306 is formed on the passivated and isolated surface to achieve shared series connection of the second epitaxial layer for each pixel.
[0095] Next, in step 607, as Figure 7GAs shown, a second electrode is formed. An annular reflective electrode 303 is formed at the deep trench. In one embodiment of the invention, the annular reflective electrode is implemented using magnetron sputtering or vapor deposition. In another embodiment of the invention, the second electrode uses Al or Al alloy metal as the sidewall reflective mirror, and the electrode stack metal uses metal materials such as Ni, Al, Ti, Pt, and Au.
[0096] Next, in step 608, as Figure 7H As shown, a first electrode is formed. A first electrode 302 is formed on the drive backplane. The first electrode is connected to the IC copper pillar, which serves to protect and elevate the IC, and facilitates subsequent wire bonding.
[0097] Next, in step 609, as Figure 7I As shown, the initial deposition of the microlens is performed. SiO2 is deposited, and the photolithographic morphology is adjusted to form the initial microlens. In one embodiment of the present invention, a SiO2 film layer, i.e., the first transmission layer, is deposited by PECVD. The thickness of the film layer is approximately 2.5 to 3.5 μm. Subsequently, by adjusting the photolithographic morphology of the microlens, such as the resist thickness, exposure energy, and hardening temperature, the photolithographic array morphology at the corresponding pixel position is completed. The SiO2 material of the microlens passivation protective layer is ion-etched to form a hemispherical SiO2 microlens with a lens-like morphology, which can improve the light extraction efficiency to a certain extent. At this point, the initial structure of the micro light-emitting diode chip is formed. However, due to the poor step coverage of the SiO2 deposited by PECVD, microcracks are easily formed at the deep trenches of the pixel, causing diffuse reflection of the quantum well light source at this location, reducing the light extraction efficiency of the microlens. In addition, due to the photolithographic size of the microlens and ion etching, the overall radius of curvature, lower spacing height, spherical height, and lens spherical width of the microlens are all relatively small, failing to achieve the optimal conditions for the lens. Therefore, it is necessary to proceed to step 510 for a second deposition.
[0098] Finally, in step 610, as Figure 7JAs shown, a secondary deposition is performed to deposit a second transmission layer. Secondary deposition is performed on the initial structure to increase the microlens radius of curvature, lower spacer height, sphere height, and lens sphere width to form a microlens 308. In one embodiment of the invention, the film thickness of the secondary SiO2 deposition needs to be determined based on the film thickness of the preceding microlens deposition SiO2 and the microlens etching morphology. In one embodiment of the invention, the film thickness of the secondary deposition is preferably between 0.2 and 1 μm, and can be performed in a single or multiple deposition operations. In one embodiment of the invention, the secondary SiO2 deposition uses a mixed gas of SiH4 and N2O, with a SiH4 to N2O ratio of 1:5. Simultaneously, the gas flow rate is controlled at a low level to ensure a deposition rate much lower than that of the preceding microlens deposition. The secondary deposition employs a high-vacuum process and a large flow rate of inert gas N2 to further improve the step coverage effect of the secondary SiO2 deposition, making it less prone to defects and even capable of repairing micro-defects in the preceding microlens deposition, resulting in a better brightness enhancement effect.
[0099] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.
Claims
1. A miniature light-emitting diode chip, characterized in that, include: The miniature light-emitting diode array region includes several miniature light-emitting diodes; as well as A microlens array, located above a micro-light-emitting diode array region and comprising multiple microlenses, wherein at least one microlens is disposed on the surface of a conductive layer on top of the micro-light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro-light-emitting diode.
2. The micro light-emitting diode chip as described in claim 1, characterized in that... The micro LED array region includes a continuous top conductive layer disposed above the micro LED array region and contacting and covering the top of each micro LED.
3. The micro light-emitting diode chip as described in claim 1, characterized in that... The micro light-emitting diode includes a bottom conductive bonding layer, the micro light-emitting diode is disposed on the bottom conductive bonding layer, and the horizontal profile of the bottom conductive bonding layer is greater than or equal to the horizontal profile of the micro light-emitting diode.
4. The micro light-emitting diode chip as described in claim 1, characterized in that... There are gaps between adjacent microlenses and their bottoms are connected to each other.
5. The micro light-emitting diode chip as described in claim 4, characterized in that... The micro LED includes a light-emitting mesa, and the bottom of the gap is lower than the top of the light-emitting mesa of the micro LED.
6. The micro light-emitting diode chip as described in claim 5, characterized in that... The light-emitting platform sequentially includes a first epitaxial layer, a light-emitting layer, and a second epitaxial layer, with the bottom of the gap being lower than the bottom of the light-emitting layer.
7. The micro light-emitting diode chip as described in claim 4, characterized in that... A second electrode is provided between adjacent light-emitting platforms, and the bottom of the gap is located above the second electrode.
8. The micro light-emitting diode chip as described in claim 7, characterized in that... The second electrode between adjacent light-emitting platforms has at least two peaks, and the bottom of the gap is located between the two peaks.
9. The micro light-emitting diode chip as described in claim 7, characterized in that... Each second electrode is interconnected.
10. The micro light-emitting diode chip as described in claim 1, characterized in that, The microlens has an upper curvature portion and a lower spacer portion.
11. The micro light-emitting diode chip as described in claim 10, characterized in that, The curvature centers of the sidewalls of the lower spacer do not coincide with the curvature centers of the upper spacer.
12. The micro light-emitting diode chip as described in claim 10, characterized in that, The thickness of the lower spacer is set such that the focal point of the microlens is located in the light-emitting platform of the micro-light-emitting diode.
13. The micro light-emitting diode chip as described in claim 10, characterized in that, The microlens has an air gap inside.
14. The micro light-emitting diode chip as described in claim 10, characterized in that... , The radius of curvature of the upper curvature portion of the microlens is 1.5 to 2.2 μm; and / or The height of the lower spacer portion of the microlens is 0.2 to 1.6 μm; and / or The height of the sphere at the upper curvature of the microlens is 1.2 to 2 μm; and / or The spherical width of the microlens is 3 to 4.5 μm.
15. The micro light-emitting diode chip as described in claim 1, characterized in that... The material of the microlens is SiO2.
16. The micro light-emitting diode chip as described in claim 1, characterized in that... The microlens is in the shape of a perfect semicircle.
17. The micro light-emitting diode chip as described in claim 10, characterized in that... The spherical height of the upper curvature portion of the microlens is 1.2 to 2 μm, and the spherical height of the lower spacer portion is 0.2 to 1.8 μm.
18. The micro light-emitting diode chip as described in claim 1, characterized in that, Also includes: A driving backplane has a metal layer on its surface. A plurality of IC copper pillars are disposed on the driving backplane. The IC copper pillars are electrically connected to the metal layer. The micro light-emitting diode array region is bonded to the driving backplane through a bottom conductive bonding layer. The micro light-emitting diode array region includes a plurality of semiconductor light-emitting mesa, each semiconductor light-emitting mesa corresponding to an IC copper pillar. The semiconductor light-emitting mesa includes a first epitaxial layer, a light-emitting layer and a second epitaxial layer deposited sequentially. At least one first electrode is electrically connected to the copper pillar of the IC; A passivation barrier layer covers the surface of the semiconductor light-emitting mesa, but exposes at least a portion of the second epitaxial layer; A continuous top conductive layer is disposed on the surface of the passivation barrier layer and is in electrical contact with the first epitaxial layer; as well as The second electrode is disposed on the surface of the continuous top conductive layer.
19. The micro light-emitting diode chip as described in claim 18, characterized in that, The second electrode is a ring-shaped reflective electrode, which is arranged around the semiconductor light-emitting platform.
20. The micro light-emitting diode chip as described in claim 19, characterized in that, The polarity of the second electrode is opposite to that of the first electrode.
21. The micro light-emitting diode chip as described in claim 18, characterized in that, The second epitaxial layer is a material layer of the second conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P, and the first epitaxial layer is a material layer of the first conductivity type, comprising at least two or more elements including Ga, N, As, Al, In, and P; the first conductivity type is different from the second conductivity type.
22. The micro light-emitting diode chip as described in claim 18, characterized in that, The light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an InGaAs / AlGaAs multi-quantum well layer.
23. The micro light-emitting diode chip as described in claim 22, characterized in that, An electron blocking layer is provided on the first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer.
24. The micro light-emitting diode chip as described in claim 18, characterized in that, The material of the metal layer is one or more alloys of the following metals: Ni, Al, Ti, Ni, Pt, Au.
25. The micro light-emitting diode chip as described in claim 18, characterized in that, The material of the passivation barrier layer is a SiO2 film or an Al2O3 film.