Synaptic transistor based on porous heterojunction semiconductor layer and preparation method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2026-01-27
- Publication Date
- 2026-06-19
Smart Images
Figure CN122248892A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a synaptic transistor based on a porous heterojunction semiconductor layer and its fabrication method, belonging to the field of semiconductor device technology. Background Technology
[0002] As artificial intelligence develops towards "low power consumption, high parallelism, and brain-like" architectures, the traditional von Neumann architecture faces the dual challenges of computational bottlenecks and excessive energy consumption. Neuromorphic computing, by simulating the information processing mode of the human brain, has become a core direction for overcoming this predicament. The biological brain, with approximately 10... 11 10 neurons and 10 14 The complex connections of synapses enable efficient perception, memory, and learning functions. The core of this lies in the "plasticity" of synapses—that is, the dynamic change in synaptic weights with the timing and intensity of neural impulses. Therefore, developing electronic devices that can accurately simulate the functions of biological synapses is a crucial prerequisite for constructing neuromorphic computing systems.
[0003] Among numerous synaptic simulation devices, synaptic transistors stand out due to their unique three-terminal structure, which consists of a semiconductor channel layer, a gate dielectric layer, and source / drain / gate electrodes. To simulate a synapse, the gate electrode and channel layer are considered the pre-synaptic and post-synaptic terminals, respectively, while the channel conductivity, modulated by the gate voltage, acts as the synaptic weight. Compared to memristors, these devices, with their additional gate port, achieve synchronous learning—meaning that signal transmission and synaptic weight updates can occur simultaneously. Therefore, synaptic transistors offer greater flexibility in simulating synaptic behavior and demonstrate significant application potential in the field of next-generation advanced neuromorphic electronic devices.
[0004] In the performance optimization of neuromorphic devices, heterojunction structures, due to their unique interface modulation advantages, have become a key technological path to overcome the performance limitations of single-material channels. A heterojunction is an interface region formed by stacking or compositing two or more semiconductor materials with different band structures. Its core value lies in utilizing the band shift of different materials to construct efficient charge transport channels. For example, by controlling the band alignment of a heterojunction, the separation and transfer of interface charges can be significantly promoted, carrier recombination can be suppressed, and the device's response capability to multimodal stimuli such as light and electricity can be expanded. This aligns perfectly with the requirements of synaptic transistors for high charge transfer efficiency and a wide response range.
[0005] Breathing patterning is defined as the process of preparing ordered porous thin films using condensed water droplets as templates. Over the past two decades, this method has been widely used to prepare porous thin films, and the ordered pores formed on the film using this method are called breathing pattern arrays. Compared with other template methods and photolithography techniques commonly used in the preparation of ordered patterns for thin films, the unique advantage of breathing patterning lies in using water droplets as sacrificial templates, and the template can be spontaneously removed without additional cumbersome steps. Furthermore, the water droplets formed by condensation are flexible, and their shape and size can be flexibly controlled, which facilitates precise control of the final pattern. This method is simple to operate, low in cost, and suitable for large-area preparation, opening up a new path for the development of porous thin films. Summary of the Invention
[0006] This invention aims to overcome the technical shortcomings of existing synaptic transistors, such as limited contact area at the planar heterojunction interface, low charge transfer efficiency, and severe carrier recombination. It also addresses the issues of single-material channel functional modes, insufficient precision in synaptic weight control, and complex fabrication processes. The invention provides a synaptic transistor based on a porous heterojunction semiconductor layer and its fabrication method. This device, through the synergistic design of the porous structure and heterojunction, combined with the domain-controlled quantum effect of noble metal doping (i.e., the effect of spatial confinement stabilization of noble metal quantum size), achieves precise control of synaptic weights, multimodal stimulus response, and low-cost, large-area fabrication, making it suitable for demanding applications in neuromorphic computing.
[0007] The technical solution of the present invention is as follows:
[0008] A synaptic transistor based on a porous heterojunction semiconductor layer uses a p-type doped silicon wafer with a SiO2 layer as a substrate. The SiO2 layer is a dielectric layer, and a porous metal oxide layer is disposed on the dielectric layer. A source electrode and a drain electrode are disposed above the metal oxide layer. A noble metal doped organic semiconductor layer is disposed above the metal oxide layer and the source / drain electrode. The source / drain electrode forms an ohmic contact or a Schottky contact with the metal oxide layer and the organic semiconductor layer.
[0009] Preferably, the porous metal oxide layer is an amorphous composite metal oxide.
[0010] Further preferred, the amorphous composite metal oxide material includes one of IGO (indium gallium oxide), ITO (indium tin oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), AZO (aluminum-doped zinc oxide), and GZO (gallium-doped zinc oxide).
[0011] Preferably, the organic material includes one of N2200, DPP-g2T, and P3HT.
[0012] Preferably, the precious metals doped in the organic matter include one of gold, silver, platinum, palladium, rhodium, iridium, osmium, and ruthenium.
[0013] Preferably, the polymer used in the breath mapping method includes one of polyvinyl cinnamate and SEBS.
[0014] Preferably, the dielectric layer is a dielectric layer inherent to the substrate, specifically a silicon dioxide dielectric layer formed by thermal oxidation of the silicon wafer substrate.
[0015] Preferably, the dielectric layer thickness is 100-300 nm.
[0016] Preferably, the thickness of the semiconductor layer is 50–100 nm.
[0017] Preferably, the source electrode and drain electrode materials are one of titanium, aluminum, silver, gold, iron, copper, nickel, cobalt, manganese, cadmium, indium, tin, tungsten, and platinum.
[0018] The effects of different amounts of noble metal doping on the photoresponse performance and synaptic modulation performance of the device vary significantly, and the specific patterns are shown in Table 1.
[0019]
[0020] Table 1
[0021] Note: The doping levels in the table are reference values and can be adjusted according to the type of precious metal and organic semiconductor material.
[0022] A method for fabricating a synaptic transistor based on a porous heterojunction semiconductor layer includes the following steps:
[0023] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0024] ② Prepare a metal oxide precursor solution and use the breath diagram method to prepare a porous layer on the substrate surface;
[0025] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0026] ④ Prepare source and drain electrodes on the porous metal oxide layer to form ohmic or Schottky contacts with the metal oxide layer.
[0027] ⑤ Prepare a noble metal-doped organic semiconductor solution, and fabricate an organic semiconductor layer above the metal oxide and source / drain electrodes to form an ohmic contact or a Schottky contact with the source / drain electrodes.
[0028] Preferably, in step ②, when preparing the respiratory map method, the ambient humidity is between 60%RH and 95%RH during spin coating, with the optimal effect being around 90%RH.
[0029] Furthermore, in step ③, during high-temperature annealing oxidation, the annealing temperature is between 400 ℃ and 600 ℃, with the optimal effect being around 450 ℃.
[0030] Furthermore, in step ④, the source electrode and the drain electrode are prepared by one of the following methods: vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, screen printing, inkjet printing, or spin coating.
[0031] Furthermore, in step ⑤, the organic semiconductor layer is prepared by one of the following methods: spin coating, roll coating, drop coating, embossing, printing, or spray coating.
[0032] The beneficial effects of this invention are as follows:
[0033] I. This invention employs the breath mapping method to prepare porous metal oxide layers. Compared with traditional porous metal oxide thin film preparation processes, it significantly simplifies the preparation process, eliminating the need for complex template removal procedures. Furthermore, by adjusting the ambient humidity, the morphology and pore size distribution of the pores can be precisely controlled, solving the technical pain points of complex porous thin film preparation processes and uneven pore size in existing technologies. At the same time, the breath mapping method is suitable for coating large-area substrates and, combined with solution methods for preparing organic semiconductor layers, greatly reduces the production cost of devices, facilitating large-scale mass production.
[0034] Second, by adjusting the combination of source / drain electrodes and organic semiconductors, this invention can achieve the switching of ohmic and Schottky contacts between the source / drain electrodes and the semiconductor layer, so that the directionality of current transmission produces an asymmetric modulation effect on the conductivity state of the device, thereby simulating the asymmetric signal transmission behavior unique to biological synapses. Its functional characteristics are closer to the information processing law of real biological neural networks.
[0035] Third, this invention expands the contact area between the source / drain electrodes and the metal oxide from "planar two-dimensional" to "three-dimensional" through a porous metal oxide layer, reducing contact resistance and ensuring that the gate voltage is regulated by the change in the conductivity of the channel itself (synaptic weight), rather than the fluctuation of contact resistance, making the change in synaptic weight more precise and repeatable; at the same time, it improves response sensitivity and is suitable for weak signal processing.
[0036] Fourth, this invention increases the contact area at the interface between the organic layer and the metal oxide layer through the porous metal oxide layer, which can increase charge transfer sites, suppress charge recombination, retain more controllable charge carriers, and realize the multi-level weighted regulation unique to biological synapses.
[0037] V. This invention achieves efficient domain control quantum effect by doping noble metals in organic semiconductors, which stabilizes the quantum size of noble metal dopants in organic materials due to the spatial confinement effect of the porous structure; at the same time, by leveraging the resonance between the discrete energy levels of noble metals and surface plasmons, the photoresponse is broadened to the near-infrared region, enhancing the intensity of the photoresponse signal. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of the present invention;
[0039] In the figure: 1-gate electrode, 2-dielectric layer, 3-porous metal oxide, 4-organic semiconductor, 5-source electrode, 6-drain electrode;
[0040] Figure 2 shows the photoresponse comparison curves of porous devices and dense devices (horizontal axis: time (s), vertical axis: relative rate of change of current (ΔI)). d / I d ,%)) Detailed Implementation
[0041] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.
[0042] Example 1
[0043] A synaptic transistor based on a porous heterojunction semiconductor layer, such as Figure 1 The diagram shows a bottom-gate top-contact structure. A p-type doped silicon wafer with a SiO2 layer formed by thermal oxidation on the surface serves as the substrate. The p-type doped silicon is the gate electrode, and SiO2 is the dielectric layer. A porous metal oxide layer is located above the dielectric layer, and a source electrode and a drain electrode are located above the metal oxide layer. An organic semiconductor layer is located above the metal oxide layer and the source / drain electrodes. The source electrode and the drain electrode form ohmic or Schottky contacts with the semiconductor layer, depending on the material.
[0044] like Figure 1 The diagram shows a bottom-gate top-contact structure. The materials and thicknesses of each layer are as follows: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode with a thickness of 100 nm; the drain and source electrodes are aluminum; and the semiconductor layer is porous indium gallium oxide (IGO) and N2200 with a thickness of 80 nm. This structure can be used to realize a synaptic transistor based on a porous heterojunction semiconductor layer with high sensitivity and high stability.
[0045] The fabrication of the above-mentioned synaptic transistor based on a porous heterojunction semiconductor layer includes the following steps:
[0046] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0047] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0048] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0049] ④ A source electrode and a drain electrode are fabricated on a porous metal oxide layer to form an ohmic contact with the semiconductor layer. The source electrode and the drain electrode are fabricated using one of the following methods: vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, screen printing, inkjet printing, or spin coating.
[0050] ⑤ Prepare a gold-doped N2200 solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes. The semiconductor layer is prepared by one of the conventional methods of spin coating, roll coating, drop casting, imprinting, printing, or spraying.
[0051] like Figure 2 As shown, the synaptic transistor based on a porous heterojunction semiconductor layer constructed using the method of this embodiment exhibits a responsivity more than five times that of a conventional synaptic transistor under the same stimulus. This demonstrates that this structure can effectively improve the sensitivity and other response characteristics of the synaptic transistor.
[0052] Example 2
[0053] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are aluminum; and the semiconductor layer is a porous indium gallium oxide (IGO) and DPP-g2T, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0054] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0055] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0056] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0057] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0058] ⑤ Prepare a gold-doped DPP-g2T solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0059] Example 3
[0060] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed. It features a bottom-gate, top-contact structure, as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are aluminum; and the semiconductor layer is a porous indium gallium oxide (IGO) and P3HT, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0061] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0062] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0063] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0064] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0065] ⑤ Prepare a gold-doped P3HT solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0066] Example 4
[0067] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium oxide (IGO) and N2200, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0068] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0069] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0070] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0071] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0072] ⑤ Prepare a gold-doped N2200 solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0073] Example 5
[0074] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed. It features a bottom-gate, top-contact structure, as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium oxide (IGO) and DPP-g2T, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0075] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0076] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0077] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0078] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0079] ⑤ Prepare a gold-doped DPP-g2T solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0080] Example 6
[0081] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium oxide (IGO) and P3HT, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0082] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0083] ② Prepare an indium gallium oxide (IGO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0084] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0085] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0086] ⑤ Prepare a gold-doped P3HT solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0087] Example 7
[0088] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and N2200, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0089] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0090] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0091] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0092] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0093] ⑤ Prepare a gold-doped N2200 solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0094] Example 8
[0095] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and DPP-g2T, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0096] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0097] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0098] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0099] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0100] ⑤ Prepare a gold-doped DPP-g2T solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0101] Example 9
[0102] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain and source electrodes are made of gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and P3HT, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0103] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0104] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0105] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0106] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0107] ⑤ Prepare a gold-doped P3HT solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0108] Example 10
[0109] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed. It features a bottom-gate, top-contact structure, as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain electrode is aluminum; the source electrode is gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and N2200, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0110] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0111] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0112] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0113] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0114] ⑤ Prepare a silver-doped N2200 solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0115] Example 11
[0116] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain electrode is aluminum; the source electrode is gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and DPP-g2T, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0117] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0118] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0119] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0120] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0121] ⑤ Prepare a silver-doped DPP-g2T solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
[0122] Example 12
[0123] A synaptic transistor based on a porous heterojunction semiconductor layer is disclosed, featuring a bottom-gate top-contact structure as shown in Example 1. The difference lies in the materials and thicknesses of each layer: the gate electrode is a p-type doped silicon electrode; the dielectric layer is a SiO2 dielectric layer formed by thermal oxidation of the gate electrode, with a thickness of 100 nm; the drain electrode is aluminum; the source electrode is gold; and the semiconductor layer is a porous indium gallium zinc oxide (IGZO) and P3HT, with a thickness of 80 nm. This structure enables a highly sensitive and stable synaptic transistor based on a porous heterojunction semiconductor layer. The fabrication method is as follows:
[0124] ① The substrate was cleaned using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas.
[0125] ② Prepare an indium gallium zinc oxide (IGZO) precursor solution and use the breath pattern method to prepare a porous layer on the substrate surface;
[0126] ③ A porous metal oxide layer is prepared by high-temperature annealing and oxidation of the porous layer;
[0127] ④ Fabricate source and drain electrodes on a porous metal oxide layer;
[0128] ⑤ Prepare a silver-doped P3HT solution and fabricate an organic semiconductor layer on the metal oxide layer and the source / drain electrodes.
Claims
1. A synaptic transistor based on a porous heterojunction semiconductor layer, characterized by, The device includes a p-type doped silicon wafer with a SiO2 layer as the substrate, wherein the SiO2 layer is the dielectric layer, a porous metal oxide layer is disposed on the dielectric layer, a source electrode and a drain electrode are disposed above the porous metal oxide layer, and a noble metal doped organic semiconductor layer is disposed above the porous metal oxide layer and the source / drain electrode; the body of the p-type doped silicon wafer also serves as the gate electrode, and the porous metal oxide layer and the noble metal doped organic semiconductor layer between the source electrode and the drain electrode constitute a porous heterojunction semiconductor layer and form an enhanced conductive channel, wherein the source electrode / drain electrode respectively forms an ohmic contact or a Schottky contact with the porous heterojunction semiconductor layer.
2. The porous heterojunction semiconductor layer-based synaptic transistor according to claim 1, wherein The porous metal oxide layer is an amorphous composite metal oxide, which includes one of IGO (indium gallium oxide), ITO (indium tin oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), AZO (aluminum-doped zinc oxide), and GZO (gallium-doped zinc oxide).
3. The porous heterojunction semiconductor layer-based synaptic transistor according to claim 1, wherein The organic semiconductor material includes one of N2200, DPP-g2T, and P3HT; the precious metal includes one of gold, silver, ruthenium, rhodium, palladium, osmium, iridium, and platinum.
4. The porous heterojunction semiconductor layer-based synaptic transistor according to claim 1, wherein The dielectric layer is a silicon dioxide dielectric layer formed by thermal oxidation of a p-type doped silicon wafer, and the thickness of the dielectric layer is 100-300 nm.
5. The synaptic transistor based on a porous heterojunction semiconductor layer according to claim 1, characterized in that, The thickness of the porous heterojunction semiconductor layer is 50–100 nm.
6. The synaptic transistor based on a porous heterojunction semiconductor layer according to claim 1, characterized in that, The source electrode and drain electrode are made of one of the following materials: titanium, aluminum, silver, gold, iron, copper, nickel, cobalt, manganese, cadmium, indium, tin, tungsten, and platinum.
7. A method for fabricating a synaptic transistor based on a porous heterojunction semiconductor layer as described in any one of claims 1-6, characterized in that, Includes the following steps: ① The substrate was cleaned sequentially using acetone solution, isopropanol solution and ethanol solution, and then dried with nitrogen gas. ② Prepare a metal oxide precursor solution and use the breath pattern method to prepare a porous layer on the surface of the SiO2 dielectric layer of the substrate. The ambient humidity during the preparation of the breath pattern method is 60%RH-95%RH. ③ The porous layer prepared in step ② is used to prepare a porous metal oxide layer by high-temperature annealing oxidation, with an annealing temperature of 400℃-600℃; ④ Use one of the following methods to prepare source and drain electrodes on a porous metal oxide layer, such as vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, screen printing, inkjet printing or spin coating, so that the source and drain electrodes form ohmic or Schottky contacts with the porous metal oxide layer. ⑤ Prepare a noble metal-doped organic semiconductor solution and use one of the following methods: spin coating, roll coating, drop film, imprinting, printing or spraying to prepare an organic semiconductor layer above the porous metal oxide layer and the source / drain electrodes, so that the source electrode, drain electrode and organic semiconductor layer form ohmic contact or Schottky contact.
8. The method for fabricating a synaptic transistor based on a porous heterojunction semiconductor layer according to claim 7, characterized in that, In step ②, the optimal ambient humidity for preparing the breath diagram method is approximately 90% RH.
9. The method for fabricating a synaptic transistor based on a porous heterojunction semiconductor layer according to claim 7, characterized in that, In step ③, the optimal temperature for high-temperature annealing oxidation is around 450℃.
10. The method for fabricating a synaptic transistor based on a porous heterojunction semiconductor layer according to claim 8, characterized in that, In step ②, the polymer used in the breath chart method is selected from one of polyvinyl cinnamate and SEBS.