Display device, electronic device including the same, and method of providing the same

Abstract

A display device, an electronic device including the display device, and a method of providing the display device are provided. The display device includes: a dam structure defining an anode contact hole in an emitting region, the dam structure having a side surface defining the anode contact hole and a hanging structure in a non-emitting region; a first insulating layer on the dam structure and extending into the anode contact hole to cover the side surface of the dam structure; an anode of a light-emitting element on the first element insulating layer and in the emitting region, the anode including a first conductive layer and a second conductive layer facing each other in the emitting region; an organic anode planarization layer located between the first conductive layer and the second conductive layer in the emitting region; and a second insulating layer covering the edge of the anode and defining an opening overlapping the anode contact hole in the second insulating layer, the second insulating layer contacting the first insulating layer.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0187939, filed on December 17, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, an electronic device using the display device, and a method of manufacturing (or providing) the display device. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel display devices (such as liquid crystal displays, field emission displays, and organic light-emitting diode displays). Among these flat panel display devices, light-emitting display devices include light-emitting elements that enable each pixel of the display panel to emit its own light. Therefore, light-emitting display devices can display images without a backlight unit that provides light to the display panel. Summary of the Invention

[0004] This disclosure provides a display device capable of providing high-resolution images, an electronic device using the display device, and a method of manufacturing (or providing) the display device.

[0005] This disclosure addresses reliability deficiencies in light-emitting elements included in display devices.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0007] In the disclosed embodiments, the display device includes: a substrate including an emitting region and a non-emitting region; a dam structure located on the non-emitting region of the substrate and having a hanging structure; an anode contact hole superimposed on the emitting region and penetrating the dam structure; a first element insulating layer located on the dam structure and superimposed on the anode contact hole to cover a side surface of the dam structure; an anode located on the first element insulating layer and including a first conductive layer and a second conductive layer comprising a metallic material; an anode planarization layer superimposed on the anode contact hole, comprising an organic material and located between the first conductive layer and the second conductive layer; and a second element insulating layer covering the edge of the anode, defining an opening, and contacting the first element insulating layer.

[0008] In an embodiment, the dam structure may include: a first dam layer; a second dam layer located on the first dam layer; and a third dam layer having a tip that protrudes much further toward the non-emission region than the first side surface of the second dam layer, wherein an anode planarization layer is stacked with an anode contact hole to penetrate the first dam layer, the second dam layer, and the third dam layer.

[0009] In an embodiment, the first conductive layer may be spaced apart from the first, second, and third dam layers, and the first element insulating layer is disposed between the first conductive layer and the first, second, and third dam layers.

[0010] In an embodiment, the first conductive layer may include steps in the portion overlapping with the anode contact hole, and the anode planarization layer planarizes the steps formed by the first conductive layer.

[0011] In an embodiment, the display device may include: a first light-emitting layer located on the anode and covering the entire second element insulating layer; a cathode located on the first light-emitting layer; and an auxiliary electrode located on the cathode and contacting the tip of the third diaphragm layer.

[0012] In one embodiment, the auxiliary electrode may contact the first side surface of the second dam layer and, in the portion overlapping with the non-emission region, be spaced apart from the first dam layer in a direction perpendicular to the substrate.

[0013] In an embodiment, the anode planarization layer may contact the first conductive layer and the second conductive layer, and may be completely surrounded by the first conductive layer and the second conductive layer.

[0014] In an embodiment, the second conductive layer may include a first portion that contacts the anode planarization layer and a second portion that contacts the first conductive layer.

[0015] In an embodiment, the first and second conductive layers of the anode may be in contact with each other in the portion overlapping with the non-emissive region, and the anode planarization layer is not overlapping with the non-emissive region.

[0016] In one embodiment, the anodic planarization layer may include a first surface facing the second conductive layer, and the first surface is a curved surface.

[0017] In one embodiment, the first surface may protrude in the direction toward the second conductive layer.

[0018] In one embodiment, the first surface may be recessed in the direction toward the substrate.

[0019] In the disclosed embodiments, a method for manufacturing a display device includes the following steps: forming an anode contact hole that penetrates a dam structure and a first element insulating layer; forming a first conductive layer, an anode planarization layer, and a second conductive layer of the anode; forming a tip of the dam structure after forming a second element insulating layer that defines an opening; and forming a light-emitting layer, a cathode, an auxiliary electrode, and an element inorganic layer on the anode.

[0020] In an embodiment, a portion of the anode planarization layer, which forms the first conductive layer, the anode planarization layer, and the second conductive layer of the anode, can be removed by performing a chemical mechanical polishing (CMP) process. The anode planarization layer includes a first surface that contacts the second conductive layer of the anode, and the first surface includes a surface polished by the CMP process.

[0021] In the disclosed embodiments, the electronic device includes: at least one display device comprising a substrate, the substrate including an emitting region and a non-emitting region; and at least one of a display module, a processor, a memory, and a power module connected to the at least one display device, wherein the at least one display device includes: a dam structure located on the non-emitting region of the substrate and having a hanging structure; an anode contact hole superimposed on the emitting region and penetrating the dam structure; a first element insulating layer located on the dam structure and superimposed on the anode contact hole to cover a side surface of the dam structure; an anode located on the first element insulating layer and including a first conductive layer and a second conductive layer comprising a metallic material; an anode planarization layer superimposed on the anode contact hole, comprising an organic material and located between the first conductive layer and the second conductive layer; and a second element insulating layer covering the edge of the anode, defining an opening, and contacting the first element insulating layer.

[0022] According to embodiments of this disclosure, a high-resolution display device can be provided. Furthermore, reliability deficiencies in light-emitting devices included in the display device can be addressed.

[0023] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become clear to those skilled in the art from the following description. Attached Figure Description

[0024] These and / or other features will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view of a display device according to an embodiment; Figure 2 This is a cross-sectional view of a display device according to an embodiment; Figure 3 This is a plan view of the display layer of the display device according to an embodiment; Figure 4 It is shown Figure 3A magnified plan view of the arrangement of multiple pixels in the display area; Figure 5 It is along Figure 4 A cross-sectional view of an example of the display layer, taken by line A1-A1'; Figure 6 Is with Figure 5 An enlarged cross-sectional view of the display element layer superimposed on the first emission region; Figure 7 yes Figure 6 An enlarged sectional view of region "A" in the image; Figure 8 yes Figure 6 An enlarged cross-sectional view of an embodiment of region "A" in the diagram; Figure 9 yes Figure 6 An enlarged cross-sectional view of an embodiment of region "A" in the diagram; Figure 10 It shows the manufacturing process. Figure 5 A flowchart of the method for displaying the element layer; Figures 11 to 13 It is shown Figure 10 A sectional view of operation S100; Figures 14 to 17 It is shown Figure 10 The sectional view of operation S200; Figures 18 to 21 It is shown Figure 10 The sectional view of the S300 operation; Figures 22 to 25 It is shown Figure 10 The sectional view of the S400 operation; Figure 26 This is a block diagram of an electronic device according to an embodiment; and Figure 27 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0025] The advantages and features of this disclosure, as well as the methods of implementing this disclosure, can be more readily understood by referring to the following detailed description and accompanying drawings of the embodiments. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art, and this disclosure will be defined only by the appended claims.

[0026] It will be understood that when an element or layer is referred to as being associated with another element, such as “on” another element or layer, the element or layer may be directly on the other element or layer, or there may be an intervening element or layer therebetween. Conversely, when an element or layer is referred to as being associated with another element, such as “directly on” another element or layer, there is no intervening element or layer therebetween.

[0027] Throughout this specification, the same reference numerals refer to the same elements. In the disclosed drawings and text, the singular form of reference numerals denoteing elements may also be used to refer to multiple elements. The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments are merely examples, and this disclosure is not limited to the details shown.

[0028] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “an” element following “the” element in a claim includes one element and multiple elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” will not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” or “including” and / or variations thereof are used in this specification, it indicates the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0030] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, the element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, the term “lower” can encompass both “lower” and “upper” orientations depending on the specific orientation of the drawing. Similarly, if the device in one of the drawings is flipped, the element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the terms “below” or “under” can encompass both above and below orientations.

[0031] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation from the stated value, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0033] The embodiments are described herein with reference to a cross-sectional view, which is a schematic representation of an idealized embodiment. Thus, variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shape of the areas shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded (rounded). Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas, nor are they intended to limit the scope of the given claims.

[0034] Features of the various embodiments of this disclosure can be combined or integrated with each other in part or in whole, and can operate and drive each other in various technical ways. Embodiments can be implemented independently of each other, or they can be implemented together in an interdependent relationship.

[0035] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0036] Figure 1 This is a perspective view of the display device 10 according to an embodiment.

[0037] Reference Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices. As another example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays (HMDs).

[0038] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral, having a short side in a first direction DR1 and a long side in a second direction DR2. In the planar view, each corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be rounded to have a predetermined curvature, or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0039] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0040] Display panel 100 (and its layers or components, such as substrate SUB) may include a main region MA and a sub-region SBA, which together provide a flat total planar area of ​​display panel 100. The main region MA may include a display area DDA and a non-display area NDA, whereby the display area DDA includes pixels PX for displaying images (see...). Figure 3 The non-display area NDA is adjacent to the display area DDA (such as being located around the display area DDA in a plan view).

[0041] The display area DDA can emit light from multiple emission areas or multiple openings, which will be described later. For example, the display panel 100 may include pixel circuitry in a circuit layer containing switching elements, an element insulating layer defining the emission area or opening, and a self-emissive element. For example, the self-emissive element may include, but is not limited to, at least one of an organic light-emitting diode (OLED) containing an organic light-emitting layer, a quantum dot OLED containing a quantum dot emitting layer, an inorganic OLED containing an inorganic semiconductor, and a micro OLED. The following figures illustrate the case where the self-emissive element is an organic light-emitting diode.

[0042] The non-display area NDA can be an area outside the display area DDA. The non-display area NDA can be defined as an edge area of ​​the main area MA of the display panel 100, such as one closer to the outer edge of the display device 10. The non-display area NDA can be in the main area MA, but is not limited thereto.

[0043] The sub-region SBA can extend from one side of the main region MA. The sub-region SBA can include a flexible material that can be bent, folded, rolled, etc. For example, when the display device 10 is bent at the sub-region SBA, the sub-region SBA can be stacked on the main region MA in the thickness direction (e.g., third-direction DR3) (or along the thickness direction (e.g., third-direction DR3)). The sub-region SBA can include a display driver 200 and pad units connected to the circuit board 300. In embodiments, the sub-region SBA can be omitted, and the display driver 200 and pad units can be located in the non-display area NDA.

[0044] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can be formed (or configured) as an integrated circuit and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be located in a sub-region SBA and can be stacked with the main region MA in the thickness direction by bending the display panel 100 at the sub-region SBA. As another example, the display driver 200 can be mounted on a circuit board 300.

[0045] The circuit board 300 can be attached to the pad unit of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0046] Touch driver 400 can be mounted on circuit board 300. Touch driver 400 can be connected to touch sensor layer TSL (see [link to TSL]) for sensing touch as external input. Figure 2 And drive the touch sensor layer TSL.

[0047] Figure 2 This is a cross-sectional view of the display device 10 according to an embodiment.

[0048] Reference Figure 2 The display panel 100 may include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL may include a substrate SUB, a transistor layer TFTL, a display element layer EML, and an encapsulation layer such as a thin-film encapsulation layer TFEL.

[0049] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, rolled, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but the embodiments are not limited thereto. In the embodiments, the substrate SUB can include glass or metal materials.

[0050] The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL can be located in the portion superimposed with the display area DDA, the non-display area NDA, and the sub-area SBA. The transistor layer TFTL may include multiple transistor TFTs (see...). Figure 5 ).

[0051] The display element layer (EML) may be located on the transistor layer (TFTL). The display element layer (EML) may be located in the portion superimposed with the display area (DDA). The display element layer (EML) may include, but is not limited to, at least one of organic light-emitting diodes (OLEDs) containing an organic light-emitting layer, quantum dot light-emitting diodes (LEDs) containing a quantum dot light-emitting layer, inorganic light-emitting diodes (LEDs) containing inorganic semiconductors, and micro LEDs.

[0052] A thin-film encapsulation layer (TFEL) may be located on the display element layer (EML). The TFEL may be located in the portion overlapping the display area (DDA) and the non-display area (NDA). The TFEL may cover the top and side surfaces of the display element layer (EML) and protect it from external oxygen and moisture. The TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the display element layer (EML). According to an embodiment, the TFEL may be omitted.

[0053] The touch sensor layer (TSL) can be located on the thin-film encapsulation layer (TFEL). The touch sensor layer (TSL) can be located in the portion superimposed with the display area (DDA) and the non-display area (NDA). The touch sensor layer (TSL) can sense external input (such as a user's touch) using mutual capacitance or self-capacitance. According to an embodiment, the touch sensor layer (TSL) can be omitted.

[0054] The color filter layer CFL can be located on the touch sensor layer TSL. The color filter layer CFL can be located in the portion superimposed with the display area DDA and the non-display area NDA. The color filter layer CFL can absorb a portion of the light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer CFL can prevent color distortion caused by the reflection of external light.

[0055] Since the color filter layer CFL is directly disposed on the touch sensor layer TSL, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small. According to an embodiment, the color filter layer CFL can be omitted.

[0056] like Figure 2 As shown, the portion of the display panel 100 that overlaps with the sub-region SBA can be bent. When the portion of the display panel 100 is bent at the sub-region SBA, the display driver 200, the circuit board 300, and the touch driver 400 can be overlapped with the main region MA on the third-party DR3.

[0057] When the portion of the display panel 100 is bent, the bending protection layer BPL can protect the structure or layer located below it and superimposed with the sub-region SBA from bending stress.

[0058] Figure 3 This is a plan view of the display layer DPL of the display device 10 according to an embodiment.

[0059] Reference Figure 3 In the portion superimposed with the display area DDA, the display layer DPL may include multiple pixels PX (including multiple pixels PX), multiple power lines VL, multiple scan lines SL (including multiple scan lines SL), multiple emission control lines EDL (including multiple emission control lines EDL), and multiple data lines DL (including multiple data lines DL connected to the pixels PX).

[0060] Scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. Scan lines SL can be arranged along the second direction DR2. Scan lines SL can sequentially supply scan signals to pixels PX.

[0061] The transmit control lines EDL can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The transmit control lines EDL can be arranged along the second direction DR2. The transmit control lines EDL can sequentially supply transmit signals to pixels PX.

[0062] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to pixel PX. The data voltage determines the brightness of pixel PX.

[0063] The power line VL may include a main power line VL1 and a sub-power line VL2. At least one of a first power supply voltage (high potential voltage) and a second power supply voltage (low potential voltage) can be transmitted to the sub-power line VL2 through the main power line VL1, which is superimposed on the non-display area NDA. The main power line VL1 and the sub-power line VL2 may be collectively referred to as power line VL.

[0064] In a plan view (e.g., a view along the third direction DR3), the non-display area NDA may surround the display area DDA. The non-display area NDA may include a scan driver 211 and a transmit control driver 213.

[0065] The scan driver 211 can be located outside the display area DDA or on the non-display area NDA. The scan driver 211 may include multiple drive transistors that generate gate signals based on gate control signals.

[0066] The emit control driver 213 can be located outside the display area DDA or on the non-display area NDA. The emit control driver 213 may include multiple emit control transistors that generate emit signals based on emit control signals.

[0067] The display layer DPL included in the embodiment may include a display driver 200 and multiple pad electrodes PD (including multiple pad electrodes PD) in the portion superimposed with the sub-region SBA. The pad electrodes PD may be spaced apart from each other in the first direction DR1 and may be connected to different signal lines respectively.

[0068] Figure 4 It is shown Figure 3 A magnified plan view of the arrangement of multiple pixels PX in the display area DDA.

[0069] Reference Figure 4 Each of the pixels PX in the embodiment may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 located in the portion overlapping with the display area DDA. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be spaced apart from each other.

[0070] Pixel PX may include an emission region EA. The emission region EA may be a portion or planar region from which light is emitted. For example, first sub-pixel SP1 may include a first emission region EA1, second sub-pixel SP2 may include a second emission region EA2, and third sub-pixel SP3 may include a third emission region EA3.

[0071] In this embodiment, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can emit light of different colors. For example, the first emission region EA1 can emit red light, the second emission region EA2 can emit green light, and the third emission region EA3 can emit blue light. However, the embodiment is not limited to this. According to the embodiment, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can also emit light of the same color.

[0072] In an embodiment, the emission region EA may be defined by an opening OP. The opening OP may be defined by a component insulating layer PDL (see [link to embodiment]). Figure 5 )limited.

[0073] In a plan view, the anode contact hole ACTH can be located in the portion overlapping with the emission region EA. In other words, in a plan view, the anode contact hole ACTH can be located in the portion overlapping with the opening OP. The anode contact hole ACTH will be described later.

[0074] The display device 10 of the embodiment may include a non-emissive region NLA in the portion superimposed with the display area DDA. The non-emissive region NLA can prevent color mixing of light emitted from the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0075] The dam structure BN can be located in the portion superimposed with the non-emitting region NLA. The dam structure BN can surround the opening OP or the anode contact hole ACTH.

[0076] Figure 5 It is along Figure 4 The example cross-sectional view of the display layer DPL, cut by line A1-A1'. Figure 6 Is with Figure 5 An enlarged cross-sectional view of the display element layer EML stacked in the first emission region EA1. Figure 5 The cross-sectional structure of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 in the portion superimposed with the display area DDA of the display device 10 is shown.

[0077] Reference Figure 5 and Figure 6The transistor layer TFTL can be located on the substrate SUB. The transistor layer TFTL may include a first buffer layer BF1, multiple bottom metal layers BML (including multiple bottom metal layers BML), a second buffer layer BF2, multiple transistor TFTs (including multiple transistor TFTs), a gate insulating layer GI, a first insulating layer ILD1, multiple capacitor electrodes CPE (including multiple capacitor electrodes CPE), a second insulating layer ILD2, multiple first connection electrodes CNE1 (including multiple first connection electrodes CNE1), a first via layer VIA1, multiple second connection electrodes CNE2 (including multiple second connection electrodes CNE2), a second via layer VIA2, and a third insulating layer ILD3.

[0078] The first buffer layer BF1 may be located on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that can prevent the penetration of air or moisture. For example, the first buffer layer BF1 may include multiple inorganic layers that are stacked alternately.

[0079] The bottom metal layer BML may be located on the first buffer layer BF1. The bottom metal layer BML may include a conductive metal and may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0080] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer that can prevent air or moisture penetration. For example, the second buffer layer BF2 may include multiple inorganic layers stacked alternately.

[0081] Transistor TFTs can be disposed on the second buffer layer BF2. Transistor TFTs can form pixel circuits. For example, each of the transistor TFTs can be a driving transistor or a switching transistor of a pixel circuit (e.g., a pixel circuit in a circuit layer).

[0082] Each of the transistor TFTs may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0083] The active layer ACT can be located on the second buffer layer BF2. The active layer ACT can be stacked on the third-direction DR3 with the gate electrode GE and can be insulated from the gate electrode GE through the gate insulating layer GI. The source electrode SE and the drain electrode DE can be formed (or set) by making a portion of the active layer ACT conductive (e.g., electrically conductive).

[0084] The gate insulating layer GI can be located on the active layer ACT. The gate insulating layer GI can cover the active layer ACT and the second buffer layer BF2, and can insulate the active layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0085] The gate electrode GE can be located on the gate insulating layer GI. The gate electrode GE can be stacked with the active layer ACT, and the gate insulating layer GI is placed between the gate electrode GE and the active layer ACT.

[0086] The gate electrode GE may include a conductive metal and may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0087] The first insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second insulating layer ILD2.

[0088] The capacitor electrode CPE may be located on the first insulating layer ILD1. The capacitor electrode CPE may be stacked on the third-direction DR3 with the gate electrode GE. The capacitor electrode CPE and the gate electrode GE may form a capacitor (e.g., a capacitor may be formed between the capacitor electrode CPE and the gate electrode GE).

[0089] The second insulating layer ILD2 may cover the capacitor electrode CPE and the first insulating layer ILD1. The second insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second insulating layer ILD2 may be connected to the contact hole of the first insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0090] The first connection electrode CNE1 can be located on the second insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into (or through) a contact hole formed in the first insulating layer ILD1, the second insulating layer ILD2, and the gate insulating layer GI to contact the drain electrode DE of the transistor TFT. When contact is made, the components can form an interface therebetween.

[0091] A first via layer VIA1 may be located on the first connecting electrode CNE1 and the second insulating layer ILD2. The first via layer VIA1 can planarize the underlying structure, that is, planarize the underlying stacked structure to provide a flat upper surface. The first via layer VIA1 may include a contact hole through which the second connecting electrode CNE2 passes.

[0092] The first via layer VIA1 may include an organic insulating material. For example, the first via layer VIA1 may include acrylic resin, polyimide, polyamide, benzocyclobutene, or phenolic resin.

[0093] The second connection electrode CNE2 may be located on the first via layer VIA1. The second connection electrode CNE2 may be located in the portion overlapping with the emitter region EA. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer VIA1 to contact the first connection electrode CNE1.

[0094] The second via layer VIA2 can be located on the first via layer VIA1. The second via layer VIA2 can flatten the step formed by the cross-sectional shape of the second connecting electrode CNE2.

[0095] The second via layer VIA2 may include organic materials. For example, the second via layer VIA2 may include acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, or phenolic resin.

[0096] The third insulating layer ILD3 can be located on the second via layer VIA2. The third insulating layer ILD3 can help prevent gases released by the organic material of the second via layer VIA2 from permeating into the display element layer EML.

[0097] The third insulating layer ILD3 may include an inorganic insulating material. For example, the third insulating layer ILD3 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0098] The display element layer (EML) can be disposed on the transistor layer (TFTL). The display element layer (EML) may include a barrier structure (BN), an insulating layer (PDL), a light-emitting element (ED), an anode planarization layer (APL), and an inorganic layer (IO).

[0099] The dam structure BN can be disposed on the third insulating layer ILD3. The dam structure BN can be located in the portion that overlaps with or is adjacent to the emitter region EA and / or the opening OP and / or the anode contact hole ACTH.

[0100] The dam structure BN can help to position the first light-emitting element ED1 to the third light-emitting element ED3 in the portion superimposed with the first emission region EA1 to the third emission region EA3, and can help to electrically connect the cathodes CE located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other.

[0101] The dike structure BN may include a first dike layer BN1, a second dike layer BN2, and a third dike layer BN3. The first dike layer BN1, the second dike layer BN2, and the third dike layer BN3 may be stacked sequentially on a third-direction DR3. The patterns of the individual dike layers may be combined to form a dike with dike layers.

[0102] The first dam layer BN1 may be located on the third insulating layer ILD3. The first dam layer BN1 may cover the third insulating layer ILD3 in the portion that overlaps or is adjacent to the emitting region EA and in the portion that overlaps with the non-emitting region NLA.

[0103] The first diaphragm layer BN1 can facilitate the application of a low potential voltage to the cathode CE. The first diaphragm layer BN1 may include a conductive metal with etch resistance. For example, the first diaphragm layer BN1 may include titanium (Ti).

[0104] The first dam layer BN1 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the material (or solid portion) of the first dam layer BN1 can surround the anode contact hole ACTH and can be formed in the form of a single conductive pattern surrounding the anode contact hole ACTH. The pattern of the first dam layer BN1 can be a discrete pattern in a planar view, but is not limited to this.

[0105] The second dam layer BN2 can be located on top of the first dam layer BN1 to contact the first dam layer BN1. The second dam layer BN2 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the second dam layer BN2 can surround the anode contact hole ACTH.

[0106] The second embankment layer BN2 can be formed into multiple blocks, and the blocks of the second embankment layer BN2 can be spaced apart from each other in the first direction DR1. In other words, the blocks of the second embankment layer BN2 can be located in portions that are superimposed or adjacent to the first emission region EA1 to the third emission region EA3, and can be spaced apart from each other in the form of islands (or discrete patterns).

[0107] The second dike layer BN2 can facilitate the electrical connection of the first dike layer BN1 to the third dike layer BN3. In other words, the second dike layer BN2 can be electrically connected to both the first dike layer BN1 and the third dike layer BN3. Therefore, the second dike layer BN2 located in the portion overlapping or adjacent to the first transmission region EA1, the second dike layer BN2 located in the portion overlapping or adjacent to the second transmission region EA2, and the second dike layer BN2 located in the portion overlapping or adjacent to the third transmission region EA3 can be electrically connected to each other through the first dike layer BN1 extending between the two transmission regions.

[0108] The second dam layer BN2 may include a metal with high electrical conductivity. For example, the second dam layer BN2 may include aluminum (Al).

[0109] The third dam layer BN3 can be located on top of the second dam layer BN2 to contact the second dam layer BN2. The third dam layer BN3 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emission region EA. In other words, the third dam layer BN3 can surround the anode contact hole ACTH.

[0110] The third dam layer BN3 can be formed into multiple blocks, and the blocks of the third dam layer BN3 can be spaced apart from each other in the first direction DR1. In other words, the blocks of the third dam layer BN3 can be located in portions that are superimposed or adjacent to the first emission region EA1 to the third emission region EA3, and can be spaced apart from each other in the form of islands.

[0111] The third diaphragm layer BN3 may include an etch-resistant conductive metal. For example, the third diaphragm layer BN3 may be titanium (Ti).

[0112] In this embodiment, the third dike layer BN3 located in the portion overlapping or adjacent to the first transmission region EA1, the third dike layer BN3 located in the portion overlapping or adjacent to the second transmission region EA2, and the third dike layer BN3 located in the portion overlapping or adjacent to the third transmission region EA3 can be electrically connected through the second dike layer BN2 and the first dike layer BN1. Redundant descriptions will be omitted.

[0113] First dam layers BN1 to third dam layers BN3 may jointly define a dam at the non-emission region NLA. The dam layers may together define a dam opening corresponding to the respective emission region, and the dam opening may overlap with the corresponding anode contact hole ACTH. The inner surfaces (or sidewalls) of the first dam layers BN1 to third dam layers BN3 may define the thickness portion of the dam opening along the thickness direction. The dam (e.g., dam structure BN) may define a dam layer together with the dam opening. The dam at the non-emission region NLA may have a dam recess defined therein, wherein the first dam layer BN1 extending across the non-emission region NLA may provide the bottom of the dam recess.

[0114] like Figure 6As shown, the second dam layer BN2 may include a first side surface 2c, which serves as the outer surface facing the non-emitting region NLA, and the third dam layer BN3 may include a tip that protrudes significantly (e.g., far beyond) from the first side surface 2c of the second dam layer BN2 in the first direction DR1. Therefore, the first side surface 2c of the second dam layer BN2 and the tip of the third dam layer BN3 can form an undercut, and the dam structure BN can have an overhang structure.

[0115] In the display device 10 of this embodiment, since the embankment structure BN includes a tip, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, which are spaced apart from each other, can be formed in the manufacturing process without using a fine metal mask. The manufacturing process will be described later.

[0116] The component insulating layer PDL may include a first component insulating layer PDL1 and a second component insulating layer PDL2.

[0117] The first element insulating layer PDL1 may be located on the third dam layer BN3. The first element insulating layer PDL1 may cover the third dam layer BN3 and may be stacked on the tip of the third dam layer BN3 on the third directional DR3.

[0118] The first element insulating layer PDL1 can be penetrated by the anode contact hole ACTH in the portion overlapping with the emitter region EA. In other words, the first element insulating layer PDL1 can surround the anode contact hole ACTH.

[0119] The first element insulating layer PDL1 can separate and insulate the dam structure BN from the anode AE, preventing them from contacting each other. Therefore, the first element insulating layer PDL1 can completely cover the inner surface of the dam structure BN facing the anode contact hole ACTH. Thus, the first element insulating layer PDL1 can resolve the short-circuit defect in the display device 10 caused by contact between the anode AE ​​and the dam structure BN.

[0120] The first element insulating layer PDL1 may include an inorganic insulating material. For example, the first element insulating layer PDL1 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0121] The second element insulating layer PDL2 may be located on the first element insulating layer PDL1. Between the first element insulating layer PDL1 and the second element insulating layer PDL2, the second element insulating layer PDL2 may define an opening OP and expose the anode AE ​​in the portion overlapping with the opening OP. In other words, the second element insulating layer PDL2 may surround the opening OP and cover the edge of the anode AE.

[0122] The second element insulating layer PDL2 may include an inorganic insulating material. For example, the second element insulating layer PDL2 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0123] First element insulating layer PDL1 and second element insulating layer PDL2 may jointly define a pixel defining pattern at a non-emitting region NLA. The element insulating layers PDL may together define a pixel opening (e.g., opening OP) corresponding to a respective emitting region, and the pixel opening may overlap with a corresponding anode contact hole ACTH. The inner surfaces (or sidewalls) of the first element insulating layer PDL1 and second element insulating layer PDL2 may define a thickness portion of the pixel opening along the thickness direction. The pixel defining pattern, together with the pixel opening, may define an element insulating layer PDL serving as a pixel defining layer. First element insulating layer PDL1 and second element insulating layer PDL2 may together define an element insulating layer recess that opens laterally (e.g., along a first direction DR1) toward a respective emitting region EA.

[0124] In this embodiment, the light-emitting element (ED) can be located on the embankment structure BN. The ED can be stacked on the third-direction DR3 with the embankment structure BN and the element insulating layer PDL. Alternatively, the ED can be stacked on the third-direction DR3 with the anode contact hole ACTH.

[0125] The display device 10 of the embodiment can be applied to high-resolution electronic devices. Therefore, a plurality of light-emitting elements ED included in the display device 10 may need to be arranged within a narrow region (e.g., a narrow planar region) with appropriate spacing between them. Therefore, in the display device 10 of the embodiment, the light-emitting elements ED can be formed on the embankment structure BN, so that the light-emitting elements ED can be effectively arranged within the narrow region.

[0126] The light-emitting element ED may include a first light-emitting element ED1 disposed in a first emission region EA1, a second light-emitting element ED2 disposed in a second emission region EA2, and a third light-emitting element ED3 disposed in a third emission region EA3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be spaced apart from each other.

[0127] The first light-emitting element ED1 may include an anode AE, a first light-emitting layer EL1, a cathode CE, and an auxiliary electrode AX. The second light-emitting element ED2 may include an anode AE, a second light-emitting layer EL2, a cathode CE, and an auxiliary electrode AX. The third light-emitting element ED3 may include an anode AE, a third light-emitting layer EL3, a cathode CE, and an auxiliary electrode AX.

[0128] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit light of different colors. For example, the first light-emitting element ED1 can emit red light, the second light-emitting element ED2 can emit green light, and the third light-emitting element ED3 can emit blue light. The color of the light emitted from the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can be determined by the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3.

[0129] In an embodiment, the anode contact hole ACTH may be located in the portion overlapping with the emitter region EA. The anode contact hole ACTH may be formed to penetrate the third insulating layer ILD3, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3. The anode contact hole ACTH may include a third insulating layer contact hole defined in the third insulating layer ILD3, as well as dam openings in the dam layers and pixel openings in the element insulating layer PDL. The anode contact hole ACTH may expose the second connection electrode CNE2 to the outside of each of the third insulating layer ILD3 and the dam structure BN.

[0130] In the display device 10 of this embodiment, the anode contact hole ACTH may not be formed in a separate space, but rather superimposed on the emitter region EA, such that the contact area where the anode AE ​​is electrically connected to the transistor layer TFTL is integrated within the emitter region EA. Therefore, in the display device 10 of this embodiment, multiple emitter regions EA can be effectively arranged within a narrow area.

[0131] The anode AE ​​can be located on the first element insulating layer PDL1. The anode AE ​​can be located in the portion overlapping with the emission region EA and / or the opening OP and / or the anode contact hole ACTH.

[0132] Each of the anodes AE may include a first conductive layer AEa and a second conductive layer AEb. The first conductive layer AEa and the second conductive layer AEb may be sequentially stacked on the third-direction DR3.

[0133] The first conductive layer AEa can be located on the first element insulating layer PDL1. The first conductive layer AEa can contact and cover the first element insulating layer PDL1, and can extend through the dam opening and the third insulating layer contact hole to contact the second connection electrode CNE2 of the transistor layer TFTL. In other words, in the portion superimposed with each anode contact hole ACTH, the first conductive layer AEa can completely cover the exposed portions of the first element insulating layer PDL1 and the third insulating layer ILD3, and can extend to contact the second connection electrode CNE2. Therefore, the first conductive layer AEa can be electrically connected to the second connection electrode CNE2.

[0134] The first conductive layer AEa can cover the first element insulating layer PDL1, the third insulating layer ILD3, and the second connecting electrode CNE2 with a uniform thickness along the contour formed by the first element insulating layer PDL1, the third insulating layer ILD3, and the second connecting electrode CNE2. Here, the thickness is defined as perpendicular to the respective surfaces of the first element insulating layer PDL1, the third insulating layer ILD3, and the second connecting electrode CNE2. Therefore, the first conductive layer AEa may include steps having the same shape as the structure underneath. The aforementioned uniform thickness can include a process tolerance of about 10% or less.

[0135] The first conductive layer AEa may include a transparent conductive oxide (TCO). For example, the first conductive layer AEa may include at least one of indium zinc oxide (IZO) and indium tin oxide (ITO).

[0136] The second conductive layer AEb may be located on the first conductive layer AEa. The second conductive layer AEb may contact a portion of the first conductive layer AEa. Therefore, the first conductive layer AEa and the second conductive layer AEb may be electrically connected. The second conductive layer AEb may be exposed outside the element insulating layer PDL in the portion overlapping with each opening OP. The second conductive layer AEb may contact the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 in the portion overlapping with each opening OP. The edges of the second conductive layer AEb that are not overlapping with each opening OP may be covered by the solid portion of the second element insulating layer PDL2.

[0137] The second conductive layer AEb can have a stacked structure of material layers with high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3)) and reflective material layers (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), or mixtures thereof). For example, the second conductive layer AEb can have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, or ITO / Ag / ITO.

[0138] In the manufacturing process of the display device 10, the first conductive layer AEa and the second conductive layer AEb can be formed in different processes. Therefore, a boundary surface (or interface) can be formed between the facing surfaces of the first conductive layer AEa and the second conductive layer AEb. As can be seen from the boundary surface between the facing surfaces of the first conductive layer AEa and the second conductive layer AEb formed in the display device 10 of the embodiment, the first conductive layer AEa and the second conductive layer AEb are formed in different processes.

[0139] The anode planarization layer APL may be located between the first conductive layer AEa and the second conductive layer AEb. The anode planarization layer APL may contact the first conductive layer AEa and the second conductive layer AEb. The anode planarization layer APL may be completely surrounded (or enclosed) by the first conductive layer AEa and the second conductive layer AEb in the portion overlapping with each anode contact hole ACTH. The first conductive layer AEa may have an anode recess therein defining the anode planarization layer APL, and the anode planarization layer APL may fill the anode recess, but is not limited thereto. The second conductive layer AEb may be spaced apart from the first conductive layer AEa in the emission region EA. The second conductive layer AEb may be spaced apart from the first conductive layer AEa through a gap in which the anode planarization layer APL is disposed.

[0140] The anode planarization layer APL can planarize the steps included in the first conductive layer AEa in the portion stacked with each anode contact hole ACTH. Here, the upper surfaces of the anode planarization layer APL and the first conductive layer AEa, which are furthest from the transistor layer TFTL, can be coplanar with each other to provide a flat upper surface along which the second conductive layer AEb extends.

[0141] For example, when the display device 10 does not include the anode planarization layer APL, the second conductive layer AEb may include steps corresponding to the recessed shape of the first conductive layer AEa. The steps corresponding to the recessed shape of the first conductive layer AEa may have the same meaning as steps corresponding to the shape of each anode contact hole ACTH.

[0142] For example, when the second conductive layer AEb includes steps corresponding to the shape of the first conductive layer AEa or the shape of each anode contact hole ACTH, the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 may be formed with a thickness below a certain range in the portion overlapping the edge of each anode contact hole ACTH. Therefore, this may lead to reliability defects in the display device 10 (e.g., light-emitting layer shading defects). Since the material of the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 is formed on the flat upper surface of the anode AE ​​located thereunder, sufficient material thickness can be ensured.

[0143] Reliability defects (e.g., luminescent layer shadow defects) may be due to the material forming the first luminescent layer EL1 to the third luminescent layer EL3 being formed in some parts with a thickness below a certain range, so that the brightness of the display device 10 is measured to be below a certain range level in some parts.

[0144] Therefore, the display device 10 of the embodiment can planarize the steps included in the first conductive layer AEa by including an anode planarization layer APL in the portion superimposed with each anode contact hole ACTH. Therefore, the second conductive layer AEb can have a relatively flat shape, such that the first light-emitting layers EL1 to the third light-emitting layers EL3 are formed with a uniform thickness. Therefore, reliability defects of the display device 10 (e.g., light-emitting layer shading defects) can be solved. Here, the display device 10 can include not only the anode AE ​​containing the conductive layer, but also the anode planarization layer APL located between the first conductive layer AEa and the second conductive layer AEb of the anode AE.

[0145] The anode planarization layer (APL) may include organic materials. For example, the anode planarization layer (APL) may include acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, or phenolic resin. In other words, the anode (AE) may include not only conductive materials but also organic materials disposed therein.

[0146] The first emitting layer EL1 to the third emitting layer EL3 can be located on the anode AE. The first emitting layer EL1 to the third emitting layer EL3 can be located in the portion superimposed with the emitting region EA and the non-emitting region NLA. The first emitting layer EL1 to the third emitting layer EL3 can be superimposed on the third-direction DR3 with the dike structure BN and the component insulating layer PDL.

[0147] The first light-emitting layer EL1 to the third light-emitting layer EL3 can contact the anode AE ​​in the portion superimposed with the opening OP, and can cover the entire second element insulating layer PDL2 in the portion superimposed with the non-emitting region NLA.

[0148] The first light-emitting layer EL1 to the third light-emitting layer EL3 can be organic light-emitting layers made of organic materials (or containing organic materials). The first light-emitting layer EL1 to the third light-emitting layer EL3 can include any commonly used materials.

[0149] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can emit light of different colors. For example, the first light-emitting layer EL1 can emit red light, the second light-emitting layer EL2 can emit green light, and the third light-emitting layer EL3 can emit blue light, but the embodiments are not limited to this.

[0150] The first emitting layer EL1 can be located in the portion superimposed with the first emitting region EA1, the second emitting layer EL2 can be located in the portion superimposed with the second emitting region EA2, and the third emitting layer EL3 can be located in the portion superimposed with the third emitting region EA3. The first emitting layer EL1, the second emitting layer EL2, and the third emitting layer EL3 can be spaced apart from each other in the portion superimposed with the non-emitting region NLA.

[0151] In the display device 10 of this embodiment, since the third diaphragm layer BN3 includes a tip, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, which are spaced apart from each other, can be formed in the manufacturing process of the display device 10 without using a fine metal mask. The manufacturing process will be described later.

[0152] The cathode CE can be located on the first light-emitting layer EL1 to the third light-emitting layer EL3. The cathode CE can be located in the portion superimposed with the emitting region EA and the non-emitting region NLA. The cathode CE can completely cover the first light-emitting layer EL1 to the third light-emitting layer EL3.

[0153] The cathode CE can contact the dam structure BN, and therefore can be electrically connected to the dam structure BN. Specifically, the cathode CE can contact the tip of the third dam layer BN3.

[0154] The cathode CE may include a transparent conductive material to transmit light generated from the first light-emitting layer EL1 to the third light-emitting layer EL3. For example, the cathode CE may include a material layer with a low work function, such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, their compounds or mixtures (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. The cathode CE may also include a transparent metal oxide layer disposed on the material layer with a low work function.

[0155] In this embodiment, the cathodes CE located in the portion superimposed with the first emission region EA1, the portion superimposed with the second emission region EA2, and the portion superimposed with the third emission region EA3 can be spaced apart from each other. The cathodes CE located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other can be electrically connected via a dam structure BN. Specifically, the cathodes CE located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other can contact the third dam layer BN3 spaced apart from the first emission region EA1 to the third emission region EA3, and can be electrically connected to each other via a second dam layer BN2 and a first dam layer BN1 electrically connected to the third dam layer BN3.

[0156] In the display device 10 of this embodiment, since the third embankment layer BN3 includes a tip, cathodes CE, located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other, can be formed without using a fine metal mask. The manufacturing process will be described later.

[0157] The auxiliary electrode AX can be located on the cathode CE. The auxiliary electrode AX can be located in the portion superimposed with the emitting region EA and the non-emitting region NLA. The auxiliary electrode AX can completely cover the cathode CE. The auxiliary electrode AX can facilitate the electrical connection of the cathode CE to the dam structure BN. Here, the auxiliary electrode AX can be considered as part of the cathode layer, but is not limited thereto.

[0158] The auxiliary electrode AX may include a transparent conductive oxide (TCO). For example, the auxiliary electrode AX may include at least one of indium zinc oxide (IZO) and indium tin oxide (ITO).

[0159] In this embodiment, the auxiliary electrode AX located in the portion superimposed with the first emission region EA1, the auxiliary electrode AX located in the portion superimposed with the second emission region EA2, and the auxiliary electrode AX located in the portion superimposed with the third emission region EA3 can be spaced apart from each other. The auxiliary electrodes AX located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other can be electrically connected to each other through the dike structure BN. Specifically, the auxiliary electrodes AX located in the first emission region EA1 to the third emission region EA3 and spaced apart from each other can contact the third dike layer BN3 spaced apart from the first emission region EA1 to the third emission region EA3, and can be electrically connected to each other through the second dike layer BN2 and the first dike layer BN1, which are electrically connected to the third dike layer BN3.

[0160] The auxiliary electrode AX can be spaced apart from the first dam layer BN1 on the third-direction DR3 in the portion superimposed with the non-emitting region NLA.

[0161] The inorganic layer IO can be located on the light-emitting element ED. The inorganic layer IO can completely cover the light-emitting element ED and prevent oxygen or moisture from penetrating into the light-emitting element ED.

[0162] The inorganic layer IO of a component may include an inorganic insulating material. For example, the inorganic layer IO of a component may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0163] The inorganic layer IO may include a first inorganic layer IO1, a second inorganic layer IO2, and a third inorganic layer IO3. The first inorganic layer IO1 may be disposed on the first light-emitting element ED1 in the first emission region EA1, the second inorganic layer IO2 may be disposed on the second light-emitting element ED2 in the second emission region EA2, and the third inorganic layer IO3 may be located on the third light-emitting element ED3 in the third emission region EA3. The first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3 may be spaced apart from each other in the portion superimposed with the non-emission region NLA.

[0164] In the accompanying drawings, the first element inorganic layer IO1, the second element inorganic layer IO2, and the third element inorganic layer IO3 appear to be formed in the same layer. However, in the manufacturing process of the display device 10, the first element inorganic layer IO1 can be formed after the first light-emitting element ED1, the second element inorganic layer IO2 can be formed after the second light-emitting element ED2, and the third element inorganic layer IO3 can be formed after the third light-emitting element ED3. The manufacturing process will be described later.

[0165] In an embodiment, the layers from the anode AE ​​to the inorganic layer IO (including the anode AE ​​and the inorganic layer IO) at the corresponding emission regions can define a light-emitting structure.

[0166] The thin-film encapsulation layer TFEL can be located on the display element layer EML. The thin-film encapsulation layer TFEL can include an organic encapsulation layer TFE1 and an inorganic encapsulation layer TFE3.

[0167] In this embodiment, the organic encapsulation layer TFE1 can be located on the inorganic layer IO of the component. For example, the organic encapsulation layer TFE1 can completely contact and cover the first inorganic layer IO1, the second inorganic layer IO2, and the third inorganic layer IO3.

[0168] The organic encapsulation layer TFE1 can flatten the steps formed according to the contour of the underlying structure. The organic encapsulation layer TFE1 can fill the portion between the auxiliary electrode AX and the first dam layer BN1 in the part stacked with the non-emitting region NLA. Here, the organic encapsulation layer TFE1 can fill the empty spaces at the dam recesses.

[0169] The organic encapsulation layer TFE1 may include polymeric materials. For example, the organic encapsulation layer TFE1 may include acrylic resin, silicone resin, epoxy resin, silicone acrylate resin, polyimide, or polyethylene.

[0170] The inorganic encapsulation layer TFE3 can be located on top of the organic encapsulation layer TFE1. The inorganic encapsulation layer TFE3 can protect the underlying structure from moisture and oxygen penetration. According to an embodiment, the inorganic encapsulation layer TFE3 can be omitted.

[0171] The inorganic encapsulation layer TFE3 may include an inorganic insulating material. For example, the inorganic encapsulation layer TFE3 may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0172] Figure 7 yes Figure 6 An enlarged sectional view of region "A" in the image.

[0173] Apart from Figures 1 to 6 In addition, refer to Figure 7The embankment structure BN can have an asymmetrical cross-sectional structure in the part facing the anode contact hole ACTH and in the part opposite to the above part.

[0174] For example, in the portion facing the anode contact hole ACTH, the second side surface 1d of the first dam layer BN1, the second side surface 2d of the second dam layer BN2, and the second side surface 3d of the third dam layer BN3 can be located on the same line. Being on the same line can have the same meaning as alignment or extension, such as coplanarity. Here, these three inner surfaces can be coplanar with each other and together form the inner wall defining the dam opening. The three inner surfaces can define corresponding thickness portions of the dam opening.

[0175] Since the first diaphragm layer BN1, the second diaphragm layer BN2, and the third diaphragm layer BN3 are removed by the same etching process in the manufacturing process of the display device 10, the second side surface 1d of the first diaphragm layer BN1, the second side surface 2d of the second diaphragm layer BN2, and the second side surface 3d of the third diaphragm layer BN3 can be located on the same line. The manufacturing process will be described later.

[0176] For example, in the portion opposite to the portion facing the anode contact hole ACTH, the first side surface 3c, which is the outermost wall of the third dam layer BN3, may protrude significantly more in the first direction DR1 than the first side surface 2c, which is the outermost wall of the second dam layer BN2. That is, the third dam layer BN3 may include a tip that protrudes significantly more in the first direction DR1 than the first side surface 2c of the second dam layer BN2. Redundant descriptions will be omitted.

[0177] In this embodiment, the cathode CE can be located on the first side surface 3c of the third dam layer BN3 to contact the first side surface 3c. Additionally, the auxiliary electrode AX can contact the tip of the third dam layer BN3 and can extend to contact the second dam layer BN2.

[0178] In an embodiment, the first side surface 2c of the second dam layer BN2 may include a first portion 2ca as a first sidewall portion and a second portion 2cb as a second sidewall portion, depending on the portion in contact with it. The first portion 2ca may be the portion in contact with the auxiliary electrode AX, and the second portion 2cb may be the portion in contact with the organic encapsulation layer TFE1.

[0179] In this embodiment, the contact area between the auxiliary electrode AX and the dam structure BN can be larger than the contact area between the cathode CE and the dam structure BN. (Refer to...) Figure 6 and Figure 7 The contact area can be defined along the third direction DR3 and the second direction DR2. Along... Figure 6 and Figure 7 The dimensions of the third-direction DR3 in the diagram can represent the relative contact area.

[0180] In an embodiment, the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 may be spaced apart from the anode planarization layer APL and may surround the anode planarization layer APL.

[0181] The first element insulating layer PDL1 can completely cover the second side surface 1d of the first dam layer BN1, the second side surface 2d of the second dam layer BN2, and the second side surface 3d of the third dam layer BN3.

[0182] The second element insulating layer PDL2 may cover the edges (or end surfaces) of the first conductive layer AEa and the second conductive layer AEb of the anode AE, and may extend to contact the first element insulating layer PDL1.

[0183] The second conductive layer AEb of the anode AE ​​may include a first portion b11 and a second portion b12 depending on the extent to which it is stacked. The first portion b11 may be the portion that contacts or is stacked with the anode planarization layer APL, and the second portion b12 may be the portion that contacts or is stacked with the first conductive layer AEa. The first portion b11 may be the middle portion of the second conductive layer AEb, and the second portion b12 may be the edge portion of the second conductive layer AEb.

[0184] In an embodiment, the anolyte planarization layer APL may include a first surface p1 facing the second conductive layer AEb. In the manufacturing process of the display device 10 of this embodiment, the anolyte planarization layer APL can be formed by performing a chemical mechanical polishing (CMP) process. Therefore, the anolyte planarization layer APL may include the first surface p1. The manufacturing process will be described later.

[0185] In an embodiment, the first surface p1 of the anode planarization layer APL may extend from the first surface a11 of the first conductive layer AEa in a first direction DR1, such that the first surface p1 and the first surface a11 are coplanar with each other. The first surface a11 of the first conductive layer AEa may be the surface facing the second conductive layer AEb. For example, the first surface p1 of the anode planarization layer APL included in the display device 10 may be a flat surface without curvature.

[0186] The first surface p1 of the anolyte planarization layer APL can have various shapes depending on the process conditions for performing the CMP process.

[0187] Figure 8 and Figure 9 yes Figure 6 An enlarged cross-sectional view of an embodiment of region "A" in the diagram.

[0188] Apart from Figures 1 to 7 In addition, refer to Figure 8The first surface p1 of the anode planarization layer APL included in the display device 30 may have a different cross-sectional shape than the first surface p1 of the anode planarization layer APL included in the display device 10. Therefore, the common description of the display device 10 and the display device 30 will be omitted, and the differences will be described below.

[0189] The first surface p1 of the anode planarization layer APL included in the display device 30 may be curved. For example, the first surface p1 of the anode planarization layer APL included in the display device 30 may protrude in a direction toward the third-party DR3 (i.e., toward the second conductive layer AEb). In other words, the first surface p1 of the anode planarization layer APL included in the display device 30 may have a protrusion that protrudes much more than the first surface a11 of the first conductive layer AEa in a direction toward the third-party DR3.

[0190] In the process of manufacturing display device 30, the first surface p1 of the anolyte planarization layer APL can be formed by a CMP process. However, the CMP process performed in the process of manufacturing display device 30 may have different process conditions than the CMP process performed in the process of manufacturing display device 10. For example, the process conditions may include at least one of abrasive particles, oxidant, polymer compound, inhibitor, chelating agent, pH adjuster such as acid or base, pad rotation speed, head pressure, and process time.

[0191] According to the above process conditions of CMP process, the first surface p1 of the anodic planarization layer APL included in the display device 30 can have a different polishing speed and planarization degree than the first surface p1 of the anodic planarization layer APL included in the display device 10, so it can protrude to one side on the third direction DR3.

[0192] In the accompanying drawings, the second conductive layer AEb, which includes the anode AE ​​in the display device 30, protrudes to one side on the third direction DR3 because it covers the anode planarization layer APL in the display device 30 along the shape of the anode planarization layer APL. However, this specification is not limited thereto. According to an embodiment, even if the anode planarization layer APL has a protruding portion, the second conductive layer AEb, which includes the anode AE ​​in the display device 30, can also have a flat surface.

[0193] Because the display device 30 includes an anode planarization layer APL in the portion superimposed with the anode contact hole ACTH, the steps included in the first conductive layer AEa can be planarized. Therefore, the second conductive layer AEb can have a relatively flat shape, allowing the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 to be formed with a uniform thickness. Thus, the display device 30 can address reliability defects (e.g., light-emitting layer shading defects). Further redundant descriptions will be omitted.

[0194] Apart from Figures 1 to 8 In addition, refer to Figure 9 The first surface p1 of the anode planarization layer APL included in the display device 50 may have a different shape than the first surface p1 of the anode planarization layer APL included in the display device 10. Therefore, the common description of the display device 10 and the display device 50 will be omitted, and the differences will be described below.

[0195] The first surface p1 of the anode planarization layer APL included in the display device 50 may be curved. For example, the first surface p1 of the anode planarization layer APL included in the display device 50 may be recessed in the direction opposite to the third-direction DR3 (i.e., towards the second connecting electrode CNE2). In other words, the first surface p1 of the anode planarization layer APL included in the display device 50 may have a recess that protrudes much more than the first surface a11 of the first conductive layer AEa in the direction opposite to the third-direction DR3.

[0196] According to the above-mentioned process conditions of CMP process, the first surface p1 of the anodic planarization layer APL included in the display device 50 may have a different polishing speed and planarization degree than the first surface p1 of the anodic planarization layer APL included in the display device 10, and thus may be recessed toward the other side opposite to the third direction DR3.

[0197] In the accompanying drawings, the second conductive layer AEb, which is included in the anode AE ​​in the display device 50, is recessed toward the other side opposite to the third direction DR3 because it covers the anode planarization layer APL included in the display device 50 along the shape of the anode planarization layer APL, but this specification is not limited thereto.

[0198] According to an embodiment, even if the anode planarization layer APL has a recessed portion, the second conductive layer AEb, which includes the anode AE ​​in the display device 50, can also have a flat surface.

[0199] Because the display device 50 includes an anode planarization layer APL in the portion superimposed with the anode contact hole ACTH, the steps included in the first conductive layer AEa can be planarized. Therefore, the second conductive layer AEb can have a relatively flat shape, allowing the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 to be formed with a uniform thickness. Thus, the display device 50 can address reliability defects (e.g., light-emitting layer shading defects). Further redundant descriptions will be omitted.

[0200] Although the emitting region EA, the opening OP, and the anode contact hole ACTH are superimposed on each other in a common plane region, the respective boundaries of the emitting region EA, the opening OP, and the anode contact hole ACTH can be defined by the inner sidewalls of different layers. In an embodiment, for example, the emitting region EA can be defined by the maximum distance between the inner sidewalls of the element insulating layer PDL, or it can be defined by the outer edge of the light-emitting layer. The opening OP can be defined by the maximum distance between the inner sidewalls of the element insulating layer PDL. Since the anode AE ​​has a contact area with the second connecting electrode CNE2 between the inner sidewalls of the third insulating layer ILD3, the third insulating layer contact hole of the anode contact hole ACTH can be defined by the inner sidewall of the third insulating layer ILD3.

[0201] Figure 10 This indicates that it is manufactured (or supplied). Figure 5 The flowchart of method S1 for display element layer EML.

[0202] Reference Figure 10 The method S1 for manufacturing the display element layer EML included in the display device 10 according to the embodiment may include: forming (or setting) a penetration dam structure BN and an anode contact hole ACTH of a first element insulating layer PDL1 as a lower layer of the element insulating layer PDL at the emission region EA (operation S100); forming (or setting) a first conductive layer AEa, an anode planarization layer APL and a second conductive layer AEb of the anode AE ​​at the emission region EA (operation S200); forming the tip of the dam structure BN after forming a second element insulating layer PDL2 defining an opening (operation S300); and forming a light-emitting layer EL, a cathode CE, an auxiliary electrode AX and an element inorganic layer IO on the anode AE ​​(operation S400).

[0203] Figures 11 to 13 It is shown Figure 10 The sectional view of operation S100.

[0204] Reference Figures 11 to 13 The thickness portion of the anode contact hole ACTH that forms the penetrating dike structure BN and the first element insulating layer PDL1 at the emission region EA is described (operation S100).

[0205] First, a plurality of second connection electrodes CNE2 are formed on the first via layer VIA1. A second via layer VIA2, a third insulating layer ILD3, and a dam structure BN are formed on the entire surface of the first via layer VIA1 and the second connection electrodes CNE2. The dam structure BN may include a first dam layer BN1, a second dam layer BN2, and a third dam layer BN3 stacked sequentially. Figure 11 Each of the layers ILD3, BN1, BN2 and BN3 shown can be considered as the initial layer of these layers, respectively.

[0206] In the current process, the second dam layer BN2 and the third dam layer BN3 can be made of different materials. For example, the third dam layer BN3 can be made of a material with higher etch resistance than the second dam layer BN2. Redundant descriptions will be omitted.

[0207] Although not shown in the accompanying drawings, the transistor layer TFTL, including the first via layer VIA1 and the second via layer VIA2, can be located on the substrate SUB, and the detailed structure of the transistor layer TFTL is similar to... Figure 5 The same as shown in the image.

[0208] Next, a photoresist PR1 (as a first photoresist) is formed on the third diaphragm layer BN3, and a first etching process is performed. In the current process, multiple photoresists PR1 can be formed, and the multiple photoresists PR1 can be located in portions not superimposed with the second connection electrode CNE2. That is, the first photoresist can be adjacent to or between the second connection electrode CNE2 along the direction of the transistor layer TFTL. This position of the first photoresist can be superimposed with or correspond to the non-emitting region NLA.

[0209] In the current process, the first etching process can be performed as a dry etching process. For example, a dry etching process can be performed using reactive ion etching (RIE) using reactive gases such as CHF3, CH3F, CH2F2, CF4, C2F6, or C3F6 and sputtering gases such as Ar or O2 / Ar. In this case, an inductively coupled plasma (ICP) source or a capacitively coupled plasma (CCP) source can be used as the plasma source.

[0210] like Figure 12As shown, the thickness of the dam structure BN that is not stacked with the photoresist PR1 (e.g., exposed to the outside of the first photoresist) can be completely removed at once to form a hole HOL1 as a first initial hole. This hole HOL1 can be an initial dam opening. The side surfaces of the first dam layer BN1 facing the hole HOL1, the side surfaces of the second dam layer BN2 facing the hole HOL1, and the side surfaces of the third dam layer BN3 facing the hole HOL1 can be located on the same line. Since they are on the same line, the side surfaces can be coplanar with each other to provide the inner sidewall of the dam structure BN that defines the dam opening at the emission region EA.

[0211] In the current process, the third insulating layer ILD3 can be exposed to the outside of the embankment structure BN in the portion overlapping with the hole HOL1.

[0212] Although not shown in the accompanying drawings, the photoresist PR1 can be removed by an ashing process. Removing the first photoresist exposes the upper surface of the initial first element insulating layer.

[0213] Next, such as by making Figure 12 The initial first element insulating layer shown is patterned to form a first element insulating layer PDL1 on the dam structure BN. The initial form of the first element insulating layer PDL1 can be formed on the entire surface of the dam structure BN and can completely cover the side surfaces of the first dam layer BN1 facing the hole HOL1, the second dam layer BN2 facing the hole HOL1, and the third dam layer BN3 facing the hole HOL1. Additionally, the initial form of the first element insulating layer PDL1 can extend to cover the third insulating layer ILD3 in the portion overlapping with the hole HOL1. Here, the initial first element insulating layer can have a recessed structure, which is provided with a recess overlapping with the second connection electrode CNE2.

[0214] In the current process, the first element insulating layer PDL1 in its initial form can be formed by a layer forming process (e.g., a deposition process) used to form at least one of the above-mentioned inorganic materials.

[0215] Next, a photoresist PR2, serving as a second photoresist, is formed on the initial form of the first element insulating layer PDL1, and a second etching process is performed. Multiple photoresists PR2 can be formed, and these multiple photoresists PR2 can be located in portions not overlapping with the hole HOL1. For example, the second etching process can be performed as a dry etching process. Redundant descriptions will be omitted.

[0216] In the current process, the thickness portions of the first element insulating layer PDL1 and the third insulating layer ILD3 that are not stacked with the photoresist PR2 can be completely removed in one step. Therefore, an anode contact hole ACTH can be formed, and the second connection electrode CNE2 can be exposed outside the third insulating layer ILD3 in the portion stacked with the anode contact hole ACTH. Here, the size of the anode contact hole ACTH can be the minimum distance between the sidewalls of the etched layers ILD3 or PDL1. In an embodiment, the boundary of the anode contact hole ACTH can be defined by the sidewalls of the etched third insulating layer ILD3 or the first element insulating layer PDL1.

[0217] Each of the anode contact holes ACTH can be stacked with the emitter region EA. The etched first element insulating layer PDL1 can provide an initial opening corresponding to the opening OP (e.g., the pixel opening of the element insulating layer PDL).

[0218] Although not shown in the accompanying drawings, photoresist PR2 can be removed by an ashing process.

[0219] Figures 14 to 17 It is shown Figure 10 The sectional view of operation S200.

[0220] Reference Figures 14 to 17 The formation of a first conductive layer AEa, an anode planarization layer APL, and a second conductive layer AEb of the anode AE ​​within the anode contact hole ACTH is described (operation S200).

[0221] First, a first conductive layer AEa in the initial form of the anode AE ​​is formed on the first element insulating layer PDL1.

[0222] In the current process, the first conductive layer AEa in its initial form can be formed by a layer forming process (e.g., sputtering) used to form at least one of the aforementioned metallic materials.

[0223] In the current process, the initial form of the first conductive layer AEa can fully contact and cover the portion of the second connection electrode CNE2 exposed in the overlap with the anode contact hole ACTH, and can extend to cover the first element insulating layer PDL1. In a direction perpendicular to the outer surface of the dam structure BN, the first conductive layer AEa can be separated from the dam structure BN through the first element insulating layer PDL1.

[0224] Next, an initial-form anodic planarization layer APL is formed on the first conductive layer AEa.

[0225] In the current process, the initial form of the anode planarization layer APL can be formed by a layer forming process (e.g., sputtering) used to form at least one of the above-mentioned metal materials, and the initial form of the anode planarization layer APL can be formed to a thickness that planarizes the step St formed in the portion of the first conductive layer AEa that overlaps with the anode contact hole ACTH.

[0226] Next, the CMP process is performed. For example, CMP refers to a process that planarizes an irregular or uneven surface by using chemical / mechanical polishing elements. For instance, in the current process, the CMP process could be performed as an organic layer CMP process. The polishing speed and degree of planarization in the current process can be controlled according to process conditions such as abrasive particles, oxidants, polymer compounds, inhibitors, chelating agents, pH adjusters such as acids or bases, pad rotation speed, head pressure, and process time.

[0227] like Figure 15 As shown, in the current process, the thickness portion of the anode planarization layer APL that protrudes far beyond the upper surface of the first conductive layer AEa can be polished and removed, and the polished anode planarization layer APL can have a first surface p1 in the portion overlapping with the anode contact hole ACTH.

[0228] like Figures 7 to 9 The first surface p1 of the anolyte planarization layer APL, as shown and described, can have various shapes depending on the conditions of the process being performed. Redundant descriptions will be omitted.

[0229] With the current process, the anode planarization layer APL can flatten or planarize the step St formed by the first conductive layer AEa in the portion superimposed with the anode contact hole ACTH.

[0230] With current processes, the anode planarization layer (APL) can be formed into multiple blocks or patterns, and the blocks of APL can be spaced apart from each other along the transistor layer (TFTL). The APL may not be located in a portion not stacked with the anode contact hole (ACTH). That is, the anode planarization layer can be removed from the region adjacent to the anode contact hole (ACTH).

[0231] Next, as Figure 16 As shown, a second conductive layer AEb in the initial form of the anode AE ​​is formed on the first conductive layer AEa and the anode planarization layer APL. The second conductive layer AEb in the initial form can be formed on the entire surface of the first conductive layer AEa and the anode planarization layer APL, and the second conductive layer AEb in the initial form can completely cover the first conductive layer AEa and the anode planarization layer APL.

[0232] In the current process, the second conductive layer AEb in its initial form can be formed by a layer forming process (e.g., sputtering) used to form at least one of the aforementioned metallic materials.

[0233] In an embodiment, the second conductive layer AEb providing the anode AE ​​may include: providing an anode planarization layer APL extending from a recess in the first conductive layer AEa to define an extended portion of the anode planarization layer APL; removing the extended portion by chemical mechanical polishing to provide a polished upper surface (e.g., a first surface p1) of the anode planarization layer APL that overlaps with the anode contact hole; and contacting the second conductive layer AEb with the polished upper surface of the anode planarization layer APL.

[0234] Next, a photoresist PR3, serving as a third photoresist, is formed on the second conductive layer AEb, and a third etching process is performed. In the current process, multiple photoresists PR3 can be formed, and these multiple photoresists PR3 can be located in the portion superimposed with the anode contact hole ACTH. For example, the third etching process can be performed by at least one of a dry etching process and a wet etching process.

[0235] For example, wet etching processes can be performed using liquid chemical solutions such as diluted hydrofluoric acid solution, nitric acid solution, tetramethylammonium hydroxide solution, or potassium hydroxide solution.

[0236] The current process can remove the thickness portion of the first conductive layer AEa and the second conductive layer AEb of the anode AE ​​that is not stacked with the photoresist PR3, thus allowing the first conductive layer AEa and the second conductive layer AEb of the anode AE ​​to be patterned.

[0237] In the current process, the anode planarization layer APL can be completely surrounded by the first conductive layer AEa and the second conductive layer AEb. Here, the upper surface of the first element insulating layer PDL1 can be exposed to the outside of the anode AE.

[0238] Although not shown in the accompanying drawings, photoresist PR3 can be removed by an ashing process.

[0239] Figures 18 to 21 It is shown Figure 10 The sectional view of operation S300.

[0240] Reference Figures 18 to 21 The tip of the dam structure is formed after the second element insulating layer PDL2 is formed, which defines the opening OP at the emission region EA (operation S300).

[0241] First, after forming a second element insulating layer PDL2 in its initial form on the anode AE ​​and the first element insulating layer PDL1, a photoresist PR4, serving as a fourth photoresist, is formed on the second element insulating layer PDL2, and a fourth etching process is performed. In the current process, multiple photoresists PR4 can be formed, and these multiple photoresists PR4 can be located in portions not overlapping with the anode contact hole ACTH, i.e., located between adjacent emission regions EA that are adjacent to each other and adjacent to the anode contact hole ACTH. For example, the fourth etching process can be performed as a dry etching process. Redundant descriptions will be omitted.

[0242] In the current process, the thickness portion of the second element insulating layer PDL2 that is not stacked with the photoresist PR4 can be removed to form an opening OP in the element insulating layer PDL that overlaps with the dam opening and the anode contact hole ACTH. In other words, the opening OP can be defined by the inner sidewall of the second element insulating layer PDL2, and the solid portion of the second element insulating layer PDL2 can surround the opening OP. In the portion stacked with the opening OP, the second conductive layer AEb of each anode AE ​​can be exposed to the outside of the element insulating layer PDL.

[0243] In the accompanying drawings, the width of each anode contact hole ACTH in the first direction DR1 and the width of each opening OP in the first direction DR1 are equal. However, this specification is not limited thereto. The anode contact holes ACTH and openings OP may be stacked on a third direction DR3, but the width of each anode contact hole ACTH and the width of each opening OP may also be different from each other, such as due to the sidewalls defining the corresponding contact holes or openings.

[0244] Although not shown in the accompanying drawings, photoresist PR4 can be removed by an ashing process.

[0245] like Figure 19 As shown, a photoresist PR5, serving as a fifth photoresist, is formed on the anode AE ​​and the second element insulating layer PDL2 having an opening OP defined therein, and a fifth etching process is performed. In the current process, multiple photoresists PR5 can be formed to overlap with and fill the opening OP, and can be located in the portion overlapping with the anode contact hole ACTH. For example, the fifth etching process can be performed as a dry etching process. Redundant descriptions will be omitted.

[0246] In the current process, the thickness portions of the second element insulating layer PDL2, the first element insulating layer PDL1, the second dam layer BN2, and the third dam layer BN3 that are not stacked with the photoresist PR5 can be completely removed in one step to form the hole HOL2. The hole HOL2, serving as the second initial hole, can be formed in the portion not stacked with the anode contact hole ACTH, and the side surfaces of the second element insulating layer PDL2 facing the hole HOL2, the first element insulating layer PDL1 facing the hole HOL2, the second dam layer BN2 facing the hole HOL2, and the third dam layer BN3 facing the hole HOL2 can be located on the same line, such as being coplanar. In other words, in the current process, the second element insulating layer PDL2, the first element insulating layer PDL1, the second dam layer BN2, and the third dam layer BN3 that are not stacked with the photoresist PR5 can be removed isotropically.

[0247] In the current process, the first dam layer BN1, which is superimposed on the aperture HOL2, can be exposed. The aperture HOL2 can be superimposed on or correspond to the region between the emission regions EA (such as the non-emission region NLA). The aperture HOL2 can be an initial dam recess between the emission regions EA.

[0248] Although not shown in the accompanying drawings, photoresist PR5 can be removed by an ashing process.

[0249] Next, as Figure 20 As shown, a photoresist PR6, serving as a sixth photoresist, is formed on the anode AE ​​and the second element insulating layer PDL2, and a sixth etching process is performed. In the current process, multiple photoresists PR6 can be formed, and these multiple photoresists PR6 can be located in the portion overlapping with the anode contact hole ACTH. The photoresist PR6 can completely cover the upper surface of the anode AE ​​and the upper surface of the second element insulating layer PDL2. For example, the sixth etching process can be performed as a wet etching process. Redundant descriptions will be omitted.

[0250] In current processes, the second dam layer BN2 and the third dam layer BN3, which consist of different metallic materials, can have different etching selectivity. Specifically, in the same etching process, the third dam layer BN3 can have higher etching resistance than the second dam layer BN2. In other words, in the same etching process, the second dam layer BN2 can include materials with a higher etching rate than the third dam layer BN3.

[0251] Therefore, as Figure 21 As shown, at each dam recess, the third dam layer BN3 may include a tip that protrudes significantly beyond the first side surface 2c of the second dam layer BN2 in the first direction DR1. The first element insulating layer PDL1 and the second element insulating layer PDL2 may overlap the tip of the third dam layer BN3 in the third direction DR3. Redundant descriptions will be omitted.

[0252] Although not shown in the accompanying drawings, photoresist PR6 can be removed by an ashing process.

[0253] Figure 21 The stacked structure can be a substrate structure on which a light-emitting element can be disposed. Referring to a common surface such as a substrate (SUB) or a transistor layer (TFTL), the stacked structure can provide a protruding structure at the emission region (EA) (and / or the opening (OP) and / or the anode contact hole (ACTH), while providing a recessed structure at the non-emission region (NLA) between the emission regions (EA). The light-emitting element (ED) can be disposed on... Figures 11 to 21 The matrix structure provided during the operation.

[0254] Figures 22 to 25 It is shown Figure 10 The operation of the S400 sectional view.

[0255] Reference Figures 22 to 25 The description describes the formation of a light-emitting layer EL, a cathode CE, an auxiliary electrode AX, and an inorganic layer IO on the anode AE ​​(operation S400).

[0256] First, an initial (material) layer of the first light-emitting layer EL1, the cathode CE, and the auxiliary electrode AX is deposited on the anode AE ​​to form the first light-emitting element ED1.

[0257] In the current process, the formation of the first light-emitting layer EL1 can be performed using a thermal deposition process. In this process, the material forming the first light-emitting layer EL1 can be formed not only on the anode AE ​​superimposed on the first emission region EA1, but also on the anode AE ​​located in the portions superimposed on the second emission region EA2 and the third emission region EA3. The first light-emitting layers EL1 located in the portions superimposed on the first emission region EA1 to the third emission region EA3 can be spaced apart from each other.

[0258] Alternatively, the material forming the first light-emitting layer EL1 can also be formed on the first dam layer BN1 within the dam recess at the non-emitting region NLA. The materials forming the first light-emitting layer EL1 on the anode AE ​​and the materials forming the first light-emitting layer EL1 on the first dam layer BN1 can be spaced apart from each other. The material forming the first light-emitting layer EL1 on the first dam layer BN1 can be referred to as an organic patterned ELP. Here, the pattern of the first light-emitting layer EL1 and the organic patterned ELP can be in the same layer, such as corresponding portions of the same material layer. The first light-emitting layer EL1 and the organic patterned ELP can also be separated from each other.

[0259] When in the same layer, components can be formed in the same process and / or comprise the same material as each other. Components can be corresponding parts of the same material layer. Components can be in the same layer by forming an interface with the same lower or upper layer. Components can be coplanar with each other or set with the same thickness, etc., but are not limited to these.

[0260] In current processes, the cathode (CE) can be formed using either thermal deposition or sputtering. The process for forming the cathode (CE) can exhibit higher step coverage characteristics than the process for forming the first light-emitting layer (EL1). Therefore, the cathode (CE) can completely cover the first light-emitting layer (EL1).

[0261] In the current process, the material forming the cathode (CE) can be formed not only on the first light-emitting layer (EL1) superimposed on the first emitting region (EA1), but also on the portion of the first emitting layer (EL1) superimposed on the second emitting region (EA2) and the third emitting region (EA3). The cathodes (CE) in the portions superimposed on the first emitting region (EA1) to the third emitting region (EA3) can be spaced apart from each other.

[0262] Furthermore, the material forming the cathode (CE) can be formed not only on the first light-emitting layer (EL1) but also on the organic pattern (ELP). The materials forming the cathode CE on the first light-emitting layer (EL1) and the materials forming the cathode CE on the organic pattern (ELP) can be spaced apart from each other. The material forming the cathode CE on the first diaphragm layer (BN1) can be referred to as the electrode pattern (CEP). Here, the cathode CE pattern and the electrode pattern (CEP) can be in the same layer, such as corresponding portions of the same material layer. Alternatively, the cathode CE and the electrode pattern (CEP) can be separated from each other.

[0263] In the current process, the cathode (CE) can contact the tip surface of the third dam layer (BN3). Redundant descriptions will be omitted.

[0264] The auxiliary electrode AX can be formed using a sputtering process. The process for forming the auxiliary electrode AX can exhibit higher step coverage characteristics than the process for forming the cathode CE. Therefore, the initial form of the auxiliary electrode AX can be formed across the entire surface. In other words, the auxiliary electrode AX can completely cover the cathode CE.

[0265] In the current process, the material forming the auxiliary electrode AX can contact the tip of the third dam layer BN3 and the first side surface 2c of the second dam layer BN2. Redundant descriptions will be omitted. The initial layer of material forming the auxiliary electrode AX can be continuously disposed along the stacked structure, i.e., located in the dam recesses and also on the protruding structures.

[0266] Next, an inorganic element layer IO in its initial form is formed on the auxiliary electrode AX. The inorganic element layer IO can cover the underlying layer structure with a uniform thickness along the contour of the structure and can cover the entire auxiliary electrode AX.

[0267] In the current process, the inorganic layer IO of the element can be formed by a layer forming process (e.g., a deposition process) used to form at least one of the aforementioned inorganic materials. The initial layer of material forming the inorganic layer IO of the element can be continuously disposed along the stacked structure, i.e., located in the recessed portion of the embankment and also on the protruding structure.

[0268] Next, as Figure 23 and Figure 24 As shown, a photoresist PR7, serving as a seventh photoresist, is formed in the portion superimposed on the first emission region EA1 and the periphery of the first emission region EA1, and the photoresist PR7 is used as a mask to perform the seventh etching process.

[0269] In the current process, the thickness portions of the materials forming the first light-emitting layer EL1, the cathode CE, the auxiliary electrode AX, and the element inorganic layer IO that are not stacked with the photoresist PR7 can be completely removed in one step. Therefore, the anode AE ​​stacked with the second emission region EA2 and the anode AE ​​stacked with the third emission region EA3 can be exposed again, and the element inorganic layer IO in the form of the first element inorganic layer IO1 can be formed.

[0270] Therefore, the first light-emitting element ED1 and the first element inorganic layer IO1 located in the portion superimposed with the first emission region EA1 can be formed as a (first) light-emitting structure.

[0271] Next, by repeating the above process, an initial material layer for forming the second light-emitting layer EL2, the cathode CE, the auxiliary electrode AX, and the inorganic layer IO is formed on the anode AE ​​stacked with the second emission region EA2. This is achieved by... Figures 22 to 24 The process shown is similar to current processes, which can form a second light-emitting element ED2 and a second element inorganic layer IO2 superimposed on the second emission region EA2.

[0272] Furthermore, by repeating the above process, an initial material layer for forming the third light-emitting layer EL3, the cathode CE, the auxiliary electrode AX, and the inorganic layer IO of the device is formed on the anode AE ​​stacked with the third emission region EA3. Figures 22 to 24 The process shown is similar to current processes, which can form a third light-emitting element ED3 and a third element inorganic layer IO3 superimposed on the third emission region EA3.

[0273] Therefore, refer to Figure 25 It can form with Figure 5 The image shows an ACTH-stacked display element layer EML with anode contact holes. Redundant descriptions will be omitted.

[0274] In the display device 10 of the embodiment, since the third dam layer BN3, which is the uppermost thickness portion of the dam, includes a tip, material patterns of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, which are spaced apart from each other, can be formed in the portions that are respectively superimposed with the first emission region EA1 to the third emission region EA3 without using a fine metal mask.

[0275] Furthermore, in the display device 10 of the embodiment, since the third embankment layer BN3 includes a tip, a material pattern of the cathode CE spaced apart from each other can be formed in the portion overlapping with the first emission region EA1 to the third emission region EA3 without using a fine metal mask. Therefore, the display device 10 of the embodiment can be easily manufactured.

[0276] Additionally, the display device 10 of the embodiment can planarize the steps included in the first conductive layer AEa, which has a recessed structure, by including an anode planarization layer APL that fills the anode contact hole ACTH in the portion overlapping with the anode contact hole ACTH. Therefore, the uppermost surface of the second conductive layer AEb for each anode AE ​​can be formed with a substantially flat surface, thereby allowing the material of the first light-emitting layer EL1, the second light-emitting layer EL2, or the third light-emitting layer EL3 to be formed with a uniform thickness. Thus, reliability defects of the display device 10 (e.g., light-emitting layer shading defects) can be resolved. Further redundant descriptions will be omitted.

[0277] Figure 26 This is a block diagram of electronic device 1 according to an embodiment.

[0278] Apart from Figures 1 to 25 In addition, refer to Figure 26 The display devices 10, 30, and 50 according to the embodiments can be applied to various electronic devices 1. The electronic device 1 according to the embodiments includes at least one of the above-described display devices 10, 30, and 50, and may also include modules or devices with other additional functions besides the display devices 10, 30, or 50.

[0279] The electronic device 1 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0280] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0281] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0282] The power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module that generates the power required for the operation of the electronic device 1 by converting the power supplied by the power module.

[0283] At least one of the components of the electronic device 1 described above may be included in the display device of the display devices 10, 30, and 50 according to the above embodiments. Furthermore, some of the modules functionally included in the electronic device 1 may be included in the display device of the display devices 10, 30, and 50, while other modules may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may not be disposed in the display device but rather in other devices within the electronic device 1.

[0284] Figure 27 These are schematic diagrams of electronic devices according to various embodiments.

[0285] Reference Figure 27 The various electronic devices 1 that employ the display devices 10, 30, and 50 according to the embodiments may include not only image display electronic devices (such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, televisions 1_1d, and desktop monitors 1_1e), but also wearable electronic devices (such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c) and vehicle electronic devices 1_3 (such as central information displays (CIDs) and interior mirror displays placed on the dashboard, central instrument panel, and instrument cluster of a vehicle) that include display modules.

[0286] According to a display device based on one or more embodiments, an electronic device 1 using the display device, and a method of manufacturing (or providing) the display device, high-resolution images can be provided and reliability defects of light-emitting elements included in the display device can be solved.

[0287] In an embodiment, electronic device 1 includes a display device and a display module, processor, memory, or power module connected to the display device. The display device (e.g., Figures 1 to 7 The display device 10 shown Figure 8 The display device 30 shown is or Figure 9The display device 50 shown includes: a substrate SUB including an emitting region EA and a non-emitting region NLA; a dam structure BN on the substrate SUB and in the dam structure BN, defining an anode contact hole ACTH in the emitting region EA, the dam structure BN having a side surface defining the anode contact hole ACTH and a hanging structure in the non-emitting region NLA; a first element insulating layer PDL1 on the dam structure BN and extending into the anode contact hole ACTH to cover the side surface of the dam structure BN; an anode AE ​​of a light-emitting element ED on the first element insulating layer PDL1 and in the emitting region EA, the anode AE ​​including a first conductive layer AEa and a second conductive layer AEb facing each other in the emitting region EA; an anode planarization layer APL located in the emitting region EA between the first conductive layer AEa and the second conductive layer AEb, the anode planarization layer APL comprising an organic material; and a second element insulating layer PDL2 covering the edge of the anode AE, and defining an opening OP in the second element insulating layer PDL2 overlapping with the anode contact hole ACTH, the second element insulating layer PDL2 contacting the first element insulating layer PDL1.

[0288] The display device may further include a circuit layer connected to a light-emitting element ED. A first conductive layer AEa may penetrate each of the first dam layer BN1, the second dam layer BN2, and the third dam layer BN3 to define a portion of the anode AE ​​exposed to the outside of the dam structure BN. Here, the light-emitting element ED may be electrically connected to the circuit layer at the portion of the anode AE.

[0289] However, the effects of this disclosure are not limited to those set forth herein. The above and other effects of this disclosure will become more apparent to those skilled in the art upon reference to the claims.

Claims

1. A display device, the display device comprising: The substrate includes both emitting and non-emitting regions; A dam structure, on the substrate, and in the dam structure, defining an anode contact hole in the emission region, the dam structure having a side surface defining the anode contact hole and a hanging structure in the non-emission region; A first element insulating layer is present on the dam structure and extends into the anode contact hole to cover the side surface of the dam structure; The anode of the light-emitting element is located on the insulating layer of the first element and in the emitting region, and the anode includes a first conductive layer and a second conductive layer facing each other in the emitting region; An anode planarization layer is located in the emission region between the first conductive layer and the second conductive layer, and the anode planarization layer comprises an organic material; as well as A second element insulating layer covers the edge of the anode and defines an opening in the second element insulating layer that overlaps with the anode contact hole, the second element insulating layer contacting the first element insulating layer.

2. The display device according to claim 1, wherein, The dike structure includes: The first, second, and third dike layers are arranged in the order of the base. Each of the first, second, and third embankment layers has a first side surface facing the non-emission region and a second side surface opposite the first side surface and defining a portion of the side surface of the embankment structure. The first side surface of the third embankment protrudes further than the first side surface of the second embankment to define the tip of the overhang structure, and The anode planarization layer penetrates the first dam layer, the second dam layer, and the third dam layer in the emission region.

3. The display device of claim 2, wherein, The first conductive layer is spaced apart from the first dam layer, the second dam layer and the third dam layer, and the first element insulating layer is located between the first conductive layer and the first dam layer, the second dam layer and the third dam layer.

4. The display device according to claim 3, wherein, The first conductive layer includes steps defined therein, and The anodic planarization layer located between the first conductive layer and the second conductive layer in the emission region flattens the step of the first conductive layer.

5. The display device according to claim 2, further comprising: The first light-emitting layer of the light-emitting element is on the anode and covers the entire insulating layer of the second element; The cathode of the light-emitting element is located on the first light-emitting layer; as well as An auxiliary electrode is placed on the cathode and contacts the tip of the third dam layer.

6. The display device of claim 5, wherein, The auxiliary electrode contacts the first side surface of the second dam layer and is spaced apart from the first dam layer in a direction perpendicular to the substrate.

7. The display device according to claim 1, wherein, The anolyte layer contacts the first conductive layer and the second conductive layer, and is completely surrounded by the first conductive layer and the second conductive layer.

8. The display device according to claim 7, wherein, The second conductive layer includes: The first part is stacked with the anode planarization layer, and The second part is stacked on top of and in contact with the first conductive layer.

9. The display device according to claim 1, wherein, The first conductive layer and the second conductive layer are in contact with each other in the non-emitting region, and The anode planarization layer is not superimposed on the non-emissive region.

10. The display device according to claim 1, wherein, The anodic planarization layer includes a first surface that faces the second conductive layer and is curved.

11. The display device according to claim 10, wherein, The first surface protrudes in the direction toward the second conductive layer.

12. The display device according to claim 10, wherein, The first surface is recessed in the direction toward the substrate.

13. A method of providing a display device, the method comprising the steps of: Provide a first element insulation layer on the dike structure; An anode contact hole is provided, the anode contact hole penetrating the insulating layer of the first element and the dam structure and overlapping with the emission area of ​​the display device; An anode for a light-emitting element is provided on the first element insulating layer in the emitting region by providing the following layers: a first conductive layer of the anode, the first conductive layer extending into the anode contact hole to form a recess in the first conductive layer; and an anode planarization layer, on the first conductive layer and in the anode contact hole. And the second conductive layer of the anode, which is stacked with both the first conductive layer and the anode planarization layer; A second element insulating layer is provided on the first element insulating layer and the second conductive layer, wherein an opening is defined in the second element insulating layer that overlaps with the anode contact hole; as well as The emission region provides a light-emitting layer of the light-emitting element, a cathode of the light-emitting element, an auxiliary electrode, and an inorganic layer of the element stacked on the anode.

14. The method according to claim 13, wherein, Providing the anode includes the following steps: An anode planarization layer is provided that extends out of the recess in the first conductive layer to define an extended portion of the anode planarization layer. The extended portion is removed by chemical mechanical polishing to provide a polished upper surface of the anode planarization layer that overlaps with the anode contact hole, and The second conductive layer is brought into contact with the polished upper surface of the anolyte layer.

15. An electronic device, the electronic device comprising: Display device; as well as A display module, processor, memory, or power module is connected to the display device. The display device includes: The substrate includes both emitting and non-emitting regions; A dam structure, on the substrate, and in the dam structure, defining an anode contact hole in the emission region, the dam structure having a side surface defining the anode contact hole and a hanging structure in the non-emission region; A first element insulating layer is present on the dam structure and extends into the anode contact hole to cover the side surface of the dam structure; The anode of the light-emitting element is located on the insulating layer of the first element and in the emitting region, and the anode includes a first conductive layer and a second conductive layer facing each other in the emitting region; An anode planarization layer, located in the emission region between the first conductive layer and the second conductive layer, the anode planarization layer comprising an organic material; and A second element insulating layer covers the edge of the anode and defines an opening in the second element insulating layer that overlaps with the anode contact hole, the second element insulating layer contacting the first element insulating layer.

16. The electronic device according to claim 15, wherein, The dike structure includes: The first, second, and third dike layers are arranged in the order of the base. Each of the first, second, and third embankment layers has a first side surface facing the non-emission region and a second side surface opposite the first side surface and defining a portion of the side surface of the embankment structure. The first side surface of the third embankment protrudes further than the first side surface of the second embankment to define the tip of the overhang structure, and The anode planarization layer penetrates the first dam layer, the second dam layer, and the third dam layer in the emission region.

17. The electronic device according to claim 16, wherein, The first conductive layer is spaced apart from the first dam layer, the second dam layer and the third dam layer, and the first element insulating layer is located between the first conductive layer and the first dam layer, the second dam layer and the third dam layer.

18. The electronic device according to claim 17, wherein, The first conductive layer includes steps defined therein, and The anodic planarization layer located between the first conductive layer and the second conductive layer in the emission region flattens the step of the first conductive layer.

19. The electronic device according to claim 15, wherein, The anolyte layer contacts the first conductive layer and the second conductive layer, and is completely surrounded by the first conductive layer and the second conductive layer.

20. The electronic device according to claim 19, wherein, The second conductive layer includes: The first portion is stacked with the anode planarization layer; and the second portion is stacked with and in contact with the first conductive layer.

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