Display panel and display device

Abstract

This application discloses a display panel and a display device, relating to the field of display technology. The display panel includes a substrate, multiple pixel units, and multiple signal lines. The second segment of a first type of signal line located in a non-pixel area is made of transparent material, thereby increasing the transparent display area of ​​the display panel and improving the transparent display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Display panels typically include multiple pixel units arranged in an array in the display area of ​​a substrate, and signal lines for providing drive signals to each pixel unit.

[0003] In related technologies, the substrate includes a display area and a peripheral area surrounding the display area. The two ends of the signal line are located in the peripheral area and are used to connect to the driving circuitry. The middle portion of the signal line is located in the display area and is used to connect to the pixel unit.

[0004] However, because the material of the signal line has low transmittance, the transparent display effect of the display panel is poor. Summary of the Invention

[0005] This application provides a display panel and display device that can solve the problem of poor transparency display effect of the display panel. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel comprising:

[0007] A substrate, the substrate including a display area;

[0008] Multiple pixel units are located in the display area. The multiple pixel units form a group of multiple pixel units arranged along a first direction and extending along a second direction. The group of pixel units includes multiple pixel units. The second direction intersects the first direction.

[0009] In addition, a plurality of signal lines arranged along the first direction and extending along the second direction, the signal lines being electrically connected to the pixel units, the plurality of signal lines including a first type of signal lines, the first type of signal lines including a first line segment and a second line segment electrically connected, the orthographic projection of the first line segment on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlapping and not located between adjacent pixel units arranged along the second direction, the orthographic projection of the second line segment on the substrate being at least located between adjacent pixel units arranged along the second direction, the material of the second line segment including a light-transmitting material.

[0010] Optionally, the first type of signal lines includes: data signal lines and sensing signal lines; the plurality of signal lines further includes a first power signal line and a second power signal line;

[0011] The pixel unit includes a pixel circuit and a light-emitting unit. The pixel circuit includes a plurality of thin-film transistors and at least one storage capacitor. The light-emitting unit includes an anode, a light-emitting portion, and a cathode. The pixel circuit and the anode of the light-emitting unit are electrically connected.

[0012] The data signal line, the sensing signal line, and the first power signal line are all electrically connected to the thin-film transistor in the pixel circuit. The second power signal line is electrically connected to the cathode in the light-emitting unit. The potential of the first power signal line providing the first power signal to the pixel unit is higher than the potential of the second power signal line providing the second power signal to the pixel unit.

[0013] Optionally, the plurality of signal lines may further include a second type of signal line, wherein the material of the second type of signal line includes a non-transparent material;

[0014] The plurality of signal lines constitute a plurality of signal line groups arranged along the first direction and corresponding to the plurality of pixel unit groups; the plurality of signal line groups include a first signal line group and a second signal line group arranged along the first direction and adjacent to each other, and at least one of the first signal line group and the second signal line group includes a first power signal line and a second power signal line.

[0015] In the signal line group that includes the first power signal line and the second power signal line, one of the first power signal line and the second power signal line is a first type of signal line, and the other is a second type of signal line.

[0016] Optionally, the first signal line group includes the first power signal line, and the second signal line group includes the first power signal line and the second power signal line; the display panel further includes: a first connection signal line extending along the first direction;

[0017] One end of the first connection signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group.

[0018] Optionally, the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group;

[0019] Among them, the first power signal line in the second signal line group is a first type of signal line, and the first power signal line in the second signal line group is a second type of signal line.

[0020] Optionally, both the first signal line group and the second signal line group include the first power signal line and the second power signal line; the display panel further includes: a first connection signal line and a second connection signal line extending along the first direction;

[0021] One end of the first connecting signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group. One end of the second connecting signal line is connected to the second power signal line in the first signal line group, and the other end is connected to the second power signal line in the second signal line group.

[0022] Optionally, the second power signal line in the first signal line group is closer to the second signal line group than the first power signal line in the first signal line group, and the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group.

[0023] Among them, the second power signal line in the first signal line group and the first power signal line in the second signal line group are both Class I signal lines, and the first power signal line in the first signal line group and the second power signal line in the second signal line group are both Class II signal lines.

[0024] Optionally, the display panel includes: a pixel unit layer, the pixel unit layer including a pixel circuit layer and a light-emitting unit layer, the pixel circuit layer including pixel circuits of the plurality of pixel units, and the light-emitting unit layer including light-emitting units of the plurality of pixel units;

[0025] The pixel circuit layer includes: a light-shielding conductive layer, a light-transmitting conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer, which are sequentially stacked along the direction away from the substrate.

[0026] The light-emitting unit layer includes: an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer stacked sequentially in a direction away from the substrate.

[0027] Wherein, the first line segment is located in the light-shielding conductive layer, the second line segment is located in the light-transmitting conductive layer, and the second line segment and the first line segment overlap and are electrically connected in contact;

[0028] The active layer includes an active pattern of a thin-film transistor, and the gate layer includes a gate, a source, and a drain of a thin-film transistor. The gate is located between the source and the drain, and the source and the drain are electrically connected to the active pattern through vias in the gate insulating layer.

[0029] The anode layer is made of a light-transmitting material. The anode layer includes the anode of the light-emitting unit of the plurality of pixel units. The pixel defining layer includes a plurality of pixel openings for exposing at least a portion of the anode. The light-emitting functional layer includes the light-emitting portion of the light-emitting unit of the plurality of pixel units. The light-emitting portion is located within the pixel opening and is connected to at least a portion of the anode exposed by the pixel opening. The cathode layer includes the cathode of the light-emitting unit of the plurality of pixel units, and the cathode is connected to the light-emitting portion.

[0030] Optionally, the anode in the light-emitting unit of each pixel unit includes a first anode portion and a second anode portion arranged at intervals; the display panel further includes a maintenance structure, which includes a first maintenance section and a second maintenance section;

[0031] The first repair section is electrically connected to the pixel circuit, the second repair section is electrically connected to the first repair section, and the first end of the second repair section is electrically connected to the first anode section, the second end of the second repair section is electrically connected to the second anode section, and the first end and the second end of the second repair section are respectively located on both sides of the position where the second repair section and the first repair section are electrically connected;

[0032] The first repair section is located in the light-transmitting conductive layer, and the second repair section is located in the anode layer.

[0033] Optionally, the display panel further includes: a connection portion located on the gate layer, wherein the orthographic projection of the connection portion on the substrate and the orthographic projection of the first repair portion on the substrate have a first overlapping area, and the orthographic projection of the connection portion on the substrate and the orthographic projection of the second repair portion on the substrate have a second overlapping area, wherein the first overlapping area and the second overlapping area do not overlap;

[0034] The connection portion and the first maintenance portion are electrically connected in the first overlap region through vias in the gate insulating layer and the buffer layer, and the connection portion and the second maintenance portion are electrically connected in the second overlap region through vias in the passivation layer and the planarization layer.

[0035] Optionally, the target power trace in the first power signal line and the second power signal line of the plurality of signal lines includes a first power line portion and a second power line portion located in the light-shielding conductive layer, and a third power line portion located in the gate layer.

[0036] Both the first power line portion and the second power line portion extend along the second direction, and the first power line portion and the second power line portion are spaced apart in the second direction. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the first power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the first power line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the second power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the second power line portion through vias in the gate insulating layer and the buffer layer.

[0037] Optionally, the storage capacitor included in the pixel circuit includes a first capacitor plate located in the light-shielding conductive layer and a second capacitor plate located in the gate layer, wherein the orthographic projection of the second capacitor plate on the substrate and the orthographic projection of the first capacitor plate on the substrate at least partially overlap.

[0038] The first repair section is a strip-shaped structure extending along the first direction. The first end of the first repair section overlaps with the first capacitor plate and is electrically connected. The second end of the first repair section is located on the side of the target power line away from the first capacitor plate.

[0039] The first repair section is at least partially located at the interval between the first power cord section and the second power cord section in the second direction.

[0040] Optionally, the plurality of signal lines includes a plurality of data signal lines, wherein the orthographic projection of the first target data signal line among the plurality of data signal lines on the substrate is located between the orthographic projection of the first end of the first repair part on the substrate and the orthographic projection of the second end of the first repair part on the substrate.

[0041] The first target data signal line includes: at least a first data line portion and a second data line portion located in the transparent conductive layer, and a third data line portion located in the gate layer;

[0042] Both the first data line portion and the second data line portion extend along the second direction, and the first data line portion and the second data line portion are spaced apart in the second direction. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the first data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the first data line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the second data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the second data line portion through vias in the gate insulating layer and the buffer layer.

[0043] The first repair section is located at least partially between the first data line portion and the second electrical data line portion in the second direction.

[0044] Optionally, the plurality of data signal lines further includes a second target data signal line, wherein the orthographic projection of the second target data signal line on the substrate and the orthographic projection of the first repair part on the substrate are spaced apart in the first direction; the second target data signal line is located at least in the transparent conductive layer.

[0045] Optionally, the first data line portion, the second data line portion, and the second target data signal line are also located in a light-shielding conductive layer;

[0046] The orthographic projections of the first data line portion, the second data line portion, and the portion of the second target data signal line located on the light-shielding conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction.

[0047] The orthographic projections of the first data line portion, the second data line portion, and the second target data signal line portion located on the transparent conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

[0048] Optionally, the orthographic projections of the sensing signal lines on the substrate and the orthographic projections of the first repair part on the substrate are spaced apart in the first direction; the sensing signal lines are located at least in the transparent conductive layer.

[0049] Optionally, the sensing signal line is also located in a light-shielding conductive layer;

[0050] The orthographic projection of the portion of the sensing signal line located on the light-shielding conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction;

[0051] The orthographic projection of the portion of the sensing signal line located on the transparent conductive layer onto the substrate and the orthographic projection of the pixel unit onto the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

[0052] Optionally, the display panel further includes: a transition structure, the transition structure including a first transition portion located in the transparent conductive layer, a second transition portion located in the gate layer, and a third transition portion located in the anode layer;

[0053] The first adapter is a strip-shaped structure extending along the first direction. The first end of the first adapter is electrically connected to the second power signal line in the display panel. The second end of the first adapter is electrically connected to the second adapter through vias in the gate insulating layer and the buffer layer. The third adapter is electrically connected to the second adapter through vias in the planarization layer and the passivation layer. The third adapter is electrically connected to the cathode layer.

[0054] Optionally, the anode layer includes a first material layer, a second material layer, and a third material layer stacked in a direction away from the substrate, wherein the material etching rates of the first material layer and the third material layer are lower than the material etching rate of the second material layer;

[0055] The third transition portion includes a first portion located in the first material layer, a second portion located in the second material layer, and a third portion located in the third material layer, wherein the boundary of the second portion is recessed relative to the boundaries of the first portion and the third portion;

[0056] The light-emitting functional layer further includes an electronic functional layer and a hole functional layer. The electronic functional layer and the hole functional layer are integral film layers, and the electronic functional layer and the hole functional layer are in a broken state at the boundary of the third part. The cathode layer is electrically connected to the second part through the broken positions of the electronic functional layer and the hole functional layer.

[0057] On the other hand, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0058] The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

[0059] The beneficial effects of the technical solution provided in this application include at least the following:

[0060] This application provides a display panel and a display device. The display panel includes a substrate, multiple pixel units, and multiple signal lines. The second segment of a first type of signal line located in a non-pixel area is made of a transparent material, thereby increasing the transparent display area of ​​the display panel and improving the transparent display effect. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a partial top view of a display panel provided in an embodiment of this application;

[0063] Figure 2 This is an equivalent circuit diagram of a pixel unit provided in an embodiment of this application;

[0064] Figure 3 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0065] Figure 4 This is a partial top view of another display panel provided in an embodiment of this application;

[0066] Figure 5 This is a partial top view of another display panel provided in the embodiments of this application;

[0067] Figure 6 This is a partial top view of another display panel provided in an embodiment of this application;

[0068] Figure 7 This is a partial top view of a light-transmitting conductive layer provided in an embodiment of this application;

[0069] Figure 8 This is a partial top view of a light-shielding conductive layer provided in an embodiment of this application;

[0070] Figure 9 This is a partial top view of a stack of a light-transmitting conductive layer and a light-shielding conductive layer provided in an embodiment of this application;

[0071] Figure 10 This is a partial top view of an active layer provided in an embodiment of this application;

[0072] Figure 11 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, and an active layer provided in an embodiment of this application;

[0073] Figure 12 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, and a gate insulating layer provided in an embodiment of this application.

[0074] Figure 13 This is a partial top view of a gate layer provided in an embodiment of this application;

[0075] Figure 14 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, and a gate layer provided in an embodiment of this application.

[0076] Figure 15 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided in an embodiment of this application.

[0077] Figure 16 This is a partial top view of a flat layer provided in an embodiment of this application;

[0078] Figure 17 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer provided in an embodiment of this application.

[0079] Figure 18 This is a partial top view of an anode layer provided in an embodiment of this application;

[0080] Figure 19 This is a partial top view of a stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, a planarization layer, and an anode layer provided in an embodiment of this application.

[0081] Figure 20 This is a partial top view of a stack of a planarization layer, an anode layer, and a pixel-defining layer provided in an embodiment of this application;

[0082] Figure 21 This is a partial cross-sectional schematic diagram of a transition structure provided in an embodiment of this application;

[0083] Figure 22 This is a partial top view of another light-transmitting conductive layer provided in the embodiments of this application;

[0084] Figure 23 This is a partial top view of another light-shielding conductive layer provided in the embodiments of this application;

[0085] Figure 24 This is a partial top view of another stack of a light-transmitting conductive layer and a light-shielding conductive layer provided in an embodiment of this application;

[0086] Figure 25 This is a partial top view of another active layer provided in an embodiment of this application;

[0087] Figure 26 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, and an active layer provided in an embodiment of this application;

[0088] Figure 27 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, and a gate insulating layer provided in the embodiments of this application.

[0089] Figure 28 This is a partial top view of another gate layer provided in an embodiment of this application;

[0090] Figure 29 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, and a gate layer provided in the embodiments of this application.

[0091] Figure 30 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided in the embodiments of this application.

[0092] Figure 31 This is a partial top view of another flat layer provided in an embodiment of this application;

[0093] Figure 32 This is a partial top view of another stack of a transparent conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer provided in the embodiments of this application.

[0094] Figure 33 This is a partial top view of another anode layer provided in an embodiment of this application;

[0095] Figure 34 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, a planarization layer, and an anode layer provided in the embodiments of this application.

[0096] Figure 35 This is a partial top view of another stack of a light-transmitting conductive layer, a light-shielding conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided in the embodiments of this application.

[0097] Figure 36 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0099] Currently, the most mature display technologies include liquid crystal display (LCD) and active-matrix organic light-emitting diode (OLED) displays. OLED display panels generally form patterns by exciting various wavelengths of light through the recombination of electrons and holes. Display devices made with OLED panels are self-emissive, have fast response times, and can achieve maximum contrast, thus OLED displays are expected to become the next generation of mainstream display products.

[0100] Figure 1 This is a partial top view of a display panel provided in an embodiment of this application. (Reference) Figure 1 As can be seen, the display panel 100 includes: a substrate 101, multiple pixel units 102, and multiple signal lines 103.

[0101] The substrate 101 includes a display area. Figure 1 This can be a partial top view of the portion of the display panel 100 located within the display area. (Reference) Figure 1 Multiple pixel units 102 may be located in display area 101a. The multiple pixel units 102 constitute a group of multiple pixel units 102z arranged along a first direction X and extending along a second direction Y. The pixel unit group 102z includes multiple pixel units 102. The second direction Y intersects the first direction X. Figure 1 The image shows a portion of a pixel unit group 102z.

[0102] Optionally, the second direction Y is perpendicular to the first direction X. For example, the first direction X is the pixel row direction of the display panel 100, and the second direction Y is the pixel column direction of the display panel 100.

[0103] refer to Figure 1Multiple signal lines 103 are arranged along a first direction X and extend along a second direction Y. The signal lines 103 are electrically connected to pixel units 102 and provide driving signals to the pixel units 102. The multiple signal lines 103 include a first type of signal line 1031. The first type of signal line 1031 includes a first segment 10311 and a second segment 10312 that are electrically connected. The orthographic projection of the first segment 10311 onto the substrate 101 at least partially overlaps with the orthographic projection of the pixel unit 102 onto the substrate 101, but is not located between adjacent pixel units 102 arranged along the second direction Y. The orthographic projection of the second segment 10312 onto the substrate 101 is at least located between adjacent pixel units 102 arranged along the second direction Y. The material of the second segment 10312 includes a light-transmitting material.

[0104] In this embodiment, the area projected orthographically onto the substrate 101 by the pixel unit 102 can be a pixel region, and the area projected orthographically onto the substrate 101 by the region between the pixel units 102 can be a non-pixel region. Typically, because the pixel region has pixel units 102, while the non-pixel region does not, the transparency of the pixel region is lower than that of the non-pixel region. Therefore, to improve the transparency of the display panel 100, the area of ​​the non-pixel region can be increased.

[0105] Optionally, since the signal lines 103 in the display panel 100 need to transmit signals, the material used to fabricate the signal lines 103 needs to be a metal material with low sheet resistance. Because metal materials have poor transparency, the solution in this embodiment sets the first type of signal lines 1031 among the multiple signal lines 103 as segmented signal lines, and sets the first segment 10311 of the first type of signal lines 1031 located in the pixel area as a non-transparent material (such as a metal material) to ensure signal transmission, and sets the second segment 10312 of the first type of signal lines 1031 located in the non-pixel area as a transparent material (such as indium tin oxide, ITO) to improve the transparent display effect in the non-pixel area.

[0106] Optionally, indium tin oxide (ITO) has a higher sheet resistance than metallic materials. Therefore, setting the material of the second segment 10312 of the first type signal line 1031 as indium tin oxide may have a certain impact on the reliability of signal transmission on the signal line 103. Therefore, in order to reduce the impact on signal transmission, the first type signal line 1031, which has lower requirements for the stability of signal transmission, can be set as a segmented signal line with transparent segments among the multiple signal lines 103 of the display panel 100.

[0107] In summary, this application provides a display panel including a substrate, multiple pixel units, and multiple signal lines. The second segment of the first type of signal lines located in the non-pixel area is made of transparent material, thereby increasing the transparent display area of ​​the display panel and improving the transparent display effect.

[0108] refer to Figure 1 As can be seen, in addition to setting the first type signal line 1031 as a segmented signal line to make the area between adjacent pixel units 102 arranged along the second direction Y transparent, the area between adjacent pixel unit groups 102z arranged along the first direction X in the multiple pixel unit groups 102z can also be a transparent display area. This allows the display panel 100 to have a larger transparent display area, improving the overall transmittance of the display panel 100 and ensuring the transparent display effect of the display panel 100. Furthermore, it eliminates the long black line display of the first type signal line 1031 when the display panel 100 is in the off state (i.e., when not displayed), instead transforming it into a discontinuous, virtual black line, further improving the transparent display effect of the display panel 100.

[0109] In this embodiment, since the signal transmitted by the data signal line is a data signal, the stability requirement is relatively low. Therefore, the data signal line can be set as a segmented signal line including a transparent segment (second segment 10312). That is, the first type of signal line 1031 can include a data signal line.

[0110] Furthermore, since sensing signal lines are typically used to transmit various control signals, their primary focus is on signal transmission speed and efficiency, with relatively low requirements for stability. Therefore, sensing signal lines can also be configured as segmented signal lines including transparent segments (second segment 10312). That is, the first type of signal line 1031 can include sensing signal lines.

[0111] Optionally, in addition to data signal lines and sense signal lines, the multiple signal lines 103 may also include a first power signal line and a second power signal line. Both the first power signal line (VDD) and the second power signal line are used to provide power signals to the pixel unit 102. For example, the potential of the first power signal provided by the first power signal line to the pixel unit is higher than the potential of the second power signal provided by the second power signal line to the pixel unit 102. The first power signal line can be a positive power supply trace (or VDD trace), and the second power signal line can be a negative power supply trace (or VSS trace).

[0112] Figure 2 This is an equivalent circuit diagram of a pixel unit provided in an embodiment of this application. (Reference) Figure 2 The pixel unit 102 includes a pixel circuit 1021 and a light-emitting unit 1022. The pixel circuit 1021 may include a plurality of thin film transistors (TFTs) and at least one storage capacitor.

[0113] For example Figure 2 The diagram illustrates a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst, meaning the pixel circuit 1021 can be a 3T1C pixel circuit. Of course, the pixel circuit 1021 can also include other numbers of transistors and other numbers of storage capacitors. This application does not impose specific limitations on the number of transistors and storage capacitors included in the pixel circuit 1021.

[0114] Optionally, the first transistor T1, the second transistor T2, and the third transistor T3 can all be N-type transistors (denoted as NTFT), such as oxide thin-film transistors.

[0115] Figure 3 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application. (Reference) Figure 3 The light-emitting unit 1022 includes an anode 10221, a light-emitting portion 10222, and a cathode 10223. (Combined) Figure 2 and Figure 3 The pixel circuit 1021 and the anode 10221 of the light-emitting unit 1022 are electrically connected. The data signal line, the sense signal line, and the first power signal line VDD are all electrically connected to the thin-film transistor in the pixel circuit 1021, and the second power signal line VSS is electrically connected to the cathode 10223 in the light-emitting unit 1022. Optionally, the display panel 100 also includes multiple gate signal lines (scans) arranged along the second direction Y and extending along the first direction X.

[0116] refer to Figure 2 The gate of the first transistor T1 is connected to the gate signal line, the first electrode of the first transistor T1 is connected to the data signal line, and the second electrode of the first transistor T1 is connected to the first node J1.

[0117] The gate of the second transistor T2 is connected to the gate signal line, the first terminal of the second transistor T2 is connected to the sensing signal line, and the second terminal of the second transistor T2 is connected to the second node J2.

[0118] The gate of the third transistor T3 is connected to the first node J1, the first terminal of the third transistor T3 is connected to the first power supply signal line VDD, and the second terminal of the third transistor T3 is connected to the second node J2.

[0119] The first terminal of the storage capacitor Cst is connected to the first node J1, and the second terminal of the storage capacitor Cst is connected to the second node J2.

[0120] Furthermore, the anode 10221 of the light-emitting unit 1022 can be connected to the second node J2 of the pixel circuit 1021, and the cathode 10223 of the light-emitting unit 1022 can be connected to the second power signal line VSS.

[0121] Optional, see reference Figure 4 Multiple signal lines 103 constitute multiple signal line groups 103z arranged along the first direction X and corresponding to multiple pixel unit groups 102z. The multiple signal line groups 103z include a first signal line group 103z1 and a second signal line group 103z2 arranged adjacent to each other along the first direction X. At least one of the first signal line group 103z1 and the second signal line group 103z2 includes a first power signal line VDD and a second power signal line VSS. For example... Figure 4 In the above, the first signal line group 103z1 and the second signal line group 103z2 both include a first power signal line VDD and a second power signal line VSS.

[0122] In this embodiment, the multiple signal lines 103 may include a second type of signal line 1032, and the material of the second type of signal line 1032 includes a non-transparent material. The fact that the material of the second type of signal line 1032 is a non-transparent material means that the entire second type of signal line 1032 is made of a non-transparent material, and it is not a segmented signal line that includes transparent segments. For example... Figure 4 In the first signal line group 103z1 and the second signal line group 103z2, the first power signal line VDD and the second power signal line VSS are both second type signal lines 1032.

[0123] Since both the first power signal line VDD and the second power signal line VSS are used to provide power voltage, the stability requirements for the signal are relatively high. Therefore, the first power signal line VDD and the second power signal line VSS can be the second type of signal line 1032 included in multiple signal lines 103, which can ensure the stability and reliability of the transmission of the first power signal line VDD and the second power signal line VSS.

[0124] Of course, to further increase the area of ​​the transparent display area of ​​the display panel 100, in every two adjacent signal line groups 103z, one signal line group 103z's first power signal line VDD can be designated as a first-type signal line 1031, and the other signal line group 103z's first power signal line VDD can be designated as a second-type signal line 1032. Simultaneously, to ensure the stability and reliability of the first power signal transmission, the first power signal lines VDD of these two signal line groups 103z can be connected using a single connecting signal line extending along the first direction X. Furthermore, in every two adjacent signal line groups 103z, one signal line group 103z's second power signal line VSS can be designated as a first-type signal line 1031, and the other signal line group 103z's second power signal line VSS can be designated as a second-type signal line 1032. Simultaneously, to ensure the stability and reliability of the second power signal transmission, the second power signal lines VSS of these two signal line groups 103z can be connected using a single connecting signal line extending along the first direction X.

[0125] Optionally, in the signal line group 103z including the first power signal line VDD and the second power signal line VSS, one of the power signal lines 103 is a first type signal line 1031, and the other is a second type signal line 1032.

[0126] As an optional implementation, refer to Figure 5 The first signal line group 103z1 and the second signal line group 103z2 both include a first power signal line VDD and a second power signal line VSS. The display panel 100 also includes a first connection signal line L1 and a second connection signal line L2 extending along the first direction X.

[0127] One end of the first connecting signal line L1 is connected to the first power signal line VDD in the first signal line group 103z1, and the other end is connected to the first power signal line VDD in the second signal line group 103z2. One end of the second connecting signal line L2 is connected to the second power signal line VSS in the first signal line group 103z1, and the other end is connected to the second power signal line VSS in the second signal line group 103z2.

[0128] For example, the second power signal line VSS in the first signal line group 103z1 is closer to the second signal line group 103z2 than the first power signal line VDD in the first signal line group 103z1. The first power signal line VDD in the second signal line group 103z2 is closer to the first signal line group 103z1 than the second power signal line VSS in the second signal line group 103z2. That is, the arrangement order of the first power signal line VDD and the second power signal line VSS in the first signal line group 103z1 and the second power signal line VDD and the second power signal line VSS in the second signal line group 103z2 can be: first power signal line VDD of the first signal line group 103z1, second power signal line VSS of the first signal line group 103z1, first power signal line VDD of the second signal line group 103z2, and second power signal line VSS of the second signal line group 103z2. That is, the second power signal line VSS of the first signal line group 103z1 and the first power signal line VDD of the second signal line group 103z2 can be located between the first power signal line VDD of the first signal line group 103z1 and the second power signal line VSS of the second signal line group 103z2.

[0129] To increase the area of ​​the transparent display region, the two power signal lines located in the middle can be segmented signal lines (i.e., first-type signal lines 1031) that include the transparent segment. Specifically, the second power signal line VSS in the first signal line group 103z1 and the first power signal line VDD in the second signal line group 103z2 are both first-type signal lines 1031. Furthermore, the first power signal line VDD in the first signal line group 103z1 and the second power signal line VSS in the second signal line group 103z2 are both second-type signal lines 1032.

[0130] refer to Figure 5 As can be seen, the first transparent display area A1 between adjacent pixel units 102 arranged along the second direction Y can be connected to the second transparent display area A2 between adjacent pixel unit groups 102z arranged along the first direction X, further increasing the area of ​​the transparent display area, improving the overall transmittance of the display panel 100, and ensuring the transparent display effect of the display panel 100. Furthermore, it can further improve the display effect of the display panel 100 in the off state.

[0131] It should be noted that since the gate signal lines scan included in the display panel 100 can be made of metal (not a light-transmitting material), multiple gate signal lines extending along the first direction X will divide the transparent display area between adjacent pixel unit groups 102z arranged along the first direction X into multiple sub-transparent display areas arranged along the second direction Y. Accordingly, the connection between the first transparent display area and the second transparent display area described above can mean that the second transparent display area A2 can be connected to the nearest first transparent display area A1.

[0132] Optionally, the reason why the display panel 100 needs to include a first connection signal line L1 and a second connection signal line L2 is that the first power signal line VDD or the second power signal line VSS of the signal line group 103z is set as a first-type signal line 1031. In this case, to ensure the stability and reliability of the power signal transmission of the first connection signal line L1 and the second connection signal line L2, the materials of the first connection signal line L1 and the second connection signal line L2 can be made of a metal material with low sheet resistance.

[0133] Typically, metallic materials have poor light transmittance. Therefore, to reduce the impact of the placement of the first connection signal line L1 and the second connection signal line L2 on transparent displays, both the first connection signal line L1 and the second connection signal line L2 can be placed in the region close to the gate signal line. For example... Figure 5 The diagram shows two gate signal lines, scan1. A first connection signal line L1 can be located below the first gate signal line scan1, and a second connection signal line L2 can be located above the second gate signal line scan2. Furthermore, the distances between the first connection signal line L1 and the first gate signal line scan1, as well as the distances between the second connection signal line L2 and the second gate signal line scan2, are both small. In this case, the upper and lower boundaries of the second transparent display area A2 can be defined by the first connection signal line L1 and the second connection signal line L2.

[0134] As another alternative implementation, refer to Figure 6 The first signal line group 103z1 includes a first power signal line VDD, and the second signal line group 103z2 includes a first power signal line VDD and a second power signal line VSS. Alternatively, it can be understood that the second power signal line VSS of the first signal line group 103z1 and the second signal line group 103z2 are shared, and this shared second power signal line VSS is located at the location of the second signal line group 103z2.

[0135] exist Figure 6In this configuration, the first power signal line VDD in the second signal line group 103z2 is closer to the first signal line group 103z1 than the second power signal line VSS in the second signal line group 103z2. In this case, the first power signal line VDD included in the second signal line group 103z2 is a first-type signal line 1031, and the second power signal line VSS included in the second signal line group 103z2 is a second-type signal line 1032. In this configuration, to ensure the stability and reliability of the first power signal line VDD transmitting the first power signal, the display panel further includes a first connection signal line L1 extending along the first direction X. One end of the first connection signal line L1 is connected to the first power signal line VDD in the first signal line group 103z1, and the other end is connected to the first power signal line VDD in the second signal line group 103z2.

[0136] refer to Figure 6 It can be seen that the first transparent display area A1 between adjacent pixel units 102 arranged along the second direction Y can be connected with the second transparent display area A2 between adjacent pixel unit groups 102z arranged along the first direction X, which further increases the area of ​​the transparent display area and ensures the transparent display effect of the display panel 100.

[0137] It should be noted that since the gate signal lines scan included in the display panel 100 can be made of metal (not a light-transmitting material), multiple gate signal lines extending along the first direction X will divide the transparent display area between adjacent pixel unit groups 102z arranged along the first direction X into multiple sub-transparent display areas arranged along the second direction Y. Accordingly, the connection between the first transparent display area A1 and the second transparent display area A2 described above can mean that the second transparent display area A2 can be connected to the nearest first transparent display area A1.

[0138] Optionally, the reason why a first connection signal line L1 is required in the display panel 100 is that the first power signal line VDD of the first signal line group 103z1 in two adjacent signal line groups 103z is set as a first type signal line 1031. In this case, in order to ensure the stability and reliability of the first power signal transmitted by the first connection signal line L1, the material of the first connection signal line L1 can be a metal material with low sheet resistance.

[0139] Typically, metallic materials have poor light transmittance. Therefore, to reduce the impact of the first connection signal line L1 on transparent displays, it can be positioned near the gate signal line. For example... Figure 6The diagram shows two gate signal lines, with the first connection signal line L1 located above the second gate signal line scan2. Furthermore, the distance between the first connection signal line L1 and the second gate signal line scan2 is small. In this case, the upper and lower boundaries of the second transparent display area A2 can be defined by the first gate signal line scan1 and the first connection signal line L1.

[0140] refer to Figure 3 As can be seen, the display panel 100 includes a pixel unit 102 layer. The pixel unit 102 layer includes a pixel circuit layer M and a light-emitting unit layer N. The pixel circuit layer M includes pixel circuits 1021 of multiple pixel units 102, and the light-emitting unit layer N includes light-emitting units 1022 of multiple pixel units 102.

[0141] Optionally, the pixel circuit layer M includes: a light-transmitting conductive layer m1, a light-shielding conductive layer (SHL) m2, a buffer layer m3, an active layer (poly) m4, a gate insulator (GI) layer m5, a gate layer m6, a passivation layer (PVX) m7, and a planarization layer (PLN) m8, stacked sequentially along a direction away from the substrate 101. Optionally, the material of the light-transmitting conductive layer m1 can be indium tin oxide (ITO). The material of the planarization layer m8 can be resin.

[0142] The light-emitting unit layer N includes: an anode layer n1, a pixel definition layer (PDL) n2, a light-emitting functional layer n3, and a cathode layer n4, which are stacked sequentially along the direction away from the substrate 101.

[0143] The first segment 10311 can be located in the light-shielding conductive layer m2, and the second segment 10312 can be located in the light-transmitting conductive layer m1. Since there is no insulating layer between the light-shielding conductive layer m2 and the light-transmitting conductive layer m1, the second segment 10312 and the first segment 10311 can be electrically connected by overlapping and direct contact.

[0144] The active layer m4 includes the active pattern m41 of the thin-film transistor, and the gate layer m6 includes the gate, source, and drain of the thin-film transistor. The gate is located between the source and drain, and the source and drain are electrically connected through vias and the active pattern in the gate insulating layer m5. Figure 3In this embodiment, the gate, source, and drain of the thin-film transistor are located on the same layer, which can reduce the number of film layers in the display panel 100 and simplify the manufacturing process of the display panel 100. Of course, the source and drain of the thin-film transistor can also be located on different layers from the gate of the thin-film transistor, and this embodiment does not limit this.

[0145] The anode layer n1 is made of a light-transmitting material, such as indium tin oxide (ITO). The anode layer n1 includes the anode 10221 of the light-emitting units 1022 of the multiple pixel units 102. The pixel defining layer n2 includes multiple pixel openings n21, which expose at least a portion of the anode 10221. The light-emitting functional layer n3 includes the light-emitting portions 10222 of the light-emitting units 1022 of the multiple pixel units 102. The light-emitting portions 10222 may be located within the pixel openings n21 and connected to at least a portion of the anode 10221 exposed by the pixel openings n21. The cathode layer n4 includes the cathode 10223 of the light-emitting units 1022 of the multiple pixel units 102, and the cathode 10223 is connected to the light-emitting portions 10222. Optionally, the cathodes 10223 of the light-emitting units 1022 of the multiple pixel units 102 may be interconnected, meaning the cathode layer n4 can be a single, continuous film layer.

[0146] Optionally, the light-emitting functional layer n3, in addition to the light-emitting portion 10222 of the light-emitting unit 1022 of the multiple pixel units 102, may also include an electronic functional layer and a hole functional layer. The electronic functional layer may include an electron injection layer (EIL), an electron transport layer (ETL), and an electron blocking layer (EBL), etc. The hole functional layer may include a hole injection layer (HIL), a hole transport layer (HTL), and a hole blocking layer (HBL), etc. The electronic functional layer and the hole functional layer may be integral film layers, i.e., covering the entire substrate 101.

[0147] refer to Figure 1 ,as well as Figures 4 to 6As can be seen, the anode 10221 of the light-emitting unit 1022 in each pixel unit 102 includes a first anode portion 102211 and a second anode portion 102212 arranged at intervals. The areas where the first anode portion 102211 and the second anode portion 102212 are located in the light-emitting unit 1022 can both be the light-emitting areas of the light-emitting unit 1022. The display panel 100 also includes a maintenance structure 104. The maintenance structure 104 includes a first maintenance section 1041 and a second maintenance section 1042.

[0148] The first repair section 1041 is electrically connected to the pixel circuit 1021. For example, the first repair section 1041 can be electrically connected to the second node J2 in the pixel circuit 1021. The second repair section 1042 is electrically connected to the first repair section 1041. The first end of the second repair section 1042 is electrically connected to the first anode section 102211, and the second end of the second repair section 1042 is electrically connected to the second anode section 102212. The first end and the second end of the second repair section 1042 are located on both sides of the electrical connection point between the second repair section 1042 and the first repair section 1041. The first repair section 1041 is located in the light-transmitting conductive layer m1, and the second repair section 1042 is located in the anode layer n1.

[0149] In this embodiment, the anode 10221 of the light-emitting unit 1022 of the pixel unit 102 is divided into a first anode portion 102211 and a second anode portion 102212, and a maintenance structure 104 is provided. When the light emission of one of the anode portions 102211 and 102212 of the light-emitting unit 1022 is abnormal, the connection between the maintenance structure 104 and that anode portion can be directly cut off, thereby preventing abnormal display of the display panel 100. In this case, the other anode portion of the light-emitting unit 1022 can be displayed normally, ensuring the reliability of the display panel 100.

[0150] Furthermore, since both the light-transmitting conductive layer m1 and the anode layer n1 are made of light-transmitting materials, the first maintenance part 1041 of the maintenance structure 104 is disposed in the light-transmitting conductive layer m1 and the second maintenance part 1042 is disposed in the anode layer n1. This avoids the maintenance structure 104 from causing a significant impact on the transparent display of the display panel 100.

[0151] Optionally, since the second repair section 1042 is electrically connected to the first anode section 102211 and the second anode section 102212, and the second repair section 1042, the first anode section 102211 and the second anode section 102212 are all located in the anode layer n1, the second repair section 1042, the first anode section 102211 and the second anode section 102212 can be an integral structure.

[0152] In this embodiment, the repair architecture 104 further includes a connection portion 1043 located on the gate layer m6. The orthographic projection of the connection portion 1043 on the substrate 101 and the orthographic projection of the first repair portion 1041 on the substrate 101 have a first overlapping region. The orthographic projection of the connection portion 1043 on the substrate 101 and the orthographic projection of the second repair portion 1042 on the substrate 101 have a second overlapping region. The first and second overlapping regions may not overlap.

[0153] Optionally, the connection portion 1043 and the first maintenance portion 1041 are electrically connected in the first overlapping region through a first via K1 in the gate insulating layer m5 and the buffer layer m3, and the connection portion 1043 and the second maintenance portion 1042 are electrically connected in the second overlapping region through a second via K2 in the passivation layer m7 and the planarization layer m8.

[0154] Since the connection portion 1043 is located in the gate layer m6, and the material of the gate layer m6 is usually a non-transparent material, in order to reduce the impact of the connection portion 1043 on the transparent display, the size of the connection portion 1043 can be minimized as much as possible while ensuring the electrical connection between the first maintenance portion 1041 and the second maintenance portion 1042. For example, the size of the connection portion 1043 can be slightly larger than the total size of the first via K1 and the second via K2.

[0155] The embodiments of this application are as follows: Figure 4 The illustrated scheme serves as an example to introduce each membrane layer. Combined with... Figures 7 to 19 The light-shielding conductive layer m2 includes a first power signal line VDD and a second power signal line VSS. The target power trace B includes a first power line portion B1 and a second power line portion B2 located in the light-shielding conductive layer m2. Furthermore, the target power trace B also includes a third power line portion B3 located in the gate layer m6. Figures 7 to 19 Taking the first power signal line VDD and the second power signal line VSS as examples, both of which are target power traces B.

[0156] The first power line portion B1 and the second power line portion B2 both extend along the second direction Y, and are spaced apart in the second direction Y. The orthographic projection of the third power line portion B3 on the substrate 101 at least partially overlaps with the orthographic projection of the first power line portion B1 on the substrate 101. The third power line portion B3 is electrically connected to the first power line portion B1 through vias in the gate insulating layer m5 and the buffer layer m3. Furthermore, the orthographic projection of the third power line portion B3 on the substrate 101 also at least partially overlaps with the orthographic projection of the second power line portion B2 on the substrate 101, and the third power line portion B3 is electrically connected to the second power line portion B2 through vias in the gate insulating layer m5 and the buffer layer m3. That is, the target power trace B can be wired in the light-shielding conductive layer m2 and the gate layer m6.

[0157] Optionally, the reason why there is a gap G between the first power line portion B1 and the second power line portion B2 of the target power line B is to avoid the first maintenance section 1041 of the maintenance architecture 104 here.

[0158] For example, the pixel circuit 1021 includes a storage capacitor Cst comprising a first capacitor plate Cst1 located in the light-shielding conductive layer m2 and a second capacitor plate Cst2 located in the gate layer m6. The orthographic projection of the second capacitor plate Cst2 onto the substrate 101 at least partially overlaps with the orthographic projection of the first capacitor plate Cst1 onto the substrate 101. Since the first maintenance part 1041 of the maintenance architecture 104 is connected to the second node J2 of the pixel circuit 1021, the first maintenance part 1041 can be connected to the first capacitor plate Cst1 of the storage capacitor.

[0159] refer to Figures 7 to 19 The first repair section 1041 is a strip-shaped structure extending along the first direction X. The first end of the first repair section 1041 (transparent conductive layer m1) overlaps with and is electrically connected to the first capacitor plate Cst1 (light-shielding conductive layer m2). The second end of the first repair section 1041 is located on the side of the target power line B away from the first capacitor plate Cst1.

[0160] for example Figure 4Multiple maintenance structures 104 are shown. Some maintenance structures 104 are located on the side of the first power signal line VDD away from the second power signal line VSS, while other maintenance structures 104 are located on the side of the second power signal line VSS away from the first power signal line VDD. The second end of the first maintenance section 1041 in the maintenance structure 104 located on the side of the first power signal line VDD away from the second power signal line VSS can be located on the side of the first power signal line VDD away from the first capacitor plate Cst1. Similarly, the second end of the first maintenance section 1041 in the maintenance structure 104 located on the side of the second power signal line VSS away from the first power signal line VDD can be located on the side of the second power signal line VSS away from the first capacitor plate Cst1.

[0161] In this case, to avoid a short circuit caused by the first maintenance section 1041 of the maintenance architecture 104 intersecting with the target power line B, the distance G between the first power line portion B1 and the second power line portion B2 of the first maintenance section 1041 passing through the target power line B can be made. That is, at least a portion of the first maintenance section 1041 can be located at the distance G between the first power line portion B1 and the second power line portion B2 in the second direction Y.

[0162] In this embodiment of the application, the plurality of pixel units 102 may include a pixel unit 102 of a first color (hereinafter referred to as the first pixel unit), a pixel unit 102 of a second color (hereinafter referred to as the second pixel unit), a pixel unit 102 of a third color (hereinafter referred to as the third pixel unit), and a pixel unit 102 of a fourth color (hereinafter referred to as the fourth pixel unit). The first color, second color, third color, and fourth color are all different.

[0163] For example, the first pixel unit can be a red pixel unit (red, R), and the first pixel unit 102 can be used to emit red light. The second pixel unit can be a green pixel unit (green, G), and the second pixel unit can be used to emit green light. The third pixel unit can be a blue pixel unit (blue, B), and the third pixel unit can be used to emit blue light. The fourth pixel unit can be a white pixel unit (white, W), and the fourth pixel unit can be used to emit white light.

[0164] Optionally, the display panel 100 may include a first pixel unit 102, a second pixel unit 102, a third pixel unit 102, and a fourth pixel unit 102. Optionally, the pixel unit group 102z described in this embodiment may include a plurality of light-emitting pixels arranged along the second direction Y. Each light-emitting pixel may include two columns of pixel units 102 arranged along the first direction X, and two rows of pixel units arranged along the second direction Y.

[0165] For example, in Figure 1 In each luminescent pixel F, white pixel units W and green pixel units G are arranged along a first direction X, and red pixel units R and blue pixel units B are arranged along the first direction X. Furthermore, in each luminescent pixel F, white pixel units W and red pixel units R are arranged along a second direction Y, and green pixel units G and blue pixel units B are arranged along the second direction Y. Alternatively, it can be understood that the four pixel units 102 included in the luminescent pixel F can be arranged in a 2x2 grid, where the pixel unit 102 in the first row and first column is the white pixel unit W, the pixel unit 102 in the first row and second column is the green pixel unit G, the pixel unit 102 in the second row and first column is the red pixel unit R, and the pixel unit 102 in the second row and second column is the blue pixel unit B.

[0166] Optionally, each color pixel unit 102 can be provided with a corresponding data signal line. That is, each pixel unit group 102z can have multiple data signal lines. For example, each pixel unit group 102z can have four data signal lines, namely: the data signal line (dataR) corresponding to the red pixel unit R, the data signal line (dataG) corresponding to the green pixel unit G, the data signal line (dataB) corresponding to the blue pixel unit B, and the data signal line (dataW) corresponding to the white pixel unit W.

[0167] Since there are a large number of data signal lines corresponding to each pixel unit group 102z, some data signal lines will be located on one side of the light-emitting pixel in the layout (these data signal lines will be referred to as the first target data signal line dataM1 in the following text), and other data signal lines will be located between the two columns of pixel units 102 in the light-emitting pixel F (these data signal lines will be referred to as the second target data signal line dataM2 in the following text).

[0168] Example, reference Figure 9 The orthographic projection of the first target data signal line dataM1 on the substrate 101 is located between the orthographic projection of the first end of the first repair unit 1041 on the substrate 101 and the orthographic projection of the second end of the first repair unit 1041 on the substrate 101. That is, the first repair unit 1041 is positioned across the first target data signal line dataM1.

[0169] In this case, to avoid the first repair unit 1041 affecting the first target data signal line dataM1, the first target data signal line dataM1 can include: a first data line portion C1 and a second data line portion C2 located at least in the light-transmitting conductive layer m1, and a third data line portion C3 located in the gate layer m6. Both the first data line portion C1 and the second data line portion C2 extend along the second direction Y, and are spaced apart by a distance H in the second direction Y. The orthographic projection of the third data line portion C3 on the substrate 101 at least partially overlaps with the orthographic projection of the first data line portion C1 on the substrate 101, and the third data line portion C3 is electrically connected to the first data line portion C1 through vias in the gate insulating layer m5 and the buffer layer m3. The orthographic projection of the third data line portion C3 on the substrate 101 also at least partially overlaps with the orthographic projection of the second data line portion C2 on the substrate 101, and the third data line portion C3 is electrically connected to the second data line portion C2 through vias in the gate insulating layer m5 and the buffer layer m3. At least a portion of the first repair section 1041 is located at the interval H between the first data line portion C1 and the second data line portion C2 in the second direction Y.

[0170] That is, the first target data signal line dataM1 can be routed to the gate layer m6 at the position where it overlaps with the first repair section 1041, thereby avoiding a short circuit between the first repair section 1041 and the first target data signal line dataM1.

[0171] In the embodiments of this application, reference is made to Figure 9 The orthographic projection of the second target data signal line dataM2 on the substrate 101 and the orthographic projection of the first repair part 1041 on the substrate 101 are spaced apart in the first direction X. That is, the orthographic projection of the first repair part 1041 on the substrate 101 and the orthographic projection of the second target data signal line dataM2 on the substrate 101 do not overlap. In this case, the second target data signal line dataM2 does not need to be routed to the gate layer m6, but can be located in the light-transmitting conductive layer m1.

[0172] refer to Figure 9Each pixel unit group 102z can have four data signal lines. The data signal line (dataW) corresponding to the white pixel unit W is located between the first power signal line VDD and the first column of pixel units 102; the data signal line (dataR) corresponding to the red pixel unit R and the data signal line (dataG) corresponding to the green pixel unit G are located between the first column of pixel units 102 and the second column of pixel units 102; and the data signal line (dataB) corresponding to the blue pixel unit B is located between the second column of pixel units 102 and the second power signal line VSS. In this case, the data signal lines (dataW) and (dataB) can be the first target data signal line dataM1, and the data signal lines (dataR) and (dataG) can be the second target data signal lines dataM2.

[0173] In the embodiments of this application, reference is made to Figure 9 The orthographic projections of the sensing signal line 'sense' on the substrate 101 and the orthographic projection of the first repair part 1041 on the substrate 101 are spaced apart in the first direction X. That is, the orthographic projections of the sensing signal line and the first repair part 1041 on the substrate 101 do not overlap. In this case, the sensing signal line 'sense' can be located in the light-transmitting conductive layer m1 without needing to be wired to the gate layer m6.

[0174] In this embodiment, since both the data signal line and the sensing signal line are used to transmit signals, in order to reduce the resistance of signal transmission, the data signal line and the sensing signal line can be wired with a double layer of light-shielding conductive layer m2 and light-transmitting conductive layer m1.

[0175] Optionally, the first target data signal line dataM1 includes a first data line portion C1 and a second data line portion C2, and the second target data signal line dataM2 may be located in the light-transmitting conductive layer m1 or the light-shielding conductive layer m2.

[0176] For example, the orthographic projections of the first data line portion C1, the second data line portion C2, and the portion of the second target data signal line dataM2 located in the light-shielding conductive layer m2 on the substrate 101 at least partially overlap with the orthographic projections of the pixel units 102 on the substrate 101, and are not located between adjacent pixel units 102 arranged in the second direction Y. Furthermore, the orthographic projections of the first data line portion C1, the second data line portion C2, and the portion of the second target data signal line dataM2 located in the light-transmitting conductive layer m1 on the substrate 101 at least partially overlap with the orthographic projections of the pixel units 102 on the substrate 101, and are located between adjacent pixel units 102 arranged in the second direction Y. Alternatively, it can be understood that the portions of the first data line portion C1, the second data line portion C2, and the second target data signal line dataM2 located in the pixel area can be configured as a double-layer wiring of the light-shielding conductive layer m2 and the light-transmitting conductive layer m1, while the portions located in the non-pixel area can be configured as a single-layer wiring of the light-transmitting conductive layer m1.

[0177] Optionally, the sensing signal line *sense* is located not only in the light-transmitting conductive layer *m1*, but also in the light-shielding conductive layer *m2*. For example, the orthographic projection of the portion of the sensing signal line *sense* located in the light-shielding conductive layer *m2* onto the substrate 101 at least partially overlaps with the orthographic projection of the pixel unit 102 onto the substrate 101, and is not located between adjacent pixel units 102 arranged along the second direction Y. Furthermore, the orthographic projection of the portion of the sensing signal line *sense* located in the light-transmitting conductive layer *m1* onto the substrate 101 at least partially overlaps with the orthographic projection of the pixel unit 102 onto the substrate 101, and is located between adjacent pixel units 102 arranged along the second direction Y. Alternatively, it can be understood that the portion of the sensing signal line *sense* located in the pixel region can be configured as a double-layer wiring of the light-shielding conductive layer *m2* and the light-transmitting conductive layer *m1*, while the portion located in the non-pixel region can be configured as a single-layer wiring of the light-transmitting conductive layer *m1*.

[0178] Combination Figure 1 ,as well as Figures 4 to 19The display panel 100 further includes a transition structure 105. The transition structure 105 includes a first transition portion 1051 located in the light-transmitting conductive layer m1, a second transition portion 1052 located in the gate layer m6, and a third transition portion 1053 located in the anode layer n1. The first transition portion 1051 is a strip-shaped structure extending along a first direction X. The first end of the first transition portion 1051 is electrically connected to the second power signal line VSS in the display panel 100, and the second end of the first transition portion 1051 is electrically connected to the second transition portion 1052 through vias in the gate insulating layer m5 and the buffer layer m3. The third transition portion 1053 is electrically connected to the second transition portion 1052 through vias in the planarization layer m8 and the passivation layer m7, and is electrically connected to the cathode layer n4. That is, in this embodiment, the second power signal line VSS and the cathode layer n4 can be electrically connected through the transition structure 105.

[0179] Since the first adapter portion 1051 of the adapter structure 105 is located in the light-transmitting conductive layer m1, the transparent display of the display panel 100 can be avoided from being significantly affected by the adapter structure 105.

[0180] Optionally, the planarization layer m8 can be located at the electrical connection position between the third transition section 1053 and the second transition section 1052, which can be a cut-out area. Therefore, the third transition section 1053 can be directly electrically connected to the second transition section 1052 through the cut-out area of ​​the planarization layer m8 and the through hole m71 of the passivation layer m7.

[0181] In the embodiments of this application, reference is made to Figure 10 The active layer m4 includes the active pattern m41 of the first transistor T1, the active pattern m41 of the second transistor T2, and the active pattern m41 of the third transistor T3. The size and shape of the active patterns m41 of the different transistors can be different. In this embodiment, the channel width-to-length ratio of the transistors can be determined according to the actual product requirements, thereby determining the size and shape of the active patterns m41. This embodiment does not specifically limit the size and shape of the active patterns m41 of each transistor.

[0182] In the embodiments of this application, reference is made to Figure 20 In addition to the pixel opening n21, the pixel defining layer n2 can have any area outside the pixel region that is a cut-out area. The orthogonal projection of the cut-out area onto the substrate 101 can cover the orthogonal projection of the third transition portion 1053 onto the substrate 101. In this case, the cathode layer n4 can be directly connected to the third transition portion 1053 located on the anode layer n1. Optionally, Figure 20 The passivation layer (via), planarization layer, anode layer, and pixel delimiting layer shown herein can be applied to the solutions of all embodiments of this application.

[0183] Optionally, the anode layer n1 includes a first material layer, a second material layer, and a third material layer stacked along a direction away from the substrate 101. The first material layer and the third material layer may be made of the same material, while the second material layer may be made of a different material than the first and third material layers. The etching rates of the first and third material layers are lower than the etching rate of the second material layer, thereby allowing the first, second, and third material layers to form as shown in the etching process during the formation of the third transition portion 1053. Figure 21 The undercut structure shown.

[0184] Optionally, the first and third material layers can be made of titanium (Ti), and the second material layer can be made of aluminum (Al).

[0185] refer to Figure 21 The third transition portion 1053 includes a first portion 10531 located in the first material layer, a second portion 10532 located in the second material layer, and a third portion 10533 located in the third material layer. The boundary of the second portion 10532 is recessed relative to the boundaries of the first portion 10531 and the third portion 10533. Thus, in forming the light-emitting functional layer n3, the electron functional layer and the hole functional layer ( Figure 21 When the electron functional layer and hole functional layer are labeled with EL, the electron functional layer and hole functional layer can be broken at the boundary of the third part 10533. This allows the cathode layer n4 to be electrically connected to the second part 10532 of the third transition part 1053 through the broken positions of the electron functional layer and hole functional layer.

[0186] In this embodiment, since the first adapter portion 1051 of the adapter structure 105 is located in the light-transmitting conductive layer m1, the impact of the adapter structure 105 on the transparent display can be reduced, and the transparent display effect of the display panel 100 can be ensured.

[0187] The embodiments of this application are as follows: Figure 6 The illustrated scheme serves as an example to introduce each membrane layer. Combined with... Figures 22 to 35 The diagram illustrates a partial structure of a first signal line group 103z1 that includes a first power signal line VDD but does not include a second power signal line VSS. In this scheme, since the first signal line group 103z1 does not include the second power signal line VSS, it is correspondingly unnecessary to provide a transition architecture 105 at the location of the pixel unit group 102z corresponding to the first signal line group 103z1. Explanations of other features besides the transition architecture 105 can be found in the above embodiments, and will not be repeated here.

[0188] from Figure 35It can be seen that the first power supply signal line VDD in the first signal line group 103z1 is connected to the first power supply signal line VDD in the second signal line group 103z2 through the first connection signal line L1. The first connection signal line L1 can be located in the gate layer.

[0189] In this embodiment, the shape of each via can be rectangular. Of course, it can also be circular, elliptical, polygonal, etc. This embodiment does not specifically limit the shape of the vias.

[0190] In this embodiment of the application, the process of preparing the substrate 101 to the pixel defining layer n2 in the display panel 100 may include:

[0191] 1. Obtain the substrate. The substrate can be a transparent substrate, such as a glass substrate or a flexible substrate.

[0192] 2. A transparent conductive film is formed on one side of a substrate, and a first mask is used to pattern the transparent conductive film to obtain a transparent conductive layer. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0193] 3. A light-shielding conductive film is formed on the side of the transparent conductive layer away from the substrate, and the light-shielding conductive film is patterned using a second mask to obtain the light-shielding conductive layer. The second mask and the first mask are different masks, but no insulating layer is provided between the light-shielding conductive layer and the transparent conductive layer, allowing for direct electrical connection.

[0194] 4. A buffer film is formed on the side of the light-shielding conductive layer away from the substrate.

[0195] 5. An active film is formed on one side of the buffer film on the substrate, and the active film is patterned using a third mask to obtain the active layer.

[0196] 5. A gate insulating film is formed on the side of the active layer away from the substrate using a deposition process.

[0197] 6. The gate insulating film and the buffer film are processed using a fourth mask to obtain the gate insulating layer and the buffer layer. The gate insulating layer and the buffer layer may include vias.

[0198] 7. A gate thin film is formed on the side of the gate insulating layer away from the substrate, and the gate thin film is patterned using a fifth mask to obtain the gate layer.

[0199] 8. A passivation film is formed on the side of the gate layer away from the substrate using a deposition process.

[0200] 9. A flat film is formed on the side of the passivation film away from the substrate using a deposition process.

[0201] 10. The flat film is patterned using the sixth mask to obtain a flat layer.

[0202] 11. The passivation film is patterned using the seventh mask to obtain the passivation layer.

[0203] 12. An anode thin film is formed on the side of the passivation layer away from the substrate, and the anode thin film is patterned using an eighth mask to obtain the anode layer.

[0204] 13. A pixel defining film is formed on the side of the anode layer away from the substrate, and the pixel defining film is patterned using a ninth mask to obtain a pixel defining layer.

[0205] That is, the process of preparing the substrate 101 to the pixel defining layer n2 in the display panel 100 can be as follows: transparent conductive layer → light-shielding conductive layer → buffer film → active layer → deposit gate insulating film → form vias for gate insulating layer and buffer layer → gate layer → deposit passivation film → deposit planarization film → planarization layer → passivation layer → anode layer → pixel defining layer.

[0206] In summary, this application provides a display panel including a substrate, multiple pixel units, and multiple signal lines. The second segment of the first type of signal lines located in the non-pixel area is made of transparent material, thereby increasing the transparent display area of ​​the display panel and improving the transparent display effect.

[0207] Figure 36 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 36 The display device includes a power supply component 200 and a display module 100 as provided in the above embodiments. The power supply component 200 is connected to the display module 100 and is used to supply power to the display module 100.

[0208] Optionally, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, car navigation systems, and e-readers, as well as any product or component with display functionality.

[0209] Since the display device can have essentially the same technical effects as the display panel described in the previous embodiments, the technical effects of the display panel will not be described again here for the sake of brevity.

[0210] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0211] The Description of Embodiments section of this application describes several embodiments; however, this description is exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0212] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0213] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0214] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Furthermore, the drawings schematically illustrate ideal examples, and this application is not limited to the shapes or numerical values ​​shown in the drawings.

[0215] The ordinal numbers "first," "second," and "third" used in this specification are for the purpose of avoiding confusion among the constituent elements, not for limiting the quantity. The term "multiple" in this application refers to two or more quantities.

[0216] The thickness range of the film layer in this specification is A to B, which means that the thickness is between A and B, including the two endpoints of A and B.

[0217] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0218] In this specification, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this application according to the specific circumstances.

[0219] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode (drain terminal, drain region, or drain), and a source electrode (source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0220] In this specification, the first terminal of a transistor can be the drain electrode and the second terminal of a transistor can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0221] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0222] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0223] In this application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer closer to the substrate.

[0224] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0225] In this application, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0226] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate, the substrate including a display area; Multiple pixel units are located in the display area. The multiple pixel units form a group of multiple pixel units arranged along a first direction and extending along a second direction. The group of pixel units includes multiple pixel units. The second direction intersects the first direction. In addition, a plurality of signal lines arranged along the first direction and extending along the second direction, the signal lines being electrically connected to the pixel units, the plurality of signal lines including a first type of signal lines, the first type of signal lines including a first line segment and a second line segment electrically connected, the orthographic projection of the first line segment on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlapping and not located between adjacent pixel units arranged along the second direction, the orthographic projection of the second line segment on the substrate being at least located between adjacent pixel units arranged along the second direction, the material of the second line segment including a light-transmitting material.

2. The display panel according to claim 1, characterized in that, The first type of signal lines includes: data signal lines and sensing signal lines; the plurality of signal lines also include a first power signal line and a second power signal line; The pixel unit includes a pixel circuit and a light-emitting unit. The pixel circuit includes a plurality of thin-film transistors and at least one storage capacitor. The light-emitting unit includes an anode, a light-emitting portion, and a cathode. The pixel circuit and the anode of the light-emitting unit are electrically connected. The data signal line, the sensing signal line, and the first power signal line are all electrically connected to the thin-film transistor in the pixel circuit. The second power signal line is electrically connected to the cathode in the light-emitting unit. The potential of the first power signal line providing the first power signal to the pixel unit is higher than the potential of the second power signal line providing the second power signal to the pixel unit.

3. The display panel according to claim 2, characterized in that, The plurality of signal lines also includes a second type of signal line, wherein the material of the second type of signal line includes a non-transparent material; The plurality of signal lines constitute a plurality of signal line groups arranged along the first direction and corresponding to the plurality of pixel unit groups; the plurality of signal line groups include a first signal line group and a second signal line group arranged along the first direction and adjacent to each other, and at least one of the first signal line group and the second signal line group includes a first power signal line and a second power signal line. In the signal line group that includes the first power signal line and the second power signal line, one of the first power signal line and the second power signal line is a first type of signal line, and the other is a second type of signal line.

4. The display panel according to claim 3, characterized in that, The first signal line group includes the first power signal line, and the second signal line group includes the first power signal line and the second power signal line; the display panel further includes: a first connection signal line extending along the first direction; One end of the first connection signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group.

5. The display panel according to claim 4, characterized in that, The first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group. Among them, the first power signal line in the second signal line group is a first type of signal line, and the first power signal line in the second signal line group is a second type of signal line.

6. The display panel according to claim 3, characterized in that, Both the first signal line group and the second signal line group include the first power signal line and the second power signal line; the display panel further includes: a first connection signal line and a second connection signal line extending along the first direction; One end of the first connecting signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group. One end of the second connecting signal line is connected to the second power signal line in the first signal line group, and the other end is connected to the second power signal line in the second signal line group.

7. The display panel according to claim 6, characterized in that, The second power signal line in the first signal line group is closer to the second signal line group than the first power signal line in the first signal line group, and the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group. Among them, the second power signal line in the first signal line group and the first power signal line in the second signal line group are both Class I signal lines, and the first power signal line in the first signal line group and the second power signal line in the second signal line group are both Class II signal lines.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel includes: a pixel unit layer, the pixel unit layer including a pixel circuit layer and a light-emitting unit layer, the pixel circuit layer including pixel circuits of the plurality of pixel units, and the light-emitting unit layer including light-emitting units of the plurality of pixel units; The pixel circuit layer includes: a light-shielding conductive layer, a light-transmitting conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer, which are sequentially stacked along the direction away from the substrate. The light-emitting unit layer includes: an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer stacked sequentially in a direction away from the substrate. Wherein, the first line segment is located in the light-shielding conductive layer, the second line segment is located in the light-transmitting conductive layer, and the second line segment and the first line segment overlap and are electrically connected in contact; The active layer includes an active pattern of a thin-film transistor, and the gate layer includes a gate, a source, and a drain of a thin-film transistor. The gate is located between the source and the drain, and the source and the drain are electrically connected to the active pattern through vias in the gate insulating layer. The anode layer is made of a light-transmitting material. The anode layer includes the anode of the light-emitting unit of the plurality of pixel units. The pixel defining layer includes a plurality of pixel openings for exposing at least a portion of the anode. The light-emitting functional layer includes the light-emitting portion of the light-emitting unit of the plurality of pixel units. The light-emitting portion is located within the pixel opening and is connected to at least a portion of the anode exposed by the pixel opening. The cathode layer includes the cathode of the light-emitting unit of the plurality of pixel units, and the cathode is connected to the light-emitting portion.

9. The display panel according to claim 8, characterized in that, The anode in the light-emitting unit of each pixel unit includes a first anode portion and a second anode portion arranged at intervals; the display panel further includes a maintenance structure, which includes a first maintenance section and a second maintenance section; The first repair section is electrically connected to the pixel circuit, the second repair section is electrically connected to the first repair section, and the first end of the second repair section is electrically connected to the first anode section, the second end of the second repair section is electrically connected to the second anode section, and the first end and the second end of the second repair section are respectively located on both sides of the position where the second repair section and the first repair section are electrically connected; The first repair section is located in the light-transmitting conductive layer, and the second repair section is located in the anode layer.

10. The display panel according to claim 9, characterized in that, The display panel further includes: a connection portion located on the gate layer, wherein the orthographic projection of the connection portion on the substrate and the orthographic projection of the first repair portion on the substrate have a first overlapping area, and the orthographic projection of the connection portion on the substrate and the orthographic projection of the second repair portion on the substrate have a second overlapping area, wherein the first overlapping area and the second overlapping area do not overlap; The connection portion and the first maintenance portion are electrically connected in the first overlap region through vias in the gate insulating layer and the buffer layer, and the connection portion and the second maintenance portion are electrically connected in the second overlap region through vias in the passivation layer and the planarization layer.

11. The display panel according to claim 9, characterized in that, The target power traces in the first power signal line and the second power signal line of the multiple signal lines include a first power line portion and a second power line portion located in the light-shielding conductive layer, and a third power line portion located in the gate layer. Both the first power line portion and the second power line portion extend along the second direction, and the first power line portion and the second power line portion are spaced apart in the second direction. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the first power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the first power line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the second power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the second power line portion through vias in the gate insulating layer and the buffer layer.

12. The display panel according to claim 11, characterized in that, The pixel circuit includes a storage capacitor comprising a first capacitor plate located in the light-shielding conductive layer and a second capacitor plate located in the gate layer, wherein the orthographic projection of the second capacitor plate on the substrate and the orthographic projection of the first capacitor plate on the substrate at least partially overlap. The first repair section is a strip-shaped structure extending along the first direction. The first end of the first repair section overlaps with the first capacitor plate and is electrically connected. The second end of the first repair section is located on the side of the target power line away from the first capacitor plate. The first repair section is at least partially located at the interval between the first power cord section and the second power cord section in the second direction.

13. The display panel according to claim 12, characterized in that, The plurality of signal lines include a plurality of data signal lines, wherein the orthographic projection of the first target data signal line among the plurality of data signal lines on the substrate is located between the orthographic projection of the first end of the first repair part on the substrate and the orthographic projection of the second end of the first repair part on the substrate. The first target data signal line includes: at least a first data line portion and a second data line portion located in the transparent conductive layer, and a third data line portion located in the gate layer; Both the first data line portion and the second data line portion extend along the second direction, and the first data line portion and the second data line portion are spaced apart in the second direction. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the first data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the first data line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the second data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the second data line portion through vias in the gate insulating layer and the buffer layer. The first repair section is located at least partially between the first data line portion and the second electrical data line portion in the second direction.

14. The display panel according to claim 13, characterized in that, The plurality of data signal lines also includes a second target data signal line, wherein the orthographic projection of the second target data signal line on the substrate and the orthographic projection of the first repair part on the substrate are spaced apart in the first direction; The second target data signal line is located at least in the transparent conductive layer.

15. The display panel according to claim 14, characterized in that, The first data line portion, the second data line portion, and the second target data signal line are also located in the light-shielding conductive layer; The orthographic projections of the first data line portion, the second data line portion, and the portion of the second target data signal line located on the light-shielding conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction. The orthographic projections of the first data line portion, the second data line portion, and the second target data signal line portion located on the transparent conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

16. The display panel according to any one of claims 9 to 15, characterized in that, The multiple signal lines include a sensing signal line whose orthogonal projection on the substrate and the first repair part's orthogonal projection on the substrate are spaced apart in the first direction; the sensing signal line is located at least in the transparent conductive layer.

17. The display panel according to claim 16, characterized in that, The sensing signal line is also located in the light-shielding conductive layer; The orthographic projection of the portion of the sensing signal line located on the light-shielding conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction; The orthographic projection of the portion of the sensing signal line located on the transparent conductive layer onto the substrate and the orthographic projection of the pixel unit onto the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

18. The display panel according to claim 8, characterized in that, The display panel further includes: a transition structure, the transition structure including a first transition portion located in the transparent conductive layer, a second transition portion located in the gate layer, and a third transition portion located in the anode layer; The first adapter is a strip-shaped structure extending along the first direction. The first end of the first adapter is electrically connected to the second power signal line in the display panel. The second end of the first adapter is electrically connected to the second adapter through vias in the gate insulating layer and the buffer layer. The third adapter is electrically connected to the second adapter through vias in the planarization layer and the passivation layer. The third adapter is electrically connected to the cathode layer.

19. The display panel according to claim 18, characterized in that, The anode layer includes a first material layer, a second material layer, and a third material layer stacked in a direction away from the substrate, wherein the material etching rates of the first material layer and the third material layer are less than the material etching rate of the second material layer; The third transition portion includes a first portion located in the first material layer, a second portion located in the second material layer, and a third portion located in the third material layer, wherein the boundary of the second portion is recessed relative to the boundaries of the first portion and the third portion; The light-emitting functional layer further includes an electronic functional layer and a hole functional layer. The electronic functional layer and the hole functional layer are integral film layers, and the electronic functional layer and the hole functional layer are in a broken state at the boundary of the third part. The cathode layer is electrically connected to the second part through the broken positions of the electronic functional layer and the hole functional layer.

20. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 19; The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

Images