Display device

Abstract

This disclosure provides a display device including a display panel and a driver chip disposed in a non-display area. The display panel includes a display area and a non-display area. A first wiring portion around the driver chip includes a substrate, a first metal wiring layer on the substrate, a GIP wiring above the first metal wiring layer, and a second metal wiring layer above the GIP wiring.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device capable of improving reliability. Background Technology

[0002] As we enter the information age, the field of display devices that visually display electrical information signals is developing rapidly, and research is underway to improve the performance of various display devices, such as thinner designs, lighter weights, and lower power consumption.

[0003] Recently, various display devices, such as liquid crystal displays (LCDs), field emission displays (FEDs), and organic light-emitting diodes (OLEDs), have been used.

[0004] The descriptions provided in the discussion of this Related Art section should not be assumed to be prior art simply because they are mentioned in or associated with the description in the Related Art section. The discussion of the Related Art section may include information describing one or more aspects of the subject matter art, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0005] This disclosure provides a display device that improves reliability by protecting in-panel gated-in-in-patch (GIP) wiring from moisture penetration caused by cracks around the driver chip and corrosion failures of the pads or wiring.

[0006] This disclosure provides a display device that can prevent screen malfunctions by preventing short circuits in the GIP lines caused by cracks that occur around the driver chip due to stress concentration when the driver chip is mounted on the display panel.

[0007] This disclosure provides a display device that can improve the reliability degradation of the display device due to cracks.

[0008] The purposes of this disclosure are not limited to those described above. Other purposes and advantages not mentioned in this disclosure may be understood based on the following description and may be more clearly understood based on embodiments according to this disclosure. Furthermore, it will be readily understood that the purposes and advantages of this disclosure can be achieved using the means set forth in the claims or a combination thereof.

[0009] A display device according to an exemplary embodiment of the present disclosure may include a display panel and a driver chip disposed in a non-display area. The display panel has a display area and a non-display area. The first wiring portion around the driver chip may include a substrate, a first metal wiring disposed on the substrate, a GIP wiring disposed above the first metal wiring, and a second metal wiring disposed above the GIP wiring, but is not limited thereto.

[0010] The display device according to an exemplary embodiment of the present disclosure may further include: a buffer layer disposed between the first metal wiring layer and the GIP wiring; a gate insulating layer disposed between the GIP wiring and the second metal wiring layer; and an interlayer insulating layer disposed on the second metal wiring layer, but is not limited thereto.

[0011] GIP wiring may include molybdenum (Mo), which is the same material as the gate electrode, but is not limited to it.

[0012] The first and second metal wirings can be floating metals and can include molybdenum (Mo) or aluminum (Al), but are not limited thereto.

[0013] GIP cabling can be installed between the first metal cabling and the second metal cabling.

[0014] The first metal wiring can be placed below the GIP wiring. The second metal wiring can be placed above the GIP wiring.

[0015] The width of each of the first and second metal cablings can be greater than or equal to the width of the GIP cabling.

[0016] The first metal wiring layer can be placed below the GIP wiring on the same layer as the light-shielding layer wiring of the display area.

[0017] Each of the first and second metal wirings can be formed as a separate structure, similar to GIP wiring.

[0018] GIP cabling can be structured as separate components.

[0019] The first metal wiring layer, the second metal wiring layer, and the GIP wiring can be spaced apart from each other.

[0020] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0021] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and forming part of this application, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0022] Figure 1 This is a plan view of a display device according to an example implementation.

[0023] Figure 2 This is a circuit diagram of a sub-pixel according to an example implementation.

[0024] Figure 3 yes Figure 1 A magnified plan view of part A.

[0025] Figure 4 It is along Figure 3 The cross-sectional view taken from line I-I'.

[0026] Figure 5 It is along Figure 3 A cross-sectional view taken from line A-A'.

[0027] Figure 6 This is a diagram showing a crack situation when an example implementation is applied.

[0028] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative dimensions and depictions of these elements may be exaggerated for clarity, illustrative purposes, and convenience. Detailed Implementation

[0029] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of corresponding elements used in the following description may be chosen solely for ease of writing and therefore may differ from the names used in actual products.

[0030] In the following description, embodiments will be described with reference to the accompanying drawings.

[0031] The same reference numerals denote the same parts. Furthermore, in the drawings, the shape (e.g., dimensions, length, width, height, thickness, position, radius, diameter, and area), size, ratio, angle, quantity, etc., of parts may be exaggerated to effectively illustrate the technical content. For ease of interpretation, the scale of the parts shown in the drawings differs from the actual scale and is not limited to the scale shown in the drawings.

[0032] In this disclosure, when a component, region, layer, part, etc., is referred to as being "on" another component, "connected to" or "attached to" another component, it means that the component, region, layer, part, or area may be directly connected / attached to or in direct contact with or overlap with other components, regions, layers, parts, or areas, or a third component, region, layer, or part may be disposed between them. Here, the other component may include at least one of two or more components that are "connected or attached," "in contact with or overlap" each other.

[0033] "And / or" includes any combination of one or more related constructs that can be defined.

[0034] While terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this embodiment, a “first” component may be referred to as a “second” component, and similarly, a “second” component may be referred to as a “first” component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] Terms such as “below,” “under,” “above,” and “upper” are used to describe the relationship between components depicted in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. For example, one or more other components may be located between two components unless “directly” or “directly” is used. Spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” can be used to readily describe the relationship between one element or component and another element or component as depicted in the accompanying drawings. In addition to the orientations depicted in the drawings, spatially relative terms should be understood to include different orientations of elements during use or operation. For example, if an element depicted in the drawings is flipped, an element described as “below” or “under” another element may actually be located “above” another element. Thus, the exemplary term “below” can encompass both downward and upward directions.

[0036] Terms such as “comprising,” “having,” “including,” “constituting,” “composed of,” and “formed from” should be understood to specify the presence of a feature, quantity, step, operation, component, part, or combination thereof described in this disclosure, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0037] The various features of the various exemplary embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically linked and operated in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0038] The display device of this disclosure will be examined below with reference to the accompanying drawings and embodiments. Figure 1 This is a plan view of a display device according to an example embodiment, and Figure 2 This is a circuit diagram of a sub-pixel according to an example implementation.

[0039] Reference Figure 1 and Figure 2 According to an exemplary embodiment of the present disclosure, the display device 100 includes a display panel 110 and a driver chip 107. The display panel 110 includes a display area AA and a non-display area NA. The driver chip 107 is disposed in the non-display area NA of the display panel 110. The driver chip 107 may be disposed in the driving circuit area 109 of the non-display area NA.

[0040] The display area AA is the area where an image is displayed. Multiple subpixels SP are disposed within the display area AA of the display panel 110, and the multiple subpixels SP can be used to display an image. The area containing the multiple subpixels SP becomes the display area AA, and the area other than the display area AA can become the non-display area NA. At least a portion of the non-display area NA can be bent to be invisible from the front surface of the display device 100, or can be covered by the housing or casing (not shown) of the display device 100. The non-display area NA can also be referred to as an edge area or a border area.

[0041] Reference Figure 2 At least one sub-pixel SP among multiple pixels may include a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light-emitting diode (OLED), and may include more or fewer components. The sub-pixel SP may be composed of 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, etc.

[0042] The first electrode (e.g., drain electrode) of the switching transistor SW is electrically connected to the data line DL, and the second electrode (e.g., source electrode) is electrically connected to the first node N1. The gate electrode of the switching transistor SW is electrically connected to the gating line GL. In response to a scan signal provided via the gating line GL, the switching transistor SW transmits a data signal provided via the data line DL to the first node N1. For example, when the switching transistor SW is turned on in response to a scan signal provided via the gating line GL, the data signal provided via the data line DL can be transmitted to the first node N1 of the driving transistor DR.

[0043] The capacitor Cst is electrically connected to the first node N1 and is charged by the voltage applied to the first node N1.

[0044] The first electrode (e.g., drain electrode) of the driving transistor DR is applied with a high-potential driving voltage EVDD, and the second electrode (e.g., source electrode) is electrically connected to the first electrode (e.g., anode) of the organic light-emitting diode OLED. The driving transistor DR can control the amount of driving current flowing in the organic light-emitting diode OLED in response to the voltage applied to the gate electrode.

[0045] The semiconductor layer of the switching transistor SW and / or the driving transistor DR may include silicon such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si), or may include oxides such as indium gallium zinc oxide (IGZO), but is not limited thereto.

[0046] Organic light-emitting diodes (OLEDs) emit light corresponding to a driving current. OLEDs can emit light corresponding to any of the following colors: red, green, blue, and white, but are not limited thereto. In another exemplary embodiment, an OLED can emit one of the colors cyan, magenta, and yellow. In various embodiments, an OLED can emit one of the colors red, green, and blue.

[0047] An organic light-emitting diode (OLED) may include an anode, an emissive layer disposed on the anode, and a cathode providing a common voltage. The emissive layer may be configured to emit light of the same color, such as white light, for each pixel, or may be configured to emit light of a different color, such as red, green, or blue light, for each sub-pixel (SP). For example, the emissive layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto.

[0048] Organic light-emitting diodes (OLEDs) can be either top-emitting or bottom-emitting diodes.

[0049] A compensation circuit CC can be disposed within a sub-pixel SP to compensate for the threshold voltage of the driving transistor DR, etc. The compensation circuit CC can consist of one or more transistors. The compensation circuit CC may include one or more transistors and capacitors, and can be configured in various ways depending on the compensation method. Pixels including the compensation circuit CC can have various structures, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0050] The non-display area NA can be formed in the edge region surrounding the display area AA of the displayed image, such as... Figure 1 As shown. The non-display area NA includes a driving circuit area 109 for driving multiple sub-pixels SP, and at least one driving chip 107 may be disposed in the driving circuit area 109. The driving chip 107 may be in the form of a driver integrated circuit (D-IC). The driving chip 107 may be mounted in the non-display area NA of the display panel 110 using a chip-on-panel (COP) method. The driving chip 107 may be used as a data driving circuit.

[0051] The driving circuit area 109 may further include a gating driving circuit (not shown), which is provided in the non-display area NA in the form of a panel-in-panel gating (GIP), but is not limited thereto. Alternatively, the gating driving circuit may be provided in the display area AA of the display panel. The gating driving circuit may be a circuit for driving multiple gating lines and can provide gating signals to the multiple gating lines. In one or more aspects, at least one of the data driving circuit and the gating driving circuit may be provided in the display area AA of the display panel.

[0052] Figure 3 yes Figure 1 A magnified plan view of part A.

[0053] Reference Figure 1 and Figure 3 The display panel 110 may also include a first pad PAD1, a second pad PAD2, and multiple wires W1, W2, and L1, wherein the second pad PAD2 is electrically connected to the driver chip 107 disposed in the non-display area NA, and the multiple wires W1, W2, and L1 are disposed in the non-display area NA and electrically connected to the pads PAD1 and PAD2.

[0054] The driver chip 107 can be disposed in the non-display area NA of the display panel 110 using a chip-on-panel (COP) method, but is not limited thereto. The COP method is a method of directly attaching the driver IC to the pads of the substrate using an anisotropic conductive film (ACF).

[0055] The driver chip 107 receives signals from the outside required to drive the display panel 110, and provides or sends signals to the display panel 110. The driver chip 107 can be a source driver integrated circuit that provides data signals to the data line DL of the display area AA, but is not limited thereto.

[0056] The driver chip 107 is electrically connected to the display panel 110 via the second pad PAD2 and the first pad PAD1. The driver chip 107 receives signals from the outside via the second wiring W2 and the second pad PAD2. The driver chip 107 can provide the signals received from the outside to the display area AA via the first pad PAD1, the first wiring W1, and the connecting line L1.

[0057] The first pad PAD1 is set to be relatively closer to the display area AA than the second pad PAD2, but is not limited to this.

[0058] The first pads PAD1 can be arranged in multiple rows. Multiple first pads PAD1 arranged in a row are spaced apart from each other. The first pads PAD1 are shown as arranged in three rows, but are not limited to this, and can be arranged in two or fewer rows, or four or more rows. The first pads PAD1 can have a short side and a long side. For example, each of the multiple first pads PAD1 can have a short side and a long side, but is not limited to this. The short side of the first pad PAD1 can be in a direction perpendicular to the long side of the driver chip 107.

[0059] The first pad PAD1 is connected to the link line L1 and the first wiring W1. Each of the plurality of first pads PAD1 can be connected one-to-one to each of the link lines L1 and the first wiring W1, but is not limited thereto. The link line L1 can be connected to the data line DL of the display area AA.

[0060] The first pad PAD1 may be disposed on the same layer as any one of the multiple adjacent traces (e.g., first trace W1, third trace W3, link line L1, and fourth trace W1), but is not limited thereto. The first pad PAD1 may be made of the same material as any one of the multiple adjacent traces (e.g., first trace W1, third trace W3, link line L1, and fourth trace W1), but is not limited thereto. For example, the first pad PAD1 may be made of a different material than any one of the multiple adjacent traces (e.g., first trace W1, third trace W3, link line L1, and fourth trace W1).

[0061] The first pad PAD1 may be disposed on the same layer as the second wiring W2 electrically connected to the second pad PAD positioned opposite it, but is not limited thereto. The first pad PAD1 may be made of the same material as the second wiring W2, but is not limited thereto. For example, the first pad PAD1 may be made of a different material than the second wiring W2.

[0062] The first pad PAD1 is connected to the driver chip 107 via an anisotropic conductive film, but is not limited thereto. At this time, bumps disposed on the driver chip 107 are electrically connected to the first pad PAD1. Each of the first pads PAD1 can be connected one-to-one to a bump. Therefore, the first pad PAD1 can receive voltages and signals applied to the driver chip 107 through the bumps.

[0063] The second pads PAD2 can be arranged in a single row. Multiple second pads PAD2 arranged in a single row are spaced apart from each other. The second pads PAD2 are shown as arranged in one row, but are not limited to this, and can be arranged in two or more rows. The second pads PAD2 can have a short side and a long side. For example, each of the multiple second pads PAD2 can have a short side and a long side, but is not limited to this. The short side of the second pad PAD2 can be in a direction perpendicular to the long side of the driver chip 107.

[0064] The second pad PAD2 is connected to the second wiring W2. Each of the plurality of second pads PAD2 can be connected one-to-one to each of the second wirings W2, but is not limited thereto. The second wiring W2 can be connected to an external circuit board (not shown).

[0065] The second pad PAD2 may be disposed on the same layer as the second wiring W2 to which it is electrically connected. The second pad PAD2 may be made of the same material as the second wiring W2, but is not limited thereto. For example, the second pad PAD2 may be made of a different material than the second wiring W2. The second pad PAD2 may be disposed on the same layer as any one of the multiple wirings (e.g., the first wiring W1, the third wiring W3, the link line L1, and the fourth wiring W4) adjacent to and opposite to the first pad PAD1. The second pad PAD2 may be made of the same material as any one of the first wiring W1, the third wiring W3, the link line L1, and the fourth wiring W4, but is not limited thereto.

[0066] The second pad PAD2 is connected to the driver chip 107 via an anisotropic conductive film 103, but is not limited thereto. In this case, the bumps provided on the driver chip 107 are electrically connected to the second pad PAD2. Each of the second pads PAD2 can be connected one-to-one to a bump. For example, one second pad PAD2 can be connected to one bump. Therefore, the second pads PAD2 can provide external voltage and signals to the driver chip 107 through the bumps.

[0067] The structures of the first pad PAD1 and the second pad PAD2 can be basically the same.

[0068] The first wiring W1 can connect the first pad PAD1 and some signal lines (e.g., strobe lines GL). The first wiring W1 can be a strobe control line.

[0069] The link cable L1 can connect the first pad PAD1 and some signal lines (e.g., data line DL).

[0070] The first wiring W1 and the linking line L1 can be located on the same layer. The first wiring W1 and the linking line L1 can be made of the same material, but are not limited to this.

[0071] The first wiring W1 and the link line L1 can be positioned in the direction intersecting the long side of the driver chip 107. The first wiring W1 and the link line L1 can form a certain angle with the long side of the driver chip 107, but are not limited thereto.

[0072] The second wiring W2 is located at one end of the display panel 110 and connects the second pad PAD2 to an external circuit board (not shown). For example, the external circuit board can be a flexible printed circuit board (FPC). The second wiring W2 can be located in the direction intersecting the long side of the driver chip 107.

[0073] The second wiring W2 and the linking line L1 can be placed on the same layer. The second wiring W2 and the linking line L1 can be made of the same material.

[0074] The display panel 110 may also include a third wiring W3 and a fourth wiring W4 disposed in a non-display area NA surrounding the driver chip 107.

[0075] The third wiring W3 can be positioned in a direction parallel to the short side of the driver chip 107, without being electrically connected to the driver chip 107. The third wiring W3 can be a power wiring. For example, the third wiring W3 can be positioned in a direction intersecting the long side of the driver chip 107.

[0076] The third wiring W3 can be disposed on the same layer as the first wiring W1. The third wiring W3 and the first wiring W1 can be made of the same material. However, this disclosure is not limited thereto. For example, the third wiring W3 can be made of a different material than the first wiring W1. The third wiring W3 can be disposed on the same layer as the link line L1. The third wiring W3 and the link line L1 can be made of the same material. However, this disclosure is not limited thereto. For example, the third wiring W3 can be made of a different material than the link line L1.

[0077] The third wiring W3 can be disposed on the same layer as the second wiring W2. The third wiring W3 and the second wiring W2 can be made of the same material. However, this disclosure is not limited thereto. For example, the third wiring W3 can be made of a different material than the second wiring W2. The third wiring W3 can be disposed on the same layer as the fourth wiring W4. The third wiring W3 and the fourth wiring W4 can be made of the same material. However, this disclosure is not limited thereto. For example, the third wiring W3 can be made of a different material than the fourth wiring W4.

[0078] The fourth wiring W4 can be positioned in a direction intersecting the short side of the driver chip 107. For example, a portion of the fourth wiring W4 can be positioned in a direction intersecting the short side of the driver chip 107, and another portion of the fourth wiring W4 can be positioned in a direction parallel to the third wiring W3, but is not limited thereto. The fourth wiring W4 can be a multiplexer driver line or a test line.

[0079] The fourth wiring W4 can be disposed on the same layer as the first wiring W1. The fourth wiring W4 and the first wiring W1 can be made of the same material. The fourth wiring W4 can be disposed on the same layer as the link line L1. The fourth wiring W4 and the link line L1 can be made of the same material. However, this disclosure is not limited thereto.

[0080] The fourth wiring W4 may be disposed on the same layer as the second wiring W2. The fourth wiring W4 and the second wiring W2 may be made of the same material. The fourth wiring W4 may be disposed on the same layer as the third wiring W3. The fourth wiring W4 and the third wiring W3 may be made of the same material. However, this disclosure is not limited thereto.

[0081] As described above, the COP method is used to attach the driver chip 107 to the substrate 111 as a source driver IC. Therefore, pressure mark checks are performed to check the connection status of the driver chip 107, and high voltage must be applied when attaching the driver chip 107 to the substrate 111 to prevent poor connection of the driver chip 107.

[0082] According to this disclosure, the GIP wiring portion can be protected from moisture penetration caused by cracks around the driver chip and corrosion failures of the pads or wiring by arranging a first metal wiring layer and a second metal wiring layer on the lower and upper parts of the GIP wiring.

[0083] According to this disclosure, the first and second metal wiring layers disposed at the lower and upper parts of the GIP wiring have a wiring width greater than or equal to that of the GIP wiring. Even if cracks occur due to the space between the metal wiring layers, the first and second metal wiring layers disposed at the lower and upper parts of the GIP wiring preferentially prevent oxidation, and the oxidation and dissolution of the floating metal wiring layer occur first, so that the GIP wiring can be protected from moisture penetration caused by cracks around the driver chip and corrosion failures of the pads or wiring.

[0084] Figure 4 It is along Figure 3 The cross-sectional view taken from line I-I'.

[0085] Reference Figure 4 Display panel 110 (e.g.) Figure 1 (As shown) includes a substrate 111. An insulating layer 120 may be disposed on the substrate 111 in a non-display area NA, and a planarization layer 131 may be disposed on the insulating layer 120. For example, the planarization layer 131 may be disposed on a portion of the insulating layer 120.

[0086] Multiple insulating layers 120 may be laminated and disposed on the substrate 111 in the non-display area NA. The insulating layers 120 may include a buffer layer 121, a gate insulating layer 123, and an interlayer insulating layer 125. For example, the buffer layer 121 may be disposed on the substrate 111, and the gate insulating layer 123 may be disposed between the buffer layer 121 and the interlayer insulating layer 125.

[0087] The substrate 111 can be formed of a flexible plastic material and therefore can have flexible properties. The substrate 111 can be formed by including polyimide and can include a thin flexible glass material.

[0088] The substrate 111 may be formed of a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), these are merely examples and are not necessarily limited thereto.

[0089] The substrate 111 may include a support substrate such as PET (polyethylene terephthalate), a polyimide film, and an adhesive film such as PSA (pressure-sensitive adhesive) for bonding the PET and the polyimide film.

[0090] Substrate 111 may include multiple substrates. For example, substrate 111 may include a first substrate 113, a second substrate 115, and an intermediate layer 114 disposed between the first substrate 113 and the second substrate 115. Intermediate layer 114 may include an adhesive material. Intermediate layer 114 may include, but is not limited to, an insulating material such as silicon nitride or silicon oxide.

[0091] On substrate 111, such as Figure 1 As shown, multiple sub-pixels SP can be set in the display area AA, and the driver chip 107 can be set in the non-display area NA.

[0092] A buffer layer 121 is disposed on the substrate 111. The buffer layer 121 is disposed on the substrate 111 to protect the thin-film transistors and light-emitting elements disposed in the display area AA from moisture penetrating the substrate 111. The buffer layer 121 is configured to overlap with the driving chip 107 in the non-display area AA to prevent moisture from penetrating from the edges of the substrate 111.

[0093] The buffer layer 121 may be formed from, but is not limited to, multiple inorganic films that are alternately laminated. For example, the buffer layer 121 may be formed from a single inorganic film. For example, the buffer layer 121 may include multiple films, wherein one or more inorganic films of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy) are alternately laminated. For example, the single inorganic film may be a silicon oxide (SiO) film or a silicon nitride (SiN) film.

[0094] A gate insulating layer 123 is disposed on a buffer layer 121. The gate insulating layer 123 is disposed on... Figure 1 and Figure 2 In the shown display area AA, a gate insulating layer 123 is provided to prevent short circuits between the electrodes constituting the thin-film transistors. This gate insulating layer 123 extends into the non-display area NA to prevent short circuits between the electrodes constituting the thin-film transistors disposed in the non-display area NA. The gate insulating layer 123 may be configured to overlap with the driving chip 107 in the non-display area NA.

[0095] For example, the gate insulating layer 123 may be composed of a single layer or multiple layers of inorganic films. The gate insulating layer 123 may include inorganic films, such as silicon oxide films (SiOx), silicon nitride films (SiNx), or multiple layers thereof.

[0096] An interlayer insulating layer 125 may be disposed on the gate insulating layer 123. The interlayer insulating layer 125 is disposed on... Figure 1 and Figure 2 In the display area AA shown, the vertically arranged electrodes constituting the thin-film transistors are electrically isolated. An interlayer insulating layer 125 may extend to the non-display area NA to electrically isolate the vertically arranged electrodes constituting the thin-film transistors in the non-display area NA. The interlayer insulating layer 125 may be configured to overlap with the driving chip 107 in the non-display area NA.

[0097] The interlayer insulating layer 125 may include an inorganic material. The inorganic material may include, for example, silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the interlayer insulating layer 125 may be arranged to include multiple layers thereof.

[0098] The first pad PAD1 can be disposed on multiple insulating layers 120. For example, the first pad PAD1 can be disposed on a portion of the interlayer insulating layer 125 covering the insulating layer 120.

[0099] The first pad PAD1 can be formed by including a metal layer.

[0100] A planarization layer 131 is disposed on the first pad PAD1. The planarization layer 131 may be configured to extend to the side of the first pad PAD1 to cover the side of the first pad PAD1 and the insulating layer 120. For example, the planarization layer 131 may be configured to cover the upper surface of the interlayer insulating layer 125 of the insulating layer 120 and the side of the first pad PAD1.

[0101] The planarization layer 131 can be configured to overlap with one short side CE of the driver chip 107. In this case, one short side CE of the driver chip 107 can overlap with the planarization layer 131. For example, the driver chip 107 can overlap with a portion of the planarization layer 131 and the first pad PAD1.

[0102] The planarization layer 131 may include an organic material. The organic material may include, but is not limited to, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0103] In addition to the insulating layer 120 mentioned above, various organic or inorganic films can be further arranged between the substrate 111 and the planarization layer 131.

[0104] The driver chip 107 may include bumps 105 corresponding to the first pad PAD1. Multiple bumps 105 may be configured to face pads, such as the first pad PAD1, located in the non-display area NA. For example, the bumps 105 of the driver chip 107 may overlap with the first pad PAD1.

[0105] An anisotropic conductive film 103 is disposed between the driver chip 107 and the pad PAD1.

[0106] The anisotropic conductive film 103 includes an adhesive member 101 and a plurality of conductive balls 102. The adhesive member 101 allows the driver chip 107 to be attached to the display panel 110, and the conductive balls 102 are irregularly distributed within the adhesive member 101 to allow the driver chip 107 to be electrically connected to the first pad PAD1.

[0107] The conductive ball 102 can be the conductive particle itself, a particle with a metal layer coated on a polymer resin particle, or a particle with an insulating resin coated on the surface of the conductive particle or the particle with the metal layer. For example, the metal layer can be made of a material such as nickel (Ni) or gold (Au). However, this disclosure is not limited thereto.

[0108] The anisotropic conductive film 103 can be configured to overlap with the edge portion of the planarization layer 131, which is arranged to overlap with the edge CE of the driver chip 107.

[0109] Since the driver chip 107 is electrically connected to the first pad PAD1 via the conductive ball 102, pressure is applied when the driver chip 107 is installed, causing the conductive ball 102 to contact the bump 105 and the first pad PAD1. Figure 4 It is along Figure 3 The cross-sectional view taken from line I-I'.

[0110] Figure 5 (A) and Figure 5 (B) is along Figure 3 A cross-sectional view taken from line A-A'.

[0111] Figure 5 (A) and Figure 5 (B) is a cross-sectional view of the first wiring structure B of the example embodiment, wherein, compared with the existing first wiring structure A, a metal wiring layer is disposed above and below the GIP wiring to prevent the GIP wiring from breaking due to cracks appearing around the driver chip in a high-temperature and high-humidity reliability environment after the COP process of bonding the driver chip to the display panel.

[0112] Reference Figure 5 (A) Figure 5 (A) is a conventional first wiring structure in which no metal wiring layers are set on the top and bottom of the GIP wiring, and Figure 5 (B) is a first wiring structure according to an exemplary embodiment of the present disclosure, wherein metal wiring layers are disposed above and below the GIP wiring, thereby preventing the GIP wiring from breaking even if a crack occurs around the driver chip. For example, a first metal wiring layer 116 may be disposed below the GIP wiring 122, and a second metal wiring layer 124 may be disposed above the GIP wiring 122.

[0113] Reference Figure 5 (A) The existing first wiring W1 structure is such that a buffer layer 121 is disposed on a substrate 111, a GIP wiring 122 is disposed on the buffer layer 121, and a gate insulating layer 123 is disposed on the GIP wiring 122. After the COP process of bonding the driver chip to the display panel, it is not possible to prevent the GIP wiring from breaking due to cracks around the driver chip in a high temperature and high humidity reliability environment.

[0114] Reference Figure 5(B) The first wiring W1 structure of the exemplary embodiment of this disclosure is a structure in which a first metal wiring layer 116 is disposed on a substrate 111, a buffer layer 121 is disposed on the first metal wiring layer 116, a GIP wiring 122 is disposed on the buffer layer 121, a gate insulating layer 123 is disposed on the GIP wiring 122, a second metal wiring layer 124 is disposed on the gate insulating layer 123, and an interlayer insulating layer 125 is disposed on the second metal wiring layer 124. After the COP process of bonding the driver chip to the display panel, it is possible to prevent the GIP wiring from breaking due to cracks appearing around the driver chip in a high temperature and high humidity reliability environment.

[0115] Reference Figure 5 In section (B), the first metal wiring layer 116 and the second metal wiring layer 124, which are disposed at the bottom and top to protect the GIP wiring 122, are not in the form of a single board, but have a wiring width greater than or equal to that of the GIP wiring 122, and space may exist between each wiring layer. For example, the wiring width of the first metal wiring layer 116 and the second metal wiring layer 124 may be greater than or equal to the wiring width of the GIP wiring 122.

[0116] The first metal wiring layer 116 and the second metal wiring layer 124 are in an electrically floating state.

[0117] The first metal wiring layer 116 and the second metal wiring layer 124 can be made of both Mo and Al, and can overlap with all the metal layers used in TFTs and TOEs without adding a mask.

[0118] To prevent mask addition, the first metal wiring layer 116, which serves as the lower floating wiring, uses a light-shielding layer wiring below the GIP wiring, and the second metal wiring layer 124, which serves as the upper floating wiring, can use any metal below the touch interlayer insulating layer, which serves as the top layer of the corresponding region. For example, the second metal wiring layer 24 can be any of the following: dummy metal layer TM1, the gate metal layer O-GATE of the oxide transistor, the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the touch electrode metal layer TOE TM1.

[0119] Figure 6 This is a diagram showing a crack situation when an example implementation is applied.

[0120] Figure 6(A) is a diagram illustrating the occurrence of cracks in the film. When stress concentrates and cracks appear around the driver chip when the driver chip is mounted on the display panel, gaps caused by the cracks can be formed in the buffer layer 121 between the GIP wiring 122 and the first metal wiring layer 116, gaps caused by the cracks can be formed in the gate insulating layer 123 between the GIP wiring 122 and the second metal wiring layer 124, and gaps caused by the cracks can be formed in the interlayer insulating layer 125 between the second metal wiring layer 124 and the ACF 140.

[0121] Figure 6 (B) is a diagram illustrating the oxidation and dissolution of the first metal wiring layer 116 and the second metal wiring layer 124 after cracks appear in the inorganic film. Even if cracks appear in the inorganic film in a reliable environment, the second metal wiring layer 124 and the first metal wiring layer 116, as floating wiring disposed on the upper and lower parts of the GIP wiring 122, preferentially prevent oxidation, and the oxidation and dissolution of the second metal wiring layer 124 and the first metal wiring layer 116 on the upper and lower parts of the GIP wiring 122 first enter into the gaps formed in the buffer layer 121, the gate insulating layer 123, and the interlayer insulating layer 125, thereby preventing the oxidation and dissolution of the GIP wiring 122. Furthermore, even if cracks occur in the GIP wiring 122 and a short circuit occurs between the first metal wiring layer 116 and the second metal wiring layer 124, which are floating wiring, the GIP wiring 122 can still operate normally because the GIP wiring 122 is separated from each other.

[0122] The GIP wiring of the display device according to this disclosure can provide a display device with improved reliability by arranging a first metal wiring layer and a second metal wiring layer at the bottom and top of the GIP wiring, so as to protect the GIP wiring from moisture penetration caused by cracks around the driver chip and corrosion failures of the pads or wiring.

[0123] The first and second metal wiring layers, which are floating wirings disposed below and above the GIP wirings of the display device according to the present disclosure, are greater than or equal to the GIP wirings. The first and second metal wiring layers disposed below and above the GIP wirings are first protected from oxidation, and the oxidation and dissolution of the first and second metal wiring layers, which are floating wirings, are first performed. This protects the GIP wirings from moisture penetration caused by cracks around the driver chip and corrosion failures of the pads or wirings, thereby improving the reliability of the display device.

[0124] The display device according to this disclosure can minimize the occurrence of defects in the display device by utilizing the same process, thereby reducing the production energy used to produce the display device and reducing the use of hazardous production materials or regulated substances, which is conducive to recycling and can achieve an eco-friendly display device.

[0125] The display device according to this disclosure can improve reliability by providing a first metal wiring layer and a second metal wiring layer below and above the GIP wiring, so as to protect the GIP wiring from moisture penetration caused by cracks around the driver chip and corrosion defects of the pads or wiring.

[0126] The width of the first and second metal wiring layers, which are floating wiring disposed below and above the GIP wiring of the display device according to this disclosure, can be greater than or equal to the width of the GIP wiring. The first and second metal wiring layers disposed below and above the GIP wiring can prevent oxidation first, and oxidation and dissolution of the floating wiring (i.e., the first and second metal wiring layers) can occur first, thereby protecting the GIP wiring from moisture penetration due to cracks around the driver chip and corrosion defects in the pads or wiring, and thus providing a display device with improved reliability.

[0127] The display device according to this disclosure can minimize the occurrence of defects in the display device by utilizing the same process, thereby reducing the production energy required to manufacture the display device and reducing the use of hazardous production materials or regulated substances, thus facilitating the recycling and realization of environmentally friendly display devices.

[0128] Although the above description focuses on implementation methods, these are merely examples and do not limit this disclosure. This disclosure is not limited to the above-described implementation methods and drawings, and the features, structures, effects, etc., illustrated in each implementation can be achieved by combining or modifying them. Therefore, anything related to such combinations and modifications should be interpreted as being included within the scope of this disclosure.

[0129] Cross-reference to related applications

[0130] This application claims priority to Korean Patent Application No. 10-2024-0188780, filed on December 17, 2024, which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising: The display panel includes a display area and a non-display area. as well as A driver chip is disposed in the non-display area. The first wiring portion surrounding the driver chip includes: substrate; A first metal wiring layer is located on the substrate; The panel features a gated GIP (Guided In-line Package) wiring, which is located above the first metal wiring layer; and A second metal wiring layer is located above the GIP wiring.

2. The display device according to claim 1, further comprising: A buffer layer is located between the first metal wiring layer and the GIP wiring; A gate insulating layer, wherein the gate insulating layer is located between the GIP wiring and the second metal wiring layer; as well as An interlayer insulating layer is located on the second metal wiring layer.

3. The display device according to claim 1, in, The first metal wiring layer and the second metal wiring layer are in an electrically floating state.

4. The display device according to claim 1, in, The first metal wiring layer and the second metal wiring layer comprise molybdenum (Mo) or aluminum (Al).

5. The display device according to claim 1, in, The first metal wiring layer is disposed on the same layer as the light-shielding layer wiring of the display area, below the GIP wiring.

6. The display device according to claim 1, in, The GIP wiring includes molybdenum (Mo).

7. The display device according to claim 1, in, The wiring width of the first metal wiring layer and the second metal wiring layer is greater than or equal to the wiring width of the GIP wiring.

8. The display device according to claim 1, in, The GIP wiring is formed as a structure that is separate from each other.

9. The display device according to claim 1, wherein, The first metal wiring layer, the second metal wiring layer, and the GIP wiring are spaced apart from each other.

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