Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes: an interlayer insulating film disposed on a substrate, the interlayer insulating film having a recess that exposes a portion of the substrate; a bottom electrode contact (BEC) embedded in at least a portion of the recess; and an MTJ layer disposed on the interlayer insulating film and the bottom electrode contact, wherein the bottom electrode contact comprises a Co alloy, an Fe alloy, a Ni alloy, or a Mn alloy, the alloy comprising at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, Zr, Hf, and rare earth metals.

Description

Cross-references to relevant applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0189468, filed on December 18, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to semiconductor devices having a magnetic tunnel junction structure and methods for manufacturing the semiconductor device. Background Technology

[0003] In recent years, to address the trends of miniaturization, low power consumption, high performance, and diversification in electronic devices, there is a need for semiconductor devices capable of storing data in various electronic devices, such as computers and portable communication devices. Therefore, the semiconductor industry has devoted significant research and development efforts to researching and developing such semiconductor devices. Typically, semiconductor devices include memories that can store data by utilizing the characteristic of switching between different resistance states according to applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses. Summary of the Invention

[0004] Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the same, which enable an increase in magnetoresistance (MR) and exchange bias field (Hex) by forming a layer that simultaneously serves as an offset cancellation layer (SCL) and a bottom electrode contact (BEC), without the need to use a specific alloy to form a separate offset cancellation layer (SCL), thereby reducing the height of the magnetic tunnel junction (MTJ) structure and enabling high-temperature heat treatment.

[0005] According to one embodiment of the present disclosure, a semiconductor device includes: an interlayer insulating film disposed on a substrate, the interlayer insulating film having a recess that exposes a portion of the substrate; a bottom electrode contact (BEC) embedded in at least a portion of the recess; and an MTJ layer disposed on the interlayer insulating film and the bottom electrode contact, wherein the bottom electrode contact comprises a Co alloy, an Fe alloy, a Ni alloy, or a Mn alloy, the alloy comprising at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, Zr, Hf, and rare earth metals.

[0006] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device includes: forming an interlayer insulating film on a substrate; selectively etching the interlayer insulating film to form a recess exposing a portion of the substrate; and forming a bottom electrode contact embedded in at least a portion of the recess; and forming a variable resistance element on the bottom electrode contact, wherein the bottom electrode contact comprises a Co alloy, an Fe alloy, a Ni alloy, or a Mn alloy, the alloys comprising at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, and rare earth metals.

[0007] These and other features and advantages of the present invention will be better understood by those skilled in the art through the description of the embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figures 1A to 1D These are perspective and cross-sectional views of a semiconductor device according to a comparative example.

[0009] Figures 2A to 2C These are perspective and cross-sectional views illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 3A to 3G This is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to an embodiment of the present disclosure. Detailed Implementation

[0011] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same components in the various figures and embodiments.

[0012] Different embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0013] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When referring to a first layer being "on" a second layer or "on" a substrate, this means not only that the first layer is formed directly on the second layer or substrate, but also that a third layer exists between the first layer and the second layer or substrate.

[0014] Figures 1A to 1D A perspective view and a cross-sectional view of the semiconductor device according to the comparative example are shown. Figure 1A A floor plan is shown. Figure 1B It shows along Figure 1A A cross-sectional view of line A-A'.

[0015] refer to Figure 1A and Figure 1B According to the comparative example, the semiconductor device may have a cross-point structure, including a first wiring 110 formed on the substrate 100 and extending along a first direction, a second wiring 180 located on the first wiring 110 and extending along a second direction intersecting the first direction, and a memory cell 170 disposed at a corresponding cross-section between the first wiring 110 and the second wiring 180.

[0016] The substrate 100 may include a semiconductor material, such as silicon. Any desired predetermined substructure (not shown) may be formed within the substrate 100. For example, the substructure may include electrically connected drive circuitry (not shown) to control a first wiring 110 and / or a second wiring 180 formed on the substrate 100.

[0017] The first wiring 110 and the second wiring 180 can be connected to the memory cell 170 to provide voltage or current to drive the memory cell 170. One of the first wiring 110 and the second wiring 180 can be used as a word line, and the other can be used as a bit line. The first wiring 110 and the second wiring 180 can have a multi-film structure or a single-film structure including conductive material.

[0018] The storage cells 170 can be arranged in a matrix along the first and second directions to overlap with the intersection area of ​​the first wiring 110 and the second wiring 180. The space between the first wiring 110, the second wiring 180 and the storage cells 170 can be embedded with insulating material.

[0019] The storage cell 170 may include a stacked structure that may include a bottom electrode contact 120, an offset cancellation layer 130, a spacer layer 140, an MTJ layer 150, and a selector layer 160. Furthermore, a first interlayer insulating film 125 may be formed covering the sidewalls of the bottom electrode contact 120, and a second interlayer insulating film 165 may be formed covering the sidewalls of the multilayer (ML) offset cancellation layer 130, the spacer layer 140, the MTJ layer 150, and the selector layer 160.

[0020] An offset compensation layer 130 may be formed between the bottom electrode contact 120 and the spacer layer 140. The offset compensation layer 130 can be used to compensate for magnetic offset via a magnetization direction antiparallel to the fixed layer, which reduces sensitivity to changes in external magnetic fields, thereby improving the reliability of the MTJ device and reducing data errors. Furthermore, the offset compensation layer 130 can form a synthetic antiferromagnetic (SAF) structure with the fixed layer to improve magnetic stability and control the hysteresis of the MTJ device, thus enabling it to maintain high sensitivity in low magnetic fields. The offset compensation layer 130 can be magnetically coupled to the fixed layer via the spacer layer 140, which typically comprises a nonmagnetic metal such as Ru, Ir, or Cr.

[0021] Reference Figure 1C and Figure 1D The comparative example shows a cross-sectional view of the variable resistor element to describe the length from the upper surface of the bottom electrode contact 120 to the upper surface of the MTJ layer 150, i.e., the height H1 of the variable resistor element in the semiconductor device according to this comparative example.

[0022] Figure 1C The diagram shows a cross-sectional view of a variable resistive element having multiple layers of offset cancellation layers 130, spacer layers 140, a fixed layer 151 with a fixed magnetization direction, a free layer 153 with a variable magnetization direction, and a tunnel barrier layer 152 between the fixed layer 151 and the free layer 153, all stacked on a bottom electrode contact 120. The variable resistive element may include an MTJ layer 150, which may include the fixed layer 151, the free layer 153, and the tunnel barrier layer 152.

[0023] The multilayer offset cancellation layer 130 can have a stacked structure in which magnetic (FM) and non-magnetic (NM) layers alternate in a repeating structure. For example, this is a structure such as [FM / NM]n, where the combination of the layers forms the desired magnetic properties. The multilayer offset cancellation layer 130 can tune its magnetic properties by adjusting the thickness and composition of each layer, can exhibit a synthetic antiferromagnetic (SAF) effect through interlayer coupling, and has relatively low thermal stability due to interlayer diffusion that may occur during high-temperature processing.

[0024] In contrast, alloy offset offset layer ( Figure 1D The 130A (of which) is made of a single material or a homogeneous alloy and has unique magnetic properties. These magnetic properties can be obtained directly from the bulk properties of the material itself and usually have high magnetic anisotropy, making them thermally stable and suitable for high-temperature processes.

[0025] refer to Figure 1DThe multilayer offset offset layer 130 has low thermal stability and can be replaced by an alloy offset offset layer 130A with higher thermal stability. However, although the alloy offset offset layer 130A is thermally stable, it has a larger thickness compared to the multilayer offset offset layer 130. Figure 1D The alloy offset cancellation layer 130A may require a relatively thick layer to possess inherent magnetic anisotropy. Specifically, cobalt alloys or rare-earth-transition metal alloys with bulk magnetic anisotropy may be limited in forming effective magnetic coupling in thin layers such as multilayer offset cancellation layers, requiring a certain thickness to guarantee performance. Furthermore, since the alloy offset cancellation layer 130A must provide overall performance as a single material, it must be manufactured thicker to maintain performance and stability, and its physical thickness can be greater to achieve magnetic properties such as those of the multilayer offset cancellation layer 130 by being composed of a single material. As a result, the height H2 of the variable resistor element including the alloy offset cancellation layer 130A can be higher than the height H1 of the variable resistor element including the multilayer offset cancellation layer 130.

[0026] The lower height of variable resistors allows for the placement of more components within the same area, increasing device density—crucial for capacity enhancement, especially in memory semiconductors. Furthermore, the lower height of variable resistors allows for shorter current paths, reducing resistance and minimizing power loss, while faster signal transmission speeds further reduce power consumption and enable efficient operation of memory semiconductors. Simultaneously, heat generation is also reduced.

[0027] According to one embodiment of the present disclosure, a semiconductor device and a method for manufacturing the semiconductor device solve the following problem: Figure 1C The problem of decreased thermal stability observed in the multilayer offset compensation layer 130, and the problem caused by Figure 1D The present disclosure addresses the problem of increased height of the variable resistor element caused by the alloy offset offset layer 130A. To resolve these issues, a method is provided in which an alloy offset offset layer (which serves as both an offset offset layer and a bottom electrode contact) is embedded in at least a portion of a recess in an interlayer insulating film using a specific alloy, effectively reducing the height of the variable resistor element and improving thermal stability. This will be referenced... Figures 2A to 2C To provide a more detailed description.

[0028] Figure 2A and Figure 2B A diagram illustrating a semiconductor memory according to an embodiment of the present disclosure. Figure 2A A floor plan is shown, and Figure 2B It shows along Figure 2A A cross-sectional view of line A-A'.

[0029] refer to Figure 2A and Figure 2B According to this embodiment, the semiconductor memory may have a crossover structure, including: a first wiring 210 formed on a substrate 200 and extending along a first direction; a second wiring 280 located on the first wiring 210 and extending along a second direction intersecting the first direction; and memory cells 270 disposed at corresponding intersections between the first wiring 210 and the second wiring 280. The semiconductor memory may include: a plurality of first wirings 210 spaced apart from each other; a plurality of second wirings 280 spaced apart from each other; and a plurality of memory cells 270 disposed at corresponding intersections of the plurality of first wirings 210 and the plurality of second wirings 280.

[0030] The substrate 200 may include a semiconductor material, such as silicon. Any desired predetermined substructure (not shown) may be formed within the substrate 200. For example, the substructure may include electrically connected drive circuitry (not shown) to control a first wiring 210 and / or a second wiring 280 formed on the substrate 200.

[0031] The first wiring 210 and the second wiring 280 can be connected to the memory cell 270 to provide voltage or current to the memory cell 270 to drive the memory cell 270. One of the first wiring 210 and the second wiring 280 can be used as a word line, and the other can be used as a bit line. The first wiring 210 and the second wiring 280 can have a multi-film structure or a single-film structure containing a conductive material. Examples of conductive materials may include, but are not limited to, metals, metal nitrides, conductive carbon materials, or combinations thereof. For example, the first wiring 210 and the second wiring 280 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), or any combination thereof.

[0032] Storage cells 270 can be arranged in a matrix along a first direction and a second direction to overlap with the intersection areas of the first wiring 210 and the second wiring 280. In this embodiment, the size of the storage cells 270 can be smaller than or equal to the intersection areas of the first wiring 210 and the second wiring 280; however, in other embodiments, the size of the storage cells 270 can be larger than these intersection areas. The space between the first wiring 210, the second wiring 280 and the storage cells 270 can be embedded with insulating material.

[0033] The memory cell 270 may include a stacked structure, wherein the stacked structure may include a bottom electrode contact 220, a spacer layer 240, an MTJ layer 250, and a selector layer 260. Furthermore, a first interlayer insulating film 225 may be formed covering the sidewalls of the bottom electrode contact 220. Additionally, a second interlayer insulating film 265 may be formed covering the sidewalls of the spacer layer 240, the MTJ layer 250, and the selector layer 260.

[0034] The first interlayer insulating film 225 and the second interlayer insulating film 265 may comprise insulating materials, polysilicon (Poly-Si), or any combination thereof, and may be organized into a single-film structure or a multi-film structure. For example, the first interlayer insulating film 225 and the second interlayer insulating film 265 may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or low-k materials. Materials with a dielectric constant (k) of 4 or lower are generally referred to as low-k materials, and lower values ​​provide better electrical insulation properties, thereby reducing parasitic capacitance between devices. The semiconductor memory according to this embodiment may have a crossover structure, which includes a first wiring 210 formed on a substrate 200 and extending along a first direction, a second wiring 280 located on the first wiring 210 and extending along a second direction intersecting the first direction, and memory cells 270 disposed at corresponding crossovers between the first wiring 210 and the second wiring 280. These low-k materials include, but are not limited to, silicon oxide, organosiloxanes, silicon carbide, organic-based materials including benzene rings or fluorine, and void materials.

[0035] Bottom electrode contact 220 may be formed between the first wiring 210 and the spacer layer 240. Bottom electrode contact 220 may be located at the bottom of the storage cell 270 and may be electrically connected to the first wiring 210. Bottom electrode contact 220 may be used as a conduit for transmitting current or voltage between the first wiring 210 and the storage cell 270.

[0036] The bottom electrode contact 220 serves not only as a conduit for carrying current or voltage between the first wiring 210 and the storage cell 270, but also as an offset cancellation layer that compensates for magnetic offset by a magnetization direction that is antiparallel to the fixed layer of the MTJ layer 250. This reduces sensitivity to changes in external magnetic fields, thereby improving the reliability of the MTJ device and reducing data errors. The bottom electrode contact 220, acting as an offset cancellation layer, can have a magnetization direction antiparallel to the fixed layer of the MTJ layer 250, and can suppress unwanted magnetization changes in the magnetic material due to external magnetic fields. By setting the magnetization direction antiparallel to the fixed layer of the MTJ layer 250, unwanted magnetization reversals that may be caused by external magnetic fields can be counteracted, thus improving stability. This, in turn, reduces magnetic noise in the storage device, enabling the MTJ device to maintain a constant state and ensuring accurate data storage and retrieval.

[0037] The bottom electrode contact 220 can be used simultaneously as an offset cancellation layer and a bottom electrode contact by comprising a Co alloy, Fe alloy, Ni alloy, or Mn alloy (these alloys contain at least one selected from the group consisting of platinum (Pt), palladium (Pd), aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals). These alloys are suitable as materials for bottom electrode contacts because they allow gap filling in the recessed region, offset cancellation, and simultaneously form synthetic antiferromagnetism (SAF) perpendicular to the fixed layer, as well as maintaining perpendicular magnetic anisotropy (PMA) at high temperatures without degrading the synthetic antiferromagnetism. While gap-filling materials have been used for bottom electrode contacts in the past, the inventors have unexpectedly discovered for the first time an alloy that serves as an offset cancellation layer while filling the gap, and without degrading performance at high temperatures.

[0038] Specifically, the bottom electrode contact 220 may comprise a Pt-containing Co alloy, an ordered phase alloy, or a rare earth transition metal (RE-TM) alloy. Pt-containing Co alloys improve corrosion resistance and thermal stability by introducing Pt, and are also more conductive, making them suitable for use as bottom electrode contacts. Ordered phase alloys are ideal for use as bottom electrode contacts because their structural stability and predictable magnetic and electronic properties allow for consistent conductivity and improve device reliability. Furthermore, rare earth transition metal (RE-TM) alloys possess strong magnetism and stable layer formation, which minimizes diffusion and enhances the interfacial stability of the bottom electrode contact.

[0039] Co alloys containing Pt can consist of only Co and Pt, or they can contain other elements besides Co and Pt. For example, CoPt alloys have high magnetic anisotropy, making them suitable as offset cancellation layers. In particular, CoPt alloys with L10 alignment can help maintain stable magnetization orientation, thereby reducing sensitivity to external magnetic fields. CoPt3 alloys have high magnetic anisotropy and low domain transition coercivity, which can help maintain stable magnetic properties. CoCrPt alloys have the effect of improving magnetic stability and durability, which can further enhance their function as offset cancellation layers. The addition of Cr improves corrosion resistance and enables stable magnetic properties to be maintained at high temperatures.

[0040] Ordered phase alloys include alloys with special structures designed to be magnetic and possessing stable magnetic properties, and can include, for example, CoPt, NiPt, FePt, FePd, MnAl, MnGa, NiPt, CoZr, CoHf, and Co3Pt alloys. CoPt alloys with an L10 structure (where the Co to Pt ratio is 1:1 and they are arranged in an ordered manner) provide high magnetic anisotropy and stable magnetization direction, making them suitable as offset compensation layers to compensate for magnetic deflection. FeNi alloys with an L10 structure composed of Fe and Ni exhibit high magnetic anisotropy and are suitable for use as offset compensation layers in memory cells. FePt alloys with an L11 structure (where Fe and Pt are arranged in an ordered manner) provide high magnetic stability and maintain good magnetic properties even at high temperatures, making them suitable as offset compensation layers. [The text then abruptly shifts to a different topic:] ...with D0... 19 The Co3Pt alloy structure has Co and Pt arranged in a specific pattern and can provide high magnetic stability. The high resistance of the Co3Pt alloy to external magnetic fields makes it suitable as a offset cancellation layer.

[0041] Rare-earth transition metal alloys are alloys that combine rare-earth (RE) metals with transition metals (TM) and possess high magnetic anisotropy, meaning that the magnetization direction can be controlled, thus achieving high magnetic stability. Furthermore, rare-earth transition metal alloys can have high magnetic susceptibility, meaning that they can easily change their magnetization direction under the influence of a magnetic field. These properties make them suitable for performing functions such as magnetic deflection. Rare-earth transition metals can include, for example, TbFe, GdCo, DyFe, HoFe, NdFeB, SmCo, LaCoO3, GdFe2, TbDyFe, PrCo, etc. TbFe alloys have high magnetic anisotropy and high magnetic stability, making them suitable as deflection compensation layers and maintaining stable magnetic properties even at high temperatures. GdCo alloys offer high magnetic susceptibility and strong magnetic interaction, making them effective as deflection compensation layers and suitable for applications requiring the maintenance of magnetic properties, especially at high temperatures. DyFe alloys offer high magnetic stability and strong magnetic properties, making them advantageous when used as deflection compensation layers to compensate for magnetic deflection. HoFe alloys offer strong magnetic anisotropy and high magnetic stability, and are effective as offset cancellation layers. NdFeB alloys offer high magnetic anisotropy and extremely high magnetic susceptibility, making them suitable as strong magnetic offset cancellation layers. NdFeB alloys not only provide strong magnetic properties but also effectively perform offset cancellation.

[0042] The selector layer 260 can be implemented as a thin film within the memory cell 270 and can be used to control electrical access to any one of the plurality of memory cells 270 in the array, and to prevent current leakage that may occur between memory cells 270 sharing the first wiring 210 or the second wiring 280. To this end, the selector layer 260 can have threshold switching characteristics, i.e., allowing current to be blocked or a small amount of current to flow when the magnitude of the voltage supplied to the top and bottom sides of the selector layer is below a predetermined threshold voltage, and allowing current to flow rapidly when the magnitude of the voltage supplied to the top and bottom sides of the selector layer is above the threshold voltage. In other words, the selector layer 260 can be turned on above the threshold voltage and turned off below the threshold voltage. In one embodiment, the selector layer 260 may include an insulating material implanted with dopant.

[0043] In the semiconductor device according to this embodiment, reference will be made to the diagram shown below. Figure 2C The cross-sectional view of the variable resistor element in the embodiment is used to describe the length from the upper surface of the bottom electrode contact 220 to the upper surface of the MTJ layer 250, which is the height H3 of the variable resistor element.

[0044] Figure 2CThis is a cross-sectional view of a variable resistor element, wherein an MTJ layer 250 is stacked on a bottom electrode contact formed of a Co alloy including Pt, an ordered phase alloy, or a rare earth-transition metal alloy, which also serves as an offset cancellation layer. The MTJ layer 250 includes a spacer layer 240, a fixed layer 251 having a fixed magnetization direction, a free layer 253 having a variable magnetization direction, and a tunnel barrier layer 252 between the fixed layer 251 and the free layer 253.

[0045] The free layer 253 and the fixed layer 251 may contain materials with interfacial perpendicular magnetic anisotropy. Interfacial perpendicular magnetic anisotropy refers to the phenomenon that a magnetic layer with inherent horizontal magnetization characteristics has a magnetization direction perpendicular to its interface due to the influence from the interface of another layer adjacent to it. Here, inherent horizontal magnetization characteristics mean that, in the absence of external factors, the magnetization direction of the magnetic layer is parallel to its widest surface. For example, if a magnetic layer with inherent horizontal magnetization characteristics is formed on a substrate, and there are no external factors, the magnetization direction of the magnetic layer can be substantially parallel to the top surface of the substrate. Each of the free layer 253 and the fixed layer 251 may have a multi-film structure or a single-film structure containing ferromagnetic materials. Ferromagnetic materials may include Fe, Ni, or Co-based alloys, such as Fe-Pt alloys, Fe-Pd alloys, Co-Fe alloys, Co-Pd alloys, Co-Pt alloys, Co-Fe-Ni alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, Co-Fe-B alloys, etc., or may include laminated structures, such as Co / Pt, Co / Pd, etc. The positions of the free layer 253 and the fixed layer 251 may be reversed across the tunnel barrier layer 252. For example, the free layer 253 may be located above the tunnel barrier layer 252, while the fixed layer 251 may be located below the tunnel barrier layer 252 and above the bottom electrode pattern 221. The tunnel barrier layer 252 can cause electrons to tunnel between the free layer and the fixed layer during a write operation that changes the resistance state of the variable resistive element, thereby causing a change in the magnetization direction of the free layer 253. The tunnel barrier layer 252 may include at least one of the following: oxides of magnesium (Mg), oxides of titanium (Ti), aluminum (Al), oxides of magnesium zinc (MgZn), oxides of magnesium boron (MgB), nitrides of titanium (Ti), and nitrides of vanadium (V). In one embodiment, the tunnel barrier layer 252 may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier layer 252 may include multiple layers. The free layer 253, the tunnel barrier layer 252, and the fixed layer 251 may form the MTJ layer 250.

[0046] The resistance of the MTJ layer 250 can depend on the magnetization directions of the fixed layer 251 and the free layer 253. For example, the resistance of the MTJ layer 250 can be much larger when the magnetization directions of the fixed layer 251 and the free layer 253 are antiparallel than when they are parallel. Therefore, the resistance of the MTJ layer 250 can be adjusted by changing the magnetization direction of the free layer 253, which can be used as a data storage principle in the semiconductor device according to this disclosure.

[0047] Because the offset cancellation layer is embedded in the recessed portion of the first interlayer insulating film 225, the height H3 of the variable resistor element in this embodiment can be determined according to... Figure 1C The height of the multi-layer offset offset layer 130 in the comparative example or according to Figure 1D The height of the alloy offset offset layer 130A in the comparative example is as low. Therefore, according to Figure 1D In the comparative example, the height H2 of the variable resistor element can be the highest, according to Figure 1C The height H1 of the variable resistor element in the comparative example may be the second highest, while the height H3 of the variable resistor element in this embodiment can be significantly lower compared to them. Therefore, in the semiconductor device according to this embodiment, more devices can be arranged in the same area, thereby increasing device density and shortening the current flow path, thereby reducing resistance and minimizing power loss. In addition, signal transmission speed can be improved, which can reduce power consumption and enable efficient operation of memory semiconductors, while also reducing heat generation.

[0048] If according to Figure 1C In the comparative example, the multilayer offset cancellation layer 130, when subjected to high-temperature heat treatment, may experience interdiffusion, leading to a decrease in the synthesized antiferromagnetic properties. In contrast, the bottom electrode contact 220 in this embodiment is made of a Co alloy containing platinum (Pt), an ordered phase alloy, or a rare-earth transition metal (RE-TM) alloy, which possesses excellent thermal stability and is suitable for high-temperature processing. This allows for high-temperature processing, which in turn can improve the magnetoresistance (MR) of the MTJ layer (250). Meanwhile, according to... Figure 1D The alloy offset cancellation layer 130A of the comparative example can improve magnetoresistance and exchange bias field, but the height of the variable resistor element increases due to the lower magnetic saturation intensity (Ms) * thickness (t). However, in the semiconductor device of this embodiment, the bottom electrode contact 220 can also act as an offset cancellation layer, so the height of the variable resistor element can be reduced as the magnetoresistance and exchange bias field of the MTJ layer 250 increase.

[0049] As a offset compensation layer, the bottom electrode contact 220 can be used to offset or reduce the influence of stray magnetic fields generated by the fixed layer 251, thereby reducing the influence of stray magnetic fields on the free layer 253 and reducing the deflection magnetic field in the free layer 253. This can offset the offset of the magnetization reversal characteristics (hysteresis curve) of the free layer 253 caused by the fixed layer 251.

[0050] Therefore, the magnetization direction of the bottom electrode contact 220 can be parallel to the magnetization direction of the fixed layer 251. For example, if the magnetization direction of the fixed layer 251 is from top to bottom, the magnetization direction of the bottom electrode contact 220 can be from bottom to top; conversely, if the magnetization direction of the fixed layer 251 is from bottom to top, the magnetization direction of the bottom electrode contact 220 can be from top to bottom. Furthermore, the bottom electrode contact 220 can be antiferromagnetically exchange-coupled with the fixed layer 251 via the spacer layer 240 to form a synthetic antiferromagnetic (SAF) structure.

[0051] In this embodiment, by using a specific alloy as the bottom electrode contact 220, there are fewer interlayer junctions, and the interface energy and interface diffusion problems that may occur in the multilayer offset cancellation layer can be reduced, which can further improve the thermal stability in high-temperature processes. In addition, the single-layer structure of the bottom electrode contact 220 made of this alloy can simplify the manufacturing process, thereby improving production efficiency, and can maintain high magnetic properties by reducing interlayer scattering, which allows it to function more effectively as an offset cancellation layer.

[0052] For multilayer offset offset layers, since each layer in the multilayer structure is made up independently, it may be difficult to uniformly embed them into the recessed region. This is because the interfaces between the layers in the recessed region may be uneven, making it difficult to maintain thickness uniformity and interface consistency, and potentially leading to inconsistencies in thermal and magnetic properties. On the other hand, the bottom electrode contact 220 made of the alloy is composed of a uniform monolayer, which facilitates its embedding into the recessed region, thereby simultaneously improving the consistency of the manufacturing process and the reliability of the device.

[0053] A material layer (not shown) may be inserted between the fixing layer 251 and the bottom electrode contact 220 to bridge the lattice structure differences and lattice mismatch between the fixing layer 251 and the bottom electrode contact 220. For example, such a material layer may be amorphous and may further include conductive materials such as metals, metal nitrides, metal oxides, etc.

[0054] Spacer layer 240 may be situated between fixed layer 251 and bottom electrode contact 220 to act as a buffer layer between the two and enhance the performance of bottom electrode contact 220 as an offset offset layer. Specifically, fixed layer 251 and bottom electrode contact 220 may be antiferromagnetically exchange-coupled via spacer layer 240 to form a synthetic antiferromagnetic (SAF) structure. Spacer layer 240 may contain noble metals such as Ru, Ir, Cr, or any combination thereof. For example, the thickness of spacer layer 240 may be 0.5 nm or greater. Thus, a thicker spacer layer 240 can prevent its performance from degrading due to subsequent heat treatment processes and can improve the strength of the antiferromagnetic exchange coupling between fixed layer 251 and bottom electrode contact 220.

[0055] Alternatively, an intermediate layer (not shown) may be inserted between the tunnel barrier layer 252 and the fixed layer 251. The intermediate layer may be the magnetic layer closest to the tunnel barrier layer 252 and may contain Co, Fe, Ni, B, other noble metals or combinations thereof.

[0056] A variable resistive element comprising spacer layer 240 and MTJ layer 250 can be used to store different data by switching between different resistance states according to the voltage or current applied through the top and bottom. The variable resistive element may include metal oxides (such as transition metal oxides used in RRAM, PRAM, FRAM, MRAM, etc., perovskite materials, etc.), phase change materials (such as chalcogenide materials), ferroelectric materials, ferromagnetic materials, etc. The variable resistive element may have a single-film structure or a multi-film structure, in which a combination of two or more films exhibits variable resistive characteristics.

[0057] Figures 3A to 3G This is a cross-sectional view used to illustrate a semiconductor device and a method for manufacturing the same according to an embodiment of the present disclosure, and is an enlarged cross-sectional view of only one memory cell among a plurality of memory cells. Since its portions are substantially the same as those of the foregoing embodiments, detailed descriptions thereof can be omitted.

[0058] The manufacturing method will be described first.

[0059] refer to Figure 3A and Figure 3B The first wiring 310 can be formed on a substrate 300 on which a predetermined substructure (not shown) is formed. The first wiring 310 can be formed by forming an interlayer insulating film having trenches for forming the first wiring 310 on the substrate 300, forming a conductive layer for forming the first wiring 310 in the trenches, and etching the conductive layer using a linear mask pattern extending in a first direction.

[0060] Subsequently, a bottom electrode contact 320 can be formed on the first wiring 310. The bottom electrode contact 320 can be formed by forming an interlayer insulating film 325 with holes on the structure where the first wiring 310 is formed, forming a material layer for forming the bottom electrode contact 320 on these holes, and then performing a planarization process (such as chemical mechanical planarization). Specifically, photolithography and etching processes can form precisely sized holes at the locations where the bottom electrode contact 320 is to be placed, and the formed holes can be filled with a material layer suitable for the bottom electrode contact 320. Materials suitable for the bottom electrode contact 320 can include Co alloys, Fe alloys, Ni alloys, or Mn alloys, which contain at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, and rare earth metals. These alloys can have high corrosion resistance, thermal stability, and electrical conductivity for use as bottom electrode contacts, while also providing high magnetic stability and serving as a offset offset layer by maintaining good magnetic properties even at high temperatures. Deposition methods can include sputtering or chemical vapor deposition (CVD). After deposition, a chemical mechanical planarization (CMP) process can be performed to planarize the surface, preventing the material filling the pores from overflowing the surface of the first interlayer insulating film 325. Thus, the bottom electrode contact 320 can be planarized and formed to the same height as the surface of the first interlayer insulating film 325. The bottom electrode contact 320 formed by this gap-filling method possesses high corrosion resistance, thermal stability, and conductivity for use as a bottom electrode contact, as well as magnetic properties that enable it to function as an offset offset layer. The formed bottom electrode contact 320 can have a connection with the fixing layer ( Figure 3G The magnetization direction (351A) is parallel to the anti-magnetization direction, which can counteract unwanted magnetization shifts that may be caused by external magnetic fields and has the effect of improving stability.

[0061] refer to Figure 3C A material layer 340 for forming a spacer layer can be formed on the planarized bottom electrode pattern 320 and the first interlayer insulating film 325. Subsequently, a material layer 351 for forming a stationary layer, a material layer 352 for forming a tunnel barrier layer, and a material layer 353 for forming a free layer are formed, all contained within the material layer 350 for forming the MTJ layer. Next, a material layer 360 for forming a selector layer can be formed. The material layers 351 for forming the stationary layer and 353 for forming the free layer can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or electron beam deposition. The material layer 352 for forming the tunnel barrier layer can be deposited using alkali metal oxide or atomic layer deposition (ALD). This method allows for the formation of very thin and uniform oxide films, which enables precise control of the tunneling current.

[0062] Spacer layer ( Figure 3G 340A in the middle can be between Figure 3G A buffer layer 340A is placed between the fixed layer 351A and the bottom electrode contact 320, which acts as a offset offset layer, to achieve antiferromagnetic exchange coupling between the fixed layer 351A and the bottom electrode contact 320 and enhance the performance of the bottom electrode contact 320. The spacer layer 340A may contain a noble metal, such as Ru, Ir, Cr, or any combination thereof. For example, the thickness of the spacer layer 340A may be 0.5 nm or greater. Therefore, a spacer layer 340A with a thickness of 0.5 nm or greater can prevent material diffusion or interaction that may occur during high-temperature heat treatment processes. This thicker spacer layer can prevent any deformation or reaction that may occur in the material at high temperatures, thereby protecting the fixed layer 351A and the bottom electrode contact 320 from any property changes or deterioration. Therefore, the fixed layer 351A and the bottom electrode contact 320 can maintain stability at high temperatures. Furthermore, when the thickness of the spacer layer 340A is 0.5 nm or greater, the antiferromagnetic exchange bond between the fixed layer 351A and the bottom electrode contact 320 can be stronger. This is because the spacer layer 340A can more effectively modulate the interaction between the fixed layer 351A and the bottom electrode contact 320, thereby better controlling the magnetization direction of the fixed layer 351A and improving magnetic stability.

[0063] refer to Figure 3D and Figure 3E A columnar hard mask layer 365 can be deposited on the top surface of the material layer 360 used to form the selector layer. The hard mask layer 365 can be formed of an insulating material such as silicon nitride or silicon oxynitride. For example, the hard mask layer 365 can contain at least one of carbon (C), silicon (Si), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), and nitrides, oxides, borides, and metal nitrides (e.g., titanium nitride and tantalum nitride) containing these elements. The columnar hard mask layer 365 can be used as an etching barrier to selectively etch the material layer 340 used to form the spacer layer, the material layer 351 used to form the anchor layer, the material layer 352 used to form the tunnel barrier layer, the material layer 353 used to form the free layer, and the material layer 360 used to form the selector layer, to form a columnar patterned spacer layer 340A, anchor layer 351A, tunnel barrier layer 352A, free layer 353A, and selector layer 360A. The MTJ layer 350A may include a fixed layer 351A, a tunnel barrier layer 352A, and a free layer 353A.

[0064] refer to Figure 3FA second interlayer insulating film 365 can be formed, covering the sidewalls of the spacer layer 340A, the sidewalls of the MTJ layer 350A comprising the anchor layer 351A, the tunnel barrier layer 352A, and the free layer 353A, and the sidewalls of the selector layer 360A. The second interlayer insulating film 365 can comprise a highly insulating material, such as an insulating material, polysilicon (Poly-Si), or any combination thereof, which provides stability at high temperatures to prevent damage in subsequent processes. The second interlayer insulating film 365 can be deposited uniformly covering the sidewalls of the MTJ layer 350A and the selector layer 360A via chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering processes. This allows for electrical isolation of each memory cell along the sidewalls of the MTJ layer 350A and the selector layer 360A, thereby minimizing surface conductivity and leakage current.

[0065] refer to Figure 3G A second wiring 380 can be formed on top of the memory cell. The second wiring 380 can be formed by first forming a trench, depositing a conductive layer in the trench, and etching the conductive layer using a linear mask pattern (not shown) extending along a second direction. The second wiring 380 can be patterned at a 90-degree angle to the first wiring 310; that is, the first wiring 310 can be formed along... Figure 2A The first wiring extends in the direction of the second wiring 380, while the second wiring 380 can be formed along the direction of the second wiring 380. Figure 2A The second direction extends. This can result in a semiconductor device with an intersection structure, wherein the memory cell is disposed between the first wiring 310 and the second wiring 380, and is located in a region that overlaps with the region where the first wiring 310 and the second wiring 380 intersect each other.

[0066] Through the above-described process, a semiconductor device according to an embodiment of this disclosure can be formed. (See again...) Figure 3G A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first wiring 310, a bottom electrode contact 320, a spacer layer 340A, an MTJ layer 350A (which includes a fixed layer 351A, a tunnel barrier layer 352A, and a free layer 353A), a selector layer 360A, and a second wiring 380. The device may further include: a first interlayer insulating film 325 covering the sidewalls of the bottom electrode contact 320; and a second interlayer insulating film 365 covering the sidewalls of the spacer layer 340A, the sidewalls of the MTJ layer 350A (including the fixed layer 351A, the tunnel barrier layer 352A, and the free layer 353A), and the sidewalls of the selector layer 360A. Figure 3G The process structure can be the same as the above. Figure 2BThe basic process structure is the same. That is to say, the substrate 300, the first wiring 310, the bottom electrode contact 320, the first interlayer insulating film 325, the spacer layer 340A, the MTJ layer 350A, the selector layer 360A, the second interlayer insulating film 365, and the second wiring 380 can be respectively connected to… Figure 2B The substrate 200, first wiring 210, bottom electrode contact 220, first interlayer insulating film 225, spacer layer 240, MTJ layer 250, selector layer 260, second interlayer insulating film 265, and second wiring 280 are the same. Therefore, details omitted above. Figure 2B A detailed description of the process structure and its corresponding parts.

[0067] According to the aforementioned semiconductor device and its manufacturing method, the bottom electrode contact 320, made of a specific alloy, simultaneously functions as a offset cancellation layer, thereby effectively reducing the height of the variable resistor element and improving its thermal stability. In other words, by simultaneously reducing the height of the variable resistor element and increasing magnetoresistance (MR) and enhancing the exchange bias field, high device integration and high capacity of the semiconductor device can be achieved. Even with this embodiment, all the advantages described in the foregoing embodiments can be obtained.

[0068] According to embodiments of the present disclosure, a semiconductor device and its manufacturing method can increase magnetoresistive (MR) and exchange bias (Hex) by reducing the height of the variable resistor element and enabling high-temperature heat treatment, and can form a layer that simultaneously serves as an offset offset layer (SCL) and a bottom electrode contact without using a specific alloy to form a separate offset offset layer (SCL).

[0069] Embodiments of this disclosure have been described in conjunction with specific examples; however, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical concept and scope of this disclosure as defined in the appended claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: An interlayer insulating film is disposed on a substrate and has a recess that exposes a portion of the substrate; Bottom electrode contact, which is embedded in at least a portion of the recess; as well as An MTJ layer is disposed on the interlayer insulating film and the bottom electrode contact. MTJ stands for Magnetic Tunnel Junction. The bottom electrode contact includes a Co alloy, Fe alloy, Ni alloy, or Mn alloy, wherein the alloy includes at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, Zr, Hf, and rare earth metals.

2. The semiconductor device of claim 1, wherein, The MTJ layer includes a fixed layer with a fixed magnetization direction, a free layer with a variable magnetization direction, and a tunnel barrier layer between the free layer and the fixed layer.

3. The semiconductor device of claim 2, wherein, The bottom electrode contact has a magnetization direction that is parallel to and opposite to the fixing layer.

4. The semiconductor device of claim 1, wherein, The bottom electrode contact includes the Co alloy.

5. The semiconductor device of claim 1, wherein, The bottom electrode contact includes the Co alloy or the Fe alloy containing rare earth metals.

6. The semiconductor device of claim 2, further comprising a spacer layer between the fixing layer and the bottom electrode contact. wherein The fixed layer and the bottom electrode contact are antiferromagnetically coupled through the spacer layer, thereby forming a synthetic antiferromagnetic structure.

7. The semiconductor device of claim 6, wherein, The spacer layer includes Ru, Ir, Cr, or any combination thereof.

8. The semiconductor device according to claim 6, wherein, The spacer layer has a thickness of 0.5 nm or greater.

9. The semiconductor device of claim 2, further comprising an intermediate layer between the fixed layer and the tunnel barrier layer.

10. The semiconductor device according to claim 9, wherein, The intermediate layer includes Co, Fe, Ni, B, noble metals, or any combination thereof.

11. A method for manufacturing a semiconductor device, the method comprising: An interlayer insulating film is formed on the substrate; The interlayer insulating film is selectively etched to form a recess that exposes a portion of the substrate; A bottom electrode contact is formed that is embedded in at least a portion of the recess; as well as A variable resistance element is formed on the bottom electrode contact. The bottom electrode contact includes a Co alloy, Fe alloy, Ni alloy, or Mn alloy, wherein the alloy includes at least one selected from the group consisting of Pt, Pd, Al, Ga, B, Ir, and rare earth metals.

12. The method according to claim 11, wherein, The variable resistance element includes: An MTJ layer is formed on the bottom electrode contact, the MTJ layer comprising a fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a free layer with a variable magnetization direction, which are sequentially stacked.

13. The method according to claim 12, wherein, The bottom electrode contact has a magnetization direction that is parallel to and opposite to the fixing layer.

14. The method according to claim 11, wherein, The bottom electrode contact includes the Co alloy.

15. The method according to claim 11, wherein, The bottom electrode contact includes the Co alloy or the Fe alloy containing rare earth metals.

16. The method of claim 12, further comprising forming a spacer layer on the bottom electrode contact prior to forming the MTJ layer. in, The fixed layer and the bottom electrode contact are antiferromagnetically coupled through the spacer layer, thereby forming a synthetic antiferromagnetic structure.

17. The method according to claim 16, wherein, The spacer layer includes Ru, Ir, Cr, or any combination thereof.

18. The method according to claim 16, wherein, The spacer layer has a thickness of 0.5 nm or greater.

19. The method of claim 12, further comprising forming an intermediate layer between the fixed layer and the tunnel barrier layer.

20. The method according to claim 19, wherein, The intermediate layer includes Co, Fe, Ni, B, noble metals, or any combination thereof.

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